content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc284.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00284ent IS
END c03s01b03x00p12n01i00284ent;
ARCHITECTURE c03s01b03x00p12n01i00284arch OF c03s01b03x00p12n01i00284ent IS
type distance is range 0 to 2e9
units
-- base unit
mil;
inch = 1000 mil;
ft = 12 inch;
yd = 3 ft;
fm = 6 ft;
mi = 5280 ft;
end units;
BEGIN
TESTING: PROCESS
variable k : distance := 12 ft;
BEGIN
assert NOT((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
report "***PASSED TEST: c03s01b03x00p12n01i00284"
severity NOTE;
assert ((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
report "***FAILED TEST: c03s01b03x00p12n01i00284 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00284arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(9 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '0'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
-- abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
-- & abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
-- 2020/10/04 : Demuxing is adapted to MAX 10 Board r0.7 (c).
-- I initially wanted to make An and MUXn matching, but as
-- there is a couple of mistakes on PCB schematics (around U1 and U4)
-- there is still a little need of de-spaghettizying the signals.
--Address Mapping for U4 : And for U1 : (In m10brd r07c) abus_address_latched_prepatch <= abus_address
-- A7 -> MUX12 A11 -> MUX0 & abus_addressdata_buf( 4) -- A15
-- A6 -> MUX13 A10 -> MUX1 & abus_addressdata_buf( 5) -- A14
-- A5 -> MUX14 A9 -> MUX2 & abus_addressdata_buf( 6) -- A13
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf( 7) -- A12
-- A15 -> MUX4 A3 -> MUX8 & abus_addressdata_buf( 0) -- A11
-- A14 -> MUX5 A2 -> MUX9 & abus_addressdata_buf( 1) -- A10
-- A13 -> MUX6 A1 -> MUX10 & abus_addressdata_buf( 2) -- A9
-- A12 -> MUX7 A0 -> MUX11 & abus_addressdata_buf( 3) -- A8
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(12) -- A7
-- A15 -> MUX4 & abus_addressdata_buf(13) -- A6
-- A14 -> MUX5 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX6 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX7 & abus_addressdata_buf( 8) -- A3
-- A11 -> MUX0 & abus_addressdata_buf( 9) -- A2
-- A10 -> MUX1 & abus_addressdata_buf(10) -- A1
-- A9 -> MUX2 & abus_addressdata_buf(11); -- A0
-- A8 -> MUX3
-- A7 -> MUX12
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX8
-- A2 -> MUX9
-- A1 -> MUX10
-- A0 -> MUX11
abus_address_latched_prepatch <=
abus_address(8)
& abus_address(7)
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata_buf( 4) -- A15
& abus_addressdata_buf( 5) -- A14
& abus_addressdata_buf( 6) -- A13
& abus_addressdata_buf( 7) -- A12
& abus_addressdata_buf( 0) -- A11
& abus_addressdata_buf( 1) -- A10
& abus_addressdata_buf( 2) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf(12) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 8) -- A3
& abus_addressdata_buf( 9) -- A2
& abus_addressdata_buf(10) -- A1
& abus_addressdata_buf(11) -- A0
& "0";
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched_prepatch <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata_buf(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata_buf(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata_buf( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata_buf( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata_buf( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata_buf( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata_buf( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(13) -- A6
-- A14 -> MUX11 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX12 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX9 & abus_addressdata_buf( 4) -- A3
-- A11 -> MUX10 & abus_addressdata_buf( 5) -- A2
-- A10 -> MUX2 & abus_addressdata_buf( 6) -- A1
-- A9 -> MUX1 & abus_addressdata_buf( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata <= X"00"&counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out(15 downto 0);
when X"E2" =>
avalon_regs_readdata <= sniffer_data_out(31 downto 16);
when X"E4" =>
avalon_regs_readdata <= sniffer_data_out(47 downto 32);
when X"E6" =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
when X"E8" =>
avalon_regs_readdata <= X"00"&sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata <= "00000"&sniffer_fifo_full&sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
sniffer_data_ack <= '0';
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
when X"E2" =>
null;
when X"E4" =>
null;
when X"E6" =>
sniffer_data_ack <= '1';
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(22 downto 10);
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);--avalon_sdram_pending_address(0);--only 8 bit writing for avalon
sdram_dqm(1) <= not avalon_sdram_byteenable(1);--not avalon_sdram_pending_address(0);--only 8 bit writing for avalon
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE then
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_cas_n <= '0';
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_dq <= avalon_sdram_pending_data; --(7 downto 0) & avalon_sdram_pending_data(15 downto 8) ;--&avalon_sdram_pending_data;
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
--avalon_sdram_reset_pending <= '1';
--if avalon_sdram_pending_address(0) = '0' then
avalon_sdram_readdata_latched <= sdram_dq;--(7 downto 0);
--else
--avalon_sdram_readdata_latched <= sdram_dq(15 downto 8);
--end if;
--avalon_sdram_readdatavalid <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
end if;
end if;
end process;
sniffer_data_in(15 downto 0) <= abus_data_in when abus_direction_internal='0' else
abus_data_out;
sniffer_data_in(40 downto 16) <= abus_address_latched(24 downto 0);
sniffer_data_in(41) <= not abus_chipselect_buf(0);
sniffer_data_in(42) <= not abus_chipselect_buf(1);
sniffer_data_in(43) <= not abus_chipselect_buf(2);
sniffer_data_in(44) <= not abus_write_buf(0);
sniffer_data_in(45) <= not abus_write_buf(1);
sniffer_data_in(46) <= not abus_read_buf;
sniffer_data_in(47) <= '0';--reserved
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
end architecture rtl; -- of sega_saturn_abus_slave
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(9 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '0'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
-- abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
-- & abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
-- 2020/10/04 : Demuxing is adapted to MAX 10 Board r0.7 (c).
-- I initially wanted to make An and MUXn matching, but as
-- there is a couple of mistakes on PCB schematics (around U1 and U4)
-- there is still a little need of de-spaghettizying the signals.
--Address Mapping for U4 : And for U1 : (In m10brd r07c) abus_address_latched_prepatch <= abus_address
-- A7 -> MUX12 A11 -> MUX0 & abus_addressdata_buf( 4) -- A15
-- A6 -> MUX13 A10 -> MUX1 & abus_addressdata_buf( 5) -- A14
-- A5 -> MUX14 A9 -> MUX2 & abus_addressdata_buf( 6) -- A13
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf( 7) -- A12
-- A15 -> MUX4 A3 -> MUX8 & abus_addressdata_buf( 0) -- A11
-- A14 -> MUX5 A2 -> MUX9 & abus_addressdata_buf( 1) -- A10
-- A13 -> MUX6 A1 -> MUX10 & abus_addressdata_buf( 2) -- A9
-- A12 -> MUX7 A0 -> MUX11 & abus_addressdata_buf( 3) -- A8
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(12) -- A7
-- A15 -> MUX4 & abus_addressdata_buf(13) -- A6
-- A14 -> MUX5 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX6 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX7 & abus_addressdata_buf( 8) -- A3
-- A11 -> MUX0 & abus_addressdata_buf( 9) -- A2
-- A10 -> MUX1 & abus_addressdata_buf(10) -- A1
-- A9 -> MUX2 & abus_addressdata_buf(11); -- A0
-- A8 -> MUX3
-- A7 -> MUX12
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX8
-- A2 -> MUX9
-- A1 -> MUX10
-- A0 -> MUX11
abus_address_latched_prepatch <=
abus_address(8)
& abus_address(7)
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata_buf( 4) -- A15
& abus_addressdata_buf( 5) -- A14
& abus_addressdata_buf( 6) -- A13
& abus_addressdata_buf( 7) -- A12
& abus_addressdata_buf( 0) -- A11
& abus_addressdata_buf( 1) -- A10
& abus_addressdata_buf( 2) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf(12) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 8) -- A3
& abus_addressdata_buf( 9) -- A2
& abus_addressdata_buf(10) -- A1
& abus_addressdata_buf(11) -- A0
& "0";
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched_prepatch <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata_buf(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata_buf(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata_buf( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata_buf( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata_buf( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata_buf( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata_buf( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(13) -- A6
-- A14 -> MUX11 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX12 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX9 & abus_addressdata_buf( 4) -- A3
-- A11 -> MUX10 & abus_addressdata_buf( 5) -- A2
-- A10 -> MUX2 & abus_addressdata_buf( 6) -- A1
-- A9 -> MUX1 & abus_addressdata_buf( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata <= X"00"&counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out(15 downto 0);
when X"E2" =>
avalon_regs_readdata <= sniffer_data_out(31 downto 16);
when X"E4" =>
avalon_regs_readdata <= sniffer_data_out(47 downto 32);
when X"E6" =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
when X"E8" =>
avalon_regs_readdata <= X"00"&sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata <= "00000"&sniffer_fifo_full&sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
sniffer_data_ack <= '0';
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
when X"E2" =>
null;
when X"E4" =>
null;
when X"E6" =>
sniffer_data_ack <= '1';
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(22 downto 10);
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);--avalon_sdram_pending_address(0);--only 8 bit writing for avalon
sdram_dqm(1) <= not avalon_sdram_byteenable(1);--not avalon_sdram_pending_address(0);--only 8 bit writing for avalon
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE then
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_cas_n <= '0';
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_dq <= avalon_sdram_pending_data; --(7 downto 0) & avalon_sdram_pending_data(15 downto 8) ;--&avalon_sdram_pending_data;
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
--avalon_sdram_reset_pending <= '1';
--if avalon_sdram_pending_address(0) = '0' then
avalon_sdram_readdata_latched <= sdram_dq;--(7 downto 0);
--else
--avalon_sdram_readdata_latched <= sdram_dq(15 downto 8);
--end if;
--avalon_sdram_readdatavalid <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
end if;
end if;
end process;
sniffer_data_in(15 downto 0) <= abus_data_in when abus_direction_internal='0' else
abus_data_out;
sniffer_data_in(40 downto 16) <= abus_address_latched(24 downto 0);
sniffer_data_in(41) <= not abus_chipselect_buf(0);
sniffer_data_in(42) <= not abus_chipselect_buf(1);
sniffer_data_in(43) <= not abus_chipselect_buf(2);
sniffer_data_in(44) <= not abus_write_buf(0);
sniffer_data_in(45) <= not abus_write_buf(1);
sniffer_data_in(46) <= not abus_read_buf;
sniffer_data_in(47) <= '0';--reserved
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
end architecture rtl; -- of sega_saturn_abus_slave
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(9 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '0'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
-- abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
-- & abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
-- 2020/10/04 : Demuxing is adapted to MAX 10 Board r0.7 (c).
-- I initially wanted to make An and MUXn matching, but as
-- there is a couple of mistakes on PCB schematics (around U1 and U4)
-- there is still a little need of de-spaghettizying the signals.
--Address Mapping for U4 : And for U1 : (In m10brd r07c) abus_address_latched_prepatch <= abus_address
-- A7 -> MUX12 A11 -> MUX0 & abus_addressdata_buf( 4) -- A15
-- A6 -> MUX13 A10 -> MUX1 & abus_addressdata_buf( 5) -- A14
-- A5 -> MUX14 A9 -> MUX2 & abus_addressdata_buf( 6) -- A13
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf( 7) -- A12
-- A15 -> MUX4 A3 -> MUX8 & abus_addressdata_buf( 0) -- A11
-- A14 -> MUX5 A2 -> MUX9 & abus_addressdata_buf( 1) -- A10
-- A13 -> MUX6 A1 -> MUX10 & abus_addressdata_buf( 2) -- A9
-- A12 -> MUX7 A0 -> MUX11 & abus_addressdata_buf( 3) -- A8
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(12) -- A7
-- A15 -> MUX4 & abus_addressdata_buf(13) -- A6
-- A14 -> MUX5 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX6 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX7 & abus_addressdata_buf( 8) -- A3
-- A11 -> MUX0 & abus_addressdata_buf( 9) -- A2
-- A10 -> MUX1 & abus_addressdata_buf(10) -- A1
-- A9 -> MUX2 & abus_addressdata_buf(11); -- A0
-- A8 -> MUX3
-- A7 -> MUX12
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX8
-- A2 -> MUX9
-- A1 -> MUX10
-- A0 -> MUX11
abus_address_latched_prepatch <=
abus_address(8)
& abus_address(7)
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata_buf( 4) -- A15
& abus_addressdata_buf( 5) -- A14
& abus_addressdata_buf( 6) -- A13
& abus_addressdata_buf( 7) -- A12
& abus_addressdata_buf( 0) -- A11
& abus_addressdata_buf( 1) -- A10
& abus_addressdata_buf( 2) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf(12) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 8) -- A3
& abus_addressdata_buf( 9) -- A2
& abus_addressdata_buf(10) -- A1
& abus_addressdata_buf(11) -- A0
& "0";
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched_prepatch <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata_buf(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata_buf(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata_buf( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata_buf( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata_buf( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata_buf( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata_buf( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(13) -- A6
-- A14 -> MUX11 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX12 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX9 & abus_addressdata_buf( 4) -- A3
-- A11 -> MUX10 & abus_addressdata_buf( 5) -- A2
-- A10 -> MUX2 & abus_addressdata_buf( 6) -- A1
-- A9 -> MUX1 & abus_addressdata_buf( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata <= X"00"&counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out(15 downto 0);
when X"E2" =>
avalon_regs_readdata <= sniffer_data_out(31 downto 16);
when X"E4" =>
avalon_regs_readdata <= sniffer_data_out(47 downto 32);
when X"E6" =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
when X"E8" =>
avalon_regs_readdata <= X"00"&sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata <= "00000"&sniffer_fifo_full&sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
sniffer_data_ack <= '0';
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
when X"E2" =>
null;
when X"E4" =>
null;
when X"E6" =>
sniffer_data_ack <= '1';
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(22 downto 10);
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);--avalon_sdram_pending_address(0);--only 8 bit writing for avalon
sdram_dqm(1) <= not avalon_sdram_byteenable(1);--not avalon_sdram_pending_address(0);--only 8 bit writing for avalon
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE then
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_cas_n <= '0';
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_dq <= avalon_sdram_pending_data; --(7 downto 0) & avalon_sdram_pending_data(15 downto 8) ;--&avalon_sdram_pending_data;
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
--avalon_sdram_reset_pending <= '1';
--if avalon_sdram_pending_address(0) = '0' then
avalon_sdram_readdata_latched <= sdram_dq;--(7 downto 0);
--else
--avalon_sdram_readdata_latched <= sdram_dq(15 downto 8);
--end if;
--avalon_sdram_readdatavalid <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
end if;
end if;
end process;
sniffer_data_in(15 downto 0) <= abus_data_in when abus_direction_internal='0' else
abus_data_out;
sniffer_data_in(40 downto 16) <= abus_address_latched(24 downto 0);
sniffer_data_in(41) <= not abus_chipselect_buf(0);
sniffer_data_in(42) <= not abus_chipselect_buf(1);
sniffer_data_in(43) <= not abus_chipselect_buf(2);
sniffer_data_in(44) <= not abus_write_buf(0);
sniffer_data_in(45) <= not abus_write_buf(1);
sniffer_data_in(46) <= not abus_read_buf;
sniffer_data_in(47) <= '0';--reserved
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
end architecture rtl; -- of sega_saturn_abus_slave
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_waitrequest_read : std_logic := '0';
--signal abus_waitrequest_write : std_logic := '0';
--signal abus_waitrequest_read2 : std_logic := '0';
--signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
--signal abus_waitrequest_read_off : std_logic := '0';
--signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(47 downto 0) := (others => '0');
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(9 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_waitrequest <= '1';
abus_disable_out <= '0'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
-- abus_address_latched_prepatch <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
-- & abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
-- 2020/10/04 : Demuxing is adapted to MAX 10 Board r0.7 (c).
-- I initially wanted to make An and MUXn matching, but as
-- there is a couple of mistakes on PCB schematics (around U1 and U4)
-- there is still a little need of de-spaghettizying the signals.
--Address Mapping for U4 : And for U1 : (In m10brd r07c) abus_address_latched_prepatch <= abus_address
-- A7 -> MUX12 A11 -> MUX0 & abus_addressdata_buf( 4) -- A15
-- A6 -> MUX13 A10 -> MUX1 & abus_addressdata_buf( 5) -- A14
-- A5 -> MUX14 A9 -> MUX2 & abus_addressdata_buf( 6) -- A13
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf( 7) -- A12
-- A15 -> MUX4 A3 -> MUX8 & abus_addressdata_buf( 0) -- A11
-- A14 -> MUX5 A2 -> MUX9 & abus_addressdata_buf( 1) -- A10
-- A13 -> MUX6 A1 -> MUX10 & abus_addressdata_buf( 2) -- A9
-- A12 -> MUX7 A0 -> MUX11 & abus_addressdata_buf( 3) -- A8
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(12) -- A7
-- A15 -> MUX4 & abus_addressdata_buf(13) -- A6
-- A14 -> MUX5 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX6 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX7 & abus_addressdata_buf( 8) -- A3
-- A11 -> MUX0 & abus_addressdata_buf( 9) -- A2
-- A10 -> MUX1 & abus_addressdata_buf(10) -- A1
-- A9 -> MUX2 & abus_addressdata_buf(11); -- A0
-- A8 -> MUX3
-- A7 -> MUX12
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX8
-- A2 -> MUX9
-- A1 -> MUX10
-- A0 -> MUX11
abus_address_latched_prepatch <=
abus_address(8)
& abus_address(7)
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata_buf( 4) -- A15
& abus_addressdata_buf( 5) -- A14
& abus_addressdata_buf( 6) -- A13
& abus_addressdata_buf( 7) -- A12
& abus_addressdata_buf( 0) -- A11
& abus_addressdata_buf( 1) -- A10
& abus_addressdata_buf( 2) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf(12) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 8) -- A3
& abus_addressdata_buf( 9) -- A2
& abus_addressdata_buf(10) -- A1
& abus_addressdata_buf(11) -- A0
& "0";
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched_prepatch <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata_buf(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata_buf(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata_buf( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata_buf(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata_buf( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata_buf( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata_buf( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata_buf( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata_buf(13) -- A6
-- A14 -> MUX11 & abus_addressdata_buf(14) -- A5
-- A13 -> MUX12 & abus_addressdata_buf(15) -- A4
-- A12 -> MUX9 & abus_addressdata_buf( 4) -- A3
-- A11 -> MUX10 & abus_addressdata_buf( 5) -- A2
-- A10 -> MUX2 & abus_addressdata_buf( 6) -- A1
-- A9 -> MUX1 & abus_addressdata_buf( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(25 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--if abus write access is detected, disable abus wait immediately
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
-- abus_waitrequest_write <= '1';
-- else
-- abus_waitrequest_write <= '0';
-- end if;
-- end if;
-- end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read;
-- --abus_waitrequest_read3 <= abus_waitrequest_read2;
-- --abus_waitrequest_read4 <= abus_waitrequest_read3;
-- abus_waitrequest_write2 <= abus_waitrequest_write;
-- --abus_waitrequest_write3 <= abus_waitrequest_write3;
-- --abus_waitrequest_write4 <= abus_waitrequest_write4;
-- end if;
-- end process;
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata <= X"00"&counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out(15 downto 0);
when X"E2" =>
avalon_regs_readdata <= sniffer_data_out(31 downto 16);
when X"E4" =>
avalon_regs_readdata <= sniffer_data_out(47 downto 32);
when X"E6" =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
when X"E8" =>
avalon_regs_readdata <= X"00"&sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata <= "00000"&sniffer_fifo_full&sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
sniffer_data_ack <= '0';
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
when X"E2" =>
null;
when X"E4" =>
null;
when X"E6" =>
sniffer_data_ack <= '1';
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--waitrequest should be issued as long as we received some command from avalon
--keep it until the command is processed
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (avalon_sdram_read = '1' or avalon_sdram_write = '1') and avalon_sdram_read_pending = '0' and avalon_sdram_write_pending = '0' then
-- avalon_sdram_waitrequest <= '1';
-- elsif avalon_sdram_complete = '1' then
-- avalon_sdram_waitrequest <= '0';
-- end if;
-- end if;
-- end process;
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address(24 downto 0) <= avalon_sdram_address;
--avalon_sdram_pending_address(0) <= avalon_sdram_byteenable(0);
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(22 downto 10);
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);--avalon_sdram_pending_address(0);--only 8 bit writing for avalon
sdram_dqm(1) <= not avalon_sdram_byteenable(1);--not avalon_sdram_pending_address(0);--only 8 bit writing for avalon
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(22 downto 10);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE then
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "0010"&abus_address_latched(9 downto 1);
sdram_ba <= abus_address_latched(24 downto 23);
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_cas_n <= '0';
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(24 downto 23);
sdram_dq <= avalon_sdram_pending_data; --(7 downto 0) & avalon_sdram_pending_data(15 downto 8) ;--&avalon_sdram_pending_data;
sdram_addr <= "0010"&avalon_sdram_pending_address(9 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
--avalon_sdram_reset_pending <= '1';
--if avalon_sdram_pending_address(0) = '0' then
avalon_sdram_readdata_latched <= sdram_dq;--(7 downto 0);
--else
--avalon_sdram_readdata_latched <= sdram_dq(15 downto 8);
--end if;
--avalon_sdram_readdatavalid <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_data_write <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_data_write <= '1';
end if;
end if;
end if;
end process;
sniffer_data_in(15 downto 0) <= abus_data_in when abus_direction_internal='0' else
abus_data_out;
sniffer_data_in(40 downto 16) <= abus_address_latched(24 downto 0);
sniffer_data_in(41) <= not abus_chipselect_buf(0);
sniffer_data_in(42) <= not abus_chipselect_buf(1);
sniffer_data_in(43) <= not abus_chipselect_buf(2);
sniffer_data_in(44) <= not abus_write_buf(0);
sniffer_data_in(45) <= not abus_write_buf(1);
sniffer_data_in(46) <= not abus_read_buf;
sniffer_data_in(47) <= '0';--reserved
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
end architecture rtl; -- of sega_saturn_abus_slave
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CPU is
generic(
WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 10
);
Port(
inM : in std_ulogic_vector(WIDTH - 1 downto 0);
instruction : in std_ulogic_vector(WIDTH - 1 downto 0);
reset : in std_ulogic;
outM : out std_ulogic_vector(WIDTH - 1 downto 0);
writeM : out std_ulogic;
addressM : out std_ulogic_vector(ADDRESS_WIDTH - 1 downto 0);
pc : out std_ulogic_vector(ADDRESS_WIDTH - 1 downto 0);
clock : in std_ulogic
);
end CPU;
architecture Behavioral of CPU is
signal ALU_out, comp, D, ins_val_mux_out, A_or_M : std_ulogic_vector(WIDTH - 1 downto 0);
begin
our_beloved_ALU : entity work.ALU(Behavioral)
generic map(
WIDTH => WIDTH
)
port map(
clock => clock,
register_D => D,
A_or_M => A_or_M,
c => instruction,
comp => comp
);
register_A : entity work.SimpleRegister(Behavioral)
generic map(
WIDTH => WIDTH
)
port map(
inval => ins_val_mux_out,
outval => addressM,
set => instruction(5),
clock => clock,
reset => '0'
);
register_D : entity work.SimpleRegister(Behavioral)
generic map(
WIDTH => WIDTH
)
port map(
inval => comp,
outval => D,
set => instruction(4),
clock => clock,
reset => '0'
);
instruction_value_MUX : entity work.Mux(Behavioral)
generic map(
WIDTH => WIDTH
)
port map(
val1 => instruction,
val2 => comp,
switch => instruction(WIDTH - 1),
outval => ins_val_mux_out
);
ALU_instruction_MUX : entity work.Mux(Behavioral)
generic map(
WIDTH => WIDTH
)
port map(
val1 => addressM,
val2 => inM,
switch => instruction(WIDTH - 4),
outval => A_or_M
);
register_PC : entity work.ProgramCounter
generic map(
WIDTH => WIDTH
)
port map(
inval => addressM,
comp => comp,
jump => instruction(2 downto 0),
reset => reset,
clock => clock,
outval => pc
);
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DrFNe3y2P5nP7Rx95qyoQtV577JZ6mHlWcJpkpgDuMk1tMBHYOxfAvMPjf6auNpYR8gPabRS6cnK
jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IxQn8drvE7Sb9/3BUJVMQoZBd8cj4z9U1TZMSETxI02fgVKYupGpiEh+LiYhMW3es0I1ffs6McuE
bs7kk2EOtcuTfwPsa4Wu3OOcvxHHeC98yBqddgvOLVJoAEb5RNiGoYqws9c3o1iqC3JCd5sYhWwU
LB7ySr6E8tZPaq82yHw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UC27eDrtTOjJIFtKeyx8ADcLMtfAT4mJdO9dhuxbE9av5VWQotisvd42RGIAgggOPeCblnuSjCFN
MxJcsj0Ym5C2pXnWD8k45HFBUtM1CZYllaNawVznaxCoU9cbI/F/quA9dytfQ6E3nYD7NRUiQeXI
qNLRVlKOd3sHDl4Ml8BUzkUxkau+CLIMqPeItwxQ3t7N51OKF7jRvSKtsM42GZNwvj8StkQqJPGy
f05noKhb6G5GDYG/WWfCFpt3qATC3nfEMt61wsILal4ZZQnpwZN9UWH8SrVihRpVT0MA2gdJUbVX
9rjCb9QcTD0k1vglSUdT7+KsLKo6kCJgvn2v/A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iqIbH529vk+Zbr4o+0lOrJs0Ntf6Ib2MR0xJbZnnBLs3D+25tJbl1QpWtBcK9/Y2IAVXAleMTcjs
fxnkiRTPlx6HRCqglrfz+Vz0phKv5uAumD4xiUGt4yaxyu2wRfEx1rMjicoNaeBeKJNOOrM9a9FV
tnb/+g4KQpZTMCq7fVs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hK4UEFPXCgC7q4kNPisRaOqK53obm3ze8ng6fW4VvFqUMJP5MFWxSphzH/GYPeOeKkZBMmwyzQMN
47e7HNlOFny1piZcPvqRo22Qje54G7VKf8g4sBoKB6RwAZcCt47fKr2fP6BimKj7lZ8jjoAMqczT
V55bVQ34EHRLyi4l9r3Q2wQBGK4UQoKHoiSiCQoY2ZpDaDap/GKR7pdAqwAGcIS59GXn9NtJTQyZ
aLEkmd3ecgBvcYG/Im6ZmTT7EkS3zPDAAyygUTx3LO/s2tO4zMX2OySkUFOMbQZ8wzRO0TJ8aEkg
fSuuEquk4K9hgaUcIr+/UeW6VcPEOH9JB+BOtg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
mBVw3xJ/cTlKJIeI2d/aQKXOIw2ew8K6jdLMNJadPGPriaNdkZPjrGbWctKKO5x+hl11eZzH0d7o
csL3S+obGbzyDKjtH64QK28sn8vRMlrPI6Iq+8LOhyXxE8Q3ZT3kJNrrct/JxsAdGlMtIDzjwcAx
BHe0Fp6FoJZZWEO3JVA98nn0ydJrFn2p+MxU+Wk7Ja9V7xGGNzv2Lockm5AaoL4N7zwrLnqqREVY
2j0Uv/Du4YWX8WAVY9jC7y4oQMvJVTeyaDN8dJIxDXMPm92yK2HB9Oku88kA5e9V1DYmyRldV2Yt
2I29LXI6uhG5uwxbvUdqllm2P5CxKhpyKpipJDPgYra3CRUw/sJdgqJUSR4Bln5Gnf1r2bVVUagT
UJvkhodkcJmRyfaMmHnMzD3QmjdLaLEKmNUF/eHaHFKtlFFr7v1O0kXIqFrhoX0fZ6MAD3g5VP2F
lXa7VBx6isbyhfPTjaN+bGKSe+cwgyBhgVYBK/hOnMbDSxg/SsDn4TIPqV5Hteyhf+nkT0hg2t2u
Fg/Elubtrs9WQmaQFvhs6Zu/9rAAyV9M9e7BhuBT/0v7GDQscHZOhjwr+JmRwD2MdjyoFoC2OhR2
A8Ib/W62GtVw67lkqh2Wps0F5uSPm5smxw+BnbdFANnwkEizeFEgcwOlGuCeHcmS831uHlwCqugx
KoXn3Xcx+5a3piZNdRb3vKkPwhSiKWfRKFF+NdXAPrR5wsngoT/4YnV3vK7KDYIpe01aD/YhzXPr
KxiiaN91nKMDFi13LCAkbeQyshTFzICVwR0n62kRtQ2cmW53s8X5VpMQpdV32LuocCJFxlz1NPDC
YW380BAGENDBmOMiQjynRbib38mUo7RCuIwNIuGN8Tv1InoDR7/4PK6gi6mZKEdtRm0ltR9ZLRec
pgUZW0u12BsGqEK8KP4s1Xhzk+3VGoPkGvMHUMPVSlPT2dFPkxktG+ofYZqdxbn03hx7/h14xWZs
t3aYbtKrzE5sGxxWBJXel0LZwcxFME6WAOJQu5wDuMZYp8CZVioQT+MLm9A0+f5KqgT0OY4a0R0O
K/q03WQIlj4aYUlGXPs9GSh8vt6n1x53nyKmfNxQahIBVaaeShNWt0UFMsDxjjaFpIqSFGB0SWz3
Zp7sWW66O6jUJI81joaoKzszKttpjtwp751gId+O1ewTpSiBV0MqU5+gCCI9a3QP9Rp+/frXF+Xc
BY8OSd7dqKp52qCXYo3wEY07p64hf79FQ8pEHWrjLuwBZmHCqmxF+r/y2gMC+o1wXqETzh57aAlQ
yDuHCLh1h5dR7FC7Bi10wiKH1DnrZ064sAqL5cglr5xIiqOZ5YmtSHVryTqnk2rOmH4ILieSFwd2
l6nUkKgZavqF5gGoXRMgKIGotBOZqA5fiFFewuSQdXCE0pQ7YmIXFXIcA+3I6LFSizSyxC82A12w
h6MY16bLQmJpk8QhtCIEiba/or0qkL4lqxrqC6PP86SHJoRpSAexC1vX7d5EIYDAanISCMZj+/bX
2kOxUr7oigcM3BtoT0WKTW78zaNu+R3yFJcxugKGpUG0xmBnrKVx8DCQ6vCV9FZdchoQ1VRg8vzQ
1ma0Q0vPA81LCMWjMPevBr4jvb6V1EWr75GtrVQjQXxe/UWBT54R6YYEug3MiiGyai6Dw756gmYW
wBbJceyLyksnZ4wCg7Av4UgpCKwc25PpuYYpYRDP8RZ2Cpy4TifEdGzzTY3X1v0LwOeKYlckACu2
QnvUZ+tsFJOQFIRKg8blaBZRhHrqljONq4OiE1arWFiYJmylVGsm9w0VmkV8A1Z6bPe4+e37qVnx
SKiUK8iFxjGQyUWHpR0wlJzrfVPm7IwIA95F40WInyHXIei0KFxtX1dh1E73tI1OLvz/SPnD8VWC
nkziaS1ABbvoOVlFF5lFHFBosAN411sLMBjaJvkgp4ONZVbdq6H7JoadEtDfeK8LeVtxkkep6IKY
VANVecXAxkM/6Bw4ofMa09O7XCKBAnRnA76Uis/hBOdKd0/k8ciQWff1OkIEFF6H7lVS8sQ1+VNh
dbUJlfFYFCLoCr/I7EZpfZ8B+ivk0OgyvTszkEO+vvxVUCmUCbWYhMYdsiYRuyGpjWrg/6GHPvHw
HDARpVPLJ68vGFUFFMnV7PaiGIxEb+lyF00jZkREnhwmyQM9zyeghVZYC3/DjX9UTH37cPGkWlxh
TK/I2Ub/Cyu+5l+QMWtHPOQBVwUEZQMylTlYMYA1FAmc48Z+imO5XgE8ioGb9FzDsBr7wyLgV5dy
vtp+j0q00rNOjeDAvkALEUlhXEVLFhCbmQ37BYVN4sm+PF69tmh9oSxRqyE2SBcK8nONc1XXhMfe
L7kTvEvwLIQfbfheyWsyFGeuv3hJKnXB5f//mpdI/j9HGv1/tR3GAHxPF46X69O4ayd7k3/HT4Tm
E5qKNT0oxDyvhErvlja+gmN7os99D1XrgxWCgoK4BHOPrBWKHwBAldHMgBIh592BOA/7z1keCM8D
ZoSbK4G/Ia93z11IiVC+He3zMl06tdOckPt+dCVqePgnsdy1JtY6ayzouRk42+aPdJI8ym0iaMcZ
z1V5bBfpkSHrgEgdDf/U1fyFCFwMtenlw/2xkU/q/6gHRCN/MN2uXuOO4W2Ad92RJHmg5sAYar6m
QWt27QrZWc3wDTulwOMlJgyxhAhWEl/uClpTj5vMCTW1L19Z+AsRVKM1MVG42YDP63GH9d0vt3H5
XKV1ga4tUtJo3J+vfpGGjVwx16icUwKm/EHcIs+oQQ5oN8MsgbJw0ct8QttJEFACRUqFbA8aR7zd
exBHF6Rgpl1xMQQ0CdoXSd4+3ZILJnwF7hhktor4K2rUpqGIUWqH4P8pQviW6eE+QwzjMmLr/zUF
dbW4FN1F/3xMzwosCbO9gfLoP+mwC031/ytplUgWHi+UNFAtaIJy+Ar5EZu6rRuPeRy7PlCb8kIn
mPiqa7TUZKIZvRLjJvU8sB5uQvnCYm7E39/mkGZELL/P52+B7hZU93LSYAd4qgRnip6iJVXjAira
sQJEOvJzonxFGgwg/0pURnFpL7z+MmRVWKbrDWguf4gMk3tfvARu/UJOPOL8JJji6h07tMLufLAC
FoYE0iHPaxCR2LMyfpOGgR9WtQIvTh/OVH0fbass9yHi4EswtZMuiDBRy8KNP8sotmTSOePPal2u
6RLidgNcPWA52IWLSvjhMhgSdTeiY7c2tvDpmecR2FlFf1xLLh4TmrqEehOy79ry9utenZF9ph5h
lpxijrOXzBfJ8sVOEwu4N19TrWv5APdVTjqltMb7VZRzOiw9Y77babkTdSnWZ35Rmv1MMxg6DI6f
tEPJ6KGdGmeITHdtkP6bLvPPKsxKADFiGQG1zonfjvO/utnNeMpQRFtPXqfq0OZdpZtgsfvsLth+
fSj3O99iQGpYiH5Xm8VV2R20oM34mM+Rn7JHucw2ZaLN9S3rhQlT0b6zLPEvKFZ2PbVdHTpqXxiT
PBN7IcSipjtmp9q6IDcADOo0tRIsC+LCXRCgpXA/PyLrZWKHiFbJEEDaor0ws9avkjSpRtkq8dlx
L9+K5Yj3k0r3JfeXBUpEPxyYvpeky0ceYEZMBZIf5GyMwWcB04G2MdqcLjTYPFut+HCKMs6RqMmp
Rzp9ThsZbvLrFI9FLUbOEWXA3s9dbB237ExK+OyLGraqsRII928YHNppCnW3aj7II4Cjkp2m/Lh4
ZjeL8yGZ6ZX5M9wktRYUyCNAxaWxQThzBdjFWbBOYkmP/eyeuz1XgSIOZfjZLTAk3xkoBpYiDpx/
urzKCE/ZEBYhLmsdDjoOEWeansX2tyNjebFX78aHCUNGMXrGjnnp++ndK3PTTKQHKhSdF1aKYoBx
7Dm6RyRZsGas3iyjLdjYKoDGLmIQ9eOPZLu7CJOIb0HImafawtvB+HlsRY13eBe0f0jhdk8SXBD6
UyH3c4TaBtEA4qEICx5zm7EWJ0xG4oX8bmCxpIolgB1ErpusqxF+jUsBps8fGSxcgse/1lgS0aYP
2RpXRzUa8IBMa29pgYi0tyhDCGYzXXu0EHA6rQ5orKl34E0uysN0fVBZcRg7FO/qbB0GME+upTeJ
sY6HjEblURxMzRaSmqBfypGy4kPVVbLveRW5juO8MM63zDTUWn8veNDK+2o9GYKu1/EH2Ytwg4oX
8GTrnJw6Mq5Udj4XdDpu6r8z6XK6GdHthGUzhxUdzA1ySuELgAosxtJp0OtYcgGUjkoYDc3xQJ0N
vJIkFHV4p5RaU1g/yMk8MDkx/lap2yk1Bx/Oh9sOgLzPq6h4tSoSTRnKUKj3QPHLFzC9+EDX7IAz
8J+GvmTUgtaU1nEI+bJxtwqXhnqHyE2e4PVaVgeAzSHr5nS+RoPlbcGj2V6gw6BlasY6sRuQ+sdP
45YB9vqiKLHADV6I4Bm9mZC2Mco+AonqqWfgVqij/JFJbbZjq543Ok99A8SiMPvKTQny6ha7pd3E
gSlZ2fkAq7HIm1hRmcHlLJpGswqfquN2ISOtg7Q0djUbNuF2JS5lc8uNIYU7kNSFfYZxxcWAUBBB
mRluywu5YT27HchXbOXs6UJB/VcmtOd77pyWIaT42PFYFRb2ox6KvRPV0dhKdL9YjpcGNRpGA4X0
q6aH03XCzEM+lWMEhzm8MaLrCKw/qGH8sX2BViT4FtEI+WP4B43eunWOYB1vjV/jMzRKWIx9z8Hc
xaPxxFcZJK2JT85Bs/zXLKTu4D3BjW72NEZxeYZpvFtcYXXV0v6yrw1BaPtMP1YTvykaHNaGSNxV
vgBmve/N0xgeoOTYrrbrLABMur/rPcXBr1Vrpp7g2oFtpHsPg6BL258G5fm7YzM4Hst2vyY6pAs8
ZneHub+k3FNRItHL7CcHEmjt4sGRZgKU4PRuQ5RjkyB6T1n7JGFCTzELNpQmKKO7677JZO306vjS
HXK6GEw/giZl9obHqoo/kXZ54elkOrQ4HzYnAWXJELcQh0gHk3qFyQf1A3RkY46Lj5W6NTOHszRP
loKBZ+irpbLjKMyTE7uZQLQj7aoV9Tgk6qzp8BavpvoklxBodijrZvc6/ahLxqTBMB49I7FLJfN/
+aL3ex/4ADjvcsA7lxQTpxHHBnmQkr+eEdGj6kgRBjPKSDdi6Xh939l7z+RRJZNFLj+v5mfnPaWL
nksNXNzRPmlHDJxiO4tMEkmWsHffSzqQNaIaXiqM479AN/hLsOtKNK/d7ow+wnY1g/aDfCMt+nfE
H6g+gNxQ1Y9Dy2iSOjTpnVA7vvFfUUCvDrTsLJ5cJNj6m6g4kftcPcSpXEJCTSUccH5BsESulexA
VFr6JDoFk7KZ0t9+VqsDboE54HslTX8gdNEMt5gs+//AA/8zeNONGtkV65v8aFhqUe8C238FsQO9
dMFFZE66De1nkDwtxLnAEVtwpt5loQZBGZpDJWWDeoNFFZ387/Dg3vBrVFoYMnrvff+8T942ICGe
4IV0rRy7VxZHUB07REoMQCQP9Bl3hh5wDtjIpqBEcR5JKml7bOgbRKKIaDtUvT7uyL/0L1XnwYTd
eJisQgJYl2y/Ge+2KQtvpBcLIezzRsdOZmqDB3bHFiYrg8/YBBwtodUx+3jwNN0WWftPkbEt5zGz
pUO/o+layBaLlAHX962DOXwXBh/3R0Z2OGven0PX91WMR0g1Vkm0pdwkz6vpOC/XTb9QbQeL3HNo
wbtFLjYw8HdZCS3zHnRURQpElNyXjKtnUA0y5VhNh4pH4oZ/tB0jifj8wv90t7xaA+1s3kfYOKGY
GHt1wm1ed4nm46UxcCD7IVchvGx9En5jlpPdbcJBincLs8BBA11yxcNzx61XxHHR9cDeOjLuq/OQ
XGvn84/eyb6N4CQ2GpiwLhqhAgTOYAbXVU7wvU7xEb5M+DfSAtzp/0h0RsHlwMh4JvZ3Ib3Kpt0d
osb/Og/yiIcbK+LG6nnXuBfCFK1ynQBBINUHqnD9D5iDglMx4SaqKtzWmWkRs2P5aF8INHkNhw82
FOa/OswYb7XvPrCpP5BfScyf/WY0mB7gdjkgaz//xH9lu6VAzClsy9HX0H8hmMAQwuUufrdfT9LI
gO5C6dyFad4d7SbUl4rZwxM85xvB+wXSglP0FIpXF5nnlWMn8IQA57q56GlZc5he3eQDZNMXeOII
qvL/RfS6k6hnhA778Yg3eBXn53U611D5PXF8qzgQAHOVRyFkqS9CeEaW/vDo5GLhvhOPn3LFtgIv
mosqO6f2EUxwNaRe3imVYshVmXNDASaLBAO/wZVfTLkLy8pPzN7ZYuQ9M9v4uliMnv+zP50auHbT
tx1Pt8pUz3nR5m4sIxNSDKLvJjEoS4GvdecIQeq1Y4W3+zUKa41CU11XWXddBbOo0h5W445tNrc1
KU2u3iMMX7fwO+BGELAOZGGw4FszWN0bLYYpY6SJUvPO2tqz0n06uPcjDbli0Lu9vCpwkCLr//xk
vr1fSK5qp5Rn8M9/+trWz2P6X7nc/euMAGIDktXRRh75OskbjSH9usHeex6fcHrNXV9xwXO+bCuy
V63vyfZ/PBulCQfY0i+9d8o7RWdZCvb3BDBcyUxr/goyuDyWMQ7JuBlWpk+tTmjoYMsHNMOfPn52
GD0C8ixjbhwj1AvsHe4R1X9Ba8KH9tPgNXD7IBitenLQUTUQD5HetuMrEZ3t25nWkqGDtycQTEVN
OJ11im/CHjYpBfG9EPV/IfESrWFlRuas
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DrFNe3y2P5nP7Rx95qyoQtV577JZ6mHlWcJpkpgDuMk1tMBHYOxfAvMPjf6auNpYR8gPabRS6cnK
jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IxQn8drvE7Sb9/3BUJVMQoZBd8cj4z9U1TZMSETxI02fgVKYupGpiEh+LiYhMW3es0I1ffs6McuE
bs7kk2EOtcuTfwPsa4Wu3OOcvxHHeC98yBqddgvOLVJoAEb5RNiGoYqws9c3o1iqC3JCd5sYhWwU
LB7ySr6E8tZPaq82yHw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UC27eDrtTOjJIFtKeyx8ADcLMtfAT4mJdO9dhuxbE9av5VWQotisvd42RGIAgggOPeCblnuSjCFN
MxJcsj0Ym5C2pXnWD8k45HFBUtM1CZYllaNawVznaxCoU9cbI/F/quA9dytfQ6E3nYD7NRUiQeXI
qNLRVlKOd3sHDl4Ml8BUzkUxkau+CLIMqPeItwxQ3t7N51OKF7jRvSKtsM42GZNwvj8StkQqJPGy
f05noKhb6G5GDYG/WWfCFpt3qATC3nfEMt61wsILal4ZZQnpwZN9UWH8SrVihRpVT0MA2gdJUbVX
9rjCb9QcTD0k1vglSUdT7+KsLKo6kCJgvn2v/A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iqIbH529vk+Zbr4o+0lOrJs0Ntf6Ib2MR0xJbZnnBLs3D+25tJbl1QpWtBcK9/Y2IAVXAleMTcjs
fxnkiRTPlx6HRCqglrfz+Vz0phKv5uAumD4xiUGt4yaxyu2wRfEx1rMjicoNaeBeKJNOOrM9a9FV
tnb/+g4KQpZTMCq7fVs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hK4UEFPXCgC7q4kNPisRaOqK53obm3ze8ng6fW4VvFqUMJP5MFWxSphzH/GYPeOeKkZBMmwyzQMN
47e7HNlOFny1piZcPvqRo22Qje54G7VKf8g4sBoKB6RwAZcCt47fKr2fP6BimKj7lZ8jjoAMqczT
V55bVQ34EHRLyi4l9r3Q2wQBGK4UQoKHoiSiCQoY2ZpDaDap/GKR7pdAqwAGcIS59GXn9NtJTQyZ
aLEkmd3ecgBvcYG/Im6ZmTT7EkS3zPDAAyygUTx3LO/s2tO4zMX2OySkUFOMbQZ8wzRO0TJ8aEkg
fSuuEquk4K9hgaUcIr+/UeW6VcPEOH9JB+BOtg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
mBVw3xJ/cTlKJIeI2d/aQKXOIw2ew8K6jdLMNJadPGPriaNdkZPjrGbWctKKO5x+hl11eZzH0d7o
csL3S+obGbzyDKjtH64QK28sn8vRMlrPI6Iq+8LOhyXxE8Q3ZT3kJNrrct/JxsAdGlMtIDzjwcAx
BHe0Fp6FoJZZWEO3JVA98nn0ydJrFn2p+MxU+Wk7Ja9V7xGGNzv2Lockm5AaoL4N7zwrLnqqREVY
2j0Uv/Du4YWX8WAVY9jC7y4oQMvJVTeyaDN8dJIxDXMPm92yK2HB9Oku88kA5e9V1DYmyRldV2Yt
2I29LXI6uhG5uwxbvUdqllm2P5CxKhpyKpipJDPgYra3CRUw/sJdgqJUSR4Bln5Gnf1r2bVVUagT
UJvkhodkcJmRyfaMmHnMzD3QmjdLaLEKmNUF/eHaHFKtlFFr7v1O0kXIqFrhoX0fZ6MAD3g5VP2F
lXa7VBx6isbyhfPTjaN+bGKSe+cwgyBhgVYBK/hOnMbDSxg/SsDn4TIPqV5Hteyhf+nkT0hg2t2u
Fg/Elubtrs9WQmaQFvhs6Zu/9rAAyV9M9e7BhuBT/0v7GDQscHZOhjwr+JmRwD2MdjyoFoC2OhR2
A8Ib/W62GtVw67lkqh2Wps0F5uSPm5smxw+BnbdFANnwkEizeFEgcwOlGuCeHcmS831uHlwCqugx
KoXn3Xcx+5a3piZNdRb3vKkPwhSiKWfRKFF+NdXAPrR5wsngoT/4YnV3vK7KDYIpe01aD/YhzXPr
KxiiaN91nKMDFi13LCAkbeQyshTFzICVwR0n62kRtQ2cmW53s8X5VpMQpdV32LuocCJFxlz1NPDC
YW380BAGENDBmOMiQjynRbib38mUo7RCuIwNIuGN8Tv1InoDR7/4PK6gi6mZKEdtRm0ltR9ZLRec
pgUZW0u12BsGqEK8KP4s1Xhzk+3VGoPkGvMHUMPVSlPT2dFPkxktG+ofYZqdxbn03hx7/h14xWZs
t3aYbtKrzE5sGxxWBJXel0LZwcxFME6WAOJQu5wDuMZYp8CZVioQT+MLm9A0+f5KqgT0OY4a0R0O
K/q03WQIlj4aYUlGXPs9GSh8vt6n1x53nyKmfNxQahIBVaaeShNWt0UFMsDxjjaFpIqSFGB0SWz3
Zp7sWW66O6jUJI81joaoKzszKttpjtwp751gId+O1ewTpSiBV0MqU5+gCCI9a3QP9Rp+/frXF+Xc
BY8OSd7dqKp52qCXYo3wEY07p64hf79FQ8pEHWrjLuwBZmHCqmxF+r/y2gMC+o1wXqETzh57aAlQ
yDuHCLh1h5dR7FC7Bi10wiKH1DnrZ064sAqL5cglr5xIiqOZ5YmtSHVryTqnk2rOmH4ILieSFwd2
l6nUkKgZavqF5gGoXRMgKIGotBOZqA5fiFFewuSQdXCE0pQ7YmIXFXIcA+3I6LFSizSyxC82A12w
h6MY16bLQmJpk8QhtCIEiba/or0qkL4lqxrqC6PP86SHJoRpSAexC1vX7d5EIYDAanISCMZj+/bX
2kOxUr7oigcM3BtoT0WKTW78zaNu+R3yFJcxugKGpUG0xmBnrKVx8DCQ6vCV9FZdchoQ1VRg8vzQ
1ma0Q0vPA81LCMWjMPevBr4jvb6V1EWr75GtrVQjQXxe/UWBT54R6YYEug3MiiGyai6Dw756gmYW
wBbJceyLyksnZ4wCg7Av4UgpCKwc25PpuYYpYRDP8RZ2Cpy4TifEdGzzTY3X1v0LwOeKYlckACu2
QnvUZ+tsFJOQFIRKg8blaBZRhHrqljONq4OiE1arWFiYJmylVGsm9w0VmkV8A1Z6bPe4+e37qVnx
SKiUK8iFxjGQyUWHpR0wlJzrfVPm7IwIA95F40WInyHXIei0KFxtX1dh1E73tI1OLvz/SPnD8VWC
nkziaS1ABbvoOVlFF5lFHFBosAN411sLMBjaJvkgp4ONZVbdq6H7JoadEtDfeK8LeVtxkkep6IKY
VANVecXAxkM/6Bw4ofMa09O7XCKBAnRnA76Uis/hBOdKd0/k8ciQWff1OkIEFF6H7lVS8sQ1+VNh
dbUJlfFYFCLoCr/I7EZpfZ8B+ivk0OgyvTszkEO+vvxVUCmUCbWYhMYdsiYRuyGpjWrg/6GHPvHw
HDARpVPLJ68vGFUFFMnV7PaiGIxEb+lyF00jZkREnhwmyQM9zyeghVZYC3/DjX9UTH37cPGkWlxh
TK/I2Ub/Cyu+5l+QMWtHPOQBVwUEZQMylTlYMYA1FAmc48Z+imO5XgE8ioGb9FzDsBr7wyLgV5dy
vtp+j0q00rNOjeDAvkALEUlhXEVLFhCbmQ37BYVN4sm+PF69tmh9oSxRqyE2SBcK8nONc1XXhMfe
L7kTvEvwLIQfbfheyWsyFGeuv3hJKnXB5f//mpdI/j9HGv1/tR3GAHxPF46X69O4ayd7k3/HT4Tm
E5qKNT0oxDyvhErvlja+gmN7os99D1XrgxWCgoK4BHOPrBWKHwBAldHMgBIh592BOA/7z1keCM8D
ZoSbK4G/Ia93z11IiVC+He3zMl06tdOckPt+dCVqePgnsdy1JtY6ayzouRk42+aPdJI8ym0iaMcZ
z1V5bBfpkSHrgEgdDf/U1fyFCFwMtenlw/2xkU/q/6gHRCN/MN2uXuOO4W2Ad92RJHmg5sAYar6m
QWt27QrZWc3wDTulwOMlJgyxhAhWEl/uClpTj5vMCTW1L19Z+AsRVKM1MVG42YDP63GH9d0vt3H5
XKV1ga4tUtJo3J+vfpGGjVwx16icUwKm/EHcIs+oQQ5oN8MsgbJw0ct8QttJEFACRUqFbA8aR7zd
exBHF6Rgpl1xMQQ0CdoXSd4+3ZILJnwF7hhktor4K2rUpqGIUWqH4P8pQviW6eE+QwzjMmLr/zUF
dbW4FN1F/3xMzwosCbO9gfLoP+mwC031/ytplUgWHi+UNFAtaIJy+Ar5EZu6rRuPeRy7PlCb8kIn
mPiqa7TUZKIZvRLjJvU8sB5uQvnCYm7E39/mkGZELL/P52+B7hZU93LSYAd4qgRnip6iJVXjAira
sQJEOvJzonxFGgwg/0pURnFpL7z+MmRVWKbrDWguf4gMk3tfvARu/UJOPOL8JJji6h07tMLufLAC
FoYE0iHPaxCR2LMyfpOGgR9WtQIvTh/OVH0fbass9yHi4EswtZMuiDBRy8KNP8sotmTSOePPal2u
6RLidgNcPWA52IWLSvjhMhgSdTeiY7c2tvDpmecR2FlFf1xLLh4TmrqEehOy79ry9utenZF9ph5h
lpxijrOXzBfJ8sVOEwu4N19TrWv5APdVTjqltMb7VZRzOiw9Y77babkTdSnWZ35Rmv1MMxg6DI6f
tEPJ6KGdGmeITHdtkP6bLvPPKsxKADFiGQG1zonfjvO/utnNeMpQRFtPXqfq0OZdpZtgsfvsLth+
fSj3O99iQGpYiH5Xm8VV2R20oM34mM+Rn7JHucw2ZaLN9S3rhQlT0b6zLPEvKFZ2PbVdHTpqXxiT
PBN7IcSipjtmp9q6IDcADOo0tRIsC+LCXRCgpXA/PyLrZWKHiFbJEEDaor0ws9avkjSpRtkq8dlx
L9+K5Yj3k0r3JfeXBUpEPxyYvpeky0ceYEZMBZIf5GyMwWcB04G2MdqcLjTYPFut+HCKMs6RqMmp
Rzp9ThsZbvLrFI9FLUbOEWXA3s9dbB237ExK+OyLGraqsRII928YHNppCnW3aj7II4Cjkp2m/Lh4
ZjeL8yGZ6ZX5M9wktRYUyCNAxaWxQThzBdjFWbBOYkmP/eyeuz1XgSIOZfjZLTAk3xkoBpYiDpx/
urzKCE/ZEBYhLmsdDjoOEWeansX2tyNjebFX78aHCUNGMXrGjnnp++ndK3PTTKQHKhSdF1aKYoBx
7Dm6RyRZsGas3iyjLdjYKoDGLmIQ9eOPZLu7CJOIb0HImafawtvB+HlsRY13eBe0f0jhdk8SXBD6
UyH3c4TaBtEA4qEICx5zm7EWJ0xG4oX8bmCxpIolgB1ErpusqxF+jUsBps8fGSxcgse/1lgS0aYP
2RpXRzUa8IBMa29pgYi0tyhDCGYzXXu0EHA6rQ5orKl34E0uysN0fVBZcRg7FO/qbB0GME+upTeJ
sY6HjEblURxMzRaSmqBfypGy4kPVVbLveRW5juO8MM63zDTUWn8veNDK+2o9GYKu1/EH2Ytwg4oX
8GTrnJw6Mq5Udj4XdDpu6r8z6XK6GdHthGUzhxUdzA1ySuELgAosxtJp0OtYcgGUjkoYDc3xQJ0N
vJIkFHV4p5RaU1g/yMk8MDkx/lap2yk1Bx/Oh9sOgLzPq6h4tSoSTRnKUKj3QPHLFzC9+EDX7IAz
8J+GvmTUgtaU1nEI+bJxtwqXhnqHyE2e4PVaVgeAzSHr5nS+RoPlbcGj2V6gw6BlasY6sRuQ+sdP
45YB9vqiKLHADV6I4Bm9mZC2Mco+AonqqWfgVqij/JFJbbZjq543Ok99A8SiMPvKTQny6ha7pd3E
gSlZ2fkAq7HIm1hRmcHlLJpGswqfquN2ISOtg7Q0djUbNuF2JS5lc8uNIYU7kNSFfYZxxcWAUBBB
mRluywu5YT27HchXbOXs6UJB/VcmtOd77pyWIaT42PFYFRb2ox6KvRPV0dhKdL9YjpcGNRpGA4X0
q6aH03XCzEM+lWMEhzm8MaLrCKw/qGH8sX2BViT4FtEI+WP4B43eunWOYB1vjV/jMzRKWIx9z8Hc
xaPxxFcZJK2JT85Bs/zXLKTu4D3BjW72NEZxeYZpvFtcYXXV0v6yrw1BaPtMP1YTvykaHNaGSNxV
vgBmve/N0xgeoOTYrrbrLABMur/rPcXBr1Vrpp7g2oFtpHsPg6BL258G5fm7YzM4Hst2vyY6pAs8
ZneHub+k3FNRItHL7CcHEmjt4sGRZgKU4PRuQ5RjkyB6T1n7JGFCTzELNpQmKKO7677JZO306vjS
HXK6GEw/giZl9obHqoo/kXZ54elkOrQ4HzYnAWXJELcQh0gHk3qFyQf1A3RkY46Lj5W6NTOHszRP
loKBZ+irpbLjKMyTE7uZQLQj7aoV9Tgk6qzp8BavpvoklxBodijrZvc6/ahLxqTBMB49I7FLJfN/
+aL3ex/4ADjvcsA7lxQTpxHHBnmQkr+eEdGj6kgRBjPKSDdi6Xh939l7z+RRJZNFLj+v5mfnPaWL
nksNXNzRPmlHDJxiO4tMEkmWsHffSzqQNaIaXiqM479AN/hLsOtKNK/d7ow+wnY1g/aDfCMt+nfE
H6g+gNxQ1Y9Dy2iSOjTpnVA7vvFfUUCvDrTsLJ5cJNj6m6g4kftcPcSpXEJCTSUccH5BsESulexA
VFr6JDoFk7KZ0t9+VqsDboE54HslTX8gdNEMt5gs+//AA/8zeNONGtkV65v8aFhqUe8C238FsQO9
dMFFZE66De1nkDwtxLnAEVtwpt5loQZBGZpDJWWDeoNFFZ387/Dg3vBrVFoYMnrvff+8T942ICGe
4IV0rRy7VxZHUB07REoMQCQP9Bl3hh5wDtjIpqBEcR5JKml7bOgbRKKIaDtUvT7uyL/0L1XnwYTd
eJisQgJYl2y/Ge+2KQtvpBcLIezzRsdOZmqDB3bHFiYrg8/YBBwtodUx+3jwNN0WWftPkbEt5zGz
pUO/o+layBaLlAHX962DOXwXBh/3R0Z2OGven0PX91WMR0g1Vkm0pdwkz6vpOC/XTb9QbQeL3HNo
wbtFLjYw8HdZCS3zHnRURQpElNyXjKtnUA0y5VhNh4pH4oZ/tB0jifj8wv90t7xaA+1s3kfYOKGY
GHt1wm1ed4nm46UxcCD7IVchvGx9En5jlpPdbcJBincLs8BBA11yxcNzx61XxHHR9cDeOjLuq/OQ
XGvn84/eyb6N4CQ2GpiwLhqhAgTOYAbXVU7wvU7xEb5M+DfSAtzp/0h0RsHlwMh4JvZ3Ib3Kpt0d
osb/Og/yiIcbK+LG6nnXuBfCFK1ynQBBINUHqnD9D5iDglMx4SaqKtzWmWkRs2P5aF8INHkNhw82
FOa/OswYb7XvPrCpP5BfScyf/WY0mB7gdjkgaz//xH9lu6VAzClsy9HX0H8hmMAQwuUufrdfT9LI
gO5C6dyFad4d7SbUl4rZwxM85xvB+wXSglP0FIpXF5nnlWMn8IQA57q56GlZc5he3eQDZNMXeOII
qvL/RfS6k6hnhA778Yg3eBXn53U611D5PXF8qzgQAHOVRyFkqS9CeEaW/vDo5GLhvhOPn3LFtgIv
mosqO6f2EUxwNaRe3imVYshVmXNDASaLBAO/wZVfTLkLy8pPzN7ZYuQ9M9v4uliMnv+zP50auHbT
tx1Pt8pUz3nR5m4sIxNSDKLvJjEoS4GvdecIQeq1Y4W3+zUKa41CU11XWXddBbOo0h5W445tNrc1
KU2u3iMMX7fwO+BGELAOZGGw4FszWN0bLYYpY6SJUvPO2tqz0n06uPcjDbli0Lu9vCpwkCLr//xk
vr1fSK5qp5Rn8M9/+trWz2P6X7nc/euMAGIDktXRRh75OskbjSH9usHeex6fcHrNXV9xwXO+bCuy
V63vyfZ/PBulCQfY0i+9d8o7RWdZCvb3BDBcyUxr/goyuDyWMQ7JuBlWpk+tTmjoYMsHNMOfPn52
GD0C8ixjbhwj1AvsHe4R1X9Ba8KH9tPgNXD7IBitenLQUTUQD5HetuMrEZ3t25nWkqGDtycQTEVN
OJ11im/CHjYpBfG9EPV/IfESrWFlRuas
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DrFNe3y2P5nP7Rx95qyoQtV577JZ6mHlWcJpkpgDuMk1tMBHYOxfAvMPjf6auNpYR8gPabRS6cnK
jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IxQn8drvE7Sb9/3BUJVMQoZBd8cj4z9U1TZMSETxI02fgVKYupGpiEh+LiYhMW3es0I1ffs6McuE
bs7kk2EOtcuTfwPsa4Wu3OOcvxHHeC98yBqddgvOLVJoAEb5RNiGoYqws9c3o1iqC3JCd5sYhWwU
LB7ySr6E8tZPaq82yHw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UC27eDrtTOjJIFtKeyx8ADcLMtfAT4mJdO9dhuxbE9av5VWQotisvd42RGIAgggOPeCblnuSjCFN
MxJcsj0Ym5C2pXnWD8k45HFBUtM1CZYllaNawVznaxCoU9cbI/F/quA9dytfQ6E3nYD7NRUiQeXI
qNLRVlKOd3sHDl4Ml8BUzkUxkau+CLIMqPeItwxQ3t7N51OKF7jRvSKtsM42GZNwvj8StkQqJPGy
f05noKhb6G5GDYG/WWfCFpt3qATC3nfEMt61wsILal4ZZQnpwZN9UWH8SrVihRpVT0MA2gdJUbVX
9rjCb9QcTD0k1vglSUdT7+KsLKo6kCJgvn2v/A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iqIbH529vk+Zbr4o+0lOrJs0Ntf6Ib2MR0xJbZnnBLs3D+25tJbl1QpWtBcK9/Y2IAVXAleMTcjs
fxnkiRTPlx6HRCqglrfz+Vz0phKv5uAumD4xiUGt4yaxyu2wRfEx1rMjicoNaeBeKJNOOrM9a9FV
tnb/+g4KQpZTMCq7fVs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hK4UEFPXCgC7q4kNPisRaOqK53obm3ze8ng6fW4VvFqUMJP5MFWxSphzH/GYPeOeKkZBMmwyzQMN
47e7HNlOFny1piZcPvqRo22Qje54G7VKf8g4sBoKB6RwAZcCt47fKr2fP6BimKj7lZ8jjoAMqczT
V55bVQ34EHRLyi4l9r3Q2wQBGK4UQoKHoiSiCQoY2ZpDaDap/GKR7pdAqwAGcIS59GXn9NtJTQyZ
aLEkmd3ecgBvcYG/Im6ZmTT7EkS3zPDAAyygUTx3LO/s2tO4zMX2OySkUFOMbQZ8wzRO0TJ8aEkg
fSuuEquk4K9hgaUcIr+/UeW6VcPEOH9JB+BOtg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
mBVw3xJ/cTlKJIeI2d/aQKXOIw2ew8K6jdLMNJadPGPriaNdkZPjrGbWctKKO5x+hl11eZzH0d7o
csL3S+obGbzyDKjtH64QK28sn8vRMlrPI6Iq+8LOhyXxE8Q3ZT3kJNrrct/JxsAdGlMtIDzjwcAx
BHe0Fp6FoJZZWEO3JVA98nn0ydJrFn2p+MxU+Wk7Ja9V7xGGNzv2Lockm5AaoL4N7zwrLnqqREVY
2j0Uv/Du4YWX8WAVY9jC7y4oQMvJVTeyaDN8dJIxDXMPm92yK2HB9Oku88kA5e9V1DYmyRldV2Yt
2I29LXI6uhG5uwxbvUdqllm2P5CxKhpyKpipJDPgYra3CRUw/sJdgqJUSR4Bln5Gnf1r2bVVUagT
UJvkhodkcJmRyfaMmHnMzD3QmjdLaLEKmNUF/eHaHFKtlFFr7v1O0kXIqFrhoX0fZ6MAD3g5VP2F
lXa7VBx6isbyhfPTjaN+bGKSe+cwgyBhgVYBK/hOnMbDSxg/SsDn4TIPqV5Hteyhf+nkT0hg2t2u
Fg/Elubtrs9WQmaQFvhs6Zu/9rAAyV9M9e7BhuBT/0v7GDQscHZOhjwr+JmRwD2MdjyoFoC2OhR2
A8Ib/W62GtVw67lkqh2Wps0F5uSPm5smxw+BnbdFANnwkEizeFEgcwOlGuCeHcmS831uHlwCqugx
KoXn3Xcx+5a3piZNdRb3vKkPwhSiKWfRKFF+NdXAPrR5wsngoT/4YnV3vK7KDYIpe01aD/YhzXPr
KxiiaN91nKMDFi13LCAkbeQyshTFzICVwR0n62kRtQ2cmW53s8X5VpMQpdV32LuocCJFxlz1NPDC
YW380BAGENDBmOMiQjynRbib38mUo7RCuIwNIuGN8Tv1InoDR7/4PK6gi6mZKEdtRm0ltR9ZLRec
pgUZW0u12BsGqEK8KP4s1Xhzk+3VGoPkGvMHUMPVSlPT2dFPkxktG+ofYZqdxbn03hx7/h14xWZs
t3aYbtKrzE5sGxxWBJXel0LZwcxFME6WAOJQu5wDuMZYp8CZVioQT+MLm9A0+f5KqgT0OY4a0R0O
K/q03WQIlj4aYUlGXPs9GSh8vt6n1x53nyKmfNxQahIBVaaeShNWt0UFMsDxjjaFpIqSFGB0SWz3
Zp7sWW66O6jUJI81joaoKzszKttpjtwp751gId+O1ewTpSiBV0MqU5+gCCI9a3QP9Rp+/frXF+Xc
BY8OSd7dqKp52qCXYo3wEY07p64hf79FQ8pEHWrjLuwBZmHCqmxF+r/y2gMC+o1wXqETzh57aAlQ
yDuHCLh1h5dR7FC7Bi10wiKH1DnrZ064sAqL5cglr5xIiqOZ5YmtSHVryTqnk2rOmH4ILieSFwd2
l6nUkKgZavqF5gGoXRMgKIGotBOZqA5fiFFewuSQdXCE0pQ7YmIXFXIcA+3I6LFSizSyxC82A12w
h6MY16bLQmJpk8QhtCIEiba/or0qkL4lqxrqC6PP86SHJoRpSAexC1vX7d5EIYDAanISCMZj+/bX
2kOxUr7oigcM3BtoT0WKTW78zaNu+R3yFJcxugKGpUG0xmBnrKVx8DCQ6vCV9FZdchoQ1VRg8vzQ
1ma0Q0vPA81LCMWjMPevBr4jvb6V1EWr75GtrVQjQXxe/UWBT54R6YYEug3MiiGyai6Dw756gmYW
wBbJceyLyksnZ4wCg7Av4UgpCKwc25PpuYYpYRDP8RZ2Cpy4TifEdGzzTY3X1v0LwOeKYlckACu2
QnvUZ+tsFJOQFIRKg8blaBZRhHrqljONq4OiE1arWFiYJmylVGsm9w0VmkV8A1Z6bPe4+e37qVnx
SKiUK8iFxjGQyUWHpR0wlJzrfVPm7IwIA95F40WInyHXIei0KFxtX1dh1E73tI1OLvz/SPnD8VWC
nkziaS1ABbvoOVlFF5lFHFBosAN411sLMBjaJvkgp4ONZVbdq6H7JoadEtDfeK8LeVtxkkep6IKY
VANVecXAxkM/6Bw4ofMa09O7XCKBAnRnA76Uis/hBOdKd0/k8ciQWff1OkIEFF6H7lVS8sQ1+VNh
dbUJlfFYFCLoCr/I7EZpfZ8B+ivk0OgyvTszkEO+vvxVUCmUCbWYhMYdsiYRuyGpjWrg/6GHPvHw
HDARpVPLJ68vGFUFFMnV7PaiGIxEb+lyF00jZkREnhwmyQM9zyeghVZYC3/DjX9UTH37cPGkWlxh
TK/I2Ub/Cyu+5l+QMWtHPOQBVwUEZQMylTlYMYA1FAmc48Z+imO5XgE8ioGb9FzDsBr7wyLgV5dy
vtp+j0q00rNOjeDAvkALEUlhXEVLFhCbmQ37BYVN4sm+PF69tmh9oSxRqyE2SBcK8nONc1XXhMfe
L7kTvEvwLIQfbfheyWsyFGeuv3hJKnXB5f//mpdI/j9HGv1/tR3GAHxPF46X69O4ayd7k3/HT4Tm
E5qKNT0oxDyvhErvlja+gmN7os99D1XrgxWCgoK4BHOPrBWKHwBAldHMgBIh592BOA/7z1keCM8D
ZoSbK4G/Ia93z11IiVC+He3zMl06tdOckPt+dCVqePgnsdy1JtY6ayzouRk42+aPdJI8ym0iaMcZ
z1V5bBfpkSHrgEgdDf/U1fyFCFwMtenlw/2xkU/q/6gHRCN/MN2uXuOO4W2Ad92RJHmg5sAYar6m
QWt27QrZWc3wDTulwOMlJgyxhAhWEl/uClpTj5vMCTW1L19Z+AsRVKM1MVG42YDP63GH9d0vt3H5
XKV1ga4tUtJo3J+vfpGGjVwx16icUwKm/EHcIs+oQQ5oN8MsgbJw0ct8QttJEFACRUqFbA8aR7zd
exBHF6Rgpl1xMQQ0CdoXSd4+3ZILJnwF7hhktor4K2rUpqGIUWqH4P8pQviW6eE+QwzjMmLr/zUF
dbW4FN1F/3xMzwosCbO9gfLoP+mwC031/ytplUgWHi+UNFAtaIJy+Ar5EZu6rRuPeRy7PlCb8kIn
mPiqa7TUZKIZvRLjJvU8sB5uQvnCYm7E39/mkGZELL/P52+B7hZU93LSYAd4qgRnip6iJVXjAira
sQJEOvJzonxFGgwg/0pURnFpL7z+MmRVWKbrDWguf4gMk3tfvARu/UJOPOL8JJji6h07tMLufLAC
FoYE0iHPaxCR2LMyfpOGgR9WtQIvTh/OVH0fbass9yHi4EswtZMuiDBRy8KNP8sotmTSOePPal2u
6RLidgNcPWA52IWLSvjhMhgSdTeiY7c2tvDpmecR2FlFf1xLLh4TmrqEehOy79ry9utenZF9ph5h
lpxijrOXzBfJ8sVOEwu4N19TrWv5APdVTjqltMb7VZRzOiw9Y77babkTdSnWZ35Rmv1MMxg6DI6f
tEPJ6KGdGmeITHdtkP6bLvPPKsxKADFiGQG1zonfjvO/utnNeMpQRFtPXqfq0OZdpZtgsfvsLth+
fSj3O99iQGpYiH5Xm8VV2R20oM34mM+Rn7JHucw2ZaLN9S3rhQlT0b6zLPEvKFZ2PbVdHTpqXxiT
PBN7IcSipjtmp9q6IDcADOo0tRIsC+LCXRCgpXA/PyLrZWKHiFbJEEDaor0ws9avkjSpRtkq8dlx
L9+K5Yj3k0r3JfeXBUpEPxyYvpeky0ceYEZMBZIf5GyMwWcB04G2MdqcLjTYPFut+HCKMs6RqMmp
Rzp9ThsZbvLrFI9FLUbOEWXA3s9dbB237ExK+OyLGraqsRII928YHNppCnW3aj7II4Cjkp2m/Lh4
ZjeL8yGZ6ZX5M9wktRYUyCNAxaWxQThzBdjFWbBOYkmP/eyeuz1XgSIOZfjZLTAk3xkoBpYiDpx/
urzKCE/ZEBYhLmsdDjoOEWeansX2tyNjebFX78aHCUNGMXrGjnnp++ndK3PTTKQHKhSdF1aKYoBx
7Dm6RyRZsGas3iyjLdjYKoDGLmIQ9eOPZLu7CJOIb0HImafawtvB+HlsRY13eBe0f0jhdk8SXBD6
UyH3c4TaBtEA4qEICx5zm7EWJ0xG4oX8bmCxpIolgB1ErpusqxF+jUsBps8fGSxcgse/1lgS0aYP
2RpXRzUa8IBMa29pgYi0tyhDCGYzXXu0EHA6rQ5orKl34E0uysN0fVBZcRg7FO/qbB0GME+upTeJ
sY6HjEblURxMzRaSmqBfypGy4kPVVbLveRW5juO8MM63zDTUWn8veNDK+2o9GYKu1/EH2Ytwg4oX
8GTrnJw6Mq5Udj4XdDpu6r8z6XK6GdHthGUzhxUdzA1ySuELgAosxtJp0OtYcgGUjkoYDc3xQJ0N
vJIkFHV4p5RaU1g/yMk8MDkx/lap2yk1Bx/Oh9sOgLzPq6h4tSoSTRnKUKj3QPHLFzC9+EDX7IAz
8J+GvmTUgtaU1nEI+bJxtwqXhnqHyE2e4PVaVgeAzSHr5nS+RoPlbcGj2V6gw6BlasY6sRuQ+sdP
45YB9vqiKLHADV6I4Bm9mZC2Mco+AonqqWfgVqij/JFJbbZjq543Ok99A8SiMPvKTQny6ha7pd3E
gSlZ2fkAq7HIm1hRmcHlLJpGswqfquN2ISOtg7Q0djUbNuF2JS5lc8uNIYU7kNSFfYZxxcWAUBBB
mRluywu5YT27HchXbOXs6UJB/VcmtOd77pyWIaT42PFYFRb2ox6KvRPV0dhKdL9YjpcGNRpGA4X0
q6aH03XCzEM+lWMEhzm8MaLrCKw/qGH8sX2BViT4FtEI+WP4B43eunWOYB1vjV/jMzRKWIx9z8Hc
xaPxxFcZJK2JT85Bs/zXLKTu4D3BjW72NEZxeYZpvFtcYXXV0v6yrw1BaPtMP1YTvykaHNaGSNxV
vgBmve/N0xgeoOTYrrbrLABMur/rPcXBr1Vrpp7g2oFtpHsPg6BL258G5fm7YzM4Hst2vyY6pAs8
ZneHub+k3FNRItHL7CcHEmjt4sGRZgKU4PRuQ5RjkyB6T1n7JGFCTzELNpQmKKO7677JZO306vjS
HXK6GEw/giZl9obHqoo/kXZ54elkOrQ4HzYnAWXJELcQh0gHk3qFyQf1A3RkY46Lj5W6NTOHszRP
loKBZ+irpbLjKMyTE7uZQLQj7aoV9Tgk6qzp8BavpvoklxBodijrZvc6/ahLxqTBMB49I7FLJfN/
+aL3ex/4ADjvcsA7lxQTpxHHBnmQkr+eEdGj6kgRBjPKSDdi6Xh939l7z+RRJZNFLj+v5mfnPaWL
nksNXNzRPmlHDJxiO4tMEkmWsHffSzqQNaIaXiqM479AN/hLsOtKNK/d7ow+wnY1g/aDfCMt+nfE
H6g+gNxQ1Y9Dy2iSOjTpnVA7vvFfUUCvDrTsLJ5cJNj6m6g4kftcPcSpXEJCTSUccH5BsESulexA
VFr6JDoFk7KZ0t9+VqsDboE54HslTX8gdNEMt5gs+//AA/8zeNONGtkV65v8aFhqUe8C238FsQO9
dMFFZE66De1nkDwtxLnAEVtwpt5loQZBGZpDJWWDeoNFFZ387/Dg3vBrVFoYMnrvff+8T942ICGe
4IV0rRy7VxZHUB07REoMQCQP9Bl3hh5wDtjIpqBEcR5JKml7bOgbRKKIaDtUvT7uyL/0L1XnwYTd
eJisQgJYl2y/Ge+2KQtvpBcLIezzRsdOZmqDB3bHFiYrg8/YBBwtodUx+3jwNN0WWftPkbEt5zGz
pUO/o+layBaLlAHX962DOXwXBh/3R0Z2OGven0PX91WMR0g1Vkm0pdwkz6vpOC/XTb9QbQeL3HNo
wbtFLjYw8HdZCS3zHnRURQpElNyXjKtnUA0y5VhNh4pH4oZ/tB0jifj8wv90t7xaA+1s3kfYOKGY
GHt1wm1ed4nm46UxcCD7IVchvGx9En5jlpPdbcJBincLs8BBA11yxcNzx61XxHHR9cDeOjLuq/OQ
XGvn84/eyb6N4CQ2GpiwLhqhAgTOYAbXVU7wvU7xEb5M+DfSAtzp/0h0RsHlwMh4JvZ3Ib3Kpt0d
osb/Og/yiIcbK+LG6nnXuBfCFK1ynQBBINUHqnD9D5iDglMx4SaqKtzWmWkRs2P5aF8INHkNhw82
FOa/OswYb7XvPrCpP5BfScyf/WY0mB7gdjkgaz//xH9lu6VAzClsy9HX0H8hmMAQwuUufrdfT9LI
gO5C6dyFad4d7SbUl4rZwxM85xvB+wXSglP0FIpXF5nnlWMn8IQA57q56GlZc5he3eQDZNMXeOII
qvL/RfS6k6hnhA778Yg3eBXn53U611D5PXF8qzgQAHOVRyFkqS9CeEaW/vDo5GLhvhOPn3LFtgIv
mosqO6f2EUxwNaRe3imVYshVmXNDASaLBAO/wZVfTLkLy8pPzN7ZYuQ9M9v4uliMnv+zP50auHbT
tx1Pt8pUz3nR5m4sIxNSDKLvJjEoS4GvdecIQeq1Y4W3+zUKa41CU11XWXddBbOo0h5W445tNrc1
KU2u3iMMX7fwO+BGELAOZGGw4FszWN0bLYYpY6SJUvPO2tqz0n06uPcjDbli0Lu9vCpwkCLr//xk
vr1fSK5qp5Rn8M9/+trWz2P6X7nc/euMAGIDktXRRh75OskbjSH9usHeex6fcHrNXV9xwXO+bCuy
V63vyfZ/PBulCQfY0i+9d8o7RWdZCvb3BDBcyUxr/goyuDyWMQ7JuBlWpk+tTmjoYMsHNMOfPn52
GD0C8ixjbhwj1AvsHe4R1X9Ba8KH9tPgNXD7IBitenLQUTUQD5HetuMrEZ3t25nWkqGDtycQTEVN
OJ11im/CHjYpBfG9EPV/IfESrWFlRuas
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DrFNe3y2P5nP7Rx95qyoQtV577JZ6mHlWcJpkpgDuMk1tMBHYOxfAvMPjf6auNpYR8gPabRS6cnK
jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IxQn8drvE7Sb9/3BUJVMQoZBd8cj4z9U1TZMSETxI02fgVKYupGpiEh+LiYhMW3es0I1ffs6McuE
bs7kk2EOtcuTfwPsa4Wu3OOcvxHHeC98yBqddgvOLVJoAEb5RNiGoYqws9c3o1iqC3JCd5sYhWwU
LB7ySr6E8tZPaq82yHw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UC27eDrtTOjJIFtKeyx8ADcLMtfAT4mJdO9dhuxbE9av5VWQotisvd42RGIAgggOPeCblnuSjCFN
MxJcsj0Ym5C2pXnWD8k45HFBUtM1CZYllaNawVznaxCoU9cbI/F/quA9dytfQ6E3nYD7NRUiQeXI
qNLRVlKOd3sHDl4Ml8BUzkUxkau+CLIMqPeItwxQ3t7N51OKF7jRvSKtsM42GZNwvj8StkQqJPGy
f05noKhb6G5GDYG/WWfCFpt3qATC3nfEMt61wsILal4ZZQnpwZN9UWH8SrVihRpVT0MA2gdJUbVX
9rjCb9QcTD0k1vglSUdT7+KsLKo6kCJgvn2v/A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iqIbH529vk+Zbr4o+0lOrJs0Ntf6Ib2MR0xJbZnnBLs3D+25tJbl1QpWtBcK9/Y2IAVXAleMTcjs
fxnkiRTPlx6HRCqglrfz+Vz0phKv5uAumD4xiUGt4yaxyu2wRfEx1rMjicoNaeBeKJNOOrM9a9FV
tnb/+g4KQpZTMCq7fVs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hK4UEFPXCgC7q4kNPisRaOqK53obm3ze8ng6fW4VvFqUMJP5MFWxSphzH/GYPeOeKkZBMmwyzQMN
47e7HNlOFny1piZcPvqRo22Qje54G7VKf8g4sBoKB6RwAZcCt47fKr2fP6BimKj7lZ8jjoAMqczT
V55bVQ34EHRLyi4l9r3Q2wQBGK4UQoKHoiSiCQoY2ZpDaDap/GKR7pdAqwAGcIS59GXn9NtJTQyZ
aLEkmd3ecgBvcYG/Im6ZmTT7EkS3zPDAAyygUTx3LO/s2tO4zMX2OySkUFOMbQZ8wzRO0TJ8aEkg
fSuuEquk4K9hgaUcIr+/UeW6VcPEOH9JB+BOtg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
mBVw3xJ/cTlKJIeI2d/aQKXOIw2ew8K6jdLMNJadPGPriaNdkZPjrGbWctKKO5x+hl11eZzH0d7o
csL3S+obGbzyDKjtH64QK28sn8vRMlrPI6Iq+8LOhyXxE8Q3ZT3kJNrrct/JxsAdGlMtIDzjwcAx
BHe0Fp6FoJZZWEO3JVA98nn0ydJrFn2p+MxU+Wk7Ja9V7xGGNzv2Lockm5AaoL4N7zwrLnqqREVY
2j0Uv/Du4YWX8WAVY9jC7y4oQMvJVTeyaDN8dJIxDXMPm92yK2HB9Oku88kA5e9V1DYmyRldV2Yt
2I29LXI6uhG5uwxbvUdqllm2P5CxKhpyKpipJDPgYra3CRUw/sJdgqJUSR4Bln5Gnf1r2bVVUagT
UJvkhodkcJmRyfaMmHnMzD3QmjdLaLEKmNUF/eHaHFKtlFFr7v1O0kXIqFrhoX0fZ6MAD3g5VP2F
lXa7VBx6isbyhfPTjaN+bGKSe+cwgyBhgVYBK/hOnMbDSxg/SsDn4TIPqV5Hteyhf+nkT0hg2t2u
Fg/Elubtrs9WQmaQFvhs6Zu/9rAAyV9M9e7BhuBT/0v7GDQscHZOhjwr+JmRwD2MdjyoFoC2OhR2
A8Ib/W62GtVw67lkqh2Wps0F5uSPm5smxw+BnbdFANnwkEizeFEgcwOlGuCeHcmS831uHlwCqugx
KoXn3Xcx+5a3piZNdRb3vKkPwhSiKWfRKFF+NdXAPrR5wsngoT/4YnV3vK7KDYIpe01aD/YhzXPr
KxiiaN91nKMDFi13LCAkbeQyshTFzICVwR0n62kRtQ2cmW53s8X5VpMQpdV32LuocCJFxlz1NPDC
YW380BAGENDBmOMiQjynRbib38mUo7RCuIwNIuGN8Tv1InoDR7/4PK6gi6mZKEdtRm0ltR9ZLRec
pgUZW0u12BsGqEK8KP4s1Xhzk+3VGoPkGvMHUMPVSlPT2dFPkxktG+ofYZqdxbn03hx7/h14xWZs
t3aYbtKrzE5sGxxWBJXel0LZwcxFME6WAOJQu5wDuMZYp8CZVioQT+MLm9A0+f5KqgT0OY4a0R0O
K/q03WQIlj4aYUlGXPs9GSh8vt6n1x53nyKmfNxQahIBVaaeShNWt0UFMsDxjjaFpIqSFGB0SWz3
Zp7sWW66O6jUJI81joaoKzszKttpjtwp751gId+O1ewTpSiBV0MqU5+gCCI9a3QP9Rp+/frXF+Xc
BY8OSd7dqKp52qCXYo3wEY07p64hf79FQ8pEHWrjLuwBZmHCqmxF+r/y2gMC+o1wXqETzh57aAlQ
yDuHCLh1h5dR7FC7Bi10wiKH1DnrZ064sAqL5cglr5xIiqOZ5YmtSHVryTqnk2rOmH4ILieSFwd2
l6nUkKgZavqF5gGoXRMgKIGotBOZqA5fiFFewuSQdXCE0pQ7YmIXFXIcA+3I6LFSizSyxC82A12w
h6MY16bLQmJpk8QhtCIEiba/or0qkL4lqxrqC6PP86SHJoRpSAexC1vX7d5EIYDAanISCMZj+/bX
2kOxUr7oigcM3BtoT0WKTW78zaNu+R3yFJcxugKGpUG0xmBnrKVx8DCQ6vCV9FZdchoQ1VRg8vzQ
1ma0Q0vPA81LCMWjMPevBr4jvb6V1EWr75GtrVQjQXxe/UWBT54R6YYEug3MiiGyai6Dw756gmYW
wBbJceyLyksnZ4wCg7Av4UgpCKwc25PpuYYpYRDP8RZ2Cpy4TifEdGzzTY3X1v0LwOeKYlckACu2
QnvUZ+tsFJOQFIRKg8blaBZRhHrqljONq4OiE1arWFiYJmylVGsm9w0VmkV8A1Z6bPe4+e37qVnx
SKiUK8iFxjGQyUWHpR0wlJzrfVPm7IwIA95F40WInyHXIei0KFxtX1dh1E73tI1OLvz/SPnD8VWC
nkziaS1ABbvoOVlFF5lFHFBosAN411sLMBjaJvkgp4ONZVbdq6H7JoadEtDfeK8LeVtxkkep6IKY
VANVecXAxkM/6Bw4ofMa09O7XCKBAnRnA76Uis/hBOdKd0/k8ciQWff1OkIEFF6H7lVS8sQ1+VNh
dbUJlfFYFCLoCr/I7EZpfZ8B+ivk0OgyvTszkEO+vvxVUCmUCbWYhMYdsiYRuyGpjWrg/6GHPvHw
HDARpVPLJ68vGFUFFMnV7PaiGIxEb+lyF00jZkREnhwmyQM9zyeghVZYC3/DjX9UTH37cPGkWlxh
TK/I2Ub/Cyu+5l+QMWtHPOQBVwUEZQMylTlYMYA1FAmc48Z+imO5XgE8ioGb9FzDsBr7wyLgV5dy
vtp+j0q00rNOjeDAvkALEUlhXEVLFhCbmQ37BYVN4sm+PF69tmh9oSxRqyE2SBcK8nONc1XXhMfe
L7kTvEvwLIQfbfheyWsyFGeuv3hJKnXB5f//mpdI/j9HGv1/tR3GAHxPF46X69O4ayd7k3/HT4Tm
E5qKNT0oxDyvhErvlja+gmN7os99D1XrgxWCgoK4BHOPrBWKHwBAldHMgBIh592BOA/7z1keCM8D
ZoSbK4G/Ia93z11IiVC+He3zMl06tdOckPt+dCVqePgnsdy1JtY6ayzouRk42+aPdJI8ym0iaMcZ
z1V5bBfpkSHrgEgdDf/U1fyFCFwMtenlw/2xkU/q/6gHRCN/MN2uXuOO4W2Ad92RJHmg5sAYar6m
QWt27QrZWc3wDTulwOMlJgyxhAhWEl/uClpTj5vMCTW1L19Z+AsRVKM1MVG42YDP63GH9d0vt3H5
XKV1ga4tUtJo3J+vfpGGjVwx16icUwKm/EHcIs+oQQ5oN8MsgbJw0ct8QttJEFACRUqFbA8aR7zd
exBHF6Rgpl1xMQQ0CdoXSd4+3ZILJnwF7hhktor4K2rUpqGIUWqH4P8pQviW6eE+QwzjMmLr/zUF
dbW4FN1F/3xMzwosCbO9gfLoP+mwC031/ytplUgWHi+UNFAtaIJy+Ar5EZu6rRuPeRy7PlCb8kIn
mPiqa7TUZKIZvRLjJvU8sB5uQvnCYm7E39/mkGZELL/P52+B7hZU93LSYAd4qgRnip6iJVXjAira
sQJEOvJzonxFGgwg/0pURnFpL7z+MmRVWKbrDWguf4gMk3tfvARu/UJOPOL8JJji6h07tMLufLAC
FoYE0iHPaxCR2LMyfpOGgR9WtQIvTh/OVH0fbass9yHi4EswtZMuiDBRy8KNP8sotmTSOePPal2u
6RLidgNcPWA52IWLSvjhMhgSdTeiY7c2tvDpmecR2FlFf1xLLh4TmrqEehOy79ry9utenZF9ph5h
lpxijrOXzBfJ8sVOEwu4N19TrWv5APdVTjqltMb7VZRzOiw9Y77babkTdSnWZ35Rmv1MMxg6DI6f
tEPJ6KGdGmeITHdtkP6bLvPPKsxKADFiGQG1zonfjvO/utnNeMpQRFtPXqfq0OZdpZtgsfvsLth+
fSj3O99iQGpYiH5Xm8VV2R20oM34mM+Rn7JHucw2ZaLN9S3rhQlT0b6zLPEvKFZ2PbVdHTpqXxiT
PBN7IcSipjtmp9q6IDcADOo0tRIsC+LCXRCgpXA/PyLrZWKHiFbJEEDaor0ws9avkjSpRtkq8dlx
L9+K5Yj3k0r3JfeXBUpEPxyYvpeky0ceYEZMBZIf5GyMwWcB04G2MdqcLjTYPFut+HCKMs6RqMmp
Rzp9ThsZbvLrFI9FLUbOEWXA3s9dbB237ExK+OyLGraqsRII928YHNppCnW3aj7II4Cjkp2m/Lh4
ZjeL8yGZ6ZX5M9wktRYUyCNAxaWxQThzBdjFWbBOYkmP/eyeuz1XgSIOZfjZLTAk3xkoBpYiDpx/
urzKCE/ZEBYhLmsdDjoOEWeansX2tyNjebFX78aHCUNGMXrGjnnp++ndK3PTTKQHKhSdF1aKYoBx
7Dm6RyRZsGas3iyjLdjYKoDGLmIQ9eOPZLu7CJOIb0HImafawtvB+HlsRY13eBe0f0jhdk8SXBD6
UyH3c4TaBtEA4qEICx5zm7EWJ0xG4oX8bmCxpIolgB1ErpusqxF+jUsBps8fGSxcgse/1lgS0aYP
2RpXRzUa8IBMa29pgYi0tyhDCGYzXXu0EHA6rQ5orKl34E0uysN0fVBZcRg7FO/qbB0GME+upTeJ
sY6HjEblURxMzRaSmqBfypGy4kPVVbLveRW5juO8MM63zDTUWn8veNDK+2o9GYKu1/EH2Ytwg4oX
8GTrnJw6Mq5Udj4XdDpu6r8z6XK6GdHthGUzhxUdzA1ySuELgAosxtJp0OtYcgGUjkoYDc3xQJ0N
vJIkFHV4p5RaU1g/yMk8MDkx/lap2yk1Bx/Oh9sOgLzPq6h4tSoSTRnKUKj3QPHLFzC9+EDX7IAz
8J+GvmTUgtaU1nEI+bJxtwqXhnqHyE2e4PVaVgeAzSHr5nS+RoPlbcGj2V6gw6BlasY6sRuQ+sdP
45YB9vqiKLHADV6I4Bm9mZC2Mco+AonqqWfgVqij/JFJbbZjq543Ok99A8SiMPvKTQny6ha7pd3E
gSlZ2fkAq7HIm1hRmcHlLJpGswqfquN2ISOtg7Q0djUbNuF2JS5lc8uNIYU7kNSFfYZxxcWAUBBB
mRluywu5YT27HchXbOXs6UJB/VcmtOd77pyWIaT42PFYFRb2ox6KvRPV0dhKdL9YjpcGNRpGA4X0
q6aH03XCzEM+lWMEhzm8MaLrCKw/qGH8sX2BViT4FtEI+WP4B43eunWOYB1vjV/jMzRKWIx9z8Hc
xaPxxFcZJK2JT85Bs/zXLKTu4D3BjW72NEZxeYZpvFtcYXXV0v6yrw1BaPtMP1YTvykaHNaGSNxV
vgBmve/N0xgeoOTYrrbrLABMur/rPcXBr1Vrpp7g2oFtpHsPg6BL258G5fm7YzM4Hst2vyY6pAs8
ZneHub+k3FNRItHL7CcHEmjt4sGRZgKU4PRuQ5RjkyB6T1n7JGFCTzELNpQmKKO7677JZO306vjS
HXK6GEw/giZl9obHqoo/kXZ54elkOrQ4HzYnAWXJELcQh0gHk3qFyQf1A3RkY46Lj5W6NTOHszRP
loKBZ+irpbLjKMyTE7uZQLQj7aoV9Tgk6qzp8BavpvoklxBodijrZvc6/ahLxqTBMB49I7FLJfN/
+aL3ex/4ADjvcsA7lxQTpxHHBnmQkr+eEdGj6kgRBjPKSDdi6Xh939l7z+RRJZNFLj+v5mfnPaWL
nksNXNzRPmlHDJxiO4tMEkmWsHffSzqQNaIaXiqM479AN/hLsOtKNK/d7ow+wnY1g/aDfCMt+nfE
H6g+gNxQ1Y9Dy2iSOjTpnVA7vvFfUUCvDrTsLJ5cJNj6m6g4kftcPcSpXEJCTSUccH5BsESulexA
VFr6JDoFk7KZ0t9+VqsDboE54HslTX8gdNEMt5gs+//AA/8zeNONGtkV65v8aFhqUe8C238FsQO9
dMFFZE66De1nkDwtxLnAEVtwpt5loQZBGZpDJWWDeoNFFZ387/Dg3vBrVFoYMnrvff+8T942ICGe
4IV0rRy7VxZHUB07REoMQCQP9Bl3hh5wDtjIpqBEcR5JKml7bOgbRKKIaDtUvT7uyL/0L1XnwYTd
eJisQgJYl2y/Ge+2KQtvpBcLIezzRsdOZmqDB3bHFiYrg8/YBBwtodUx+3jwNN0WWftPkbEt5zGz
pUO/o+layBaLlAHX962DOXwXBh/3R0Z2OGven0PX91WMR0g1Vkm0pdwkz6vpOC/XTb9QbQeL3HNo
wbtFLjYw8HdZCS3zHnRURQpElNyXjKtnUA0y5VhNh4pH4oZ/tB0jifj8wv90t7xaA+1s3kfYOKGY
GHt1wm1ed4nm46UxcCD7IVchvGx9En5jlpPdbcJBincLs8BBA11yxcNzx61XxHHR9cDeOjLuq/OQ
XGvn84/eyb6N4CQ2GpiwLhqhAgTOYAbXVU7wvU7xEb5M+DfSAtzp/0h0RsHlwMh4JvZ3Ib3Kpt0d
osb/Og/yiIcbK+LG6nnXuBfCFK1ynQBBINUHqnD9D5iDglMx4SaqKtzWmWkRs2P5aF8INHkNhw82
FOa/OswYb7XvPrCpP5BfScyf/WY0mB7gdjkgaz//xH9lu6VAzClsy9HX0H8hmMAQwuUufrdfT9LI
gO5C6dyFad4d7SbUl4rZwxM85xvB+wXSglP0FIpXF5nnlWMn8IQA57q56GlZc5he3eQDZNMXeOII
qvL/RfS6k6hnhA778Yg3eBXn53U611D5PXF8qzgQAHOVRyFkqS9CeEaW/vDo5GLhvhOPn3LFtgIv
mosqO6f2EUxwNaRe3imVYshVmXNDASaLBAO/wZVfTLkLy8pPzN7ZYuQ9M9v4uliMnv+zP50auHbT
tx1Pt8pUz3nR5m4sIxNSDKLvJjEoS4GvdecIQeq1Y4W3+zUKa41CU11XWXddBbOo0h5W445tNrc1
KU2u3iMMX7fwO+BGELAOZGGw4FszWN0bLYYpY6SJUvPO2tqz0n06uPcjDbli0Lu9vCpwkCLr//xk
vr1fSK5qp5Rn8M9/+trWz2P6X7nc/euMAGIDktXRRh75OskbjSH9usHeex6fcHrNXV9xwXO+bCuy
V63vyfZ/PBulCQfY0i+9d8o7RWdZCvb3BDBcyUxr/goyuDyWMQ7JuBlWpk+tTmjoYMsHNMOfPn52
GD0C8ixjbhwj1AvsHe4R1X9Ba8KH9tPgNXD7IBitenLQUTUQD5HetuMrEZ3t25nWkqGDtycQTEVN
OJ11im/CHjYpBfG9EPV/IfESrWFlRuas
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DrFNe3y2P5nP7Rx95qyoQtV577JZ6mHlWcJpkpgDuMk1tMBHYOxfAvMPjf6auNpYR8gPabRS6cnK
jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IxQn8drvE7Sb9/3BUJVMQoZBd8cj4z9U1TZMSETxI02fgVKYupGpiEh+LiYhMW3es0I1ffs6McuE
bs7kk2EOtcuTfwPsa4Wu3OOcvxHHeC98yBqddgvOLVJoAEb5RNiGoYqws9c3o1iqC3JCd5sYhWwU
LB7ySr6E8tZPaq82yHw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UC27eDrtTOjJIFtKeyx8ADcLMtfAT4mJdO9dhuxbE9av5VWQotisvd42RGIAgggOPeCblnuSjCFN
MxJcsj0Ym5C2pXnWD8k45HFBUtM1CZYllaNawVznaxCoU9cbI/F/quA9dytfQ6E3nYD7NRUiQeXI
qNLRVlKOd3sHDl4Ml8BUzkUxkau+CLIMqPeItwxQ3t7N51OKF7jRvSKtsM42GZNwvj8StkQqJPGy
f05noKhb6G5GDYG/WWfCFpt3qATC3nfEMt61wsILal4ZZQnpwZN9UWH8SrVihRpVT0MA2gdJUbVX
9rjCb9QcTD0k1vglSUdT7+KsLKo6kCJgvn2v/A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iqIbH529vk+Zbr4o+0lOrJs0Ntf6Ib2MR0xJbZnnBLs3D+25tJbl1QpWtBcK9/Y2IAVXAleMTcjs
fxnkiRTPlx6HRCqglrfz+Vz0phKv5uAumD4xiUGt4yaxyu2wRfEx1rMjicoNaeBeKJNOOrM9a9FV
tnb/+g4KQpZTMCq7fVs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hK4UEFPXCgC7q4kNPisRaOqK53obm3ze8ng6fW4VvFqUMJP5MFWxSphzH/GYPeOeKkZBMmwyzQMN
47e7HNlOFny1piZcPvqRo22Qje54G7VKf8g4sBoKB6RwAZcCt47fKr2fP6BimKj7lZ8jjoAMqczT
V55bVQ34EHRLyi4l9r3Q2wQBGK4UQoKHoiSiCQoY2ZpDaDap/GKR7pdAqwAGcIS59GXn9NtJTQyZ
aLEkmd3ecgBvcYG/Im6ZmTT7EkS3zPDAAyygUTx3LO/s2tO4zMX2OySkUFOMbQZ8wzRO0TJ8aEkg
fSuuEquk4K9hgaUcIr+/UeW6VcPEOH9JB+BOtg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
mBVw3xJ/cTlKJIeI2d/aQKXOIw2ew8K6jdLMNJadPGPriaNdkZPjrGbWctKKO5x+hl11eZzH0d7o
csL3S+obGbzyDKjtH64QK28sn8vRMlrPI6Iq+8LOhyXxE8Q3ZT3kJNrrct/JxsAdGlMtIDzjwcAx
BHe0Fp6FoJZZWEO3JVA98nn0ydJrFn2p+MxU+Wk7Ja9V7xGGNzv2Lockm5AaoL4N7zwrLnqqREVY
2j0Uv/Du4YWX8WAVY9jC7y4oQMvJVTeyaDN8dJIxDXMPm92yK2HB9Oku88kA5e9V1DYmyRldV2Yt
2I29LXI6uhG5uwxbvUdqllm2P5CxKhpyKpipJDPgYra3CRUw/sJdgqJUSR4Bln5Gnf1r2bVVUagT
UJvkhodkcJmRyfaMmHnMzD3QmjdLaLEKmNUF/eHaHFKtlFFr7v1O0kXIqFrhoX0fZ6MAD3g5VP2F
lXa7VBx6isbyhfPTjaN+bGKSe+cwgyBhgVYBK/hOnMbDSxg/SsDn4TIPqV5Hteyhf+nkT0hg2t2u
Fg/Elubtrs9WQmaQFvhs6Zu/9rAAyV9M9e7BhuBT/0v7GDQscHZOhjwr+JmRwD2MdjyoFoC2OhR2
A8Ib/W62GtVw67lkqh2Wps0F5uSPm5smxw+BnbdFANnwkEizeFEgcwOlGuCeHcmS831uHlwCqugx
KoXn3Xcx+5a3piZNdRb3vKkPwhSiKWfRKFF+NdXAPrR5wsngoT/4YnV3vK7KDYIpe01aD/YhzXPr
KxiiaN91nKMDFi13LCAkbeQyshTFzICVwR0n62kRtQ2cmW53s8X5VpMQpdV32LuocCJFxlz1NPDC
YW380BAGENDBmOMiQjynRbib38mUo7RCuIwNIuGN8Tv1InoDR7/4PK6gi6mZKEdtRm0ltR9ZLRec
pgUZW0u12BsGqEK8KP4s1Xhzk+3VGoPkGvMHUMPVSlPT2dFPkxktG+ofYZqdxbn03hx7/h14xWZs
t3aYbtKrzE5sGxxWBJXel0LZwcxFME6WAOJQu5wDuMZYp8CZVioQT+MLm9A0+f5KqgT0OY4a0R0O
K/q03WQIlj4aYUlGXPs9GSh8vt6n1x53nyKmfNxQahIBVaaeShNWt0UFMsDxjjaFpIqSFGB0SWz3
Zp7sWW66O6jUJI81joaoKzszKttpjtwp751gId+O1ewTpSiBV0MqU5+gCCI9a3QP9Rp+/frXF+Xc
BY8OSd7dqKp52qCXYo3wEY07p64hf79FQ8pEHWrjLuwBZmHCqmxF+r/y2gMC+o1wXqETzh57aAlQ
yDuHCLh1h5dR7FC7Bi10wiKH1DnrZ064sAqL5cglr5xIiqOZ5YmtSHVryTqnk2rOmH4ILieSFwd2
l6nUkKgZavqF5gGoXRMgKIGotBOZqA5fiFFewuSQdXCE0pQ7YmIXFXIcA+3I6LFSizSyxC82A12w
h6MY16bLQmJpk8QhtCIEiba/or0qkL4lqxrqC6PP86SHJoRpSAexC1vX7d5EIYDAanISCMZj+/bX
2kOxUr7oigcM3BtoT0WKTW78zaNu+R3yFJcxugKGpUG0xmBnrKVx8DCQ6vCV9FZdchoQ1VRg8vzQ
1ma0Q0vPA81LCMWjMPevBr4jvb6V1EWr75GtrVQjQXxe/UWBT54R6YYEug3MiiGyai6Dw756gmYW
wBbJceyLyksnZ4wCg7Av4UgpCKwc25PpuYYpYRDP8RZ2Cpy4TifEdGzzTY3X1v0LwOeKYlckACu2
QnvUZ+tsFJOQFIRKg8blaBZRhHrqljONq4OiE1arWFiYJmylVGsm9w0VmkV8A1Z6bPe4+e37qVnx
SKiUK8iFxjGQyUWHpR0wlJzrfVPm7IwIA95F40WInyHXIei0KFxtX1dh1E73tI1OLvz/SPnD8VWC
nkziaS1ABbvoOVlFF5lFHFBosAN411sLMBjaJvkgp4ONZVbdq6H7JoadEtDfeK8LeVtxkkep6IKY
VANVecXAxkM/6Bw4ofMa09O7XCKBAnRnA76Uis/hBOdKd0/k8ciQWff1OkIEFF6H7lVS8sQ1+VNh
dbUJlfFYFCLoCr/I7EZpfZ8B+ivk0OgyvTszkEO+vvxVUCmUCbWYhMYdsiYRuyGpjWrg/6GHPvHw
HDARpVPLJ68vGFUFFMnV7PaiGIxEb+lyF00jZkREnhwmyQM9zyeghVZYC3/DjX9UTH37cPGkWlxh
TK/I2Ub/Cyu+5l+QMWtHPOQBVwUEZQMylTlYMYA1FAmc48Z+imO5XgE8ioGb9FzDsBr7wyLgV5dy
vtp+j0q00rNOjeDAvkALEUlhXEVLFhCbmQ37BYVN4sm+PF69tmh9oSxRqyE2SBcK8nONc1XXhMfe
L7kTvEvwLIQfbfheyWsyFGeuv3hJKnXB5f//mpdI/j9HGv1/tR3GAHxPF46X69O4ayd7k3/HT4Tm
E5qKNT0oxDyvhErvlja+gmN7os99D1XrgxWCgoK4BHOPrBWKHwBAldHMgBIh592BOA/7z1keCM8D
ZoSbK4G/Ia93z11IiVC+He3zMl06tdOckPt+dCVqePgnsdy1JtY6ayzouRk42+aPdJI8ym0iaMcZ
z1V5bBfpkSHrgEgdDf/U1fyFCFwMtenlw/2xkU/q/6gHRCN/MN2uXuOO4W2Ad92RJHmg5sAYar6m
QWt27QrZWc3wDTulwOMlJgyxhAhWEl/uClpTj5vMCTW1L19Z+AsRVKM1MVG42YDP63GH9d0vt3H5
XKV1ga4tUtJo3J+vfpGGjVwx16icUwKm/EHcIs+oQQ5oN8MsgbJw0ct8QttJEFACRUqFbA8aR7zd
exBHF6Rgpl1xMQQ0CdoXSd4+3ZILJnwF7hhktor4K2rUpqGIUWqH4P8pQviW6eE+QwzjMmLr/zUF
dbW4FN1F/3xMzwosCbO9gfLoP+mwC031/ytplUgWHi+UNFAtaIJy+Ar5EZu6rRuPeRy7PlCb8kIn
mPiqa7TUZKIZvRLjJvU8sB5uQvnCYm7E39/mkGZELL/P52+B7hZU93LSYAd4qgRnip6iJVXjAira
sQJEOvJzonxFGgwg/0pURnFpL7z+MmRVWKbrDWguf4gMk3tfvARu/UJOPOL8JJji6h07tMLufLAC
FoYE0iHPaxCR2LMyfpOGgR9WtQIvTh/OVH0fbass9yHi4EswtZMuiDBRy8KNP8sotmTSOePPal2u
6RLidgNcPWA52IWLSvjhMhgSdTeiY7c2tvDpmecR2FlFf1xLLh4TmrqEehOy79ry9utenZF9ph5h
lpxijrOXzBfJ8sVOEwu4N19TrWv5APdVTjqltMb7VZRzOiw9Y77babkTdSnWZ35Rmv1MMxg6DI6f
tEPJ6KGdGmeITHdtkP6bLvPPKsxKADFiGQG1zonfjvO/utnNeMpQRFtPXqfq0OZdpZtgsfvsLth+
fSj3O99iQGpYiH5Xm8VV2R20oM34mM+Rn7JHucw2ZaLN9S3rhQlT0b6zLPEvKFZ2PbVdHTpqXxiT
PBN7IcSipjtmp9q6IDcADOo0tRIsC+LCXRCgpXA/PyLrZWKHiFbJEEDaor0ws9avkjSpRtkq8dlx
L9+K5Yj3k0r3JfeXBUpEPxyYvpeky0ceYEZMBZIf5GyMwWcB04G2MdqcLjTYPFut+HCKMs6RqMmp
Rzp9ThsZbvLrFI9FLUbOEWXA3s9dbB237ExK+OyLGraqsRII928YHNppCnW3aj7II4Cjkp2m/Lh4
ZjeL8yGZ6ZX5M9wktRYUyCNAxaWxQThzBdjFWbBOYkmP/eyeuz1XgSIOZfjZLTAk3xkoBpYiDpx/
urzKCE/ZEBYhLmsdDjoOEWeansX2tyNjebFX78aHCUNGMXrGjnnp++ndK3PTTKQHKhSdF1aKYoBx
7Dm6RyRZsGas3iyjLdjYKoDGLmIQ9eOPZLu7CJOIb0HImafawtvB+HlsRY13eBe0f0jhdk8SXBD6
UyH3c4TaBtEA4qEICx5zm7EWJ0xG4oX8bmCxpIolgB1ErpusqxF+jUsBps8fGSxcgse/1lgS0aYP
2RpXRzUa8IBMa29pgYi0tyhDCGYzXXu0EHA6rQ5orKl34E0uysN0fVBZcRg7FO/qbB0GME+upTeJ
sY6HjEblURxMzRaSmqBfypGy4kPVVbLveRW5juO8MM63zDTUWn8veNDK+2o9GYKu1/EH2Ytwg4oX
8GTrnJw6Mq5Udj4XdDpu6r8z6XK6GdHthGUzhxUdzA1ySuELgAosxtJp0OtYcgGUjkoYDc3xQJ0N
vJIkFHV4p5RaU1g/yMk8MDkx/lap2yk1Bx/Oh9sOgLzPq6h4tSoSTRnKUKj3QPHLFzC9+EDX7IAz
8J+GvmTUgtaU1nEI+bJxtwqXhnqHyE2e4PVaVgeAzSHr5nS+RoPlbcGj2V6gw6BlasY6sRuQ+sdP
45YB9vqiKLHADV6I4Bm9mZC2Mco+AonqqWfgVqij/JFJbbZjq543Ok99A8SiMPvKTQny6ha7pd3E
gSlZ2fkAq7HIm1hRmcHlLJpGswqfquN2ISOtg7Q0djUbNuF2JS5lc8uNIYU7kNSFfYZxxcWAUBBB
mRluywu5YT27HchXbOXs6UJB/VcmtOd77pyWIaT42PFYFRb2ox6KvRPV0dhKdL9YjpcGNRpGA4X0
q6aH03XCzEM+lWMEhzm8MaLrCKw/qGH8sX2BViT4FtEI+WP4B43eunWOYB1vjV/jMzRKWIx9z8Hc
xaPxxFcZJK2JT85Bs/zXLKTu4D3BjW72NEZxeYZpvFtcYXXV0v6yrw1BaPtMP1YTvykaHNaGSNxV
vgBmve/N0xgeoOTYrrbrLABMur/rPcXBr1Vrpp7g2oFtpHsPg6BL258G5fm7YzM4Hst2vyY6pAs8
ZneHub+k3FNRItHL7CcHEmjt4sGRZgKU4PRuQ5RjkyB6T1n7JGFCTzELNpQmKKO7677JZO306vjS
HXK6GEw/giZl9obHqoo/kXZ54elkOrQ4HzYnAWXJELcQh0gHk3qFyQf1A3RkY46Lj5W6NTOHszRP
loKBZ+irpbLjKMyTE7uZQLQj7aoV9Tgk6qzp8BavpvoklxBodijrZvc6/ahLxqTBMB49I7FLJfN/
+aL3ex/4ADjvcsA7lxQTpxHHBnmQkr+eEdGj6kgRBjPKSDdi6Xh939l7z+RRJZNFLj+v5mfnPaWL
nksNXNzRPmlHDJxiO4tMEkmWsHffSzqQNaIaXiqM479AN/hLsOtKNK/d7ow+wnY1g/aDfCMt+nfE
H6g+gNxQ1Y9Dy2iSOjTpnVA7vvFfUUCvDrTsLJ5cJNj6m6g4kftcPcSpXEJCTSUccH5BsESulexA
VFr6JDoFk7KZ0t9+VqsDboE54HslTX8gdNEMt5gs+//AA/8zeNONGtkV65v8aFhqUe8C238FsQO9
dMFFZE66De1nkDwtxLnAEVtwpt5loQZBGZpDJWWDeoNFFZ387/Dg3vBrVFoYMnrvff+8T942ICGe
4IV0rRy7VxZHUB07REoMQCQP9Bl3hh5wDtjIpqBEcR5JKml7bOgbRKKIaDtUvT7uyL/0L1XnwYTd
eJisQgJYl2y/Ge+2KQtvpBcLIezzRsdOZmqDB3bHFiYrg8/YBBwtodUx+3jwNN0WWftPkbEt5zGz
pUO/o+layBaLlAHX962DOXwXBh/3R0Z2OGven0PX91WMR0g1Vkm0pdwkz6vpOC/XTb9QbQeL3HNo
wbtFLjYw8HdZCS3zHnRURQpElNyXjKtnUA0y5VhNh4pH4oZ/tB0jifj8wv90t7xaA+1s3kfYOKGY
GHt1wm1ed4nm46UxcCD7IVchvGx9En5jlpPdbcJBincLs8BBA11yxcNzx61XxHHR9cDeOjLuq/OQ
XGvn84/eyb6N4CQ2GpiwLhqhAgTOYAbXVU7wvU7xEb5M+DfSAtzp/0h0RsHlwMh4JvZ3Ib3Kpt0d
osb/Og/yiIcbK+LG6nnXuBfCFK1ynQBBINUHqnD9D5iDglMx4SaqKtzWmWkRs2P5aF8INHkNhw82
FOa/OswYb7XvPrCpP5BfScyf/WY0mB7gdjkgaz//xH9lu6VAzClsy9HX0H8hmMAQwuUufrdfT9LI
gO5C6dyFad4d7SbUl4rZwxM85xvB+wXSglP0FIpXF5nnlWMn8IQA57q56GlZc5he3eQDZNMXeOII
qvL/RfS6k6hnhA778Yg3eBXn53U611D5PXF8qzgQAHOVRyFkqS9CeEaW/vDo5GLhvhOPn3LFtgIv
mosqO6f2EUxwNaRe3imVYshVmXNDASaLBAO/wZVfTLkLy8pPzN7ZYuQ9M9v4uliMnv+zP50auHbT
tx1Pt8pUz3nR5m4sIxNSDKLvJjEoS4GvdecIQeq1Y4W3+zUKa41CU11XWXddBbOo0h5W445tNrc1
KU2u3iMMX7fwO+BGELAOZGGw4FszWN0bLYYpY6SJUvPO2tqz0n06uPcjDbli0Lu9vCpwkCLr//xk
vr1fSK5qp5Rn8M9/+trWz2P6X7nc/euMAGIDktXRRh75OskbjSH9usHeex6fcHrNXV9xwXO+bCuy
V63vyfZ/PBulCQfY0i+9d8o7RWdZCvb3BDBcyUxr/goyuDyWMQ7JuBlWpk+tTmjoYMsHNMOfPn52
GD0C8ixjbhwj1AvsHe4R1X9Ba8KH9tPgNXD7IBitenLQUTUQD5HetuMrEZ3t25nWkqGDtycQTEVN
OJ11im/CHjYpBfG9EPV/IfESrWFlRuas
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00643ent IS
END c03s04b01x00p01n01i00643ent;
ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C1 : boolean := true;
constant C2 : boolean_vector_range := (others => C1);
type boolean_vector_range_file is file of boolean_vector_range;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_range_file open write_mode is "iofile.46";
BEGIN
for i in 1 to 100 loop
write(filein, C2);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00643arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00643ent IS
END c03s04b01x00p01n01i00643ent;
ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C1 : boolean := true;
constant C2 : boolean_vector_range := (others => C1);
type boolean_vector_range_file is file of boolean_vector_range;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_range_file open write_mode is "iofile.46";
BEGIN
for i in 1 to 100 loop
write(filein, C2);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00643arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00643ent IS
END c03s04b01x00p01n01i00643ent;
ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C1 : boolean := true;
constant C2 : boolean_vector_range := (others => C1);
type boolean_vector_range_file is file of boolean_vector_range;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_range_file open write_mode is "iofile.46";
BEGIN
for i in 1 to 100 loop
write(filein, C2);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00643arch;
|
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_2_4;
USE fifo_generator_v13_2_4.fifo_generator_v13_2_4;
ENTITY fifo_1k_x_8_dual_port IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END fifo_1k_x_8_dual_port;
ARCHITECTURE fifo_1k_x_8_dual_port_arch OF fifo_1k_x_8_dual_port IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_2_4 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_2_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "fifo_generator_v13_2_4,Vivado 2019.1.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_1k_x_8_dual_port_arch : ARCHITECTURE IS "fifo_1k_x_8_dual_port,fifo_generator_v13_2_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "fifo_1k_x_8_dual_port,fifo_generator_v13_2_4,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C" &
"_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_F" &
"ULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C" &
"_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RU" &
"SER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTAT" &
"ION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WAC" &
"H=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_" &
"RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_" &
"WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRE" &
"SH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
BEGIN
U0 : fifo_generator_v13_2_4
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_1k_x_8_dual_port_arch;
|
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_2_4;
USE fifo_generator_v13_2_4.fifo_generator_v13_2_4;
ENTITY fifo_1k_x_8_dual_port IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END fifo_1k_x_8_dual_port;
ARCHITECTURE fifo_1k_x_8_dual_port_arch OF fifo_1k_x_8_dual_port IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_2_4 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_2_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "fifo_generator_v13_2_4,Vivado 2019.1.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_1k_x_8_dual_port_arch : ARCHITECTURE IS "fifo_1k_x_8_dual_port,fifo_generator_v13_2_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_1k_x_8_dual_port_arch: ARCHITECTURE IS "fifo_1k_x_8_dual_port,fifo_generator_v13_2_4,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C" &
"_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_F" &
"ULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C" &
"_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RU" &
"SER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTAT" &
"ION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WAC" &
"H=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_" &
"RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_" &
"WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRE" &
"SH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
BEGIN
U0 : fifo_generator_v13_2_4
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_1k_x_8_dual_port_arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.1 2005/10/13 09:09:44 wig Exp $
-- $Date: 2005/10/13 09:09:44 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.1 2005/10/13 09:09:44 wig
-- Added intermediate CONN sheet split
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_ba
-- No Generated Generics
-- Generated Generics for Entity ent_ba
-- End of Generated Generics for Entity ent_ba
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_rl-c.vhd,v 1.1 2005-04-10 18:07:26 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_rl_behav_c0 of tb_rl is
for behav
for dut_b : chip
use configuration work.chip_full_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
for rl_b : ram_loader
use configuration work.ram_loader_rtl_c0;
end for;
end for;
end tb_rl_behav_c0;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
-- generic (
-- #parameters_user_design_top_component#
-- RST_ACT_LOW : integer
-- );
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v2_3_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
MASK_SIZE : integer := 8;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
CMDS_GAP_DELAY : std_logic_vector(5 downto 0) := "000000";
SEL_VICTIM_LINE : integer := 8;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
EYE_TEST : string;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
tg_only_rst : in std_logic;
manual_clear_error : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH))-1 downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v2_3_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector((64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK))-1 downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
-- generic map (
-- #parameters_mapping_user_design_top_instance#
-- RST_ACT_LOW => RST_ACT_LOW
-- )
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
device_temp_i => device_temp_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst(0) or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v2_3_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error(0),
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8)-1 downto 0),
memc_wr_data => app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic(0),
vio_modify_enable => vio_modify_enable(0),
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen(0),
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w(0),
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => tg_wr_data_counts,
rd_data_counts => tg_rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done(0)
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable(0) <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen(0) <= '0';
vio_pause_traffic(0) <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error(0) <= '0';
po_win_tg_rst <= '0';
vio_tg_rst(0) <= '0';
wdt_en_w(0) <= '1';
dbg_sel_pi_incdec(0) <= '0';
dbg_sel_po_incdec(0) <= '0';
dbg_pi_f_inc(0) <= '0';
dbg_pi_f_dec(0) <= '0';
dbg_po_f_inc(0) <= '0';
dbg_po_f_dec(0) <= '0';
dbg_po_f_stg23_sel(0) <= '0';
end architecture arch_example_top;
|
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux0.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux0 IS
PORT
(
clock : IN STD_LOGIC ;
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_mux0;
ARCHITECTURE SYN OF lpm_mux0 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire9 <= data0x(15 DOWNTO 0);
sub_wire8 <= data1x(15 DOWNTO 0);
sub_wire7 <= data2x(15 DOWNTO 0);
sub_wire6 <= data3x(15 DOWNTO 0);
sub_wire5 <= data4x(15 DOWNTO 0);
sub_wire4 <= data5x(15 DOWNTO 0);
sub_wire3 <= data6x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data7x(15 DOWNTO 0);
sub_wire2(7, 0) <= sub_wire1(0);
sub_wire2(7, 1) <= sub_wire1(1);
sub_wire2(7, 2) <= sub_wire1(2);
sub_wire2(7, 3) <= sub_wire1(3);
sub_wire2(7, 4) <= sub_wire1(4);
sub_wire2(7, 5) <= sub_wire1(5);
sub_wire2(7, 6) <= sub_wire1(6);
sub_wire2(7, 7) <= sub_wire1(7);
sub_wire2(7, 8) <= sub_wire1(8);
sub_wire2(7, 9) <= sub_wire1(9);
sub_wire2(7, 10) <= sub_wire1(10);
sub_wire2(7, 11) <= sub_wire1(11);
sub_wire2(7, 12) <= sub_wire1(12);
sub_wire2(7, 13) <= sub_wire1(13);
sub_wire2(7, 14) <= sub_wire1(14);
sub_wire2(7, 15) <= sub_wire1(15);
sub_wire2(6, 0) <= sub_wire3(0);
sub_wire2(6, 1) <= sub_wire3(1);
sub_wire2(6, 2) <= sub_wire3(2);
sub_wire2(6, 3) <= sub_wire3(3);
sub_wire2(6, 4) <= sub_wire3(4);
sub_wire2(6, 5) <= sub_wire3(5);
sub_wire2(6, 6) <= sub_wire3(6);
sub_wire2(6, 7) <= sub_wire3(7);
sub_wire2(6, 8) <= sub_wire3(8);
sub_wire2(6, 9) <= sub_wire3(9);
sub_wire2(6, 10) <= sub_wire3(10);
sub_wire2(6, 11) <= sub_wire3(11);
sub_wire2(6, 12) <= sub_wire3(12);
sub_wire2(6, 13) <= sub_wire3(13);
sub_wire2(6, 14) <= sub_wire3(14);
sub_wire2(6, 15) <= sub_wire3(15);
sub_wire2(5, 0) <= sub_wire4(0);
sub_wire2(5, 1) <= sub_wire4(1);
sub_wire2(5, 2) <= sub_wire4(2);
sub_wire2(5, 3) <= sub_wire4(3);
sub_wire2(5, 4) <= sub_wire4(4);
sub_wire2(5, 5) <= sub_wire4(5);
sub_wire2(5, 6) <= sub_wire4(6);
sub_wire2(5, 7) <= sub_wire4(7);
sub_wire2(5, 8) <= sub_wire4(8);
sub_wire2(5, 9) <= sub_wire4(9);
sub_wire2(5, 10) <= sub_wire4(10);
sub_wire2(5, 11) <= sub_wire4(11);
sub_wire2(5, 12) <= sub_wire4(12);
sub_wire2(5, 13) <= sub_wire4(13);
sub_wire2(5, 14) <= sub_wire4(14);
sub_wire2(5, 15) <= sub_wire4(15);
sub_wire2(4, 0) <= sub_wire5(0);
sub_wire2(4, 1) <= sub_wire5(1);
sub_wire2(4, 2) <= sub_wire5(2);
sub_wire2(4, 3) <= sub_wire5(3);
sub_wire2(4, 4) <= sub_wire5(4);
sub_wire2(4, 5) <= sub_wire5(5);
sub_wire2(4, 6) <= sub_wire5(6);
sub_wire2(4, 7) <= sub_wire5(7);
sub_wire2(4, 8) <= sub_wire5(8);
sub_wire2(4, 9) <= sub_wire5(9);
sub_wire2(4, 10) <= sub_wire5(10);
sub_wire2(4, 11) <= sub_wire5(11);
sub_wire2(4, 12) <= sub_wire5(12);
sub_wire2(4, 13) <= sub_wire5(13);
sub_wire2(4, 14) <= sub_wire5(14);
sub_wire2(4, 15) <= sub_wire5(15);
sub_wire2(3, 0) <= sub_wire6(0);
sub_wire2(3, 1) <= sub_wire6(1);
sub_wire2(3, 2) <= sub_wire6(2);
sub_wire2(3, 3) <= sub_wire6(3);
sub_wire2(3, 4) <= sub_wire6(4);
sub_wire2(3, 5) <= sub_wire6(5);
sub_wire2(3, 6) <= sub_wire6(6);
sub_wire2(3, 7) <= sub_wire6(7);
sub_wire2(3, 8) <= sub_wire6(8);
sub_wire2(3, 9) <= sub_wire6(9);
sub_wire2(3, 10) <= sub_wire6(10);
sub_wire2(3, 11) <= sub_wire6(11);
sub_wire2(3, 12) <= sub_wire6(12);
sub_wire2(3, 13) <= sub_wire6(13);
sub_wire2(3, 14) <= sub_wire6(14);
sub_wire2(3, 15) <= sub_wire6(15);
sub_wire2(2, 0) <= sub_wire7(0);
sub_wire2(2, 1) <= sub_wire7(1);
sub_wire2(2, 2) <= sub_wire7(2);
sub_wire2(2, 3) <= sub_wire7(3);
sub_wire2(2, 4) <= sub_wire7(4);
sub_wire2(2, 5) <= sub_wire7(5);
sub_wire2(2, 6) <= sub_wire7(6);
sub_wire2(2, 7) <= sub_wire7(7);
sub_wire2(2, 8) <= sub_wire7(8);
sub_wire2(2, 9) <= sub_wire7(9);
sub_wire2(2, 10) <= sub_wire7(10);
sub_wire2(2, 11) <= sub_wire7(11);
sub_wire2(2, 12) <= sub_wire7(12);
sub_wire2(2, 13) <= sub_wire7(13);
sub_wire2(2, 14) <= sub_wire7(14);
sub_wire2(2, 15) <= sub_wire7(15);
sub_wire2(1, 0) <= sub_wire8(0);
sub_wire2(1, 1) <= sub_wire8(1);
sub_wire2(1, 2) <= sub_wire8(2);
sub_wire2(1, 3) <= sub_wire8(3);
sub_wire2(1, 4) <= sub_wire8(4);
sub_wire2(1, 5) <= sub_wire8(5);
sub_wire2(1, 6) <= sub_wire8(6);
sub_wire2(1, 7) <= sub_wire8(7);
sub_wire2(1, 8) <= sub_wire8(8);
sub_wire2(1, 9) <= sub_wire8(9);
sub_wire2(1, 10) <= sub_wire8(10);
sub_wire2(1, 11) <= sub_wire8(11);
sub_wire2(1, 12) <= sub_wire8(12);
sub_wire2(1, 13) <= sub_wire8(13);
sub_wire2(1, 14) <= sub_wire8(14);
sub_wire2(1, 15) <= sub_wire8(15);
sub_wire2(0, 0) <= sub_wire9(0);
sub_wire2(0, 1) <= sub_wire9(1);
sub_wire2(0, 2) <= sub_wire9(2);
sub_wire2(0, 3) <= sub_wire9(3);
sub_wire2(0, 4) <= sub_wire9(4);
sub_wire2(0, 5) <= sub_wire9(5);
sub_wire2(0, 6) <= sub_wire9(6);
sub_wire2(0, 7) <= sub_wire9(7);
sub_wire2(0, 8) <= sub_wire9(8);
sub_wire2(0, 9) <= sub_wire9(9);
sub_wire2(0, 10) <= sub_wire9(10);
sub_wire2(0, 11) <= sub_wire9(11);
sub_wire2(0, 12) <= sub_wire9(12);
sub_wire2(0, 13) <= sub_wire9(13);
sub_wire2(0, 14) <= sub_wire9(14);
sub_wire2(0, 15) <= sub_wire9(15);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 1,
lpm_size => 8,
lpm_type => "LPM_MUX",
lpm_width => 16,
lpm_widths => 3
)
PORT MAP (
clock => clock,
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux0.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux0 IS
PORT
(
clock : IN STD_LOGIC ;
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_mux0;
ARCHITECTURE SYN OF lpm_mux0 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire9 <= data0x(15 DOWNTO 0);
sub_wire8 <= data1x(15 DOWNTO 0);
sub_wire7 <= data2x(15 DOWNTO 0);
sub_wire6 <= data3x(15 DOWNTO 0);
sub_wire5 <= data4x(15 DOWNTO 0);
sub_wire4 <= data5x(15 DOWNTO 0);
sub_wire3 <= data6x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data7x(15 DOWNTO 0);
sub_wire2(7, 0) <= sub_wire1(0);
sub_wire2(7, 1) <= sub_wire1(1);
sub_wire2(7, 2) <= sub_wire1(2);
sub_wire2(7, 3) <= sub_wire1(3);
sub_wire2(7, 4) <= sub_wire1(4);
sub_wire2(7, 5) <= sub_wire1(5);
sub_wire2(7, 6) <= sub_wire1(6);
sub_wire2(7, 7) <= sub_wire1(7);
sub_wire2(7, 8) <= sub_wire1(8);
sub_wire2(7, 9) <= sub_wire1(9);
sub_wire2(7, 10) <= sub_wire1(10);
sub_wire2(7, 11) <= sub_wire1(11);
sub_wire2(7, 12) <= sub_wire1(12);
sub_wire2(7, 13) <= sub_wire1(13);
sub_wire2(7, 14) <= sub_wire1(14);
sub_wire2(7, 15) <= sub_wire1(15);
sub_wire2(6, 0) <= sub_wire3(0);
sub_wire2(6, 1) <= sub_wire3(1);
sub_wire2(6, 2) <= sub_wire3(2);
sub_wire2(6, 3) <= sub_wire3(3);
sub_wire2(6, 4) <= sub_wire3(4);
sub_wire2(6, 5) <= sub_wire3(5);
sub_wire2(6, 6) <= sub_wire3(6);
sub_wire2(6, 7) <= sub_wire3(7);
sub_wire2(6, 8) <= sub_wire3(8);
sub_wire2(6, 9) <= sub_wire3(9);
sub_wire2(6, 10) <= sub_wire3(10);
sub_wire2(6, 11) <= sub_wire3(11);
sub_wire2(6, 12) <= sub_wire3(12);
sub_wire2(6, 13) <= sub_wire3(13);
sub_wire2(6, 14) <= sub_wire3(14);
sub_wire2(6, 15) <= sub_wire3(15);
sub_wire2(5, 0) <= sub_wire4(0);
sub_wire2(5, 1) <= sub_wire4(1);
sub_wire2(5, 2) <= sub_wire4(2);
sub_wire2(5, 3) <= sub_wire4(3);
sub_wire2(5, 4) <= sub_wire4(4);
sub_wire2(5, 5) <= sub_wire4(5);
sub_wire2(5, 6) <= sub_wire4(6);
sub_wire2(5, 7) <= sub_wire4(7);
sub_wire2(5, 8) <= sub_wire4(8);
sub_wire2(5, 9) <= sub_wire4(9);
sub_wire2(5, 10) <= sub_wire4(10);
sub_wire2(5, 11) <= sub_wire4(11);
sub_wire2(5, 12) <= sub_wire4(12);
sub_wire2(5, 13) <= sub_wire4(13);
sub_wire2(5, 14) <= sub_wire4(14);
sub_wire2(5, 15) <= sub_wire4(15);
sub_wire2(4, 0) <= sub_wire5(0);
sub_wire2(4, 1) <= sub_wire5(1);
sub_wire2(4, 2) <= sub_wire5(2);
sub_wire2(4, 3) <= sub_wire5(3);
sub_wire2(4, 4) <= sub_wire5(4);
sub_wire2(4, 5) <= sub_wire5(5);
sub_wire2(4, 6) <= sub_wire5(6);
sub_wire2(4, 7) <= sub_wire5(7);
sub_wire2(4, 8) <= sub_wire5(8);
sub_wire2(4, 9) <= sub_wire5(9);
sub_wire2(4, 10) <= sub_wire5(10);
sub_wire2(4, 11) <= sub_wire5(11);
sub_wire2(4, 12) <= sub_wire5(12);
sub_wire2(4, 13) <= sub_wire5(13);
sub_wire2(4, 14) <= sub_wire5(14);
sub_wire2(4, 15) <= sub_wire5(15);
sub_wire2(3, 0) <= sub_wire6(0);
sub_wire2(3, 1) <= sub_wire6(1);
sub_wire2(3, 2) <= sub_wire6(2);
sub_wire2(3, 3) <= sub_wire6(3);
sub_wire2(3, 4) <= sub_wire6(4);
sub_wire2(3, 5) <= sub_wire6(5);
sub_wire2(3, 6) <= sub_wire6(6);
sub_wire2(3, 7) <= sub_wire6(7);
sub_wire2(3, 8) <= sub_wire6(8);
sub_wire2(3, 9) <= sub_wire6(9);
sub_wire2(3, 10) <= sub_wire6(10);
sub_wire2(3, 11) <= sub_wire6(11);
sub_wire2(3, 12) <= sub_wire6(12);
sub_wire2(3, 13) <= sub_wire6(13);
sub_wire2(3, 14) <= sub_wire6(14);
sub_wire2(3, 15) <= sub_wire6(15);
sub_wire2(2, 0) <= sub_wire7(0);
sub_wire2(2, 1) <= sub_wire7(1);
sub_wire2(2, 2) <= sub_wire7(2);
sub_wire2(2, 3) <= sub_wire7(3);
sub_wire2(2, 4) <= sub_wire7(4);
sub_wire2(2, 5) <= sub_wire7(5);
sub_wire2(2, 6) <= sub_wire7(6);
sub_wire2(2, 7) <= sub_wire7(7);
sub_wire2(2, 8) <= sub_wire7(8);
sub_wire2(2, 9) <= sub_wire7(9);
sub_wire2(2, 10) <= sub_wire7(10);
sub_wire2(2, 11) <= sub_wire7(11);
sub_wire2(2, 12) <= sub_wire7(12);
sub_wire2(2, 13) <= sub_wire7(13);
sub_wire2(2, 14) <= sub_wire7(14);
sub_wire2(2, 15) <= sub_wire7(15);
sub_wire2(1, 0) <= sub_wire8(0);
sub_wire2(1, 1) <= sub_wire8(1);
sub_wire2(1, 2) <= sub_wire8(2);
sub_wire2(1, 3) <= sub_wire8(3);
sub_wire2(1, 4) <= sub_wire8(4);
sub_wire2(1, 5) <= sub_wire8(5);
sub_wire2(1, 6) <= sub_wire8(6);
sub_wire2(1, 7) <= sub_wire8(7);
sub_wire2(1, 8) <= sub_wire8(8);
sub_wire2(1, 9) <= sub_wire8(9);
sub_wire2(1, 10) <= sub_wire8(10);
sub_wire2(1, 11) <= sub_wire8(11);
sub_wire2(1, 12) <= sub_wire8(12);
sub_wire2(1, 13) <= sub_wire8(13);
sub_wire2(1, 14) <= sub_wire8(14);
sub_wire2(1, 15) <= sub_wire8(15);
sub_wire2(0, 0) <= sub_wire9(0);
sub_wire2(0, 1) <= sub_wire9(1);
sub_wire2(0, 2) <= sub_wire9(2);
sub_wire2(0, 3) <= sub_wire9(3);
sub_wire2(0, 4) <= sub_wire9(4);
sub_wire2(0, 5) <= sub_wire9(5);
sub_wire2(0, 6) <= sub_wire9(6);
sub_wire2(0, 7) <= sub_wire9(7);
sub_wire2(0, 8) <= sub_wire9(8);
sub_wire2(0, 9) <= sub_wire9(9);
sub_wire2(0, 10) <= sub_wire9(10);
sub_wire2(0, 11) <= sub_wire9(11);
sub_wire2(0, 12) <= sub_wire9(12);
sub_wire2(0, 13) <= sub_wire9(13);
sub_wire2(0, 14) <= sub_wire9(14);
sub_wire2(0, 15) <= sub_wire9(15);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 1,
lpm_size => 8,
lpm_type => "LPM_MUX",
lpm_width => 16,
lpm_widths => 3
)
PORT MAP (
clock => clock,
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Processor is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end Processor;
architecture Behavioral of Processor is
COMPONENT ALU
PORT(
CRS1 : IN std_logic_vector(31 downto 0);
CRS2mux : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT PSR_modifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
RESULT : IN std_logic_vector(31 downto 0);
RS1 : IN std_logic_vector(31 downto 0);
RS2 : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT mux01
PORT(
crs2 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
seuin : IN std_logic_vector(31 downto 0);
muxout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RegisterFile
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DtoWrite : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
crs1 : OUT std_logic_vector(31 downto 0);
crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT psr
PORT(
clk : IN std_logic;
rst : IN std_logic;
nzvc : IN std_logic_vector(3 downto 0);
ncwp : IN std_logic_vector(4 downto 0);
cwp : OUT std_logic_vector(4 downto 0);
c : OUT std_logic
);
END COMPONENT;
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
seuout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ControlUnit
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT windowsManager
PORT(
RS1 : IN std_logic_vector(4 downto 0);
RS2 : IN std_logic_vector(4 downto 0);
RD : IN std_logic_vector(4 downto 0);
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic_vector(4 downto 0);
NCWP : OUT std_logic_vector(4 downto 0);
NRS1 : OUT std_logic_vector(5 downto 0);
NRS2 : OUT std_logic_vector(5 downto 0);
NRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT InstruccionMemory
PORT(
address : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sumador32bits
PORT(
datainA : IN std_logic_vector(31 downto 0);
datainB : IN std_logic_vector(31 downto 0);
Salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT regis
PORT(
clk : IN std_logic;
rst : IN std_logic;
datain : IN std_logic_vector(31 downto 0);
dataout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--señales auxiliares
signal aux_npcsumpc: std_logic_vector(31 downto 0);
signal aux_sumnpc: std_logic_vector(31 downto 0);
signal aux_pcim: std_logic_vector(31 downto 0);
signal aux_outIM: std_logic_vector(31 downto 0);
signal aux_cwp: std_logic_vector(4 downto 0);
signal aux_ncwp: std_logic_vector(4 downto 0);
signal aux_nrs1: std_logic_vector(5 downto 0);
signal aux_nrs2: std_logic_vector(5 downto 0);
signal aux_nrd: std_logic_vector(5 downto 0);
signal aux_aluop: std_logic_vector(5 downto 0);
signal aux_seumux: std_logic_vector(31 downto 0);
signal aux_C: std_logic;
signal aux_nzvc: std_logic_vector(3 downto 0);
signal aux_aluresult: std_logic_vector(31 downto 0); --alu
signal aux_crs1: std_logic_vector(31 downto 0); --alu
signal aux_crs2mux: std_logic_vector(31 downto 0); -- registe al mux
signal aux_crs2: std_logic_vector(31 downto 0); -- mux a la alu y al psrmodifier
begin
Inst_ALU: ALU PORT MAP(
CRS1 => aux_crs1 ,
CRS2mux => aux_crs2,
ALUOP => aux_aluop,
C => aux_C,
ALURESULT => aux_aluresult
);
Inst_PSR_modifier: PSR_modifier PORT MAP(
ALUOP => aux_aluop,
RESULT => aux_aluresult,
RS1 => aux_crs1,
RS2 => aux_crs2,
NZVC => aux_nzvc
);
multiplexorCRS2: mux01 PORT MAP(
crs2 =>aux_crs2mux ,
i => aux_outIM(13),
seuin => aux_seumux,
muxout => aux_crs2
);
Inst_RegisterFile: RegisterFile PORT MAP(
rs1 =>aux_nrs1 ,
rs2 => aux_nrs2,
rd => aux_nrd ,
DtoWrite => aux_aluresult,
rst => rst,
crs1 => aux_crs1,
crs2 => aux_crs2mux
);
I_psr: psr PORT MAP(
clk => clk,
rst => rst,
nzvc => aux_nzvc,
ncwp => aux_ncwp,
cwp => aux_cwp,
c => aux_C
);
ExtDeSig: SEU PORT MAP(
imm13 => aux_outIM(12 downto 0),
seuout => aux_seumux
);
UC: ControlUnit PORT MAP(
OP => aux_outIM(31 downto 30) ,
OP3 => aux_outIM(24 downto 19) ,
ALUOP => aux_aluop
);
WinManager: windowsManager PORT MAP(
RS1 => aux_outIM(18 downto 14) ,
RS2 => aux_outIM(4 downto 0) ,
RD => aux_outIM(29 downto 25) ,
OP => aux_outIM(31 downto 30) ,
OP3 => aux_outIM(24 downto 19) ,
CWP => aux_cwp,
NCWP => aux_ncwp,
NRS1 => aux_nrs1,
NRS2 => aux_nrs2,
NRD => aux_nrd
);
IM: InstruccionMemory PORT MAP(
address => aux_pcim,
rst => RST,
instruction => aux_outIM
);
SUMADOR_PC: sumador32bits PORT MAP(
datainA => "00000000000000000000000000000001",
datainB => aux_npcsumpc,
Salida => aux_sumnpc
);
PC: regis PORT MAP(
clk => CLK,
rst => RST,
datain => aux_npcsumpc ,
dataout => aux_pcim
);
NPC: regis PORT MAP(
clk => CLK,
rst => RST,
datain => aux_sumnpc,
dataout => aux_npcsumpc
);
ALURESULT <= aux_aluresult;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Created top level for descriptor update queue management
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
ch2_updt_curdesc_wren : out std_logic ; --
ch2_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 1 generate
begin
--*****************************************************************************
--** CHANNEL 1 - DESCRIPTOR QUEUE **
--*****************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH1_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH1_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_NO_QUEUE;
end generate GEN_CH1_UPDATE_Q_IF;
-- Channel 1 NOT included therefore tie ch1 outputs off
GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
begin
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '1';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
m_axis_ch1_updt_tdata <= (others => '0');
m_axis_ch1_updt_tlast <= '0';
m_axis_ch1_updt_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
begin
--*************************************************************************
--** CHANNEL 2 - DESCRIPTOR QUEUE **
--*************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
---------------------------------------------------------------------------
I_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_FAMILY => C_FAMILY
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_QUEUE;
--*****************************************************************************
--** CHANNEL 2 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
I_NO_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_NO_QUEUE;
end generate GEN_CH2_UPDATE_Q_IF;
-- Channel 2 NOT included therefore tie ch2 outputs off
GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
begin
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '1';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
m_axis_ch2_updt_tdata <= (others => '0');
m_axis_ch2_updt_tlast <= '0';
m_axis_ch2_updt_tvalid <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
TO_DATAMVR_MUX : process(ch1_updt_active,
ch2_updt_active,
m_axis_ch1_updt_tdata,
m_axis_ch1_updt_tlast,
m_axis_ch1_updt_tvalid,
m_axis_ch2_updt_tdata,
m_axis_ch2_updt_tlast,
m_axis_ch2_updt_tvalid)
begin
if(ch1_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
elsif(ch2_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
else
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
end if;
end process TO_DATAMVR_MUX;
m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
-- Sample rate is 250MHz / 6400 = 39062.5Hz.
-- sample rate * 256 is 250MHz / 25 = 10M.
-- sample rate * 128 is 5M.
-- Let's extend samples to 32 bits.
-- Bck = 250MHz / 100 = lrck * 64, sck = 250Mhz / 50 = lrck * 128
-- The incoming sample rate is one every 400 cycles, each channel has one
-- every 1600 cycles.
entity audio is
-- So lrck is bit/(2*lcrk_divider).
generic (bits_per_sample : integer);
port (left, right : in signed(bits_per_sample-1 downto 0);
channel : in unsigned2;
last : in std_logic;
scki, lrck, data, bck : out std_logic;
clk : in std_logic);
end audio;
architecture audio of audio is
signal divider : unsigned (12 downto 0);
signal sample_hold : signed(63 downto 0);
signal shift_reg : signed(63 downto 0);
signal sample_shift, sample_load, shift_load : boolean;
signal prev_last : std_logic;
constant repeat_end : integer := 2 * bits_per_sample - 32;
begin
data <= shift_reg(63);
process
begin
wait until rising_edge(clk);
prev_last <= last;
-- In the bottom 5 bits, do /25 instead of /31. We maintain phase with
-- last by slipping a cycle if shift/load is asserted incorrectly.
if sample_shift and shift_load and not (prev_last='1' and last='0') then
else
if divider(4 downto 3) = "11" then
divider <= divider + 8;
else
divider <= divider + 1;
end if;
end if;
lrck <= divider(12);
bck <= divider(6);
scki <= divider(4);
sample_shift <= divider(6 downto 3) = "1111";
shift_load <= divider(12 downto 7) = "111111";
sample_load <= divider(12 downto 7) = "11" & (channel - "01") & "11";
if sample_shift then
if shift_load then
--shift_reg <= left & left(bits_per_sample - 1 downto repeat_end)
-- & right & right(bits_per_sample - 1 downto repeat_end);
shift_reg <= sample_hold;
else
shift_reg <= shift_reg sll 1;
end if;
if sample_load then
sample_hold <= left & right;
end if;
end if;
end process;
end audio;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_REG_S16 is
end TB_REG_S16;
architecture Behavioral of TB_REG_S16 is
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=4;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal REG_A_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_B_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_B : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_A_IN_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: REG_S16 port map(
CLOCK => Clock,
WE => WE,
RESETN => RESETN,
REG_A_ADDR => REG_A_ADDR,
REG_A => REG_A,
REG_B_ADDR => REG_B_ADDR,
REG_B => REG_B,
REG_A_IN_ADDR => REG_A_IN_ADDR,
REG_A_IN => REG_A_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
REG_A_ADDR <= (others => '0');
REG_B_ADDR <= (others => '0');
REG_A_IN_ADDR <= (others => '0');
--Reset disable
RESETN <= '1'; wait for 2*period;
REG_A_IN <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
REG_A_IN_ADDR <= x"1";
WE <= '1'; wait for 2*period;
WE <= '0';
REG_B_ADDR <= x"1"; wait for 50*period;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity d2aio is
port ( AEN : in std_logic;
D2A0 : in std_logic;
D2A1 : in std_logic;
D2A2 : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
BRDSEL : in std_logic;
SIOW : in std_logic;
clk : in std_logic; -- 50 MHz
BSD : in std_logic_vector (15 downto 0);
D2ACAL : out std_logic_vector (4 downto 0);
SDIN : out std_logic;
CLKIN : out std_logic;
FSIN : out std_logic;
LDAC : out std_logic;
BRDSELO : out std_logic
);
end d2aio;
architecture BEHAVIORAL of d2aio is
signal d2a0_old2 : std_logic:='0';
signal d2a0_old1 : std_logic:='0';
signal d2a1_old2 : std_logic:='0';
signal d2a1_old1 : std_logic:='0';
-- signal d2a2_old2 : std_logic:='0';
-- signal d2a2_old1 : std_logic:='0';
signal data_old2 : std_logic:='0';
signal data_old1 : std_logic:='0';
signal flag: std_logic:='0';
signal fsin1: std_logic:='1';
signal fsin2: std_logic:='1';
signal shift_data : std_logic_vector(15 downto 0):=X"0000";
signal shift_count : std_logic_vector(4 downto 0):="00000";
signal clk_count : std_logic_vector(1 downto 0):="00";
-- signal cal: std_logic_vector(4 downto 0):="00000";
-- signal cal_snatch: std_logic_vector(4 downto 0):="00000";
-- signal cal_flag: std_logic:='0';
-- signal cal1: std_logic:='0';
-- signal cal2: std_logic:='0';
-- signal cal3: std_logic:='0';
-- signal cal4: std_logic:='0';
-- signal cal5: std_logic:='0';
signal snatch: std_logic_vector(4 downto 0):="00001";
signal state1: std_logic:='0';
signal state2: std_logic:='0';
signal state3: std_logic:='0';
signal sig_CLKIN: std_logic:='0';
signal data_index: integer:=0;
type state_value is (s1,s2);
signal state: state_value:=s1;
signal next_state: state_value;
attribute keep: string;
attribute keep of AEN: signal is "true";
begin
-- D2ACAL(4 downto 0) <= cal(4 downto 0);
D2ACAL(4 downto 0) <= snatch(4 downto 0);
-- D2ACAL(4 downto 0) <= "00001";
FSIN <= fsin1 and fsin2;
CLKIN <= sig_CLKIN;
select_card: process(BRDSEL,AEN)
begin
if BRDSEL = '0' and AEN = '0' then
BRDSELO <= '0';
else
BRDSELO <= '1';
end if;
end process select_card;
-- calproc: process(clk)
-- begin
-- if rising_edge(clk) then
-- if cal_flag = '1' then
-- cal <= cal_snatch;
-- cal_flag <= '0';
-- elsif snatch = "00001" and cal1 = '0' then
-- cal_snatch <= "00000";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal1 <= '1';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00010" and cal2 = '0' then
-- cal_snatch <= "00011";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal2 <= '1';
-- cal1 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00100" and cal3 = '0' then
-- cal_snatch <= "00101";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal3 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "01000" and cal4 = '0' then
-- cal_snatch <= "01001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal4 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal5 <= '0';
-- elsif snatch = "10000" and cal5 = '0' then
-- cal_snatch <= "10001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal5 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- else
-- cal_snatch <= "00001";
-- cal <= "00001";
-- cal_flag <= '1';
---- cal1 <= '0';
---- cal2 <= '0';
---- cal3 <= '0';
---- cal4 <= '0';
---- cal5 <= '0';
-- end if;
-- end if;
-- end process calproc;
dacproc: process(clk)
begin
if rising_edge(clk) then
d2a0_old2 <= d2a0_old1;
d2a0_old1 <= D2A0;
d2a1_old2 <= d2a1_old1;
d2a1_old1 <= D2A1;
-- d2a2_old2 <= d2a2_old1;
-- d2a2_old1 <= D2A2;
data_old2 <= data_old1;
data_old1 <= SIOW;
if d2a0_old2 = '0' and d2a0_old1 ='1' then
state1 <= '1';
elsif BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0' then
if data_old2 = '0' and data_old1 = '1' then
shift_data <= BSD;
state2 <= state1;
end if;
else
if state3 = '1' then
state1 <= '0';
state2 <= '0';
end if;
end if;
if d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '0' then
fsin1 <= '0';
LDAC <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '0' then
flag <= '1';
fsin1 <= '1';
LDAC <= '1';
elsif d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '1' then
LDAC <= '0';
fsin1 <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '1' then
flag <= '0';
LDAC <= '1';
fsin1 <= '1';
else
fsin1 <= '1';
LDAC <= '1';
end if;
end if;
end process dacproc;
busproc: process(clk)
begin
if rising_edge(clk) then
if D2A2 = '1' and (BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0') then
if data_old2 = '0' and data_old1 = '1' then
snatch (4 downto 0) <= BSD(4 downto 0);
-- snatch (4 downto 0) <= BSD(15 downto 11);
end if;
else
snatch(4 downto 0) <= snatch(4 downto 0);
end if;
end if;
end process busproc;
states: process(clk)
begin
if falling_edge(clk) then
state <= next_state;
end if;
end process states;
machine: process(sig_CLKIN)
begin
if rising_edge(sig_CLKIN) then
case state is
when s1 => -- latch data
shift_count <= "00000";
data_index <= 0;
state3 <= '0';
fsin2 <= '1';
SDIN <= '0';
if state1 = '1' and state2 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
if shift_count = "10000" then
state3 <= '1';
fsin2 <= '1';
SDIN <= '0';
shift_count <= "00000";
data_index <= 0;
next_state <= s1;
else
state3 <= '0';
fsin2 <= '0';
data_index <= data_index + 1;
SDIN <= shift_data(15 - data_index);
shift_count <= shift_count + 1;
next_state <= s2;
end if;
end case;
end if;
end process machine;
DAC_CLK: process(clk)
begin
if rising_edge (clk) then
if clk_count = "00" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "01" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "10" then
sig_CLKIN <= '0';
clk_count <= clk_count + 1;
elsif clk_count = "11" then
sig_CLKIN <= '0';
clk_count <= "00";
else
sig_CLKIN <= '0';
clk_count <= "00";
end if;
end if;
end process DAC_CLK;
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity clk_refresh_gen is
port
(
clk25Mhz,rst : in std_logic;
clk_refresh : out std_logic
);
end clk_refresh_gen;
architecture bhv of clk_refresh_gen is
constant THIS_WIDTH : integer := integer(ceil(log2(real(208333))));
constant overflow : unsigned := to_unsigned(208333,THIS_WIDTH);
signal count,next_count : unsigned(THIS_WIDTH-1 downto 0);
signal clk,next_clk : std_logic;
begin
process(clk25Mhz)
begin
if(rst = '1') then
count <= (others => '0');
clk <= '0';
elsif(rising_edge(clk25Mhz)) then
count <= next_count;
clk <= next_clk;
end if;
end process;
process(clk25Mhz)
begin
if(count /= overflow) then
next_count <= count + 1;
next_clk <= clk;
else
next_count <= to_unsigned(0,THIS_WIDTH);
next_clk <= not clk;
end if;
end process;
clk_refresh <= clk;
end bhv; |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05700_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of gated clocks: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_05700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_Data : in std_logic; -- Input data
o_Data : out std_logic; -- Output data
o_Gated_Clock : out std_logic -- Gated clock
);
end STD_05700_good;
architecture Behavioral of STD_05700_good is
signal Enable_r : std_logic;
signal Data_r : std_logic; -- Data signal registered
signal Data_r2 : std_logic; -- Data signal registered twice
begin
DFF_En : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_Enable,
o_Q => Enable_r,
o_Q_n => open
);
-- Make the Flip-Flop work when Enable signal is at 1
-- Enable signal on D Flip-flop
P_Sync_Data : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Data_r <= '0';
Data_r2 <= '0';
elsif (rising_edge(i_Clock)) then
if (Enable_r = '1') then
Data_r <= i_Data;
Data_r2 <= Data_r;
end if;
end if;
end process;
o_Data <= Data_r2;
end Behavioral;
--CODE
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : ZIGZAG --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : ZIGZAG.VHD --
-- Created : Sun Sep 3 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Zig-Zag scan --
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity zigzag is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
divalid : in STD_LOGIC;
rd_addr : in unsigned(5 downto 0);
fifo_rden : in std_logic;
fifo_empty : out std_logic;
dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out std_logic;
zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end zigzag;
architecture rtl of zigzag is
type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
(
0,1,8,16,9,2,3,10,
17,24,32,25,18,11,4,5,
12,19,26,33,40,48,41,34,
27,20,13,6,7,14,21,28,
35,42,49,56,57,50,43,36,
29,22,15,23,30,37,44,51,
58,59,52,45,38,31,39,46,
53,60,61,54,47,55,62,63
);
signal fifo_wr : std_logic;
signal fifo_q : std_logic_vector(11 downto 0);
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_empty_s : std_logic;
begin
dout <= fifo_q;
fifo_empty <= fifo_empty_s;
-------------------------------------------------------------------
-- FIFO (show ahead)
-------------------------------------------------------------------
U_FIFO : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rden,
winc => fifo_wr,
datai => fifo_data_in,
datao => fifo_q,
fullo => fifo_full,
emptyo => fifo_empty_s,
count => fifo_count
);
fifo_wr <= divalid;
fifo_data_in <= di;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
zz_rd_addr <= (others => '0');
dovalid <= '0';
else
zz_rd_addr <= std_logic_vector(
to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
dovalid <= fifo_rden and not fifo_empty_s;
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : ZIGZAG --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : ZIGZAG.VHD --
-- Created : Sun Sep 3 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Zig-Zag scan --
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity zigzag is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
divalid : in STD_LOGIC;
rd_addr : in unsigned(5 downto 0);
fifo_rden : in std_logic;
fifo_empty : out std_logic;
dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out std_logic;
zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end zigzag;
architecture rtl of zigzag is
type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
(
0,1,8,16,9,2,3,10,
17,24,32,25,18,11,4,5,
12,19,26,33,40,48,41,34,
27,20,13,6,7,14,21,28,
35,42,49,56,57,50,43,36,
29,22,15,23,30,37,44,51,
58,59,52,45,38,31,39,46,
53,60,61,54,47,55,62,63
);
signal fifo_wr : std_logic;
signal fifo_q : std_logic_vector(11 downto 0);
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_empty_s : std_logic;
begin
dout <= fifo_q;
fifo_empty <= fifo_empty_s;
-------------------------------------------------------------------
-- FIFO (show ahead)
-------------------------------------------------------------------
U_FIFO : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rden,
winc => fifo_wr,
datai => fifo_data_in,
datao => fifo_q,
fullo => fifo_full,
emptyo => fifo_empty_s,
count => fifo_count
);
fifo_wr <= divalid;
fifo_data_in <= di;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
zz_rd_addr <= (others => '0');
dovalid <= '0';
else
zz_rd_addr <= std_logic_vector(
to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
dovalid <= fifo_rden and not fifo_empty_s;
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : ZIGZAG --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : ZIGZAG.VHD --
-- Created : Sun Sep 3 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Zig-Zag scan --
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity zigzag is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
divalid : in STD_LOGIC;
rd_addr : in unsigned(5 downto 0);
fifo_rden : in std_logic;
fifo_empty : out std_logic;
dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out std_logic;
zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end zigzag;
architecture rtl of zigzag is
type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
(
0,1,8,16,9,2,3,10,
17,24,32,25,18,11,4,5,
12,19,26,33,40,48,41,34,
27,20,13,6,7,14,21,28,
35,42,49,56,57,50,43,36,
29,22,15,23,30,37,44,51,
58,59,52,45,38,31,39,46,
53,60,61,54,47,55,62,63
);
signal fifo_wr : std_logic;
signal fifo_q : std_logic_vector(11 downto 0);
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_empty_s : std_logic;
begin
dout <= fifo_q;
fifo_empty <= fifo_empty_s;
-------------------------------------------------------------------
-- FIFO (show ahead)
-------------------------------------------------------------------
U_FIFO : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rden,
winc => fifo_wr,
datai => fifo_data_in,
datao => fifo_q,
fullo => fifo_full,
emptyo => fifo_empty_s,
count => fifo_count
);
fifo_wr <= divalid;
fifo_data_in <= di;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
zz_rd_addr <= (others => '0');
dovalid <= '0';
else
zz_rd_addr <= std_logic_vector(
to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
dovalid <= fifo_rden and not fifo_empty_s;
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : ZIGZAG --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : ZIGZAG.VHD --
-- Created : Sun Sep 3 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Zig-Zag scan --
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity zigzag is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
divalid : in STD_LOGIC;
rd_addr : in unsigned(5 downto 0);
fifo_rden : in std_logic;
fifo_empty : out std_logic;
dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out std_logic;
zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end zigzag;
architecture rtl of zigzag is
type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
(
0,1,8,16,9,2,3,10,
17,24,32,25,18,11,4,5,
12,19,26,33,40,48,41,34,
27,20,13,6,7,14,21,28,
35,42,49,56,57,50,43,36,
29,22,15,23,30,37,44,51,
58,59,52,45,38,31,39,46,
53,60,61,54,47,55,62,63
);
signal fifo_wr : std_logic;
signal fifo_q : std_logic_vector(11 downto 0);
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_empty_s : std_logic;
begin
dout <= fifo_q;
fifo_empty <= fifo_empty_s;
-------------------------------------------------------------------
-- FIFO (show ahead)
-------------------------------------------------------------------
U_FIFO : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rden,
winc => fifo_wr,
datai => fifo_data_in,
datao => fifo_q,
fullo => fifo_full,
emptyo => fifo_empty_s,
count => fifo_count
);
fifo_wr <= divalid;
fifo_data_in <= di;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
zz_rd_addr <= (others => '0');
dovalid <= '0';
else
zz_rd_addr <= std_logic_vector(
to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
dovalid <= fifo_rden and not fifo_empty_s;
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : ZIGZAG --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : ZIGZAG.VHD --
-- Created : Sun Sep 3 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Zig-Zag scan --
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity zigzag is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
divalid : in STD_LOGIC;
rd_addr : in unsigned(5 downto 0);
fifo_rden : in std_logic;
fifo_empty : out std_logic;
dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out std_logic;
zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end zigzag;
architecture rtl of zigzag is
type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
(
0,1,8,16,9,2,3,10,
17,24,32,25,18,11,4,5,
12,19,26,33,40,48,41,34,
27,20,13,6,7,14,21,28,
35,42,49,56,57,50,43,36,
29,22,15,23,30,37,44,51,
58,59,52,45,38,31,39,46,
53,60,61,54,47,55,62,63
);
signal fifo_wr : std_logic;
signal fifo_q : std_logic_vector(11 downto 0);
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_empty_s : std_logic;
begin
dout <= fifo_q;
fifo_empty <= fifo_empty_s;
-------------------------------------------------------------------
-- FIFO (show ahead)
-------------------------------------------------------------------
U_FIFO : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo_rden,
winc => fifo_wr,
datai => fifo_data_in,
datao => fifo_q,
fullo => fifo_full,
emptyo => fifo_empty_s,
count => fifo_count
);
fifo_wr <= divalid;
fifo_data_in <= di;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
zz_rd_addr <= (others => '0');
dovalid <= '0';
else
zz_rd_addr <= std_logic_vector(
to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
dovalid <= fifo_rden and not fifo_empty_s;
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_CplD_Transact is
port (
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : IN std_logic; -- !!
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
CplD_Type : IN std_logic_vector(3 downto 0);
Req_ID_Match : IN std_logic;
usDex_Tag_Matched : IN std_logic;
dsDex_Tag_Matched : IN std_logic;
Tlp_has_4KB : IN std_logic;
Tlp_has_1DW : IN std_logic;
CplD_on_Pool : IN std_logic;
CplD_on_EB : IN std_logic;
CplD_is_the_Last : IN std_logic;
CplD_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : OUT std_logic;
ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Tag output to downstream DMA channel
dsDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : IN std_logic;
tRAM_addrB : IN std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : IN std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Tag output to upstream DMA channel
usDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : OUT std_logic;
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
end entity rx_CplD_Transact;
architecture Behavioral of rx_CplD_Transact is
type RxCplDEBStates is ( ST_EBWR_IDLE
, ST_EBWR_TAG
, ST_EBWR_DATA
);
signal EB_Write_State : RxCplDEBStates;
type RxCplDTrnStates is ( ST_CplD_RESET
, ST_CplD_IDLE
-- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
-- , ST_CplD_HEAD1 -- CplD Header #1
, ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
, ST_CplD_HEAD2 -- CplD Header #2
, ST_CplD_AFetch_Special --
, ST_CplD_AFetch_Special_Tail --
, ST_CplD_AFetch -- Target address fetch from tRAM/registers
, ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
, ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
-- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
, ST_CplD_1ST_DATA -- 1st data payload of the CplD
, ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
, ST_CplD_DATA -- data receiving
, ST_CplD_DATA_THROTTLE -- data receiving throttled
, ST_CplD_LAST_DATA -- Last data payload of the CplD
);
-- State variables
signal RxCplDTrn_NextState : RxCplDTrnStates;
signal RxCplDTrn_State : RxCplDTrnStates;
-- State delay
signal RxCplDTrn_State_r1 : RxCplDTrnStates;
signal RxCplDTrn_State_r2 : RxCplDTrnStates;
signal CplD_State_is_AFetch : std_logic;
signal CplD_State_is_after_AFetch : std_logic;
signal CplD_State_is_AFetch_r1 : std_logic;
-- Shifted-glued payload
signal concat_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rx stubs
signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rd_* in little endian
signal trn_rd_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rerrfwd_n_i : std_logic;
signal trn_rsrc_dsc_n_i : std_logic;
signal trn_rsof_n_i : std_logic;
signal trn_reof_n_i : std_logic;
signal trn_reof_n_r1 : std_logic;
signal trn_reof_n_r2 : std_logic;
signal trn_reof_n_r3 : std_logic;
signal trn_reof_n_r4 : std_logic;
-- signal Tlp_has_4KB_r1 : std_logic;
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- Whether address increases
signal Addr_Inc : std_logic;
-- Spaces hit
-- signal FIFO_Space_Hit : std_logic;
signal DDR_Space_Hit : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_FA_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full_i : std_logic;
-- Event Buffer write port
signal eb_FIFO_we_i : std_logic;
signal eb_FIFO_wsof_i : std_logic;
signal eb_FIFO_weof_i : std_logic;
signal eb_FIFO_sof_marker : std_logic;
signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register write port
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation @ trn_rsof_n=0
signal Dex_CplD_Illegal : std_logic;
signal Reg_WrAddr_if_last_us: std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Reg_WrAddr_if_last_ds: std_logic_vector(C_EP_AWIDTH-1 downto 0);
-- Flow control signals
signal trn_rdst_rdy_n_i : std_logic;
signal trn_rsrc_rdy_n_i : std_logic;
signal trn_rsrc_rdy_n_r1 : std_logic;
signal trn_rsrc_rdy_n_r2 : std_logic;
signal trn_rsrc_rdy_n_r3 : std_logic;
signal trn_rsrc_rdy_n_r4 : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
signal trn_rx_throttle_r2 : std_logic;
signal trn_rx_throttle_r3 : std_logic;
signal trn_rx_throttle_r4 : std_logic;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add_i : std_logic;
signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
signal CplD_is_Payloaded : std_logic;
-- Alias for header resolution
signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_Leng_in_Bytes_r1: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_is_1DW : std_logic;
-- Small_CplD means CplD with less than 4 DW payload
signal Small_CplD : std_logic;
signal Small_CplD_r1 : std_logic;
signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal CplD_Tag_on_Dex : std_logic;
-- ----------------------------------------------------------------------
signal Req_ID_Match_i : std_logic;
signal Dex_Tag_Matched_i : std_logic;
-- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
signal MSB_DSP_Tag : std_logic;
signal MSB_DSP_Tag_r1 : std_logic;
signal DSP_Tag_on_RAM : std_logic;
signal DSP_Tag_on_RAM_r1 : std_logic;
signal DSP_Tag_on_RAM_r2 : std_logic;
signal DSP_Tag_on_RAM_r3 : std_logic;
signal DSP_Tag_on_RAM_r4p : std_logic;
signal DSP_Tag_on_FIFO : std_logic;
-- ----------------------------------------------------------------------
signal FC_pop_i : std_logic;
signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Local_Reset_i : std_logic;
-- upstream Descriptors' tags
signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- downstream Descriptors' tags
signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- --- ------------------------------------------
-- --- Dual port Block Memory, used as tag RAM
-- component
-- v5tagram64x36
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- clkb : IN std_logic;
-- addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
-- );
-- end component;
--- ------------------------------------------
--- Dual port Block Memory, used as tag RAM
component
FF_TagRam64x36
port (
clk : IN std_logic;
addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
wea : IN std_logic;
dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
web : IN std_logic;
dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
);
end component;
signal tRAM_wea : std_logic_vector(0 downto 0);
signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic_vector(0 downto 0);
signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- updates the tag RAM as soon as possible
signal CplD_is_the_Last_r1 : std_logic;
signal Updates_tRAM : std_logic;
signal Updates_tRAM_r1 : std_logic;
signal Update_was_too_late : std_logic;
signal hazard_update : std_logic;
signal hazard_update_r1 : std_logic;
signal hazard_update_r2 : std_logic;
signal hazard_update_r3 : std_logic;
signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tag_matches_hazard : std_logic;
-- aka TLB unit
signal TLB_Addr : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal TLB_Content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal TLB_cnt : std_logic_vector(4-1 downto 0);
signal TLB_Valid : std_logic;
signal TLB_Hit : std_logic;
Constant C_TLB_VALID_CNT : std_logic_vector(4-1 downto 0) := X"6";
begin
-- Event Buffer write
eb_FIFO_we <= eb_FIFO_we_i ;
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
eb_FIFO_weof <= eb_FIFO_weof_i ;
eb_FIFO_din <= eb_FIFO_din_i ;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i ;
DDR_wr_eof <= DDR_wr_eof_i ;
DDR_wr_v <= DDR_wr_v_i ;
DDR_wr_FA <= DDR_wr_FA_i ;
DDR_wr_Shift <= DDR_wr_Shift_i ;
DDR_wr_Mask <= DDR_wr_Mask_i ;
DDR_wr_din <= DDR_wr_din_i ;
DDR_wr_full_i <= DDR_wr_full ;
ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i ;
ds_DMA_Bytes <= ds_DMA_Bytes_i ;
--
Tag_Map_Clear <= Tag_Map_Clear_i;
--
FC_pop <= FC_pop_i;
-- ----------------------------------------------
--
Syn_FC_pop:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_pop_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
and CplD_is_the_Last
and not MSB_DSP_Tag
and not trn_reof_n_i
and trn_reof_n_r1 -- Catch the falling edge of trn_reof_n
-- and not trn_rx_throttle
;
end if;
end process;
-- ----------------------------------------------
-- Synchronous: CplD_is_Payloaded
--
Syn_CplD_is_Payloaded:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_is_Payloaded <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' and trn_rx_throttle='0' then
CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
else
CplD_is_Payloaded <= CplD_is_Payloaded;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Syn_ds_DMA_Bytes_Add:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
ds_DMA_Bytes_Add_i <= '0' ;
ds_DMA_Bytes_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if trn_reof_n_i='0' and trn_rx_throttle='0'
and CplD_is_Payloaded='1' and MSB_DSP_Tag='0'
then
ds_DMA_Bytes_Add_i <= '1' ;
ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
else
ds_DMA_Bytes_Add_i <= '0' ;
ds_DMA_Bytes_i <= (OTHERS=>'0');
end if;
end if;
end process;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i;
--- Dex Tag output to us DMA channel
usDMA_dex_Tag <= usDMA_dex_Tag_i;
--- Dex Tag output to ds DMA channel
dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
---------------------------------------------------
Req_ID_Match_i <= Req_ID_Match;
Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
-- positive reset
Local_Reset_i <= not trn_reset_n;
-- Frame signals
trn_rsof_n_i <= trn_rsof_n;
trn_reof_n_i <= trn_reof_n;
trn_rd_i <= trn_rd;
trn_rrem_n_i <= trn_rrem_n;
trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
-- BC of the current TLP payloads
CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
& CplD_Length & "00";
-- Exception signals
trn_rerrfwd_n_i <= trn_rerrfwd_n;
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_AFetch
--
RxFSM_CplD_State_is_AFetch:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
case RxCplDTrn_State is
when ST_CplD_AFetch =>
CplD_State_is_AFetch <= '1';
when ST_CplD_AFetch_Special =>
CplD_State_is_AFetch <= '1';
when OTHERS =>
CplD_State_is_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_after_AFetch
--
RxFSM_CplD_State_is_after_AFetch:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch_Special_Tail =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_ONLY_1DW =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_1ST_DATA =>
CplD_State_is_after_AFetch <= '1';
when OTHERS =>
CplD_State_is_after_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: trn_r*
--
Syn_Delay_trn_r_x:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_reof_n_r1 <= trn_reof_n_i;
trn_reof_n_r2 <= trn_reof_n_r1;
trn_reof_n_r3 <= trn_reof_n_r2;
trn_reof_n_r4 <= trn_reof_n_r3;
trn_rsrc_rdy_n_r1 <= trn_rx_throttle; -- trn_rsrc_rdy_n_i;
trn_rsrc_rdy_n_r2 <= trn_rsrc_rdy_n_r1;
trn_rsrc_rdy_n_r3 <= trn_rsrc_rdy_n_r2;
trn_rsrc_rdy_n_r4 <= trn_rsrc_rdy_n_r3;
trn_rx_throttle_r1 <= trn_rx_throttle;
trn_rx_throttle_r2 <= trn_rx_throttle_r1;
trn_rx_throttle_r3 <= trn_rx_throttle_r2;
trn_rx_throttle_r4 <= trn_rx_throttle_r3;
-- DDR_wr_full_r1 <= DDR_wr_full_i;
-- DDR_wr_full_r2 <= DDR_wr_full_r1;
trn_rd_r1 <= trn_rd_i;
trn_rd_r2 <= trn_rd_r1;
trn_rd_r3 <= trn_rd_r2;
trn_rd_r4 <= trn_rd_r3;
trn_rrem_n_r1 <= trn_rrem_n_i;
trn_rrem_n_r2 <= trn_rrem_n_r1;
trn_rrem_n_r3 <= trn_rrem_n_r2;
trn_rrem_n_r4 <= trn_rrem_n_r3;
end if;
end process;
-- Endian reversed
trn_rd_Little <= Endian_Invert_64 (trn_rd_i);
trn_rd_Little_r1 <= Endian_Invert_64 (trn_rd_r1);
trn_rd_Little_r2 <= Endian_Invert_64 (trn_rd_r2);
trn_rd_Little_r3 <= Endian_Invert_64 (trn_rd_r3);
trn_rd_Little_r4 <= Endian_Invert_64 (trn_rd_r4);
-- ---------------------------------------------
MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
DSP_Tag_on_RAM <= not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2);
DSP_Tag_on_FIFO <= not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2);
--
-- Delay Synchronous: MSB_DSP_Tag_r1
--
Syn_Delay_MSB_DSP_Tag_r1:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
MSB_DSP_Tag_r1 <= MSB_DSP_Tag;
DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
end if;
end process;
--
-- Delay Synchronous: CplD_Leng_in_Bytes
--
Syn_Delay_CplD_Leng_in_Bytes:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: RxCplDTrn_State
--
RxFSM_Delay_RxTrn_State:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
RxCplDTrn_State_r1 <= RxCplDTrn_State;
RxCplDTrn_State_r2 <= RxCplDTrn_State_r1;
end if;
end process;
-- ----------------------------------------------
-- States synchronous
--
Syn_RxTrn_States:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RxCplDTrn_State <= ST_CplD_RESET;
elsif trn_clk'event and trn_clk = '1' then
RxCplDTrn_State <= RxCplDTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates:
process (
RxCplDTrn_State
, CplD_Type
, MSB_DSP_Tag
, trn_reof_n_i
, trn_rx_throttle
, Req_ID_Match_i
, Dex_Tag_Matched_i
)
begin
case RxCplDTrn_State is
when ST_CplD_RESET =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_IDLE =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_Cpl_HEAD2 => -- further processing to be done ...
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_HEAD2 =>
if trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_HEAD2;
elsif Req_ID_Match_i='1' and Dex_Tag_Matched_i='1' then
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
elsif Req_ID_Match_i='1' and MSB_DSP_Tag='0' then
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_AFetch_Special =>
-- !!!!!!!!!!!!!!
-- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
-- !!!!!!!!!!!!!!
RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
when ST_CplD_AFetch_Special_Tail =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_ONLY_1DW =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_1ST_DATA =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_1ST_DATA_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_LAST_DATA => -- Same as IDLE, to support
-- back-to-back transactions
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_RESET;
end case;
end process;
-- -------------------------------------------------
-- Synchronous Registered: Tag_Map_Clear_i
--
RxTrn_Tag_Map_Clear:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Clear_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
-- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
if CplD_Tag(C_TAG_WIDTH-1)='0'
and CplD_Tag(C_TAG_WIDTH-2-1 downto 0)=CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
and CplD_is_the_Last='1' then
Tag_Map_Clear_i(j) <= '1';
else
Tag_Map_Clear_i(j) <= '0';
end if;
END LOOP;
end if;
end process;
-- -------------------------------------------------
-- Synchronous Registered: CplD_Length
--
RxTrn_CplD_Length:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Length <= (OTHERS => '0');
CplD_is_1DW <= '0';
Small_CplD <= '0';
Small_CplD_r1 <= '0';
elsif trn_clk'event and trn_clk = '1' then
Small_CplD_r1 <= Small_CplD;
if trn_rsof_n_i='0' then
CplD_Length <= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
CplD_is_1DW <= Tlp_has_1DW;
if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)=C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
and trn_rd_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT)/="00"
and trn_rd_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1)="01" -- Cpl/D
then
Small_CplD <= '1';
else
Small_CplD <= '0';
end if;
else
CplD_Length <= CplD_Length;
CplD_is_1DW <= CplD_is_1DW;
Small_CplD <= Small_CplD;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: Addr_Inc
--
RxFSM_Output_Addr_Inc:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Addr_Inc <= '1';
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
Addr_Inc <= '1';
when ST_CplD_1ST_DATA =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when ST_CplD_ONLY_1DW =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when OTHERS =>
Addr_Inc <= Addr_Inc;
end case;
end if;
end process;
-------------------------------------------------
-- Calculation at trn_rsof_n
--
Syn_Dex_wrAddress:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Dex_CplD_Illegal <= '0';
Reg_WrAddr_if_last_us <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
Reg_WrAddr_if_last_ds <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i = '0' then
Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
-- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
-- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
else
Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous: RegAddr_?s_Dex
--
RxFSM_Reg_RegAddr_xs_Dex:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RegAddr_us_Dex <= (Others=>'1');
RegAddr_ds_Dex <= (Others=>'1');
elsif trn_clk'event and trn_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_us_Dex <= (Others=>'1');
elsif CplD_is_the_Last = '1' then -- us last/2nd dex
RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
else -- us 1st/unique dex
RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_ds_Dex <= (Others=>'1');
elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
else -- ds 1st/unique dex
RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous Delay: CplD_Tag_on_Dex
--
RxFSM_Delay_CplD_Tag_on_Dex:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Tag_on_Dex <= '0';
elsif trn_clk'event and trn_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
else
CplD_Tag_on_Dex <= '0';
end if;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers
--
RxFSM_Output_DMA_Registers:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_AFetch_Special =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_1ST_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_ONLY_1DW =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_LAST_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when OTHERS =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end case;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers write Address
--
RxFSM_Output_DMA_Registers_WrAddr:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrAddr_i <= (OTHERS => '1');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_IDLE =>
Regs_WrAddr_i <= (OTHERS => '1');
when ST_CplD_AFetch =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_AFetch_Special =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_1ST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_ONLY_1DW =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_LAST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when OTHERS =>
Regs_WrAddr_i <= Regs_WrAddr_i;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Register:
-- dsDMA_dex_Tag_i
-- usDMA_dex_Tag_i
--
FSM_Reg_DMA_dex_Tags:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when ST_CplD_AFetch_Special =>
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when Others =>
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end case;
end if;
end process;
-- -------------------------------------------------------------
-- RAM holding downstream Tags of packet MRd requests
-- -------------------------------------------------------------
tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i(0) <= tRAM_weB;
dspTag_BRAM:
FF_TagRam64x36
port map(
clk => trn_clk ,
wea => tRAM_wea(0) ,
addra => tRAM_addra ,
dina => tRAM_dina ,
douta => tRAM_doutA ,
web => tRAM_weB_i(0) ,
addrb => tRAM_addrB ,
dinb => tRAM_dinB ,
doutb => open
);
-- dspTag_BRAM:
-- v5tagram64x36
-- port map(
-- clka => trn_clk ,
-- addra => tRAM_addra ,
-- wea => tRAM_wea ,
-- dina => tRAM_dina ,
-- douta => tRAM_doutA ,
-- clkb => trn_clk ,
-- addrb => tRAM_addrB ,
-- web => tRAM_weB_i ,
-- dinb => tRAM_dinB ,
-- doutb => open
-- );
-- -----------------------------------------------------------------------------------
-- Synchronous delay: CplD_is_the_Last
--
Syn_Delay_CplD_is_the_Last:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_is_the_Last_r1 <= CplD_is_the_Last;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Updates_tRAM
-- Update happens only at data TLP
-- The last CplD of one MRd does not trigger tRAM update,
-- to enable back-to-back transactions.
--
RxFSM_Output_Updates_tRAM:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Updates_tRAM <= '0';
elsif trn_clk'event and trn_clk = '1' then
Updates_tRAM <= CplD_State_is_AFetch
and DSP_Tag_on_RAM_r1
-- and not trn_rx_throttle -- trn_rsrc_rdy_n_r1
and not CplD_is_the_Last_r1
;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Update_was_too_late
-- For 1DW CplD the update might be too late for the
-- next CplD with the same TAG
--
RxFSM_Output_Update_was_too_late:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Update_was_too_late <= '0';
hazard_tag <= (OTHERS=>'1');
tag_matches_hazard <= '0';
hazard_update <= '0';
hazard_update_r1 <= '0';
hazard_update_r2 <= '0';
hazard_update_r3 <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Small_CplD_r1='1' and CplD_State_is_after_AFetch='1' then
hazard_update <= '1';
hazard_tag <= CplD_Tag;
else
hazard_update <= '0';
hazard_tag <= hazard_tag;
end if;
if CplD_Tag=hazard_tag then
tag_matches_hazard <= '1';
else
tag_matches_hazard <= '0';
end if;
hazard_update_r1 <= hazard_update;
hazard_update_r2 <= hazard_update_r1;
hazard_update_r3 <= hazard_update_r2;
-- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: Updates_tRAM
--
RxFSM_Delay_Updates_tRAM:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Updates_tRAM_r1 <= Updates_tRAM;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Delay: tRAM_DoutA_r2
--
Delay_tRAM_DoutA:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
---- if CplD_State_is_AFetch='1' then -- [ avoid confilict in simulation, can be removed ]
-- if TLB_Hit='1'
-- and TLB_Valid='1' -- [ only for simulation. can be removed for imp.]
-- then
-- tRAM_DoutA_r1 <= TLB_Content;
-- else
-- tRAM_DoutA_r1 <= tRAM_doutA;
-- end if;
---- else
---- tRAM_DoutA_r1 <= tRAM_DoutA_r1;
---- end if;
if Update_was_too_late='1' and tag_matches_hazard='1' then
tRAM_DoutA_r1 <= hazard_content;
else
tRAM_DoutA_r1 <= tRAM_doutA;
end if;
-- tRAM_DoutA_r1 <= tRAM_doutA;
tRAM_DoutA_r2 <= tRAM_DoutA_r1;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: hazard_content
--
Syn_Reg_hazard_content:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
hazard_content <= (OTHERS =>'1');
elsif trn_clk'event and trn_clk = '1' then
if tRAM_wea(0)='1' then
hazard_content <= tRAM_dina;
else
hazard_content <= hazard_content;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_dina_aInc
--
Syn_Calc_tRAM_dina_aInc:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM=>'1',
OTHERS =>'0'
);
elsif trn_clk'event and trn_clk = '1' then
tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT)
<= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
<= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
+ CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0) ;
end if;
end process;
tRAM_wea(0) <= Updates_tRAM_r1;
tRAM_dina <= tRAM_dina_aInc;
-- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
-- when Addr_Inc='1'
-- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_DoutA_latch
--
Syn_tRAM_DoutA_latch:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM=>'1',OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
if CplD_State_is_AFetch_r1='0' then
tRAM_DoutA_latch <= tRAM_DoutA_latch;
elsif Update_was_too_late='1' then
tRAM_DoutA_latch <= tRAM_DoutA_r1;
else
tRAM_DoutA_latch <= tRAM_DoutA;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: TLB (not used)
--
Syn_Reg_TLB_Operation:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
TLB_Addr <= (OTHERS =>'1');
TLB_Content <= (OTHERS =>'0');
TLB_cnt <= (OTHERS =>'0');
TLB_Valid <= '0';
TLB_Hit <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Updates_tRAM_r1='0' then
TLB_Content <= TLB_Content;
TLB_Addr <= TLB_Addr;
if TLB_cnt=C_ALL_ZEROS(3 downto 0) then
TLB_cnt <= TLB_cnt;
TLB_Valid <= '0';
else
TLB_cnt <= TLB_cnt - '1';
TLB_Valid <= '1';
end if;
else
TLB_Addr <= tRAM_addra;
TLB_cnt <= C_TLB_VALID_CNT;
TLB_Valid <= '0';
if Addr_Inc='1' then
TLB_Content <= '1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0);
else
TLB_Content <= '0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0);
end if;
end if;
if TLB_Addr=tRAM_addra then
TLB_Hit <= '1';
else
TLB_Hit <= '0';
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: DDR_Space_Hit
--
RxFSM_Output_DDR_Space_Hit:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
when ST_CplD_AFetch =>
if trn_reof_n_r4='0' then
DDR_Space_Hit <= DSP_Tag_on_RAM_r1;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= DSP_Tag_on_RAM_r4p;
DDR_wr_v_i <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM; -- and not (trn_rx_throttle_r4 and trn_reof_n_r4);
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
elsif DSP_Tag_on_RAM_r1 ='1' then
DDR_Space_Hit <= '1';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
else
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_RAM_r1 ='1' then
DDR_Space_Hit <= '1';
-- DDR_wr_sof_i <= '0';
-- DDR_wr_eof_i <= '0';
-- DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
-- DDR_wr_FA_i <= '0';
-- DDR_wr_Shift_i <= '0';
-- DDR_wr_Mask_i <= (OTHERS=>'0');
-- DDR_wr_din_i <= (OTHERS=>'0');
else
DDR_Space_Hit <= '0';
-- DDR_wr_sof_i <= '0';
-- DDR_wr_eof_i <= '0';
-- DDR_wr_v_i <= '0';
-- DDR_wr_FA_i <= '0';
-- DDR_wr_Shift_i <= '0';
-- DDR_wr_Mask_i <= (OTHERS=>'0');
-- DDR_wr_din_i <= (OTHERS=>'0');
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
when ST_CplD_AFetch_Special_Tail =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= DDR_wr_din_i;
when ST_CplD_1ST_DATA =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when OTHERS =>
if trn_reof_n_r4='0' then
DDR_Space_Hit <= '0';
else
DDR_Space_Hit <= DDR_Space_Hit;
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
if DDR_wr_sof_i='1' then
DDR_wr_Mask_i <= "10";
else
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
end if;
end case;
end if;
end process;
concat_rd <= trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32);
-- -------------------------------------------------
-- Synchronous outputs: eb_FIFO_Write
--
RxFSM_Output_FIFO_Space_Hit:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
EB_Write_State <= ST_EBWR_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case EB_Write_State is
when ST_EBWR_IDLE =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
if trn_rx_throttle='0'
and CplD_Type=C_TLP_TYPE_IS_CPLD
and trn_rd_i(0)='0' -- Odd-DW CplD is illegal
then
EB_Write_State <= ST_EBWR_TAG;
else
EB_Write_State <= ST_EBWR_IDLE;
end if;
when ST_EBWR_TAG =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
if trn_rsof_n_i='0' then
eb_FIFO_sof_marker <= '0';
EB_Write_State <= ST_EBWR_TAG;
elsif trn_rx_throttle='0' and DSP_Tag_on_FIFO='1' then
eb_FIFO_sof_marker <= '1';
EB_Write_State <= ST_EBWR_DATA;
else
eb_FIFO_sof_marker <= '0';
EB_Write_State <= ST_EBWR_IDLE;
end if;
when ST_EBWR_DATA =>
eb_FIFO_we_i <= not trn_rx_throttle;
eb_FIFO_wsof_i <= eb_FIFO_sof_marker and not trn_rx_throttle;
eb_FIFO_sof_marker <= eb_FIFO_sof_marker and trn_rx_throttle;
eb_FIFO_din_i <= Endian_Invert_64(concat_rd);
if trn_rx_throttle='0' and trn_reof_n_i='0' then
eb_FIFO_weof_i <= '1';
EB_Write_State <= ST_EBWR_IDLE;
else
eb_FIFO_weof_i <= '0';
EB_Write_State <= ST_EBWR_DATA;
end if;
when OTHERS =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
EB_Write_State <= ST_EBWR_IDLE;
end case;
end if;
end process;
end architecture Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:59:31 08/26/2015
-- Design Name:
-- Module Name: Decoder_Binary_7Seg - Behavioral
-- Project Name: Decoder Binary 7 Segments
-- Target Devices:
-- Tool versions: ISE v14.7
-- Description: Binary to 7-segment decoder using behavioral
-- description
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder_Binary_7Seg is
Port ( D : in STD_LOGIC;
C : in STD_LOGIC;
B : in STD_LOGIC;
A : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder_Binary_7Seg;
architecture Behavioral of Decoder_Binary_7Seg is
-- Embedded signals delcaration
signal Ent: STD_LOGIC_VECTOR (3 downto 0);
begin
-- -- OK
-- -- Behavioral Concurrent implementation
-- --.gfedcba
-- Seg <= "11000000" when D='0' and C='0' and B='0' and A='0' else --0
-- "11111001" when D='0' and C='0' and B='0' and A='1' else --1
-- "10100100" when D='0' and C='0' and B='1' and A='0' else --2
-- "10110000" when D='0' and C='0' and B='1' and A='1' else --3
-- "10011001" when D='0' and C='1' and B='0' and A='0' else --4
-- "10010010" when D='0' and C='1' and B='0' and A='1' else --5
-- "10000010" when D='0' and C='1' and B='1' and A='0' else --6
-- "11111000" when D='0' and C='1' and B='1' and A='1' else --7
-- "10000000" when D='1' and C='0' and B='0' and A='0' else --8
-- "10011000" when D='1' and C='0' and B='0' and A='1' else --9
-- "10001000" when D='1' and C='0' and B='1' and A='0' else --10 A
-- "10000011" when D='1' and C='0' and B='1' and A='1' else --11 B
-- "11000110" when D='1' and C='1' and B='0' and A='0' else --12 C
-- "10100001" when D='1' and C='1' and B='0' and A='1' else --13 D
-- "10000110" when D='1' and C='1' and B='1' and A='0' else --14 E
-- "10001110"; --15 F
-- OK
-- Behavioral Concurrent implementation
-- Using embedded signal
-- Group input signals into a vector using aggregate
-- Ent <= D & C & B & A;
-- --.gfedcba
-- Seg <= "11000000" when Ent="0000" else --0
-- "11111001" when Ent="0001" else --1
-- "10100100" when Ent="0010" else --2
-- "10110000" when Ent="0011" else --3
-- "10011001" when Ent="0100" else --4
-- "10010010" when Ent="0101" else --5
-- "10000010" when Ent="0110" else --6
-- "11111000" when Ent="0111" else --7
-- "10000000" when Ent="1000" else --8
-- "10011000" when Ent="1001" else --9
-- "10001000" when Ent="1010" else --10 A
-- "10000011" when Ent="1011" else --11 B
-- "11000110" when Ent="1100" else --12 C
-- "10100001" when Ent="1101" else --13 D
-- "10000110" when Ent="1110" else --14 E
-- "10001110"; --15 F
-- --select display
-- Disp <= "1110";
--
-- OK
-- Behavioral Concurrent implementation using select / when
-- Using embedded signal
Ent <= D & C & B & A;
with Ent select
Seg <= "11000000" when "0000",
"11111001" when "0001", --1
"10100100" when "0010", --2
"10110000" when "0011", --3
"10011001" when "0100", --4
"10010010" when "0101", --5
"10000010" when "0110", --6
"11111000" when "0111", --7
"10000000" when "1000", --8
"10011000" when "1001", --9
"10001000" when "1010", --10 A
"10000011" when "1011", --11 B
"11000110" when "1100", --12 C
"10100001" when "1101", --13 D
"10000110" when "1110", --14 E
"10001110" when others ; --15 F
Disp <= "1110";
-- -- OK
-- --- Sequential Process
-- Ent <= D & C & B & A;
-- process (Ent)
-- VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0);
-- begin
-- if Ent = "0000" then
-- bufer := "11000000"; --0
-- elsif Ent = "0001" then
-- bufer := "11111001"; -- 1
-- elsif Ent = "0010" then
-- bufer := "10100100"; --2
-- elsif Ent = "0011" then
-- bufer := "10110000"; --3
-- elsif Ent = "0100" then
-- bufer := "10011001"; --4
-- elsif Ent = "0101" then
-- bufer := "10010010"; --5
-- elsif Ent = "0110" then
-- bufer := "10000010"; --6
-- elsif Ent = "0111" then
-- bufer := "11111000"; --7
-- elsif Ent = "1000" then
-- bufer := "10000000"; --8
-- elsif Ent = "1001" then
-- bufer := "10011000"; --9
-- elsif Ent = "1010" then
-- bufer := "10001000"; --10 A
-- elsif Ent = "1011" then
-- bufer := "10000011"; --11 B
-- elsif Ent = "1100" then
-- bufer := "11000110"; --12 C
-- elsif Ent = "1101" then
-- bufer := "10100001"; --13 D
-- elsif Ent = "1110" then
-- bufer := "10000110"; --14 E
-- else
-- bufer := "10001110"; --15 F
-- end if;
-- Seg <= bufer;
-- end process;
--
-- Disp <= "1110";
-- OK
-- Select When with hexadecimal
--Ent <= D & C & B & A;
--with Ent select
-- Seg <= x"C0" when x"0",
-- x"F9" when x"1",
-- x"A4" when x"2",
-- x"B0" when x"3",
-- x"99" when x"4",
-- x"92" when x"5",
-- x"82" when x"6",
-- x"F8" when x"7",
-- x"80" when x"8",
-- x"98" when x"9",
-- x"88" when x"A",
-- x"83" when x"B",
-- x"C6" when x"C",
-- x"A1" when x"D",
-- x"86" when x"E",
-- X"8E" when others;
--
-- Disp <= x"E";
-- OK
-- Process using IF / ELSE and Hexadecimal
-- Ent <= D & C & B & A;
-- decoder: process (Ent)
-- VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0);
-- begin
-- if Ent = x"0" then
-- bufer := "11000000"; --0
-- elsif Ent = x"1" then
-- bufer := "11111001"; -- 1
-- elsif Ent = x"2" then
-- bufer := "10100100"; --2
-- elsif Ent = x"3" then
-- bufer := "10110000"; --3
-- elsif Ent = x"4" then
-- bufer := "10011001"; --4
-- elsif Ent = x"5" then
-- bufer := "10010010"; --5
-- elsif Ent = x"6" then
-- bufer := "10000010"; --6
-- elsif Ent = x"7" then
-- bufer := "11111000"; --7
-- elsif Ent = x"8" then
-- bufer := "10000000"; --8
-- elsif Ent = x"9" then
-- bufer := "10011000"; --9
-- elsif Ent = x"A" then
-- bufer := "10001000"; --10 A
-- elsif Ent = x"B" then
-- bufer := "10000011"; --11 B
-- elsif Ent = x"C" then
-- bufer := "11000110"; --12 C
-- elsif Ent = x"D" then
-- bufer := "10100001"; --13 D
-- elsif Ent = x"E" then
-- bufer := "10000110"; --14 E
-- else
-- bufer := "10001110"; --15 F
-- end if;
-- Seg <= bufer;
--end process decoder;
--
--Disp <= x"E";
-- OK
--
-- Ent <= D & C & B & A;
-- decodercase: process(Ent)
-- VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0);
-- begin
-- case(Ent) is
-- when "0000" => bufer:= "11000000";
-- when "0001" => bufer:= "11111001";
-- when "0010" => bufer:= "10100100";
-- when "0011" => bufer:= "10110000";
-- when "0100" => bufer:= "10011001";
-- when "0101" => bufer:= "10010010";
-- when "0110" => bufer:= "10000010";
-- when "0111" => bufer:= "11111000";
-- when "1000" => bufer:= "10000000";
-- when "1001" => bufer:= "10011000";
-- when "1010" => bufer:= "10001000";
-- when "1011" => bufer:= "10000011";
-- when "1100" => bufer:= "11000110";
-- when "1101" => bufer:= "10100001";
-- when "1110" => bufer:= "10000110";
-- when "1111" => bufer:= "10001110";
-- when others => bufer:= "10111111";
-- end case;
-- Seg <= bufer;
-- end process decodercase;
--
-- Disp <= x"E";
--
--
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regmp-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of reg_multiple_plus_one_out is
begin
reg: process ( d, latch_en, out_en ) is
variable latched_value : dlx_word;
begin
if To_bit(latch_en) = '1' then
latched_value := To_X01(d);
end if;
q0 <= latched_value after Tpd;
for index in out_en'range loop
if To_bit(out_en(index)) = '1' then
q(index) <= latched_value after Tpd;
else
q(index) <= disabled_dlx_word after Tpd;
end if;
end loop;
end process reg;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regmp-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of reg_multiple_plus_one_out is
begin
reg: process ( d, latch_en, out_en ) is
variable latched_value : dlx_word;
begin
if To_bit(latch_en) = '1' then
latched_value := To_X01(d);
end if;
q0 <= latched_value after Tpd;
for index in out_en'range loop
if To_bit(out_en(index)) = '1' then
q(index) <= latched_value after Tpd;
else
q(index) <= disabled_dlx_word after Tpd;
end if;
end loop;
end process reg;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regmp-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of reg_multiple_plus_one_out is
begin
reg: process ( d, latch_en, out_en ) is
variable latched_value : dlx_word;
begin
if To_bit(latch_en) = '1' then
latched_value := To_X01(d);
end if;
q0 <= latched_value after Tpd;
for index in out_en'range loop
if To_bit(out_en(index)) = '1' then
q(index) <= latched_value after Tpd;
else
q(index) <= disabled_dlx_word after Tpd;
end if;
end loop;
end process reg;
end architecture behavior;
|
-------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : sync.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-25 V0.02 mairt omitted reset out
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : sync.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-25 V0.02 mairt omitted reset out
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : sync.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-25 V0.02 mairt omitted reset out
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : sync.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-25 V0.02 mairt omitted reset out
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : sync.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-25 V0.02 mairt omitted reset out
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cache is
end entity cache;
-- end not in book
architecture behavioral of cache is
-- not in book
subtype word is bit_vector(0 to 31);
signal mem_addr : natural;
signal mem_data_in : word;
signal mem_read, mem_ack : bit := '0';
-- end not in book
begin
behavior : process is
-- not in book
constant block_size : positive := 4;
type cache_block is array (0 to block_size - 1) of word;
type store_array is array (0 to 15) of cache_block;
variable data_store : store_array;
variable entry_index : natural := 1;
variable miss_base_address : natural := 16;
-- end not in book
-- . . .
procedure read_block( start_address : natural;
entry : out cache_block ) is
variable memory_address_reg : natural;
variable memory_data_reg : word;
procedure read_memory_word is
begin
mem_addr <= memory_address_reg;
mem_read <= '1';
wait until mem_ack = '1';
memory_data_reg := mem_data_in;
mem_read <= '0';
wait until mem_ack = '0';
end procedure read_memory_word;
begin -- read_block
for offset in 0 to block_size - 1 loop
memory_address_reg := start_address + offset;
read_memory_word;
entry(offset) := memory_data_reg;
end loop;
end procedure read_block;
begin -- behavior
-- . . .
read_block( miss_base_address, data_store(entry_index) );
-- . . .
-- not in book
wait;
-- end not in book
end process behavior;
-- not in book
memory : process is
type store_array is array (0 to 31) of word;
constant store : store_array :=
( X"00000000", X"00000001", X"00000002", X"00000003",
X"00000004", X"00000005", X"00000006", X"00000007",
X"00000008", X"00000009", X"0000000a", X"0000000b",
X"0000000c", X"0000000d", X"0000000e", X"0000000f",
X"00000010", X"00000011", X"00000012", X"00000013",
X"00000014", X"00000015", X"00000016", X"00000017",
X"00000018", X"00000019", X"0000001a", X"0000001b",
X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
begin
wait until mem_read = '1';
mem_data_in <= store(mem_addr);
mem_ack <= '1';
wait until mem_read = '0';
mem_ack <= '0';
end process memory;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cache is
end entity cache;
-- end not in book
architecture behavioral of cache is
-- not in book
subtype word is bit_vector(0 to 31);
signal mem_addr : natural;
signal mem_data_in : word;
signal mem_read, mem_ack : bit := '0';
-- end not in book
begin
behavior : process is
-- not in book
constant block_size : positive := 4;
type cache_block is array (0 to block_size - 1) of word;
type store_array is array (0 to 15) of cache_block;
variable data_store : store_array;
variable entry_index : natural := 1;
variable miss_base_address : natural := 16;
-- end not in book
-- . . .
procedure read_block( start_address : natural;
entry : out cache_block ) is
variable memory_address_reg : natural;
variable memory_data_reg : word;
procedure read_memory_word is
begin
mem_addr <= memory_address_reg;
mem_read <= '1';
wait until mem_ack = '1';
memory_data_reg := mem_data_in;
mem_read <= '0';
wait until mem_ack = '0';
end procedure read_memory_word;
begin -- read_block
for offset in 0 to block_size - 1 loop
memory_address_reg := start_address + offset;
read_memory_word;
entry(offset) := memory_data_reg;
end loop;
end procedure read_block;
begin -- behavior
-- . . .
read_block( miss_base_address, data_store(entry_index) );
-- . . .
-- not in book
wait;
-- end not in book
end process behavior;
-- not in book
memory : process is
type store_array is array (0 to 31) of word;
constant store : store_array :=
( X"00000000", X"00000001", X"00000002", X"00000003",
X"00000004", X"00000005", X"00000006", X"00000007",
X"00000008", X"00000009", X"0000000a", X"0000000b",
X"0000000c", X"0000000d", X"0000000e", X"0000000f",
X"00000010", X"00000011", X"00000012", X"00000013",
X"00000014", X"00000015", X"00000016", X"00000017",
X"00000018", X"00000019", X"0000001a", X"0000001b",
X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
begin
wait until mem_read = '1';
mem_data_in <= store(mem_addr);
mem_ack <= '1';
wait until mem_read = '0';
mem_ack <= '0';
end process memory;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cache is
end entity cache;
-- end not in book
architecture behavioral of cache is
-- not in book
subtype word is bit_vector(0 to 31);
signal mem_addr : natural;
signal mem_data_in : word;
signal mem_read, mem_ack : bit := '0';
-- end not in book
begin
behavior : process is
-- not in book
constant block_size : positive := 4;
type cache_block is array (0 to block_size - 1) of word;
type store_array is array (0 to 15) of cache_block;
variable data_store : store_array;
variable entry_index : natural := 1;
variable miss_base_address : natural := 16;
-- end not in book
-- . . .
procedure read_block( start_address : natural;
entry : out cache_block ) is
variable memory_address_reg : natural;
variable memory_data_reg : word;
procedure read_memory_word is
begin
mem_addr <= memory_address_reg;
mem_read <= '1';
wait until mem_ack = '1';
memory_data_reg := mem_data_in;
mem_read <= '0';
wait until mem_ack = '0';
end procedure read_memory_word;
begin -- read_block
for offset in 0 to block_size - 1 loop
memory_address_reg := start_address + offset;
read_memory_word;
entry(offset) := memory_data_reg;
end loop;
end procedure read_block;
begin -- behavior
-- . . .
read_block( miss_base_address, data_store(entry_index) );
-- . . .
-- not in book
wait;
-- end not in book
end process behavior;
-- not in book
memory : process is
type store_array is array (0 to 31) of word;
constant store : store_array :=
( X"00000000", X"00000001", X"00000002", X"00000003",
X"00000004", X"00000005", X"00000006", X"00000007",
X"00000008", X"00000009", X"0000000a", X"0000000b",
X"0000000c", X"0000000d", X"0000000e", X"0000000f",
X"00000010", X"00000011", X"00000012", X"00000013",
X"00000014", X"00000015", X"00000016", X"00000017",
X"00000018", X"00000019", X"0000001a", X"0000001b",
X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
begin
wait until mem_read = '1';
mem_data_in <= store(mem_addr);
mem_ack <= '1';
wait until mem_read = '0';
mem_ack <= '0';
end process memory;
-- end not in book
end architecture behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00533
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (2)
-- 14.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00533)
-- ENT00533_Test_Bench(ARCH00533_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00533 of E00000 is
begin
P :
process
type ary is array ( integer range <> ) of integer ;
subtype st_ary is ary (1 to 10) ;
type rec is record
a,b : integer ;
end record ;
subtype st_rec is rec ;
attribute ary_attr : integer ;
attribute ary_attr of ary : type is 10 ;
attribute rec_attr : integer ;
attribute rec_attr of rec : type is 20 ;
begin
test_report ( "ARCH00533" ,
"Base attribute" ,
(ary'ary_attr = 10) and
(rec'rec_attr = 20) and
(t_enum1'base'leftof(en2) = en1) and
(st_enum1'rightof(en2) = en1) and
(st_enum1'base'leftof(en2) = en1) and
(t_int1'base'rightof(-1) = 0) and
(st_int1'base'leftof(1) = 0)
) ;
wait ;
end process P ;
end ARCH00533 ;
--
entity ENT00533_Test_Bench is
end ENT00533_Test_Bench ;
architecture ARCH00533_Test_Bench of ENT00533_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00533 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00533_Test_Bench ;
--
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
entity DummyRO is
port(
osc_out : out std_logic;
clk : in std_logic
);
end DummyRO;
architecture low_level_definition of DummyRO is
signal clkDiv2 : std_logic;
attribute keep : string;
attribute keep of osc_out: signal is "true";
attribute s: string;
attribute s of osc_out: signal is "yes";
begin
osc_out <= clkDiv2;
toggle_flop: FD
port map ( D => not clkDiv2,
Q => clkDiv2,
C => clk);
end low_level_definition;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX0_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX0_0;
ARCHITECTURE design_1_MUX0_0_arch OF design_1_MUX0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX0_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX0_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX0_0;
ARCHITECTURE design_1_MUX0_0_arch OF design_1_MUX0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX0_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX0_0_arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the L_PicoBlaze namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
package pb_Devices is
-- ===========================================================================
-- PicoBlaze bus descriptions
-- ===========================================================================
constant C_PB_BUSSES : T_PB_BUS_VECTOR := (
0 => pb_CreateBus("Any", "Any", ""),
1 => pb_CreateBus("Intern", "Intern", "Any"),
2 => pb_CreateBus("Extern", "Extern", "Any")
);
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
constant PB_DEV_RESET : T_PB_DEVICE;
constant PB_DEV_ROM : T_PB_DEVICE;
constant PB_DEV_INTERRUPT : T_PB_DEVICE;
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE;
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE;
constant PB_DEV_TIMER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE;
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER : T_PB_DEVICE;
constant PB_DEV_DIVIDER8 : T_PB_DEVICE;
constant PB_DEV_DIVIDER16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER24 : T_PB_DEVICE;
constant PB_DEV_DIVIDER32 : T_PB_DEVICE;
-- constant PB_DEV_SCALER16 : T_PB_DEVICE;
-- constant PB_DEV_SCALER32 : T_PB_DEVICE;
constant PB_DEV_SCALER40 : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE;
constant PB_DEV_GPIO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE;
constant PB_DEV_LCDISPLAY : T_PB_DEVICE;
constant PB_DEV_UART : T_PB_DEVICE;
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE;
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE;
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE;
constant PB_DEV_DRP : T_PB_DEVICE;
constant PB_DEV_FREQM : T_PB_DEVICE;
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE;
end package;
package body pb_Devices is
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
-- Reset Circuit
-- ---------------------------------------------------------------------------
constant PB_DEV_RESET_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Reset", "Reset", 8)
);
constant PB_DEV_RESET : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Reset Circuit",
DeviceShort => "Reset",
Registers => (
pb_CreateRegisterWK("Reset", 0, PB_DEV_RESET_FIELDS, "Reset", 0)),
RegisterFields => PB_DEV_RESET_FIELDS
);
-- Instruction ROM
-- ---------------------------------------------------------------------------
constant PB_DEV_ROM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("PageNumber", "PageNumber", 3)
);
constant PB_DEV_ROM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Instruction ROM",
DeviceShort => "InstROM",
Registers => (
pb_CreateRegisterRWK("PageNumber", 0, PB_DEV_ROM_FIELDS, "PageNumber", 5)),
RegisterFields => PB_DEV_ROM_FIELDS
);
-- InterruptController
-- ---------------------------------------------------------------------------
constant PB_DEV_INTERRUPT8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 8) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 8) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 16) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 16) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 16) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (8 ports)",
DeviceShort => "IntC8",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntDisable0", 1, PB_DEV_INTERRUPT8_FIELDS, "IntDisable", 0) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntSource", 1, PB_DEV_INTERRUPT8_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT8_FIELDS
);
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (16 ports)",
DeviceShort => "IntC16",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntEnable1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 8) &
pb_CreateRegisterWK("IntDisable0", 2, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 0) &
pb_CreateRegisterWK("IntDisable1", 3, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 8) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntMask1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 8) &
pb_CreateRegisterRO("IntSource", 2, PB_DEV_INTERRUPT16_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT16_FIELDS
);
-- Timer
-- ---------------------------------------------------------------------------
constant PB_DEV_TIMER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Control", "Control", 8) &
pb_CreateWriteOnlyField("Max Value", "MaxValue", 16) &
pb_CreateReadOnlyField("Current Value", "CurValue", 16)
);
constant PB_DEV_TIMER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Timer",
DeviceShort => "Timer",
Registers => (
pb_CreateRegisterWK("Control", 0, PB_DEV_TIMER_FIELDS, "Control", 0) &
pb_CreateRegisterWO("MaxValue0", 2, PB_DEV_TIMER_FIELDS, "MaxValue", 0) &
pb_CreateRegisterWO("MaxValue1", 3, PB_DEV_TIMER_FIELDS, "MaxValue", 8) &
pb_CreateRegisterRO("CurValue0", 2, PB_DEV_TIMER_FIELDS, "CurValue", 0) &
pb_CreateRegisterRO("CurValue1", 3, PB_DEV_TIMER_FIELDS, "CurValue", 8)),
RegisterFields => PB_DEV_TIMER_FIELDS,
CreatesInterrupt => TRUE
);
-- Multiplier (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_MULTIPLIER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_MULTIPLIER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 32)
);
constant PB_DEV_MULTIPLIER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 48)
);
constant PB_DEV_MULTIPLIER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 64)
);
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (8 bit)",
DeviceShort => "Mult8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER8_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_MULTIPLIER8_FIELDS
);
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (16 bit)",
DeviceShort => "Mult16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER16_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER16_FIELDS, "Result", 24)),
RegisterFields => PB_DEV_MULTIPLIER16_FIELDS
);
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (24 bit)",
DeviceShort => "Mult24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER24_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER24_FIELDS, "Result", 40)),
RegisterFields => PB_DEV_MULTIPLIER24_FIELDS
);
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (32 bit)",
DeviceShort => "Mult32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER32_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER32_FIELDS, "Result", 40) &
pb_CreateRegisterRO("Result6", 6, PB_DEV_MULTIPLIER32_FIELDS, "Result", 48) &
pb_CreateRegisterRO("Result7", 7, PB_DEV_MULTIPLIER32_FIELDS, "Result", 56)),
RegisterFields => PB_DEV_MULTIPLIER32_FIELDS
);
-- Accumulator (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_ACCUMULATOR16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operation", "Operation", 8) &
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateWriteOnlyField("Operand C", "OperandC", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Accumulator (16 bit)",
DeviceShort => "Accu16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandC0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 0) &
pb_CreateRegisterWO("OperandC1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_ACCUMULATOR16_FIELDS
);
-- Divider (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_DIVIDER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 8) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 32) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (8 bit)",
DeviceShort => "Div8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER8_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER8_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (16 bit)",
DeviceShort => "Div16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_DIVIDER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER16_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER16_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (24 bit)",
DeviceShort => "Div24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_DIVIDER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_DIVIDER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_DIVIDER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Status", 5, PB_DEV_DIVIDER24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER24_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (32 bit)",
DeviceShort => "Div32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_DIVIDER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_DIVIDER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_DIVIDER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_DIVIDER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_DIVIDER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_DIVIDER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 7, PB_DEV_DIVIDER32_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER32_FIELDS,
CreatesInterrupt => TRUE
);
-- Scaler (40 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_SCALER40_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 40) &
pb_CreateWriteOnlyField("Multiplicator", "Mult", 8) &
pb_CreateWriteOnlyField("Divisor", "Div", 8) &
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Result R", "Result", 40) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_SCALER40 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Scaler (40 bit)",
DeviceShort => "Scaler40",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_SCALER40_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_SCALER40_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_SCALER40_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_SCALER40_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandA4", 4, PB_DEV_SCALER40_FIELDS, "OperandA", 32) &
pb_CreateRegisterWO("Mult", 5, PB_DEV_SCALER40_FIELDS, "Mult", 0) &
pb_CreateRegisterWO("Div", 6, PB_DEV_SCALER40_FIELDS, "Div", 0) &
pb_CreateRegisterWO("Command", 7, PB_DEV_SCALER40_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_SCALER40_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_SCALER40_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_SCALER40_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_SCALER40_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_SCALER40_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Status", 7, PB_DEV_SCALER40_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_SCALER40_FIELDS,
CreatesInterrupt => TRUE
);
-- Converter Bin2BCD (24 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_CONVERTER_BCD24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand", "OperandA", 24) &
pb_CreateReadOnlyField("Result", "Result", 28) &
pb_CreateReadOnlyField("Status", "Status", 4)
);
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Converter Bin2BCD (24 bit)",
DeviceShort => "ConvBCD24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 16) &
-- pb_CreateRegisterRO("Result3", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_CONVERTER_BCD24_FIELDS,
CreatesInterrupt => TRUE
);
-- General Purpose I/O
-- ---------------------------------------------------------------------------
constant PB_DEV_GPIO_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateRegisterField("GPIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("GPIO DataIn", "DataIn", 8) &
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8)
);
constant PB_DEV_GPIO : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "General Purpose I/O",
DeviceShort => "GPIO",
Registers => (
pb_CreateRegisterRWK("DataOut", 0, PB_DEV_GPIO_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_GPIO_FIELDS, "DataIn", 0) &
pb_CreateRegisterWO("IntEnable", 1, PB_DEV_GPIO_FIELDS, "IntEnable", 0)),
RegisterFields => PB_DEV_GPIO_FIELDS,
CreatesInterrupt => TRUE
);
-- Bit Banging I/O (8 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 8) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 8) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 8)
);
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO8",
Registers => (
pb_CreateRegisterWK("Set", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Clear", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "Clear", 0) &
pb_CreateRegisterRO("DataOut", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_BIT_BANGING_IO8_FIELDS
);
-- Bit Banging I/O (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 16) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 16) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 16) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 16)
);
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO16",
Registers => (
pb_CreateRegisterWK("Set0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Set1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 8) &
pb_CreateRegisterWK("Clear0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 0) &
pb_CreateRegisterWK("Clear1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 8) &
pb_CreateRegisterRO("DataOut0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataOut1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 8) &
pb_CreateRegisterRO("DataIn0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 0) &
pb_CreateRegisterRO("DataIn1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 8)),
RegisterFields => PB_DEV_BIT_BANGING_IO16_FIELDS
);
-- LC-Display
-- ---------------------------------------------------------------------------
constant PB_DEV_LCDISPLAY_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateWriteOnlyField("Data", "Data", 8)
);
constant PB_DEV_LCDISPLAY : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "LC Display Controller",
DeviceShort => "LCD",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_LCDISPLAY_FIELDS, "Command", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0)),
RegisterFields => PB_DEV_LCDISPLAY_FIELDS
);
-- UART
-- ---------------------------------------------------------------------------
constant PB_DEV_UART_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateWriteOnlyField("FIFO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("FIFO DataIn", "DataIn", 8)
);
constant PB_DEV_UART : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "UART",
DeviceShort => "UART",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_UART_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_UART_FIELDS, "Status", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_UART_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_UART_FIELDS,
CreatesInterrupt => TRUE
);
-- UARTStream
-- ---------------------------------------------------------------------------
constant PB_DEV_UARTSTREAM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "UARTStream",
-- DeviceShort => "UARTStream",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_UARTSTREAM_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_UARTSTREAM_FIELDS,
-- CreatesInterrupt => TRUE
-- );
-- I2C Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_IICCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Device Address [7:1]", "DeviceAddress", 8) &
pb_CreateRegisterField("RX Length [3:0]", "RXLength", 8) &
pb_CreateWriteOnlyField("TX_FIFO", "TX_FIFO", 8) &
pb_CreateReadOnlyField("RX_FIFO", "RX_FIFO", 8)
);
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "I2C Controller",
DeviceShort => "IICCtrl",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_IICCONTROLLER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_IICCONTROLLER_FIELDS, "Status", 0) &
pb_CreateRegisterRW("DeviceAddress", 1, PB_DEV_IICCONTROLLER_FIELDS, "DeviceAddress", 0) &
pb_CreateRegisterRW("Length", 2, PB_DEV_IICCONTROLLER_FIELDS, "RXLength", 0) &
pb_CreateRegisterWO("TX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "TX_FIFO", 0) &
pb_CreateRegisterRO("RX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "RX_FIFO", 0)),
RegisterFields => PB_DEV_IICCONTROLLER_FIELDS,
CreatesInterrupt => TRUE
);
-- MDIO Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_MDIOCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "MDIO Controller",
-- DeviceShort => "MDIOCtrl",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_MDIOCONTROLLER_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_MDIOCONTROLLER_FIELDS,
-- CreatesInterrupt => FALSE
-- );
-- Dynamic Reconfiguration Port
-- ---------------------------------------------------------------------------
constant PB_DEV_DRP_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Address", "Address", 8) &
pb_CreateRegisterField("Data", "Data", 16) &
pb_CreateWriteOnlyField("Mask Register Set", "MaskRegSet", 16) &
pb_CreateWriteOnlyField("Mask Register Clear", "MaskRegClr", 16)
);
constant PB_DEV_DRP : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "PicoBlaze to DRP Adapter",
DeviceShort => "DRP",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_DRP_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_DRP_FIELDS, "Status", 0) &
pb_CreateRegisterRW("Address", 1, PB_DEV_DRP_FIELDS, "Address", 0) &
pb_CreateRegisterRW("Data0", 2, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterRW("Data1", 3, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterWO("MaskRegSet0", 4, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegSet1", 5, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegClr0", 6, PB_DEV_DRP_FIELDS, "MaskRegClr", 0) &
pb_CreateRegisterWO("MaskRegClr1", 7, PB_DEV_DRP_FIELDS, "MaskRegClr", 0)),
RegisterFields => PB_DEV_DRP_FIELDS
);
-- Frequency Measurement
-- ---------------------------------------------------------------------------
constant PB_DEV_FREQM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Frequency Counter", "FreqCntValue", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_FREQM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "FrequencyMeasurement",
DeviceShort => "FreqM",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_FREQM_FIELDS, "Command", 0) &
pb_CreateRegisterRO("FreqCntValue0", 0, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue1", 1, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue2", 2, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_FREQM_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_FREQM_FIELDS
);
-- BCD Counter
-- ---------------------------------------------------------------------------
constant PB_DEV_BCDCOUNTER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Value", "Value", 32)
);
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "BCD Counter",
DeviceShort => "BCDCnt",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_BCDCOUNTER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Value0", 0, PB_DEV_BCDCOUNTER_FIELDS, "Value", 0) &
pb_CreateRegisterRO("Value1", 1, PB_DEV_BCDCOUNTER_FIELDS, "Value", 8) &
pb_CreateRegisterRO("Value2", 2, PB_DEV_BCDCOUNTER_FIELDS, "Value", 16) &
pb_CreateRegisterRO("Value3", 3, PB_DEV_BCDCOUNTER_FIELDS, "Value", 24)),
RegisterFields => PB_DEV_BCDCOUNTER_FIELDS
);
-- define aliases
constant PB_DEV_INTERRUPT : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_INTERRUPT16, "IntC");
constant PB_DEV_MULTIPLIER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_MULTIPLIER32, "Mult");
constant PB_DEV_DIVIDER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_DIVIDER32, "Div");
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_CONVERTER_BCD24, "ConvBCD");
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_BIT_BANGING_IO8, "BBIO");
end package body;
|
-- LEON3 Statistics Module
constant CFG_STAT_ENABLE : integer := CONFIG_STAT_ENABLE;
constant CFG_STAT_CNT : integer := CONFIG_STAT_CNT;
constant CFG_STAT_NMAX : integer := CONFIG_STAT_NMAX;
|
--------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : demo_tb.vhd
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core
-- to demonstrate the functionality.
--------------------------------------------------------------------------------
--
-- This testbench performs the following operations on the MAC core
-- and its design example:
-- - The MDIO interface will respond to a read request with data to prevent the
-- example design thinking it is real hardware
-- - Five frames are then pushed into the receiver from the PHY
-- interface (GMII or RGMII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- The address of fifth frame does not match with the value the address
-- filter is set to therefore gets dropped.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
-- The last frame gets dropped by the address filter due to
-- address mismatch.
-- - The five frames are then re-sent at 100Mb/s, 10Mb/s and finally 1Gb/s again.
------------------------------------------------------------------------
-- DEMONSTRATION TESTBENCH |
-- |
-- |
-- ---------------------------------------------- |
-- | TOP LEVEL WRAPPER (DUT) | |
-- | ------------------- ---------------- | |
-- | | USER LOOPBACK | | TRI-MODE | | |
-- | | DESIGN EXAMPLE | | ETHERNET MAC | | |
-- | | | | CORE | | |
-- | | | | | | Monitor |
-- | | ------->|--->| Tx |--------> Frames |
-- | | | | | PHY | | |
-- | | | | | I/F | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | Rx | | |
-- | | | | | PHY | | |
-- | | --------|<---| I/F |<-------- Generate |
-- | | | | | | Frames |
-- | ------------------- ---------------- | |
-- --------------------------------^------------- |
-- | |
-- | |
-- Stimulate |
-- Management I/F |
-- (if present) |
-- |
------------------------------------------------------------------------
entity demo_tb is
end demo_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of demo_tb is
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
config_board : in std_logic;
--serial_command : in std_logic;
serial_response : out std_logic;
gen_tx_data : in std_logic;
chk_tx_data : in std_logic;
reset_error : in std_logic;
frame_error : out std_logic;
frame_errorn : out std_logic;
activity_flash : out std_logic;
activity_flashn : out std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type tri_mode_ethernet_mac_0_frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of tri_mode_ethernet_mac_0_frame_typ;
-----------------------------------
-- testbench mode selection
-----------------------------------
-- the testbench has two modes of operation:
-- - DEMO := In this mode frames are generated and checked by the testbench
-- and looped back at the user side of the MAC.
-- - BIST := In this mode the built in pattern generators and patttern
-- checkers are used with the data looped back in the PHY domain.
constant TB_MODE : string := "BIST";
-- The following parameter does not control the value the address filter is set to
-- it is only used in the testbench
constant address_filter_value : std_logic_vector(95 downto 0) := X"06050403025A_0605040302DA"; --SA and DA
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core transmit interface by the testbench.
------------------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-------------
0 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-------------
1 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"80", VALID => '1', ERROR => '0'), -- Length/Type = Type = 8000
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'),
60 => ( DATA => X"2F", VALID => '1', ERROR => '0'), -- 47th Data byte
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-------------
2 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'),
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '1'), -- Error asserted
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => true),
-------------
-- Frame 3
-------------
3 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4
-------------
4 => (
columns => (
0 => ( DATA => X"DB", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal tx_monitor_finished_10M : boolean := false;
signal tx_monitor_finished_100M : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal test_half_duplex : std_logic := '0';
signal gmii_rxd_dut : std_logic_vector(7 downto 0);
signal gmii_rx_dv_dut : std_logic;
signal gmii_rx_er_dut : std_logic;
signal gen_tx_data : std_logic;
signal check_tx_data : std_logic;
signal config_bist : std_logic;
signal frame_error : std_logic;
signal bist_mode_error : std_logic;
signal serial_response : std_logic;
begin
-- select between loopback or local data
gmii_rxd_dut <= gmii_txd when (TB_MODE = "BIST") else gmii_rxd;
gmii_rx_dv_dut <= gmii_tx_en when (TB_MODE = "BIST") else gmii_rx_dv;
gmii_rx_er_dut <= gmii_tx_er when (TB_MODE = "BIST") else gmii_rx_er;
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: tri_mode_ethernet_mac_0_example_design
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd_dut,
gmii_rx_dv => gmii_rx_dv_dut,
gmii_rx_er => gmii_rx_er_dut,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
config_board => config_bist,
serial_response => serial_response,
gen_tx_data => gen_tx_data,
chk_tx_data => check_tx_data,
reset_error => '0',
frame_error => frame_error,
frame_errorn => open,
activity_flash => open,
activity_flashn => open
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 680 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Simulate the MDIO
------------------------------------------------------------------------------
-- respond with sensible data to mdio reads and accept writes.
-- expect mdio to try and read from reg addr 1 - return all 1's if we don't
-- want any other mdio accesses
-- if any other response then mdio will write to reg_addr 9 then 4 then 0
-- (may check for expected write data?)
-- finally mdio read from reg addr 1 until bit 5 is seen high
-- NOTE - do not check any other bits so could drive all high again..
p_mdio_count : process (mdc, reset)
begin
if (reset = '1') then
mdio_count <= (others => '0');
last_mdio <= '0';
elsif mdc'event and mdc = '1' then
last_mdio <= mdio;
if mdio_count >= "100000" then
mdio_count <= (others => '0');
elsif (mdio_count /= "000000") then
mdio_count <= mdio_count + "000001";
else -- only get here if mdio state is 0 - now look for a start
if mdio = '1' and last_mdio = '0' then
mdio_count <= "000001";
end if;
end if;
end if;
end process p_mdio_count;
mdio <= '1' when (mdio_read = '1' and (mdio_count >= "001110") and (mdio_count <= "011111")) else 'Z';
-- only respond to phy and reg address == 1 (PHY_STATUS)
p_mdio_check : process (mdc, reset)
begin
if (reset = '1') then
mdio_read <= '0';
mdio_addr <= '1'; -- this will go low if the address doesn't match required
mdio_fail <= '0';
elsif mdc'event and mdc = '1' then
if (mdio_count = "000010") then
mdio_addr <= '1'; -- reset at the start of a new access to enable the address to be revalidated
if last_mdio = '1' and mdio = '0' then
mdio_read <= '1';
else -- take a write as a default as won't drive at the wrong time
mdio_read <= '0';
end if;
elsif mdio_count <= "001100" then
-- check the phy_addr is 7 and the reg_addr is 0
if mdio_count <= "000111" and mdio_count >= "000101" then
if (mdio /= '1') then
mdio_addr <= '0';
end if;
else
if (mdio /= '0') then
mdio_addr <= '0';
end if;
end if;
elsif mdio_count = "001110" then
if mdio_read = '0' and (mdio = '1' or last_mdio = '0') then
assert false
report "ERROR - Write TA phase is incorrect" & cr
severity failure;
end if;
elsif (mdio_count >= "001111") and (mdio_count <= "011110") and mdio_addr = '1' then
if (mdio_read = '0') then
if (mdio_count = "010100") then
if (mdio = '1') then
mdio_fail <= '1';
assert false
report "ERROR - Expected bit 10 of mdio write data to be 0" & cr
severity failure;
end if;
else
if (mdio = '0') then
mdio_fail <= '1';
assert false
report "ERROR - Expected all except bit 10 of mdio write data to be 1" & cr
severity failure;
end if;
end if;
end if;
end if;
end if;
end process p_mdio_check;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
-- drives mii_tx_clk100 at 25 MHz
p_mii_tx_clk100 : process
begin
mii_tx_clk100 <= '0';
wait for 20 ns;
loop
wait for 20 ns;
mii_tx_clk100 <= '1';
wait for 20 ns;
mii_tx_clk100 <= '0';
end loop;
end process p_mii_tx_clk100;
-- drives mii_tx_clk10 at 2.5 MHz
p_mii_tx_clk10 : process
begin
mii_tx_clk10 <= '0';
wait for 10 ns;
loop
wait for 200 ns;
mii_tx_clk10 <= '1';
wait for 200 ns;
mii_tx_clk10 <= '0';
end loop;
end process p_mii_tx_clk10;
-- Select between 10Mb/s and 100Mb/s MII Tx clock frequencies
p_mii_tx_clk : process(phy_speed, mii_tx_clk100, mii_tx_clk10)
begin
if phy_speed = "11" then
mii_tx_clk <= '0';
elsif phy_speed = "01" then
mii_tx_clk <= mii_tx_clk100;
else
mii_tx_clk <= mii_tx_clk10;
end if;
end process p_mii_tx_clk;
-- Receiver and transmitter clocks are the same in this simulation: connect
-- the appropriate Tx clock source (based on operating speed) to the receiver
-- clock
gmii_rx_clk <= gmii_tx_clk when phy_speed = "10" else mii_tx_clk;
-- monitor frame error and output error when asserted
bist_mode_error_p : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if reset = '1' then
bist_mode_error <= '0';
elsif frame_error = '1' and bist_mode_error = '0' then
bist_mode_error <= '1';
assert false
report "Error: Frame mismatch seen" & cr
severity error;
end if;
end if;
end process bist_mode_error_p;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, and checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
p_management : process
-- Procedure to reset the MAC
------------------------------
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 400 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin -- process p_management
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
gen_tx_data <= '0';
check_tx_data <= '0';
config_bist <= '0';
-- reset the core
mac_reset;
wait until mdio_count = "100000";
wait until mdio_count = "000000";
if TB_MODE = "BIST" then
gen_tx_data <= '1';
check_tx_data <= '1';
-- run for a set time and then stop
wait for 100 us;
-- Our work here is done
if frame_error = '1' then
assert false
report "ERROR: Frame mismatch seen" & cr
severity failure;
elsif serial_response = '1' then
assert false
report "ERROR: AXI4 Lite state Machine error. Incorrect or non-existant PTP frame." & cr
severity failure;
else
assert false
report "Test completed successfully" & cr
severity note;
assert false
report "Simulation Stopped" & cr
severity failure;
end if;
else
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- The stimulus process will now send 5 frames at 1Gb/s.
--------------------------------------------------------------------
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
management_config_finished <= false;
-- Change the speed to 100Mb/s and send the 5 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "01";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
phy_speed <= "01";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_100M;
management_config_finished <= false;
-- Change the speed to 10Mb/s and send the 5 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "00";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
phy_speed <= "00";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_10M;
management_config_finished <= false;
-- Change the speed back to 1Gb/s and send the 4 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
wait;
end if;
end process p_management;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
---------------------------------------------------------------
-- Procedure to inject a frame into the receiver at 10/100Mb/s
---------------------------------------------------------------
procedure send_frame_10_100m (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 15 loop
gmii_rxd <= "00000101" after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "00001101" after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= "0000" & fcs(((8*j)+3) downto (8*j)) after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
gmii_rxd <= "0000" & fcs(((8*j)+7) downto ((8*j)+4)) after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after 30 ns;
gmii_rx_dv <= '0' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_10_100m;
begin
-- Send four frames through the MAC and Design Exampled
-- at each state Ethernet speed
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-------------------------------------------------------
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
wait for 10 ns;
-- 100 Mb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 100Mb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_10_100m(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_100M;
wait for 10 ns;
-- 10 Mb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 10Mb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_10_100m(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_10M;
wait for 10 ns;
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0' and bist_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
---------------------------------------------------
-- Procedure to check a transmitted frame at 1Gb/s
---------------------------------------------------
procedure check_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_type : string(1 to 4) := (others => ' ');
variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
if (addr_comp_reg /= address_filter_value) then
frame_filtered := 1;
else
frame_filtered := 0;
end if;
if (frame_filtered = 1) then
report "FRAME DROPPED by Address Filter" & cr ;
else
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
if TB_MODE = "DEMO" then
-- Start comparing transmitted data to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
else
frame_type := (others => ' ');
while (gmii_tx_en='1') loop
if current_col = 12 and gmii_txd = X"81" then
frame_type := "VLAN";
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
assert false
report frame_type & " Frame tramsmitted : Size " & integer'image(current_col) & cr
severity note;
end if;
end if;
end check_frame_1g;
--------------------------------------------------------
-- Procedure to check a transmitted frame at 10/100Mb/s
--------------------------------------------------------
procedure check_frame_10_100m (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
if (addr_comp_reg /= address_filter_value) then
frame_filtered := 1;
else
frame_filtered := 0;
end if;
if (frame_filtered = 1) then
report "FRAME DROPPED by Address Filter" & cr ;
else
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "00000101" loop
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop;
-- Start comparing transmitted dat to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "00001101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Destination Address field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Source Address field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd(3 downto 0) /= fcs(((8*j)+3) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd(3 downto 0) /= fcs(((8*j)+7) downto ((8*j)+4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop;
end if;
end check_frame_10_100m;
variable f : tri_mode_ethernet_mac_0_frame_typ; -- temporary frame variable
variable current_frame : natural := 0; -- current frame pointer
begin -- process p_monitor
-- Compare the transmitted frame to the received frames
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-- Repeated for all stated speeds.
-------------------------------------------------------
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset'event and reset = '0';
wait until management_config_finished;
wait for 300 ns;
if TB_MODE = "DEMO" then
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
-- 100 Mb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 100Mb/s frames.
-- loop over all the frames in the stimulus vector
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_10_100m(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_100M <= true;
tx_monitor_finished_1G <= false;
-- 10 Mb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 10Mb/s frames.
-- loop over all the frames in the stimulus vector
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_10_100m(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_10M <= true;
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
else
loop
check_frame_1g(current_frame);
end loop;
end if;
end process p_monitor;
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2380.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p04n01i02380ent IS
END c07s03b02x00p04n01i02380ent;
ARCHITECTURE c07s03b02x00p04n01i02380arch OF c07s03b02x00p04n01i02380ent IS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1|2 => 0, others => 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***PASSED TEST: c07s03b02x00p04n01i02380"
severity NOTE;
assert (C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***FAILED TEST: c07s03b02x00p04n01i02380 - The choices must be one or more choices separated with vertical bars(|)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p04n01i02380arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2380.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p04n01i02380ent IS
END c07s03b02x00p04n01i02380ent;
ARCHITECTURE c07s03b02x00p04n01i02380arch OF c07s03b02x00p04n01i02380ent IS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1|2 => 0, others => 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***PASSED TEST: c07s03b02x00p04n01i02380"
severity NOTE;
assert (C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***FAILED TEST: c07s03b02x00p04n01i02380 - The choices must be one or more choices separated with vertical bars(|)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p04n01i02380arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2380.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p04n01i02380ent IS
END c07s03b02x00p04n01i02380ent;
ARCHITECTURE c07s03b02x00p04n01i02380arch OF c07s03b02x00p04n01i02380ent IS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1|2 => 0, others => 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***PASSED TEST: c07s03b02x00p04n01i02380"
severity NOTE;
assert (C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
report "***FAILED TEST: c07s03b02x00p04n01i02380 - The choices must be one or more choices separated with vertical bars(|)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p04n01i02380arch;
|
package repro1 is
function return_true return boolean;
end repro1;
package body repro1 is
function slv_ones(constant width : in integer) return bit_vector is
begin
return (1 to width => '1');
end function;
function return_true return boolean is
constant ones_c : bit_vector(31 downto 0) := (others => '1');
begin
return ones_c = slv_ones(32);
end function;
end repro1;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.