content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file conta... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 30 10:05:42 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Autho... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:46 03/25/2016
-- Design Name:
-- Module Name: Fetch_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity InitialControl is
Port ( Clock : in STD_LOGIC;
Row : in STD_LOGIC_VECTOR (9 downto 0);
Column : in STD_LOGIC_VECTOR (9 downto 0);
DataOut : out STD_LOGIC_VECTOR (1 downto 0));
end InitialControl;
architect... |
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
w... |
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
w... |
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
w... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.08.2013 20:08:06
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- This should pass
context c1 is
end;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity buffer is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC);
end buffer;
architecture Behavioral of buffer is
begin
dout <= din when (en='0') else
"ZZZZZZZZ" when... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Paddle.vhd (Ball.vhd) --
-- --
-- Modeled of... |
--###############################
--# Project Name : MPU6050 demo
--# File : demo_mpu6050.vhd
--# Author : Philippe THIRION
--# Description : Check accelerometer to display gravity axis
--# Modification History
--# 2016/06/07
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
u... |
-------------------------------------------------------------------------------
-- Title : Wishbone trigger component toplevel
-- Project :
-------------------------------------------------------------------------------
-- File : wb_trigger_top.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_214;
architecture augh of mul_214 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_214;
architecture augh of mul_214 is
signal tmp_res : signed(... |
entity recur is
generic (
DEPTH : natural; delay : delay_length );
end entity;
architecture test of recur is
begin
base_g: if DEPTH = 0 generate
process is
begin
wait for delay;
report recur'path_name;
wait;
end process;
end generate;
... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
package three_multiple_types is
type three_state is (SAccept, S1, S2);
end package three_multiple_types;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : o... |
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ve... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:39:58 07/06/2014
-- Design Name:
-- Module Name: /home/tansell/foss/buffer/hdl/triple_buffer_arbiter_tb.vhd
-- Project Name: buffer
-- Target Device:
-- Tool versions:
-- Descript... |
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: heim@physik.uni-wuppertal.de
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
------------... |
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: heim@physik.uni-wuppertal.de
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
----------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLKFX_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm4 is
signal GND_BIT... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Control_Unit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- ------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity InstMem is
generic (BitWidth: integer;
InstructionWidth: integer);
port ( address : in std_logic_vector(BitWidth-1 downto 0);
data : out std_logic_vector(InstructionWidth-1 downto 0) );
end entit... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX2
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_exe2a4 IS
END TB_exe2a4;
ARCHITECTURE behavior OF TB_btn_led IS
COMPONENT btn_led
PORT(
btn : IN std_logic;
reset : IN std_logic;
ledA : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
si... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de fr... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de fr... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonLX9.vhd
-- ... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonLX9.vhd
-- ... |
library ieee;
use ieee.std_logic_1164.all;
entity dff09 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rstn : std_logic);
end dff09;
architecture behav of dff09 is
begin
process (clk, rstn) is
constant rval : std_logic := '0';
begin
if rstn = '0' then
q <= rval... |
--This file is auto-generated by compile_dspip_lib.pl
--Date:06/07/2007
--Time:19:15
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use auk_dspip_lib.auk_dspip_math_pkg.al... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/02 20:52:44
-- Nombre del módulo: pwm_dc_101 - behavior
-- Descripción:
-- Banco de pruebas para el módulo pwm_dc_101.vhd... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/02 20:52:44
-- Nombre del módulo: pwm_dc_101 - behavior
-- Descripción:
-- Banco de pruebas para el módulo pwm_dc_101.vhd... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS_pkg.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.nu... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS_pkg.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.nu... |
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
debug_out : out STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal shiftr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Notas:
-- La idea de este modulo es expandir la cantidad de registros disponibles
-- con 5 bits yo solo tengo 2**5 -1 registros. Las ventanas nos dejar ir moviendonos
-- para tener ma... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with SD feature set
--
-- $Id: chip-sd-a.vhd,v 1.7 2007-08-06 23:31:42 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ps2_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_... |
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