content stringlengths 1 1.04M ⌀ |
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--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 30 10:05:42 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-e.vhd,v 1.6 2005/11/30 14:04:19 wig Exp $
-- $Date: 2005/11/30 14:04:19 $
-- $Log: ent_ab-e.vhd,v $
-- Revision 1.6 2005/11/30 14:04:19 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ab
--
entity ent_ab is
-- Generics:
-- No Generated Generics for Entity ent_ab
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic; -- Use internally test1
port_ab_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_14 : in std_ulogic_vector(6 downto 0) -- Multiline comment 1
-- Multiline comment 2
-- Multiline comment 3
-- End of Generated Port for Entity ent_ab
);
end ent_ab;
--
-- End of Generated Entity ent_ab
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
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Spx5L6QG8uDnz1LaybdRCSDkznRBciBL8BqZcZd36Ap4YGLRUP0kIt6sL1zMhr4el7fx4FM1Rf7G
PSJ5I1TgVIIZ0EBbfDJtldhQcc/7wZRhy7ZDDEpxJwHxl6kofoY33JUu2zp+zHMGZUzqv4lfOIc2
mhkAqAmb+lPXteog1+ZyOK9Kx5QKyzmwadlJgalyYQsiNVdGh4pW9Sfj6vNDV+WHI2QSeJYuwXBv
ZRYC0mP6fXiP2I9wSI6mBOdyqFG6OxnIU0WsdbE55lIIT34ESqXP9lEX+PV+OvLsStd5HWOFZhHg
BZTqLG4jMhQq2eCfEqDh8f9c00jB5g5Gf8Eqt9stqZgnkqRkLJsvViH/PqFTRgKyXGSi2NKC+Eom
cPT7IHYOlAqfVBw6N3QvmCq4kXc5Z95o9+XiY+2/DOZjWfDdYitgeJk77tTtGLxzY1mNBN8fG1qi
WvaCuU/gaWv7VHK01i5KZZD3iZnzLMwg4YLRf74ZfdNnVC289Co01UBjJx/ndEZ4bsa2z4ndTGi6
cF9wSGojEgPqAIphsHXNQwZV2VkTVSClDpw8fEmlsX8u6simcqe9kQhiTedEzCEr3+jOPVGEaVjq
lPFy8vtzkR78qgyy4/LQGwe3+RF1Fpd0dYoY9ldwzOhlwc5Fdd3Qcs2Qdt4ULXA3oAvsOaXg4TDV
e1HZyvdNHe2TPwBzn7I9PmXwnsL7i6UOSEI6LISfR3mb4FwwMhHyMXpFaciuGsC/Sz01bJbF+cx7
eWmjZDI5ViaZ9Ks7U4dTJgWCw+JRMmMzM7d+qySvVDyhsQDd41F/BcdPAyH0u0DdoVRiQaeh3SHO
JJcUgU4djT5c8sHFdyzjM0tzjfecs8LhgnHb1rAB/oJStZcdWFOq6U12Fr/hpfnnIEPbbghmv6RG
dyy/UI1F2wyaaHJGGTbFW+IEIbsKH0zXlRUJ7HJonVXqN/JzXUqNHcN2INEmPwwO/jJJpf6Mghz4
xa6/DXOeaX3DPEztod2i5gG8oUg4Ml9fKZrF5p2JLDwHXWkg0QwQTh8Pipne1hIJ+0hCyN3YBi4S
afqq6EcTX+5pk0CZMvUVFRRWQQE+HMRYnDZcX/2j2Ad77r9kv/oqqhD9TcrO0bqD1Ck=
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:46 03/25/2016
-- Design Name:
-- Module Name: Fetch_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Fetch_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
RST : out STD_LOGIC;
INC : out STD_LOGIC;
PC_EN : out STD_LOGIC;
INST_EN : out STD_LOGIC);
end Fetch_CTL;
architecture Behavioral of Fetch_CTL is
begin
RST <= '0';
INC <= '1';
PC_EN <= '1';
INST_EN <= '1';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity InitialControl is
Port ( Clock : in STD_LOGIC;
Row : in STD_LOGIC_VECTOR (9 downto 0);
Column : in STD_LOGIC_VECTOR (9 downto 0);
DataOut : out STD_LOGIC_VECTOR (1 downto 0));
end InitialControl;
architecture Behavioral of InitialControl is
signal trimmed : STD_LOGIC_VECTOR(0 to 1599);
begin
memory: entity work.Initial PORT MAP(
clka => Clock,
addra => Row,
douta => trimmed);
DataOut <= trimmed(to_integer(unsigned(Column) * 2)) & trimmed(to_integer((unsigned(Column) * 2) + 1));
end Behavioral;
|
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
wait;
end process;
c: process is
begin
y <= 1;
wait;
end process;
end architecture;
|
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
wait;
end process;
c: process is
begin
y <= 1;
wait;
end process;
end architecture;
|
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
wait;
end process;
c: process is
begin
y <= 1;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.08.2013 20:08:06
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( clk : in std_ulogic;
reset_switch : in std_ulogic;
uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic;
sd_miso : in std_ulogic;
sd_power : out std_ulogic;
read_strobe_dbg : out std_ulogic);
end main;
architecture Behavioral of main is
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component test_program
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
component uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal sd_cs : std_ulogic := '1';
signal sd_clk : std_ulogic := '0';
-- Signals for UART_TX6
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_ulogic;
signal uart_tx_full : std_ulogic;
signal uart_tx_reset : std_ulogic;
-- Signals used to define baud rate
signal baud_count : integer range 0 to 53 := 0;
signal en_16_x_baud : std_ulogic := '0';
begin
cpu: kcpsm6
generic map ( hwbuild => X"00",
interrupt_vector => X"3FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset or (not reset_switch),
clk => clk);
kcpsm6_sleep <= '0';
interrupt <= '0';
read_strobe_dbg <= read_strobe;
programRom: test_program
generic map( C_FAMILY => "S6", --Family 'S6', 'V6' or '7S'
C_RAM_SIZE_KWORDS => 1, --Program size '1', '2' or '4'
C_JTAG_LOADER_ENABLE => 1) --Include JTAG Loader when set to '1'
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => kcpsm6_reset,
clk => clk);
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => open,
buffer_half_full => open,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
in_port <= (7 => sd_miso, 2 => uart_tx_full, others => '-');
--input_ports: process(clk)
--begin
-- if rising_edge(clk) then
-- case port_id(0) is
-- when '0' => in_port <= (7 => sd_miso, 6 downto 0 => '-');
-- when '1' => in_port(2) <= uart_tx_full;
-- when others => null;
-- end case;
-- end if;
--end process;
-- Always send CPU output to the UART...
uart_tx_data_in <= out_port;
-- But don't trigger a write unless the CPU output was actually meant for the UART (OUT on port 3).
write_to_uart_tx <= '1' when (write_strobe = '1' and port_id(0) = '1') else '0';
output_ports: process(clk)
begin
if rising_edge(clk) then
if write_strobe = '1' then
case port_id(0) is
when '0' =>
sd_clk <= out_port(0);
sd_cs <= out_port(1);
sd_mosi <= out_port(7);
--when '1' =>
-- write_to_uart_tx <= '1';
-- uart_tx_data_in <= out_port;
when others => null;
end case;
--else
-- write_to_uart_tx <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------------
-- RS232 (UART) baud rate
-----------------------------------------------------------------------------------------
--
-- To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
-- High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
-- a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
-- is only 0.5% high and well within limits.
--
baud_rate: process(clk)
begin
if rising_edge(clk) then
if baud_count = 53 then -- counts 54 states including zero
baud_count <= 0;
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if rising_edge(clk) then
if k_write_strobe = '1' then
uart_tx_reset <= out_port(0);
sd_power <= out_port(7);
end if;
end if;
end process constant_output_ports;
sd_cs_out <= sd_cs;
sd_clk_out <= sd_clk;
end Behavioral; |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- This should pass
context c1 is
end;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity buffer is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC);
end buffer;
architecture Behavioral of buffer is
begin
dout <= din when (en='0') else
"ZZZZZZZZ" when (en='1') else
"ZZZZZZZZ";
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3194.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03194ent IS
END c14s03b00x00p42n01i03194ent;
ARCHITECTURE c14s03b00x00p42n01i03194arch OF c14s03b00x00p42n01i03194ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.09";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,bit_vector'("11000011"));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03194 - This test will write TEXT into file iofile.09."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03194arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3194.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03194ent IS
END c14s03b00x00p42n01i03194ent;
ARCHITECTURE c14s03b00x00p42n01i03194arch OF c14s03b00x00p42n01i03194ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.09";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,bit_vector'("11000011"));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03194 - This test will write TEXT into file iofile.09."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03194arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3194.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03194ent IS
END c14s03b00x00p42n01i03194ent;
ARCHITECTURE c14s03b00x00p42n01i03194arch OF c14s03b00x00p42n01i03194ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.09";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,bit_vector'("11000011"));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03194 - This test will write TEXT into file iofile.09."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03194arch;
|
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Paddle.vhd (Ball.vhd) --
-- --
-- Modeled off ball.vhd version by Stephen Kempf and Viral Mehta --
-- --
-- by Raj Vinjamuri and Sai Koppula --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity paddle is
Port ( Up, Do, Le, Ri : in std_logic; --added direction signals to modify direction
Reset : in std_logic;
frame_clk : in std_logic;
PaddleX : out std_logic_vector(10 downto 0);
PaddleY : out std_logic_vector(10 downto 0);
PaddleS : out std_logic_vector(10 downto 0));
end paddle;
architecture Behavioral of paddle is
signal U, D, L, R : std_logic_vector (0 downto 0); --added signals to use for math needed to change motion vars
signal Paddle_X_Pos, Paddle_Y_Pos, Paddle_Y_motion, Paddle_X_motion : std_logic_vector(10 downto 0);
signal Paddle_Size : std_logic_vector(10 downto 0);
constant Paddle_X_Start : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(320, 11); --Center position on the X axis
constant Paddle_Y_Start : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(460, 11); --Center position on the Y axis
constant Paddle_X_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Leftmost point on the X axis
constant Paddle_X_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(639, 11); --Rightmost point on the X axis
constant Paddle_Y_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Topmost point on the Y axis
constant Paddle_Y_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(479, 11); --Bottommost point on the Y axis
constant Paddle_X_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(1, 11); --Step size on the X axis (modified)
constant Paddle_Y_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(1, 11); --Step size on the Y axis
begin
Paddle_Size <= CONV_STD_LOGIC_VECTOR(4, 11); -- assigns the value 4 as a 10-digit binary number, ie "0000000100"
U(0) <= Up; --set internal signal/vars
D(0) <= Do;
L(0) <= Le;
R(0) <= Ri;
Move_Paddle: process(Reset, frame_clk, Paddle_Size)
begin
if(Reset = '1') then --Asynchronous Reset
Paddle_Y_motion <= "00000000000"; --all the initial movement settings
Paddle_X_motion <= "00000000000";
Paddle_Y_Pos <= Paddle_Y_Start;
Paddle_X_Pos <= Paddle_X_Start;
elsif(rising_edge(frame_clk)) then
if ((R(0) or L(0)) = '1') then --see notes on up/down/y-direction
if (R(0) = '1')then
Paddle_X_Pos <= Paddle_X_Pos + "00000000011"; --Verify this works.
if (Paddle_X_Pos + ("00000000110"*Paddle_size) >= Paddle_X_Max) then
Paddle_X_Pos <= Paddle_X_Max - (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);
end if;
elsif (L(0) = '1') then
Paddle_X_Pos <= Paddle_X_Pos - "00000000011"; --Verify this works. update: this KINDA works
if (Paddle_X_Pos - ("00000000110"*Paddle_size) <= Paddle_X_Min ) then --change here to fix going off screen
Paddle_X_Pos <= Paddle_X_Min + (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);--Paddle_X_Min + (Paddle_Size + Paddle_Size);
end if;
--Paddle_X_Pos <= Paddle_X_Pos + "1111111101"; --Verify this works. update: this KINDA works
else Paddle_X_Pos <= Paddle_X_Pos;
end if;
end if;
--if (Paddle_X_Pos - ("00000000110"*Paddle_size) <= Paddle_X_Min + ("00000000110"*Paddle_size)) then --change here to fix going off screen
--Paddle_X_Pos <= Paddle_X_Min + (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);--Paddle_X_Min + (Paddle_Size + Paddle_Size);
-- if (Paddle_X_Pos + ("00000000110"*Paddle_size) >= Paddle_X_Max - ("00000000110"*Paddle_size)) then
--Paddle_X_Pos <= Paddle_X_Max - (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size); --if this were real I would take a steaming poop on it
--cant get this to work. Keeps showing up on the other side
--end if;
--Ball_Y_pos <= Ball_Y_pos + Ball_Y_Motion; -- Update ball position
--Ball_X_pos <= Ball_X_pos + Ball_X_Motion;
end if;
end process Move_Paddle;
PaddleX <= Paddle_X_Pos;
PaddleY <= Paddle_Y_Start;
PaddleS <= Paddle_Size;
end Behavioral;
|
--###############################
--# Project Name : MPU6050 demo
--# File : demo_mpu6050.vhd
--# Author : Philippe THIRION
--# Description : Check accelerometer to display gravity axis
--# Modification History
--# 2016/06/07
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DEMO_MPU6050 is
port(
MCLK : in std_logic;
RESET : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
LEDX : out std_logic;
LEDY : out std_logic;
LEDZ : out std_logic;
LEDSIGN : out std_logic
);
end DEMO_MPU6050;
architecture mixed of DEMO_MPU6050 is
-- COMPONENTS --
component MPU6050
port(
MCLK : in std_logic;
nRST : in std_logic;
TIC : in std_logic;
SRST : out std_logic;
DOUT : out std_logic_vector(7 downto 0);
RD : out std_logic;
WE : out std_logic;
QUEUED : in std_logic;
NACK : in std_logic;
STOP : in std_logic;
DATA_VALID : in std_logic;
DIN : in std_logic_vector(7 downto 0);
ADR : out std_logic_vector(3 downto 0);
DATA : out std_logic_vector(7 downto 0);
LOAD : out std_logic;
COMPLETED : out std_logic;
RESCAN : in std_logic
);
end component;
component I2CMASTER
generic(
DEVICE : std_logic_vector(7 downto 0)
);
port(
MCLK : in std_logic;
nRST : in std_logic;
SRST : in std_logic;
TIC : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RD : in std_logic;
WE : in std_logic;
NACK : out std_logic;
QUEUED : out std_logic;
DATA_VALID : out std_logic;
STATUS : out std_logic_vector(2 downto 0);
STOP : out std_logic;
SCL_IN : in std_logic;
SCL_OUT : out std_logic;
SDA_IN : in std_logic;
SDA_OUT : out std_logic
);
end component;
-- COMPONENTS --
component COMPARE
port(
MCLK : in std_logic;
nRST : in std_logic;
TIC : in std_logic;
COMPLETED : in std_logic;
RESCAN : out std_logic;
XREG : in std_logic_vector(7 downto 0);
YREG : in std_logic_vector(7 downto 0);
ZREG : in std_logic_vector(7 downto 0);
LEDX : out std_logic;
LEDY : out std_logic;
LEDZ : out std_logic;
SIGN : out std_logic
);
end component;
--
-- SIGNALS --
signal XREG : std_logic_vector(7 downto 0);
signal YREG : std_logic_vector(7 downto 0);
signal ZREG : std_logic_vector(7 downto 0);
--
--
-- SIGNALS --
signal TIC : std_logic;
signal SRST : std_logic;
signal DOUT : std_logic_vector(7 downto 0);
signal RD : std_logic;
signal WE : std_logic;
signal QUEUED : std_logic;
signal NACK : std_logic;
signal STOP : std_logic;
signal DATA_VALID : std_logic;
signal DIN : std_logic_vector(7 downto 0);
signal ADR : std_logic_vector(3 downto 0);
signal DATA : std_logic_vector(7 downto 0);
signal LOAD : std_logic;
signal COMPLETED : std_logic;
signal RESCAN : std_logic;
signal STATUS : std_logic_vector(2 downto 0);
signal SCL_IN : std_logic;
signal SCL_OUT : std_logic;
signal SDA_IN : std_logic;
signal SDA_OUT : std_logic;
signal counter : std_logic_vector(7 downto 0);
--signal counter : std_logic_vector(10 downto 0);
signal nRST : std_logic;
--
begin
nRST <= not(RESET);
-- PORT MAP --
I_MPU6050_0 : MPU6050
port map (
MCLK => MCLK,
nRST => nRST,
TIC => TIC,
SRST => SRST,
DOUT => DIN,
RD => RD,
WE => WE,
QUEUED => QUEUED,
NACK => NACK,
STOP => STOP,
DATA_VALID => DATA_VALID,
DIN => DOUT,
ADR => ADR,
DATA => DATA,
LOAD => LOAD,
COMPLETED => COMPLETED,
RESCAN => RESCAN
);
-- PORT MAP --
I_I2CMASTER_0 : I2CMASTER
generic map (
DEVICE => x"68"
)
port map (
MCLK => MCLK,
nRST => nRST,
SRST => SRST,
TIC => TIC,
DIN => DIN,
DOUT => DOUT,
RD => RD,
WE => WE,
NACK => NACK,
QUEUED => QUEUED,
DATA_VALID => DATA_VALID,
STOP => STOP,
STATUS => STATUS,
SCL_IN => SCL_IN,
SCL_OUT => SCL_OUT,
SDA_IN => SDA_IN,
SDA_OUT => SDA_OUT
);
-- PORT MAP --
I_COMPARE_0 : COMPARE
port map (
MCLK => MCLK,
nRST => nRST,
TIC => TIC,
COMPLETED => COMPLETED,
RESCAN => RESCAN,
XREG => XREG,
YREG => YREG,
ZREG => ZREG,
LEDX => LEDX,
LEDY => LEDY,
LEDZ => LEDZ,
SIGN => LEDSIGN
);
--
TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit
--TIC <= counter(10) and counter(8);
GEN: process(MCLK, nRST)
begin
if (nRST = '0') then
counter <= (others=>'0');
elsif (MCLK'event and MCLK='1') then
if (TIC = '1') then
counter <= (others=>'0');
else
counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8));
--counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1,11));
end if;
end if;
end process GEN;
REGS: process(MCLK, nRST)
begin
if (nRST = '0') then
XREG <= (others=>'0');
YREG <= (others=>'0');
ZREG <= (others=>'0');
elsif (MCLK'event and MCLK = '1') then
if (TIC = '1' and LOAD = '1') then
if (ADR = x"0") then
XREG <= DATA;
elsif (ADR = x"2") then
YREG <= DATA;
elsif (ADR = x"4") then
ZREG <= DATA;
end if;
end if;
end if;
end process REGS;
-- open drain PAD pull up 1.5K needed
SCL <= 'Z' when SCL_OUT='1' else '0';
SCL_IN <= to_UX01(SCL);
SDA <= 'Z' when SDA_OUT='1' else '0';
SDA_IN <= to_UX01(SDA);
end mixed;
|
-------------------------------------------------------------------------------
-- Title : Wishbone trigger component toplevel
-- Project :
-------------------------------------------------------------------------------
-- File : wb_trigger_top.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-02-02
-- Last update: 2016-05-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-02 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Trigger definitons
use work.trigger_pkg.all;
-- Positicon Calc constants
use work.machine_pkg.all;
-- Genrams
use work.genram_pkg.all;
-- Meta Package
--use work.synthesis_descriptor_pkg.all;
-- AXI cores
--use work.pcie_cntr_axi_pkg.all;
use work.bpm_pcie_a7_const_pkg.all;
-- PCIe Core
use work.bpm_pcie_a7_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity wb_trigger_top is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- PCIe pins
-----------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
-- Trigger signals
trig_dir_o : out std_logic_vector(7 downto 0);
trig_b : inout std_logic_vector(7 downto 0)
);
end wb_trigger_top;
architecture structural of wb_trigger_top is
-------------------------------------------------------------------------------
-- Chipscope
-------------------------------------------------------------------------------
component chipscope_icon_1_port is
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon_1_port;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component chipscope_ila;
component chipscope_vio_16 is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
SYNC_OUT : out std_logic_vector(15 downto 0));
end component chipscope_vio_16;
-----------------------------------------------------------------------------
-- Clock and system
-----------------------------------------------------------------------------
component clk_gen is
port (
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic);
end component clk_gen;
component sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_divclk_divide : integer := 1;
g_clkbout_mult_f : integer := 5;
-- Reference jitter
g_ref_jitter : real := 0.010;
-- 100 MHz output clock
g_clk0_divide_f : integer := 10;
-- 200 MHz output clock
g_clk1_divide : integer := 5;
g_clk2_divide : integer := 6
);
port (
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
clk2_o : out std_logic;
locked_o : out std_logic);
end component sys_pll;
-- Constants
constant c_width_bus_size : positive := 8;
constant c_rcv_len_bus_width : positive := 8;
constant c_transm_len_bus_width : positive := 8;
constant c_sync_edge : string := "positive";
constant c_trig_num : positive := 8;
constant c_intern_num : positive := 8;
constant c_rcv_intern_num : positive := 2;
constant c_counter_wid : positive := 16;
constant c_num_tlvl_clks : natural := 3;
constant c_masters : natural := 1;
constant c_slaves : natural := 3;
constant c_slv_trigger_iface_id : natural := 0;
constant c_slv_trigger_mux0_id : natural := 1;
constant c_slv_trigger_mux1_id : natural := 2;
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(
c_slv_trigger_iface_id => f_sdb_embed_device(c_xwb_trigger_iface_sdb, x"10000000"),
c_slv_trigger_mux0_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"20000000"),
c_slv_trigger_mux1_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"30000000")
);
constant c_button_rst_width : natural := 255;
constant c_sdb_address : t_wishbone_address := x"00000000";
constant c_ma_pcie_id : natural := 0;
constant c_num_mux_interfaces : natural := 2;
signal c_clk_sys_id : natural := 0;
signal c_clk_200mhz_id : natural := 1;
signal c_clk_133mhz_id : natural := 2;
signal CONTROL0 : std_logic_vector(35 downto 0);
-- Global Clock Single ended
signal clk_sys, clk_200mhz, clk_133mhz : std_logic;
signal sys_clk_gen_bufg : std_logic;
signal sys_clk_gen : std_logic;
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_pcie_rstn : std_logic;
signal clk_sys_pcie_rst : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_200mhz_rst : std_logic;
signal clk_200mhz_rstn : std_logic;
signal clk_133mhz_rst : std_logic;
signal clk_133mhz_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal wb_ma_pcie_rst : std_logic;
signal wb_ma_pcie_rstn : std_logic;
signal wb_ma_pcie_rstn_sync : std_logic;
signal wb_slv_in : t_wishbone_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal trig_rcv_intern : t_trig_channel_array2d(1 downto 0, 1 downto 0);
signal trig_pulse_transm : t_trig_channel_array2d(1 downto 0, 7 downto 0);
signal trig_pulse_rcv : t_trig_channel_array2d(1 downto 0, 7 downto 0);
signal trig_dir_int : std_logic_vector(7 downto 0);
begin
cmp_chipscope_icon_1 : chipscope_icon_1_port
port map (
CONTROL0 => CONTROL0);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_133mhz,
TRIG0(31 downto 24) => trig_dir_int,
TRIG0(23) => trig_pulse_rcv(0, 7).pulse,
TRIG0(22) => trig_pulse_rcv(0, 6).pulse,
TRIG0(21) => trig_pulse_rcv(0, 5).pulse,
TRIG0(20) => trig_pulse_rcv(0, 4).pulse,
TRIG0(19) => trig_pulse_rcv(0, 3).pulse,
TRIG0(18) => trig_pulse_rcv(0, 2).pulse,
TRIG0(17) => trig_pulse_rcv(0, 1).pulse,
TRIG0(16) => trig_pulse_rcv(0, 0).pulse,
TRIG0(15) => trig_pulse_transm(0, 7).pulse,
TRIG0(14) => trig_pulse_transm(0, 6).pulse,
TRIG0(13) => trig_pulse_transm(0, 5).pulse,
TRIG0(12) => trig_pulse_transm(0, 4).pulse,
TRIG0(11) => trig_pulse_transm(0, 3).pulse,
TRIG0(10) => trig_pulse_transm(0, 2).pulse,
TRIG0(9) => trig_pulse_transm(0, 1).pulse,
TRIG0(8) => trig_pulse_transm(0, 0).pulse,
TRIG0(7 downto 2) => (others => '0'),
TRIG0(1) => trig_rcv_intern(0, 1).pulse,
TRIG0(0) => trig_rcv_intern(0, 0).pulse,
TRIG1 => (others => '0'),
TRIG2 => (others => '0'),
TRIG3 => (others => '0'));
trig_dir_o <= trig_dir_int;
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen,
sys_clk_bufg_o => sys_clk_gen_bufg
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
generic map (
-- 125 MHz input clock
g_clkin_period => 8.000,
g_divclk_divide => 5,
g_clkbout_mult_f => 32,
-- 100 MHz output clock
g_clk0_divide_f => 8,
-- 200 MHz output clock
g_clk1_divide => 4,
-- 133 MHz output clock
g_clk2_divide => 6
)
port map (
rst_i => '0',
clk_i => sys_clk_gen_bufg,
--clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
clk2_o => clk_133mhz, -- 133MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200
)
port map(
--free_clk_i => sys_clk_gen,
free_clk_i => sys_clk_gen_bufg,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= clk_sys;
reset_clks(c_clk_200mhz_id) <= clk_200mhz;
reset_clks(c_clk_133mhz_id) <= clk_133mhz;
-- Reset for PCIe core. Caution when resetting the PCIe core after the
-- initialization. The PCIe core needs to retrain the link and the PCIe
-- host (linux OS, likely) will not be able to do that automatically,
-- probably.
clk_sys_pcie_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n;
clk_sys_pcie_rst <= not clk_sys_pcie_rstn;
-- Reset for all other modules
clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and
wb_ma_pcie_rstn_sync;
clk_sys_rst <= not clk_sys_rstn;
-- Reset synchronous to clk200mhz
clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id);
clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id));
-- Reset synchronous to clk133mhz
clk_133mhz_rstn <= reset_rstn(c_clk_133mhz_id);
clk_133mhz_rst <= not(reset_rstn(c_clk_133mhz_id));
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => '0', --sys_rst_button_n_i,
npulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched gc
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
--lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Button(0).
-- Interrupts 31 downto 1 are disabled
--lm32_interrupt <= (0 => not buttons_i(0), others => '0');
----------------------------------
-- PCIe Core --
----------------------------------
cmp_xwb_bpm_pcie_a7 : xwb_bpm_pcie_a7
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE,
g_ext_rst_pin => false,
g_sim_bypass_init_cal => "OFF"
)
port map (
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- Necessity signals
ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL)
pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin)
pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock
pcie_rst_n_i => clk_sys_pcie_rstn, -- PCIe core reset
-- DDR memory controller interface --
ddr_core_rst_i => clk_sys_pcie_rst,
memc_ui_clk_o => open,
memc_ui_rst_o => open,
memc_cmd_rdy_o => open,
memc_cmd_en_i => '0',
memc_cmd_instr_i => (others => '0'),
memc_cmd_addr_i => (others => '0'),
memc_wr_en_i => '0',
memc_wr_end_i => '0',
memc_wr_mask_i => (others => '0'),
memc_wr_data_i => (others => '0'),
memc_wr_rdy_o => open,
memc_rd_data_o => open,
memc_rd_valid_o => open,
---- memory arbiter interface
memarb_acc_req_i => '0',
memarb_acc_gnt_o => open,
-- Wishbone interface --
wb_clk_i => clk_sys,
-- Reset wishbone interface with the same reset as the other
-- modules, including a reset coming from the PCIe itself.
wb_rst_i => clk_sys_rst,
wb_ma_i => cbar_slave_o(c_ma_pcie_id),
wb_ma_o => cbar_slave_i(c_ma_pcie_id),
-- Additional exported signals for instantiation
wb_ma_pcie_rst_o => wb_ma_pcie_rst,
-- Debug signals
dbg_app_addr_o => open,
dbg_app_cmd_o => open,
dbg_app_en_o => open,
dbg_app_wdf_data_o => open,
dbg_app_wdf_end_o => open,
dbg_app_wdf_wren_o => open,
dbg_app_wdf_mask_o => open,
dbg_app_rd_data_o => open,
dbg_app_rd_data_end_o => open,
dbg_app_rd_data_valid_o => open,
dbg_app_rdy_o => open,
dbg_app_wdf_rdy_o => open,
dbg_ddr_ui_clk_o => open,
dbg_ddr_ui_reset_o => open,
dbg_arb_req_o => open,
dbg_arb_gnt_o => open
);
wb_ma_pcie_rstn <= not wb_ma_pcie_rst;
cmp_pcie_reset_synch : reset_synch
port map
(
clk_i => clk_sys,
arst_n_i => wb_ma_pcie_rstn,
rst_n_o => wb_ma_pcie_rstn_sync
);
cmp_xwb_trigger : xwb_trigger
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_sync_edge => c_sync_edge,
g_trig_num => c_trig_num,
g_intern_num => c_intern_num,
g_rcv_intern_num => c_rcv_intern_num,
g_num_mux_interfaces => c_num_mux_interfaces,
g_out_resolver => "fanout",
g_in_resolver => "or"
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys,
ref_clk_i => clk_133mhz,
ref_rst_n_i => clk_133mhz_rstn,
fs_clk_array_i => (clk_133mhz, clk_133mhz),
fs_rst_n_array_i => (clk_133mhz_rstn, clk_133mhz_rstn),
wb_slv_trigger_iface_i => cc_dummy_slave_in,
wb_slv_trigger_iface_o => open,
wb_slv_trigger_mux_i => (cc_dummy_slave_in, cc_dummy_slave_in),
wb_slv_trigger_mux_o => open,
trig_dir_o => trig_dir_int,
trig_rcv_intern_i => trig_rcv_intern,
trig_pulse_transm_i => trig_pulse_transm,
trig_pulse_rcv_o => trig_pulse_rcv,
trig_b => trig_b);
end architecture structural;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_214;
architecture augh of mul_214 is
signal tmp_res : signed(63 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(40 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_214;
architecture augh of mul_214 is
signal tmp_res : signed(63 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(40 downto 0));
end architecture;
|
entity recur is
generic (
DEPTH : natural; delay : delay_length );
end entity;
architecture test of recur is
begin
base_g: if DEPTH = 0 generate
process is
begin
wait for delay;
report recur'path_name;
wait;
end process;
end generate;
recur_g: if DEPTH > 0 generate
recur1_i: entity work.recur
generic map (
DEPTH => DEPTH - 1, delay => delay );
recur2_i: entity work.recur
generic map (
DEPTH => DEPTH - 1, delay => delay + (2**(depth-1)) * ns );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab13 is
end entity;
architecture test of elab13 is
begin
top_i: entity work.recur
generic map (
DEPTH => 3, delay => 0 ns );
end architecture;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2012-03-13 1.1 wterpstra Added initial value as array
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram;
architecture syn of generic_dpram is
component generic_dpram_sameclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_dualclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
gen_single_clk : if(g_dual_clock = false) generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
clkb_i => clkb_i,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_dual_clk;
end syn;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
package three_multiple_types is
type three_state is (SAccept, S1, S2);
end package three_multiple_types;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : AMBA_TestPackage (Package and body declarations)
--
-- File name : amba_tp.vhd
--
-- Purpose : AMBA AHB and APB interface access procedures
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:support@gaisler.com
-- http://www.aeroflex.com/gaisler
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
-- 0.1 SH 15 Mar 2002 New package
-- 0.2 SH 17 Mar 2003 Updated most packages
-- 0.3 SH 20 May 2003 Memory based on Integer elements
-- 0.4 SH 1 Jul 2003 Name of package changed
-- Compare function improved
-- AHB 32 bit memory with preload added
-- AHB initialisation added
-- 0.5 SH 21 Jul 2003 AHB 32 memory with diagnostics added
-- 0.6 SH 1 Nov 2003 APB read access data sample made earlier
-- AHB 32 memory extended with byte/halfword
-- 0.7 SH 25 Jan 2004 AHB read access data output corrected
-- AHB 32 memory allows overlay addressing
-- 1.7 SH 1 Oct 2004 Ported to GRLIB
-- 1.8 SH 1 Jul 2005 Added configuration support for memories
-- Modified all procedure declarations
-- 1.9 SH 10 Nov 2005 AHB 32 responds with HREADY=0 when error
-- 1.11 SH 27 Dec 2004 Split support added, using HSPLIT element
-- Proper two-cycle error response implemented
-- 1.12 SH 15 Feb 2006 Added bank select to AHB bus accesses
-- 1.13 SH 1 May 2009 AHBQuite gave incorrect TP on error resps.
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.StdLib.all;
use GRLIB.StdIO.all;
package AMBA_TestPackage is
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Initialise AMBA AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Diagnstics types for behavioural model of memory with AHB interface
-----------------------------------------------------------------------------
type AHB_Diagnostics_In_Type is
record
HADDR: Std_Logic_Vector(31 downto 0);
HWRITE: Std_ULogic;
HWDATA: Std_Logic_Vector(31 downto 0);
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HSPLIT: Std_Logic_Vector(NAHBMST-1 downto 0); -- split completion
end record AHB_Diagnostics_In_Type;
type AHB_Diagnostics_Out_Type is
record
HRDATA: Std_Logic_Vector(31 downto 0);
end record AHB_Diagnostics_Out_Type;
constant AHB_Diagnostics_Init: AHB_Diagnostics_In_Type :=
(X"00000000", '0', X"00000000", HRESP_OKAY, zero32(NAHBMST-1 downto 0));
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AMBA AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
end AMBA_TestPackage;
--============================================================================--
package body AMBA_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (O(i)=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clk: in Std_ULogic;
constant Offset: in Time := 5 ns) is
begin
wait until CLK = '1'; -- Synchronise
wait for Offset; -- output offset delay
end procedure Synchronise;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '0');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB initalised"));
WriteLine(Output, L);
end if;
end procedure APBInit;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '1';
APBIn.PWDATA <= Data;
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
end procedure APBWrite;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
wait for 5 ns;
Data := APBOut.PRDATA;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
end procedure APBQuiet;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Temp, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
Data := Temp;
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : APB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
end if;
end procedure APBRead;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Data, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
if not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
RxData := Data;
end procedure APBComp;
-----------------------------------------------------------------------------
-- Initialise AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '0');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '0';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure AHBInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK); -- first clock period
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= ahbdrivedata(Data);
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
begin
AHBWriteQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure AHBWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
Data := AHBOut.HRDATA(31 downto 0);
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
AHBQuiet(Address, Temp, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Data := Temp;
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure AHBRead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
variable Failed: Boolean;
begin
AHBQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure AHBComp;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
subtype ARange is Natural range 0 to 2**gAWidth-1;
subtype DRange is Natural range 0 to gDWidth-1;
type MType is array (ARange) of Integer;
-- memory initialisation
function Init return MType is
variable r: MType;
begin
for i in ARange loop
r(i) := -1;
end loop;
return r;
end function Init;
variable M: MType;
variable A: Std_Logic_Vector(gAWidth-1 downto 0);
variable D: Std_Logic_Vector(0 to gDWidth-1);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
variable alow : std_logic_vector(1 downto 0);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
alow := A(1 downto 0);
case alow is
when "00" =>
D := AHBIn.HWDATA(31 downto 24);
when "01" =>
D := AHBIn.HWDATA(23 downto 16);
when "10" =>
D := AHBIn.HWDATA(15 downto 8);
when others =>
D := AHBIn.HWDATA( 7 downto 0);
end case;
M(Conv_Integer(A)) := Conv_Integer(D);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_BYTE and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 0);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
D := Conv_Std_Logic_Vector(
M(Conv_Integer(A)), D'Length);
case alow is
when "00" =>
AHBOut.HRDATA(31 downto 24) <= D;
when "01" =>
AHBOut.HRDATA(23 downto 16) <= D;
when "10" =>
AHBOut.HRDATA(15 downto 8) <= D;
when others =>
AHBOut.HRDATA( 7 downto 0) <= D;
end case;
else
w :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
M(Conv_Integer(A)) := AHBIn.HWDATA(31 downto 0);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_WORD and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
else
W :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
variable L: Line;
constant Padding: Std_ULogic_Vector(1 to
(4-((gAWidth-2) mod 4))) :=
(others => '0');
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable B: Std_Logic_Vector(1 downto 0);
variable W: Std_Logic;
variable S: Std_Logic_Vector(2 downto 0);
variable D: Std_Logic_Vector(31 downto 0);
variable twocycle:Boolean := False;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
twocycle := False;
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
-- read back memory
D := M(Conv_Integer(A));
-- replace with new data
if S="000" then -- byte
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 24) &
D(23 downto 0);
elsif B(1 downto 0)="01" then
D := D(31 downto 24) &
AHBIn.HWDATA(23 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 8) &
D(7 downto 0);
elsif B(1 downto 0)="11" then
D := D(31 downto 8) &
AHBIn.HWDATA(7 downto 0);
end if;
elsif S="001" then -- halfword
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 0);
end if;
else
D := AHBIn.HWDATA(31 downto 0);
end if;
-- write back memory
M(Conv_Integer(A)) := D;
W := '0';
-- comment
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath & " Write acces to address :");
if Padding'Length > 0 and Padding'Length < 4 then
HWrite(L, Std_Logic_Vector(Padding) & Std_Logic_Vector(A));
else
HWrite(L, Std_Logic_Vector(A));
end if;
Write(L, String'(" data :"));
HWrite(L, D);
Write(L, String'(" data :"));
Write(L, To_BitVector(D));
Write(L, String'(" size :"));
HWrite(L, "0" & S);
WriteLine(Output, L);
end if;
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
(AHBIn.HSIZE=HSIZE_BYTE or
AHBIn.HSIZE=HSIZE_HWORD or
AHBIn.HSIZE=HSIZE_WORD) and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
if AHBInDiag.HRESP=HRESP_OKAY then
W := AHBIn.HWRITE;
S := AHBIn.HSIZE;
B := AHBIn.HADDR( 1 downto 0);
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
elsif AHBInDiag.HRESP=HRESP_RETRY then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_RETRY;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
elsif AHBInDiag.HRESP=HRESP_SPLIT then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_SPLIT;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
else
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_ERROR;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
end if;
else
W :='0';
AHBOut.HREADY <= '1';
if twocycle then
twocycle := False;
else
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
end if;
if HCLK'Event and HCLK='1' then -- rising edge
-- diagnostics
AHBOutDiag.HRData <= M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2)));
if AHBInDiag.HWrite='1' then
M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2))) := AHBInDiag.HWData;
-- Print("Diagnostic write to memory, address: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HAddr)) &
-- " data: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HWData)));
end if;
AHBOut.HSPLIT <= AHBInDiag.HSplit;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : WrAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWData <= Data;
AHBInDiag.HWrite <= '1';
Synchronise(HCLK);
AHBInDiag.HWrite <= '0';
end procedure WrAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RdAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(AHBOutDiag.HRData));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RdAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable Data: Std_Logic_Vector(31 downto 0);
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if not Compare(Data, Expected) then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(", value: "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(", expected: "));
HWrite(L, Std_Logic_Vector(Expected));
Write(L, String'(" # Error "));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
TP := False;
elsif Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Expected));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RcAHBMem32;
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
AHBInDiag.HSPLIT(Split) <= '1';
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : SplitAHBMem32: split acknowledge to master: "));
Write(L, Split);
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure SplitAHBMem32;
end package body AMBA_TestPackage; --=========================================--
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_binomial_gen is
generic (
width : integer := 32);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end faultify_binomial_gen;
architecture behav of faultify_binomial_gen is
signal prob_srl : std_logic_vector(width-1 downto 0);
signal prsn_srl : std_logic_vector(63 downto 0);
signal prsn_srl_in : std_logic;
signal prob_srl_in : std_logic;
type TapPointArray is array (3 downto 0) of integer;
constant Tap : TapPointArray := (63, 62, 60, 59);
signal par_fdbk : std_logic;
signal cnt : integer range 0 to width;
signal prsn_out, prob_out, done : std_logic;
begin -- behav
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
--prob_srl <= (others => '0');
--prsn_srl <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
prob_srl <= prob_srl_in & prob_srl(prob_srl'high downto 1);
prsn_srl <= prsn_srl(prsn_srl'high-1 downto 0) & prsn_srl_in;
end if;
end if;
end process;
prsn_srl_in <= seed_in when seed_in_en = '1' else par_fdbk;
prob_srl_in <= prob_in when prob_in_en = '1' else prob_srl(prob_srl'low);
par_fdbk <= prsn_srl(Tap(0)) xor prsn_srl(Tap(1)) xor prsn_srl(Tap(2)) xor prsn_srl(Tap(3));
prob_out <= prob_srl(prob_srl'low);
prsn_out <= prsn_srl(prsn_srl'high);
prob_out_c <= prob_out;
seed_out_c <= prsn_out;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= 0;
data_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if shift_en = '1' then
cnt <= cnt + 1;
if cnt < width and done = '0' then
if (prsn_out = '0') and (prob_out = '1') then
data_out <= '1';
done <= '1';
--data_out_valid <= '1';
elsif prsn_out = '1' and prob_out = '0' then
data_out <= '0';
done <= '1';
--data_out_valid <= '1';
else
done <= '0';
--data_out <= '0';
--data_out_valid <= '0';
end if;
end if;
if cnt = width -1 then
done <= '0';
cnt <= 0;
--data_out_valid <= '0';
end if;
--if done = '1' then
--data_out_valid <= '0';
--end if;
end if;
end if;
end process;
end;
|
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:39:58 07/06/2014
-- Design Name:
-- Module Name: /home/tansell/foss/buffer/hdl/triple_buffer_arbiter_tb.vhd
-- Project Name: buffer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: triple_buffer_arbiter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY triple_buffer_arbiter_tb IS
END triple_buffer_arbiter_tb;
ARCHITECTURE behavior OF triple_buffer_arbiter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT triple_buffer_arbiter
generic (
offset : integer;
size : integer;
addr : integer := 32);
PORT(
input_clk : IN std_logic;
output_clk : IN std_logic;
input_addr : OUT unsigned(7 downto 0);
output_addr : OUT unsigned(7 downto 0);
rst : IN std_logic);
END COMPONENT;
--Inputs
signal input_clk : std_logic := '0';
signal output_clk : std_logic := '0';
signal rst : std_logic := '0';
signal evt : std_logic := '0';
--Outputs
signal input_addr : unsigned(7 downto 0);
signal expected_input_addr : unsigned(7 downto 0);
signal output_addr : unsigned(7 downto 0);
signal expected_output_addr : unsigned(7 downto 0);
-- Clock period definitions
constant addr_delay : time := 5 ns;
constant buffer0_addr : unsigned(7 downto 0) := to_unsigned(100, 8);
constant buffer1_addr : unsigned(7 downto 0) := to_unsigned(120, 8);
constant buffer2_addr : unsigned(7 downto 0) := to_unsigned(140, 8);
BEGIN
evt <= rst or input_clk or output_clk;
-- Instantiate the Unit Under Test (UUT)
uut: triple_buffer_arbiter
GENERIC MAP (
offset => 100,
size => 20,
addr => 8)
PORT MAP (
input_clk => input_clk,
output_clk => output_clk,
input_addr => input_addr,
output_addr => output_addr,
rst => rst);
-- Stimulus process
stim_proc: process
procedure Reset is
begin
wait for 35 ns;
expected_input_addr <= "UUUUUUUU";
expected_output_addr <= "UUUUUUUU";
rst <= '1';
wait for 1 ns;
rst <= '0';
wait for 35 ns;
end procedure;
procedure ExpectedInputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
input_clk <= '1';
wait for addr_delay;
expected_input_addr <= expected_value;
end procedure;
procedure ExpectedInputClear is
begin
wait for 5 ns;
input_clk <= '0';
expected_input_addr <= "UUUUUUUU";
end procedure;
procedure ExpectedOutputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
output_clk <= '1';
wait for addr_delay;
expected_output_addr <= expected_value;
end procedure;
procedure ExpectedOutputClear is
begin
wait for 5 ns;
output_clk <= '0';
expected_output_addr <= "UUUUUUUU";
end procedure;
begin
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Write starts, should go to buffer1
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Write starts, should go to buffer2
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-------------------------------------------------------------------
-- Finished the initial write tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Read, should get the last input_addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Make sure read keeps getting the same addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Advance the input buffer
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Read should have advanced to the next addr
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
-- Go around the buffer
----
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
----
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
----
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-------------------------------------------------------------------
-- Finished the initial read tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Start reading from the first buffer, make sure the writer bounced
-- between the two remaining buffers
ExpectedOutputAddr(buffer0_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Release the reader, should write to buffer0 now
ExpectedOutputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Try again, except reading from buffer2
ExpectedOutputAddr(buffer2_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedOutputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
Reset;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: heim@physik.uni-wuppertal.de
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
----------------------------------------------------------------------------------
-- Changelog:
-- 20.02.2011 - Initial Version
----------------------------------------------------------------------------------
-- TODO:
-- 20.02.2011 - Add DMA capability
----------------------------------------------------------------------------------
-- Address Map:
-- 0x020 to 0x02F
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library work;
--use work.bocpack.all;
entity bram_wbs is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic
);
end bram_wbs;
architecture Behavioral of bram_wbs is
type ram_type is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM: ram_type;
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_cyc_s : std_logic;
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
for i in 0 to 2**ADDR_WIDTH-1 loop
RAM(i) <= conv_std_logic_vector(i,RAM(i)'length); -- "DEAD0001BEEF0001"
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH/2) <= conv_std_logic_vector(i,RAM(i)'length/2);
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH-4*4) <= x"DEAD";
RAM(i)(DATA_WIDTH-1-DATA_WIDTH/2 downto DATA_WIDTH-4*4-DATA_WIDTH/2) <= x"BEEF";
end loop;
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
RAM(conv_integer(ADDR)) <= wb_dat_i;
end if;
wb_dat_o <= RAM(conv_integer(ADDR)) ;
else
wb_ack_o <= '0';
end if;
end if;
end process bram;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: heim@physik.uni-wuppertal.de
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
----------------------------------------------------------------------------------
-- Changelog:
-- 20.02.2011 - Initial Version
----------------------------------------------------------------------------------
-- TODO:
-- 20.02.2011 - Add DMA capability
----------------------------------------------------------------------------------
-- Address Map:
-- 0x020 to 0x02F
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library work;
--use work.bocpack.all;
entity bram_wbs is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic
);
end bram_wbs;
architecture Behavioral of bram_wbs is
type ram_type is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM: ram_type;
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_cyc_s : std_logic;
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
for i in 0 to 2**ADDR_WIDTH-1 loop
RAM(i) <= conv_std_logic_vector(i,RAM(i)'length); -- "DEAD0001BEEF0001"
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH/2) <= conv_std_logic_vector(i,RAM(i)'length/2);
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH-4*4) <= x"DEAD";
RAM(i)(DATA_WIDTH-1-DATA_WIDTH/2 downto DATA_WIDTH-4*4-DATA_WIDTH/2) <= x"BEEF";
end loop;
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
RAM(conv_integer(ADDR)) <= wb_dat_i;
end if;
wb_dat_o <= RAM(conv_integer(ADDR)) ;
else
wb_ack_o <= '0';
end if;
end if;
end process bram;
end Behavioral;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: valid_be.vhd
-- Version: v1.00a
-- Description: Determines valid OPB access for memory devices
--
-------------------------------------------------------------------------------
-- Structure:
--
-- valid_be.vhd
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 09/21/01 -- First version
-- ^^^^^^
-- First version of valid_be created from BLT's file, valid_access. Made
-- modifications to support a target data bus width and a host data bus
-- width.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity valid_be is
generic (
C_HOST_DW : integer range 8 to 256 := 32;
C_TARGET_DW : integer range 8 to 32 := 32
);
port (
OPB_BE_Reg : in std_logic_vector(0 to C_HOST_DW/8-1);
Valid : out std_logic
);
end entity valid_be;
architecture implementation of valid_be is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant HOST_LOGVAL : integer := log2(C_HOST_DW/8); -- log value for host bus
constant TAR_LOGVAL : integer := log2(C_TARGET_DW/8); -- log value for target bus
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- VALID_ACCESS_PROCESS: this is a general purpose process that returns
-- whether or not a particular byte enable code is valid for a particular host
-- bus size and target bus size. The byte enable bus can be up to 32 bits wide,
-- supporting host bus widths up to 256 bits.
--
-- Example:
-- HOST BUS SIZE(OPB) TARGET BUS SIZE (SRAM) Valid BE
-- ----------------- ---------------------- --------
-- 8 8 '1'
-- 16 8 "01"
-- "10"
-- 16 16 "01"
-- "10"
-- "11"
-- 32 8 "0001"
-- "0010"
-- "0100"
-- "1000"
-- 32 16 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- 32 32 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- "1111"
-------------------------------------------------------------------------------
VALID_ACCESS_PROCESS: process (OPB_BE_Reg) is
variable compare_Val : integer := 0;
begin
Valid <= '0';
for i in 0 to TAR_LOGVAL loop -- loop for bits in target data bus
compare_Val := pwr(2,pwr(2,i))-1;
for j in 0 to pwr(2,HOST_LOGVAL-i) loop
if Conv_integer('0' & OPB_BE_Reg) = compare_Val then Valid <= '1'; end if;
compare_Val := compare_Val*pwr(2,pwr(2,i));
end loop;
end loop;
end process VALID_ACCESS_PROCESS;
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLKFX_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm4 is
signal GND_BIT : std_logic;
signal CLKIN : std_logic;
signal CLKFX : std_logic;
signal CLKFX_BUF : std_logic;
signal CLK0 : std_logic;
signal CLK0_BUF : std_logic;
signal CLKFB : std_logic;
begin
GND_BIT <= '0';
-- CLK0 output buffer
CLK0_BUFG_INST : BUFG
port map (I => CLK0, O => CLK0_BUF);
CLK0_OUT <= CLK0_BUF;
-- CLKFX output buffer
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX, O => CLKFX_BUF);
CLKFX_OUT <= CLKFX_BUF;
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 25.175 = 32 * 11/14
CLKFX_DIVIDE => 14,
CLKFX_MULTIPLY => 11,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX,
CLKFX180 => open,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 216,
numIn => 32,
numOut => 54)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 216,
numIn => 32,
numOut => 54)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Control_Unit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Control_Unit
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Control Unit
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Control_Unit IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
master_rst : IN std_logic;
IR_in : IN std_logic_vector(11 DOWNTO 0); -- ufix12
shifter_sel : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
ALU_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
print_data : OUT std_logic;
DM_addr : OUT std_logic_vector(7 DOWNTO 0); -- uint8
DM_r_w : OUT std_logic; -- ufix1
AC_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
AC_data : OUT std_logic_vector(7 DOWNTO 0); -- int8
IR_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
PC_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
addr_inc : OUT std_logic_vector(7 DOWNTO 0); -- int8
IM_read : OUT std_logic; -- ufix1
hlt : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END Control_Unit;
ARCHITECTURE rtl OF Control_Unit IS
-- Signals
SIGNAL data_in_signed : signed(7 DOWNTO 0); -- int8
SIGNAL in_flags_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL IR_in_unsigned : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL shifter_sel_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL out_flags_tmp : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL ALU_func_tmp : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL DM_addr_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL AC_func_tmp : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL AC_data_tmp : signed(7 DOWNTO 0); -- int8
SIGNAL IR_func_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL PC_func_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL addr_inc_tmp : signed(7 DOWNTO 0); -- int8
SIGNAL hlt_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL CPU_state : unsigned(7 DOWNTO 0); -- uint8
SIGNAL previous_CPU_state : unsigned(7 DOWNTO 0); -- uint8
SIGNAL major_opcode : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL minor_opcode : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL address_data : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL indirect_address : unsigned(7 DOWNTO 0); -- uint8
SIGNAL CPU_state_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL previous_CPU_state_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL major_opcode_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL minor_opcode_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL address_data_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL indirect_address_next : unsigned(7 DOWNTO 0); -- uint8
BEGIN
data_in_signed <= signed(data_in);
in_flags_unsigned <= unsigned(in_flags);
IR_in_unsigned <= unsigned(IR_in);
Control_Unit_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
CPU_state <= to_unsigned(2#00000000#, 8);
previous_CPU_state <= to_unsigned(2#00000000#, 8);
major_opcode <= to_unsigned(2#00000000#, 8);
minor_opcode <= to_unsigned(2#00000000#, 8);
address_data <= to_unsigned(2#00000000#, 8);
indirect_address <= to_unsigned(2#00000000#, 8);
ELSIF enb = '1' THEN
CPU_state <= CPU_state_next;
previous_CPU_state <= previous_CPU_state_next;
major_opcode <= major_opcode_next;
minor_opcode <= minor_opcode_next;
address_data <= address_data_next;
indirect_address <= indirect_address_next;
END IF;
END IF;
END PROCESS Control_Unit_1_process;
Control_Unit_1_output : PROCESS (data_in_signed, in_flags_unsigned, master_rst, IR_in_unsigned, CPU_state,
previous_CPU_state, major_opcode, minor_opcode, address_data,
indirect_address)
VARIABLE minor_opcode_bit6 : std_logic;
VARIABLE temp_address_data : signed(6 DOWNTO 0);
VARIABLE indirect_bit : std_logic;
VARIABLE c : std_logic;
VARIABLE n : std_logic;
VARIABLE minor_opcode_bit4 : std_logic;
VARIABLE v : std_logic;
VARIABLE z : std_logic;
VARIABLE c_0 : unsigned(11 DOWNTO 0);
VARIABLE c_1 : unsigned(11 DOWNTO 0);
VARIABLE c_uint : unsigned(11 DOWNTO 0);
VARIABLE c_uint_0 : unsigned(11 DOWNTO 0);
VARIABLE CPU_state_temp : unsigned(7 DOWNTO 0);
VARIABLE minor_opcode_bit6_0 : std_logic;
VARIABLE temp_address_data_0 : signed(6 DOWNTO 0);
VARIABLE temp_address_data_1 : signed(6 DOWNTO 0);
VARIABLE minor_opcode_bit6_1 : std_logic;
VARIABLE temp_address_data_2 : signed(6 DOWNTO 0);
VARIABLE temp_address_data_3 : signed(6 DOWNTO 0);
VARIABLE indirect_bit_0 : std_logic;
VARIABLE indirect_bit_1 : std_logic;
VARIABLE indirect_bit_2 : std_logic;
VARIABLE indirect_bit_3 : std_logic;
BEGIN
CPU_state_temp := CPU_state;
previous_CPU_state_next <= previous_CPU_state;
major_opcode_next <= major_opcode;
minor_opcode_next <= minor_opcode;
address_data_next <= address_data;
indirect_address_next <= indirect_address;
--MATLAB Function 'CPU_Subsystem_8_bit/Control Unit': '<S5>:1'
-- CPU Controller
--
-- The CPU Instruction Set:
-- ------------------------
--
-- LDA <loc>: AC = content(<loc>)
-- LDAI <loc>: AC = content(content(<loc>))
-- AND <loc>: AC = AC & content(<loc>)
-- ANDI <loc>: AC = AC & content(content(<loc>))
-- ADD <loc>: AC = AC + content(<loc>) + C(flag)
-- ADDI <loc>: AC = AC + content(content(<loc>)) + C(flag)
-- SUB <loc>: AC = AC - content(<loc>) - C(flag)
-- SUBI <loc>: AC = AC - content(content(<loc>)) - C(flag)
-- JMP <loc>: Jump to <PC + <loc>>
-- LI <const>: AC = <const>
-- STA <loc>: content(<loc>) = AC
-- STAI <loc>: content(content(<loc>)) = AC
-- BRA_C <loc>: Jump to <PC + <loc>> if (C(flag) == 1)
-- BRA_N <loc>: Jump to <PC + <loc>> if (N(flag) == 1)
-- BRA_V <loc>: Jump to <PC + <loc>> if (V(flag) == 1)
-- BRA_Z <loc>: Jump to <PC + <loc>> if (Z(flag) == 1)
-- NOP: Do nothing
-- CLA: AC = 0
-- CMA: Complement AC
-- CMC: Complement C(flag)
-- ASL: AC = AC << 1
-- ASR: AC = AC >> 1
-- PRINT: Display value from the memory-mapped location 255
-- CLC: C(flag) = 0
--
-- 12-bit Instruction Encoding:
-- ---------------------------
--
-- LDA: 000 0 <8-bit loc>
-- LDAI: 000 1 <8-bit loc>
-- AND: 001 0 <8-bit loc>
-- ANDI: 001 1 <8-bit loc>
-- ADD: 010 0 <8-bit loc>
-- ADDI: 010 1 <8-bit loc>
-- SUB: 011 0 <8-bit loc>
-- SUBI: 011 1 <8-bit loc>
-- JMP: 1000 <8-bit loc>
-- LI: 1001 <8-bit const>
-- STA: 101 0 <8-bit loc>
-- STAI: 101 1 <8-bit loc>
-- BRA_C: 1100 <8-bit loc>
-- BRA_N: 1101 <8-bit loc>
-- BRA_C: 1110 <8-bit loc>
-- BRA_C: 1111 <8-bit loc>
-- HLT: 111 0 0100 0 000
-- CLA: 111 0 0100 1 000
-- CMA: 111 0 0101 0 000
-- CMC: 111 0 0101 1 000
-- ASL: 111 0 0110 0 000
-- ASR: 111 0 0110 1 000
-- PRINT: 111 0 0111 0 000
-- CLC: 111 0 0111 1 000
-- HDL specific fimath
IF master_rst = '1' THEN
--'<S5>:1:81'
--'<S5>:1:82'
CPU_state_temp := to_unsigned(2#00000000#, 8);
END IF;
--'<S5>:1:85'
shifter_sel_tmp <= to_unsigned(2#00#, 2);
--'<S5>:1:86'
ALU_func_tmp <= to_unsigned(2#000#, 3);
--'<S5>:1:87'
out_flags_tmp <= in_flags_unsigned;
--'<S5>:1:88'
AC_func_tmp <= to_unsigned(2#100#, 3);
-- NOP
--'<S5>:1:89'
AC_data_tmp <= to_signed(2#00000000#, 8);
--'<S5>:1:90'
IR_func_tmp <= to_unsigned(2#11#, 2);
-- NOP
--'<S5>:1:91'
PC_func_tmp <= to_unsigned(2#11#, 2);
-- NOP
--'<S5>:1:92'
IM_read <= '0';
--'<S5>:1:93'
DM_addr_tmp <= to_unsigned(2#00000000#, 8);
--'<S5>:1:94'
DM_r_w <= '0';
--'<S5>:1:95'
addr_inc_tmp <= to_signed(2#00000000#, 8);
--'<S5>:1:96'
print_data <= '0';
--'<S5>:1:97'
hlt_tmp <= to_unsigned(2#00000000#, 8);
-- Instruction: <12..1>
-- major_opcode: <12..10>
-- indirect_addressing: <9>
-- minor_opcode: <9..4>
-- address bits: <8..1>
--'<S5>:1:117'
CASE CPU_state_temp IS
WHEN "00000000" =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- RESETTING OUTPUTS
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--'<S5>:1:122'
PC_func_tmp <= to_unsigned(2#00#, 2);
--'<S5>:1:123'
AC_func_tmp <= to_unsigned(2#000#, 3);
--'<S5>:1:124'
IR_func_tmp <= to_unsigned(2#00#, 2);
--'<S5>:1:125'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:126'
CPU_state_temp := to_unsigned(2#00000001#, 8);
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- FETCH
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
WHEN "00000001" =>
-- Read from IM
--'<S5>:1:133'
IM_read <= '1';
-- Increment PC
--'<S5>:1:135'
PC_func_tmp <= to_unsigned(2#10#, 2);
-- store into IR
--'<S5>:1:137'
IR_func_tmp <= to_unsigned(2#01#, 2);
--'<S5>:1:139'
CPU_state_temp := to_unsigned(2#00000010#, 8);
WHEN "00000010" =>
-- Read from IR
--'<S5>:1:143'
IR_func_tmp <= to_unsigned(2#10#, 2);
-- Accommodating for the 'unit delay' from IR_out to IR_in
--'<S5>:1:146'
CPU_state_temp := to_unsigned(2#00000011#, 8);
WHEN "00000011" =>
-- IR_in <12..10>
--'<S5>:1:150'
c_0 := IR_in_unsigned srl 9;
major_opcode_next <= c_0(7 DOWNTO 0);
-- IR_in <9..4>
--'<S5>:1:153'
c_1 := IR_in_unsigned srl 3;
c_uint := c_1 AND to_unsigned(2#000000111111#, 12);
minor_opcode_next <= c_uint(7 DOWNTO 0);
-- IR_in <8..1>
--'<S5>:1:156'
c_uint_0 := IR_in_unsigned AND to_unsigned(2#000011111111#, 12);
address_data_next <= c_uint_0(7 DOWNTO 0);
-- Go to the decode stage
--'<S5>:1:159'
CPU_state_temp := to_unsigned(2#00000100#, 8);
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- DECODE AND EXECUTE
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
WHEN "00000100" =>
--'<S5>:1:165'
previous_CPU_state_next <= CPU_state_temp;
CASE major_opcode IS
WHEN "00000000" =>
-- LDA
-- minor_opcode contains the address (assuming direct addressing)
--'<S5>:1:170'
DM_addr_tmp <= address_data;
-- Read the data memory
--'<S5>:1:172'
DM_r_w <= '0';
-- Simply pass the value read from memory
--'<S5>:1:174'
CPU_state_temp := to_unsigned(2#00001101#, 8);
WHEN "00000001" =>
-- AND
--'<S5>:1:178'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:180'
DM_r_w <= '0';
--'<S5>:1:182'
CPU_state_temp := to_unsigned(2#00001111#, 8);
WHEN "00000010" =>
-- ADD
--'<S5>:1:186'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:188'
DM_r_w <= '0';
--'<S5>:1:190'
CPU_state_temp := to_unsigned(2#00010001#, 8);
WHEN "00000011" =>
-- SUB
--'<S5>:1:194'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:196'
DM_r_w <= '0';
--'<S5>:1:198'
CPU_state_temp := to_unsigned(2#00010011#, 8);
WHEN "00000100" =>
--'<S5>:1:201'
minor_opcode_bit6 := minor_opcode(5);
CASE minor_opcode_bit6 IS
WHEN '0' =>
-- JMP
--'<S5>:1:205'
temp_address_data := signed(address_data(6 DOWNTO 0));
--'<S5>:1:206'
addr_inc_tmp <= resize(temp_address_data, 8) - 1;
--'<S5>:1:207'
PC_func_tmp <= to_unsigned(2#01#, 2);
WHEN '1' =>
-- LI
--'<S5>:1:211'
AC_data_tmp <= signed(address_data);
--'<S5>:1:212'
AC_func_tmp <= to_unsigned(2#001#, 3);
WHEN OTHERS =>
NULL;
END CASE;
-- Go back to the fetch stage again
--'<S5>:1:215'
CPU_state_temp := to_unsigned(2#00000001#, 8);
WHEN "00000101" =>
-- STA
-- minor_opcode contains the address (assuming direct addressing)
--'<S5>:1:220'
DM_addr_tmp <= address_data;
--'<S5>:1:221'
indirect_bit := minor_opcode(5);
IF indirect_bit /= '0' THEN
-- indirect addressing
-- Read the address from the data memory
--'<S5>:1:225'
DM_r_w <= '0';
--'<S5>:1:226'
CPU_state_temp := to_unsigned(2#00010101#, 8);
ELSE
-- Write into the data memory
--'<S5>:1:229'
DM_r_w <= '1';
-- Go back to the fetch stage again
--'<S5>:1:231'
CPU_state_temp := to_unsigned(2#00011001#, 8);
-- going to 'otherwise'
END IF;
WHEN "00000110" =>
--'<S5>:1:235'
minor_opcode_bit6_0 := minor_opcode(5);
CASE minor_opcode_bit6_0 IS
WHEN '0' =>
-- special branches:
-- BRA_C
--'<S5>:1:240'
c := in_flags_unsigned(3);
IF c /= '0' THEN
--'<S5>:1:242'
temp_address_data_0 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:243'
addr_inc_tmp <= resize(temp_address_data_0, 8) - 1;
--'<S5>:1:244'
PC_func_tmp <= to_unsigned(2#01#, 2);
END IF;
WHEN '1' =>
-- BRA_N
--'<S5>:1:249'
n := in_flags_unsigned(2);
IF n /= '0' THEN
--'<S5>:1:251'
temp_address_data_1 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:252'
addr_inc_tmp <= resize(temp_address_data_1, 8) - 1;
--'<S5>:1:253'
PC_func_tmp <= to_unsigned(2#01#, 2);
END IF;
WHEN OTHERS =>
NULL;
END CASE;
-- Go back to the fetch stage again
--'<S5>:1:257'
CPU_state_temp := to_unsigned(2#00001111#, 8);
WHEN "00000111" =>
-- by default, go back to the fetch stage again
--'<S5>:1:261'
CPU_state_temp := to_unsigned(2#00000001#, 8);
--'<S5>:1:262'
minor_opcode_bit4 := minor_opcode(3);
IF (minor_opcode_bit4 /= '0') = FALSE THEN
--'<S5>:1:263'
-- Further cases of special branches:
--'<S5>:1:265'
minor_opcode_bit6_1 := minor_opcode(5);
CASE minor_opcode_bit6_1 IS
WHEN '0' =>
-- BRA_V
--'<S5>:1:269'
v := in_flags_unsigned(1);
IF v /= '0' THEN
--'<S5>:1:271'
temp_address_data_2 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:272'
addr_inc_tmp <= resize(temp_address_data_2, 8) - 1;
--'<S5>:1:273'
PC_func_tmp <= to_unsigned(2#01#, 2);
END IF;
WHEN '1' =>
-- BRA_Z
--'<S5>:1:278'
z := in_flags_unsigned(0);
IF z /= '0' THEN
--'<S5>:1:280'
temp_address_data_3 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:281'
addr_inc_tmp <= resize(temp_address_data_3, 8) - 1;
--'<S5>:1:282'
PC_func_tmp <= to_unsigned(2#01#, 2);
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
-- Instructions having no operands
CASE minor_opcode IS
WHEN "00001000" =>
-- HLT
-- Stop the simulation
--'<S5>:1:291'
hlt_tmp <= to_unsigned(2#00000001#, 8);
--'<S5>:1:292'
CPU_state_temp := to_unsigned(2#00010110#, 8);
WHEN "00001001" =>
-- CLA
--'<S5>:1:295'
AC_func_tmp <= to_unsigned(2#000#, 3);
WHEN "00001010" =>
-- CMA
--'<S5>:1:299'
ALU_func_tmp <= to_unsigned(2#100#, 3);
--'<S5>:1:300'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
--'<S5>:1:301'
CPU_state_temp := to_unsigned(2#00000110#, 8);
WHEN "00001011" =>
-- CMC
--'<S5>:1:305'
ALU_func_tmp <= to_unsigned(2#101#, 3);
--'<S5>:1:306'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
WHEN "00001100" =>
-- ASL
--'<S5>:1:310'
shifter_sel_tmp <= to_unsigned(2#01#, 2);
--'<S5>:1:311'
CPU_state_temp := to_unsigned(2#00000110#, 8);
WHEN "00001101" =>
-- ASR
--'<S5>:1:315'
shifter_sel_tmp <= to_unsigned(2#10#, 2);
--'<S5>:1:316'
CPU_state_temp := to_unsigned(2#00000110#, 8);
WHEN "00001110" =>
-- PRINT
--'<S5>:1:320'
DM_addr_tmp <= to_unsigned(2#11111111#, 8);
-- Read the data memory
--'<S5>:1:322'
DM_r_w <= '0';
--'<S5>:1:324'
CPU_state_temp := to_unsigned(2#00001100#, 8);
WHEN "00001111" =>
-- CLC
--'<S5>:1:328'
ALU_func_tmp <= to_unsigned(2#111#, 3);
--'<S5>:1:329'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
WHEN OTHERS =>
-- by default, go back to the fetch stage again
--'<S5>:1:333'
CPU_state_temp := to_unsigned(2#00000001#, 8);
-- Minor Opcode cases end here
END CASE;
-- Major Opcode cases end here
WHEN OTHERS =>
NULL;
END CASE;
-- introducing delay
WHEN "00000110" =>
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:343'
AC_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:344'
previous_CPU_state_next <= CPU_state_temp;
-- Go back to the fetch stage again
--'<S5>:1:346'
CPU_state_temp := to_unsigned(2#00000001#, 8);
-- Operations with indirect addressing
WHEN "00000111" =>
-- LDA Indirect
-- data_in is the address read from the data memory
--'<S5>:1:352'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:354'
DM_r_w <= '0';
--'<S5>:1:356'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:357'
CPU_state_temp := to_unsigned(2#00001101#, 8);
WHEN "00001000" =>
-- AND Indirect
-- data_in is the address read from the data memory
--'<S5>:1:362'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:364'
DM_r_w <= '0';
--'<S5>:1:366'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:367'
CPU_state_temp := to_unsigned(2#00001111#, 8);
WHEN "00001001" =>
-- ADD Indirect
-- data_in is the address read from the data memory
--'<S5>:1:372'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:374'
DM_r_w <= '0';
--'<S5>:1:376'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:377'
CPU_state_temp := to_unsigned(2#00010001#, 8);
WHEN "00001010" =>
-- SUB Indirect
-- data_in is the address read from the data memory
--'<S5>:1:382'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:384'
DM_r_w <= '0';
--'<S5>:1:386'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:387'
CPU_state_temp := to_unsigned(2#00010011#, 8);
WHEN "00001011" =>
-- STA Indirect
-- data_in is the address read from the data memory
--'<S5>:1:392'
IF data_in_signed(7) = '1' THEN
DM_addr_tmp <= "00000000";
ELSE
DM_addr_tmp <= unsigned(data_in_signed);
END IF;
-- Write the data memory
--'<S5>:1:394'
DM_r_w <= '1';
--'<S5>:1:395'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:396'
CPU_state_temp := to_unsigned(2#00000001#, 8);
WHEN "00001100" =>
-- PRINT
--'<S5>:1:400'
print_data <= '1';
--'<S5>:1:401'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:402'
CPU_state_temp := to_unsigned(2#00000001#, 8);
WHEN "00001101" =>
-- LDA (contd.)
-- Simply pass the value read from memory
--'<S5>:1:407'
ALU_func_tmp <= to_unsigned(2#110#, 3);
--'<S5>:1:408'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:410'
--'<S5>:1:411'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:412'
CPU_state_temp := to_unsigned(2#00001110#, 8);
ELSE
--'<S5>:1:414'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:415'
CPU_state_temp := to_unsigned(2#00000110#, 8);
END IF;
WHEN "00001110" =>
--'<S5>:1:419'
indirect_bit_0 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:421'
AC_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:423'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_0 /= '0' THEN
-- indirect addressing
--'<S5>:1:426'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:427'
CPU_state_temp := to_unsigned(2#00000111#, 8);
ELSE
--'<S5>:1:429'
CPU_state_temp := to_unsigned(2#00011001#, 8);
END IF;
WHEN "00001111" =>
-- AND (contd.)
--'<S5>:1:435'
ALU_func_tmp <= to_unsigned(2#001#, 3);
--'<S5>:1:436'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:438'
--'<S5>:1:439'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:440'
CPU_state_temp := to_unsigned(2#00010000#, 8);
ELSE
--'<S5>:1:442'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:443'
CPU_state_temp := to_unsigned(2#00000110#, 8);
END IF;
WHEN "00010000" =>
--'<S5>:1:447'
indirect_bit_1 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:449'
AC_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:451'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_1 /= '0' THEN
-- indirect addressing
--'<S5>:1:454'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:455'
CPU_state_temp := to_unsigned(2#00001000#, 8);
ELSE
--'<S5>:1:457'
CPU_state_temp := to_unsigned(2#00011001#, 8);
END IF;
WHEN "00010001" =>
-- ADD (contd.)
--'<S5>:1:462'
ALU_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:463'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:465'
--'<S5>:1:466'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:467'
CPU_state_temp := to_unsigned(2#00010010#, 8);
ELSE
--'<S5>:1:469'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:470'
CPU_state_temp := to_unsigned(2#00000110#, 8);
END IF;
WHEN "00010010" =>
--'<S5>:1:474'
indirect_bit_2 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:476'
AC_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:478'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_2 /= '0' THEN
-- indirect addressing
--'<S5>:1:481'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:482'
CPU_state_temp := to_unsigned(2#00001001#, 8);
ELSE
--'<S5>:1:484'
CPU_state_temp := to_unsigned(2#00011001#, 8);
END IF;
WHEN "00010011" =>
-- SUB (contd.)
--'<S5>:1:489'
ALU_func_tmp <= to_unsigned(2#011#, 3);
--'<S5>:1:490'
shifter_sel_tmp <= to_unsigned(2#11#, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:492'
--'<S5>:1:493'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:494'
CPU_state_temp := to_unsigned(2#00010100#, 8);
ELSE
--'<S5>:1:496'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:497'
CPU_state_temp := to_unsigned(2#00000110#, 8);
END IF;
WHEN "00010100" =>
--'<S5>:1:501'
indirect_bit_3 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:503'
AC_func_tmp <= to_unsigned(2#010#, 3);
--'<S5>:1:505'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_3 /= '0' THEN
-- indirect addressing
--'<S5>:1:508'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:509'
CPU_state_temp := to_unsigned(2#00001010#, 8);
ELSE
--'<S5>:1:512'
CPU_state_temp := to_unsigned(2#00011001#, 8);
END IF;
WHEN "00010101" =>
-- STA indirect
--'<S5>:1:517'
CPU_state_temp := to_unsigned(2#00001011#, 8);
WHEN "00010110" =>
-- lock state
--'<S5>:1:521'
hlt_tmp <= to_unsigned(2#00000001#, 8);
--'<S5>:1:522'
CPU_state_temp := to_unsigned(2#00010110#, 8);
WHEN OTHERS =>
--'<S5>:1:525'
previous_CPU_state_next <= CPU_state_temp;
-- by default, go back to the fetch stage again
--'<S5>:1:527'
CPU_state_temp := to_unsigned(2#00000001#, 8);
-- switch(CPU_state) end here
END CASE;
CPU_state_next <= CPU_state_temp;
END PROCESS Control_Unit_1_output;
shifter_sel <= std_logic_vector(shifter_sel_tmp);
out_flags <= std_logic_vector(out_flags_tmp);
ALU_func <= std_logic_vector(ALU_func_tmp);
DM_addr <= std_logic_vector(DM_addr_tmp);
AC_func <= std_logic_vector(AC_func_tmp);
AC_data <= std_logic_vector(AC_data_tmp);
IR_func <= std_logic_vector(IR_func_tmp);
PC_func <= std_logic_vector(PC_func_tmp);
addr_inc <= std_logic_vector(addr_inc_tmp);
hlt <= std_logic_vector(hlt_tmp);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity InstMem is
generic (BitWidth: integer;
InstructionWidth: integer);
port ( address : in std_logic_vector(BitWidth-1 downto 0);
data : out std_logic_vector(InstructionWidth-1 downto 0) );
end entity InstMem;
architecture behavioral of InstMem is
type mem is array ( 0 to InstMem_depth-1) of std_logic_vector(InstructionWidth-1 downto 0);
constant my_InstMem : mem := (
0 => "10000100000000000000000000000000011000",--Load_R0_Dir R0 = 24
1 => "00111100000000000000000000000000000000",--OR_A_R0 ACC = 24
2 => "00011000000000000000000000000000000000",--IncA ACC = 25
3 => "00001100000000000000000000000000000000",--Sub_A_R0 ACC = 1
4 => "11111000000000000000000000000000000000",--NOP
5 => "01011000000000000000000000000000000111",--JmpC 7 Jump
6 => "00011000000000000000000000000000000000",--IncA should be skipped!
7 => "00110000000000000000000000000000000000",--RRC
8 => "00110100000000000000000000000000000000",--RLC ACC = 1
9 => "11111000000000000000000000000000000000",--NOP
10 => "01101100000000000000000000000000000000",--ClearC
11 => "10000000000000000000000000000000010000",--Store_A_Mem MEM[16] = 1
12 => "11110000000000000000000000000000000000",--PUSH
13 => "01111000000000000000000000000000000000",--SavePC
14 => "11110000000000000000000000000000000000",--PUSH
15 => "01001100000000000000000000000000010101",--Jmp 21
16 => "00011000000000000000000000000000000000",--IncA should be skipped!
17 => "11110100000000000000000000000000000000", --pop
18 => "00100100000000000000000000000000000000", --ShiftArithL
19 => "00011100000000000000000000000000000000",--DecA
20 => "11111100000000000000000000000000000000", --HALT
21 => "01111100000000000000000000000000010000",--Load_A_Mem
22 => "00111000000000000000000000000000000000",--AND
23 => "01010000000000000000000000000000011010",--JMPZ 26
24 => "01101100000000000000000000000000000000",--ClearZ
25 => "00000100000000000000000000000000010000",--Add_A_Mem
26 => "00010000000000000000000000000000010000",--Sub_A_Mem
27 => "00000000000000000000000000000000000000",--ADD_A_B
28 => "00010100000000000000000000000000001100",--SUB_A_DIR C
29 => "01000100000000000000000000000000000000",--FlipA
30 => "01000000000000000000000000000000000000",--XOR_A_B
31 => "01001000000000000000000000000000000000",--NegA
32 => "00100000000000000000000000000000000000",--ShiftArithR
33 => "00101100000000000000000000000000000000",--ShiftA_L
34 => "00101000000000000000000000000000000000",--ShiftA_R
35 => "10011000000000000000000000000000000001",--GPIO_DIR SET GPIO AS OUTPUT
36 => "10100000000000000000000000000000101010",--GPIO_WR SET GPIO AS OUTPUT
37 => "01110000000000000000000000000000000000",--ClearACC
38 => "10011000000000000000000000000000000000",--GPIO_DIR SET GPIO AS in
39 => "11111000000000000000000000000000000000",--NOP
40 => "10011100000000000000000000000000000000",--GPIO_RD SET GPIO AS OUTPUT
41 => "11110100000000000000000000000000000000",--POP
42 => "00001000000000000000000000000000000110",--Add_A_Dir
43 => "01110100000000000000000000000000000000",--LoadPC
others => "00000000000000000000000000000000000000"
);
begin
process(address)begin
if to_integer(unsigned(address)) <= InstMem_depth-1 then
data <= my_InstMem(to_integer(unsigned(address)));
else
data <= (others => '0');
end if;
end process;
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX2
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX2;
architecture RTL of SBOX2 is
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
begin
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
douta <= s1_douta(1 to 7) & s1_douta(0);
doutb <= s1_doutb(1 to 7) & s1_doutb(0);
end RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface_tb IS
END ENTITY avalon_dacad5668_interface_tb;
ARCHITECTURE sim OF avalon_dacad5668_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00646163"; --dac
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_analog_output_interface_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0):= (OTHERS =>'1');
SIGNAL sl_sclk : STD_LOGIC:= '0';
SIGNAL slv_Ss : STD_LOGIC:= '0';
SIGNAL sl_mosi : STD_LOGIC:= '0';
SIGNAL sl_LDAC_n : STD_LOGIC:= '0';
SIGNAL sl_CLR_n : STD_LOGIC:= '0';
BEGIN
--create component
my_unit_under_test : avalon_dacad5668_interface
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 1000000,
INTERNAL_REFERENCE => '1',
UNIQUE_ID => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
islv_avs_byteenable => slv_avs_byteenable,
oslv_avs_read_data => slv_avs_read_data,
osl_sclk => sl_sclk,
oslv_Ss => slv_Ss,
osl_mosi => sl_mosi,
osl_LDAC_n => sl_LDAC_n,
osl_CLR_n => sl_CLR_n
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = c_dacad5668_interface_version
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = c_dacad5668_subtype_id
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_analog_output_interface_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**NUMBER_OF_CHANNELS))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
WAIT FOR 10000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00527ent IS
END c03s03b00x00p03n04i00527ent;
ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
BEGIN
TESTING : PROCESS
-- first index constraint method
type bv_ptr is access bit_vector(0 to 7);
variable v_bv_ptr1: bv_ptr := new bit_vector'("00000001");
variable v_bv_ptr2: bv_ptr;
variable v_bv_ptr3: bv_ptr := v_bv_ptr1;
-- second index constraint method
subtype tbus is bit_vector(1 to 8);
type bus_ptr is access tbus;
variable v_bv_ptr4: bus_ptr := new tbus'("10000000");
-- third index constraint method
type bus_ptr2 is access bit_vector;
variable v_bv_ptr5: bus_ptr2 := new bit_vector'("1111");
variable v_bv_ptr6: bus_ptr2 := new bit_vector(1 to 4);
variable OKtest : integer := 0;
BEGIN
assert v_bv_ptr1.all = "00000001";
if (v_bv_ptr1.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr2 = null;
if (v_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr3.all = "00000001";
if (v_bv_ptr3.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr4.all = "10000000";
if (v_bv_ptr4.all = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr5.all = "1111";
if (v_bv_ptr5.all = "1111") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr6.all = "0000";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
v_bv_ptr2 := new bit_vector'("00110011");
assert v_bv_ptr2.all = "00110011";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_bv_ptr1);
deallocate(v_bv_ptr2);
deallocate(v_bv_ptr4);
deallocate(v_bv_ptr5);
deallocate(v_bv_ptr6);
assert NOT(OKtest = 12)
report "***PASSED TEST: c03s03b00x00p03n04i00527"
severity NOTE;
assert (OKtest = 12)
report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00527arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00527ent IS
END c03s03b00x00p03n04i00527ent;
ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
BEGIN
TESTING : PROCESS
-- first index constraint method
type bv_ptr is access bit_vector(0 to 7);
variable v_bv_ptr1: bv_ptr := new bit_vector'("00000001");
variable v_bv_ptr2: bv_ptr;
variable v_bv_ptr3: bv_ptr := v_bv_ptr1;
-- second index constraint method
subtype tbus is bit_vector(1 to 8);
type bus_ptr is access tbus;
variable v_bv_ptr4: bus_ptr := new tbus'("10000000");
-- third index constraint method
type bus_ptr2 is access bit_vector;
variable v_bv_ptr5: bus_ptr2 := new bit_vector'("1111");
variable v_bv_ptr6: bus_ptr2 := new bit_vector(1 to 4);
variable OKtest : integer := 0;
BEGIN
assert v_bv_ptr1.all = "00000001";
if (v_bv_ptr1.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr2 = null;
if (v_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr3.all = "00000001";
if (v_bv_ptr3.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr4.all = "10000000";
if (v_bv_ptr4.all = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr5.all = "1111";
if (v_bv_ptr5.all = "1111") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr6.all = "0000";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
v_bv_ptr2 := new bit_vector'("00110011");
assert v_bv_ptr2.all = "00110011";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_bv_ptr1);
deallocate(v_bv_ptr2);
deallocate(v_bv_ptr4);
deallocate(v_bv_ptr5);
deallocate(v_bv_ptr6);
assert NOT(OKtest = 12)
report "***PASSED TEST: c03s03b00x00p03n04i00527"
severity NOTE;
assert (OKtest = 12)
report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00527arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00527ent IS
END c03s03b00x00p03n04i00527ent;
ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
BEGIN
TESTING : PROCESS
-- first index constraint method
type bv_ptr is access bit_vector(0 to 7);
variable v_bv_ptr1: bv_ptr := new bit_vector'("00000001");
variable v_bv_ptr2: bv_ptr;
variable v_bv_ptr3: bv_ptr := v_bv_ptr1;
-- second index constraint method
subtype tbus is bit_vector(1 to 8);
type bus_ptr is access tbus;
variable v_bv_ptr4: bus_ptr := new tbus'("10000000");
-- third index constraint method
type bus_ptr2 is access bit_vector;
variable v_bv_ptr5: bus_ptr2 := new bit_vector'("1111");
variable v_bv_ptr6: bus_ptr2 := new bit_vector(1 to 4);
variable OKtest : integer := 0;
BEGIN
assert v_bv_ptr1.all = "00000001";
if (v_bv_ptr1.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr2 = null;
if (v_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr3.all = "00000001";
if (v_bv_ptr3.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr4.all = "10000000";
if (v_bv_ptr4.all = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr5.all = "1111";
if (v_bv_ptr5.all = "1111") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr6.all = "0000";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
v_bv_ptr2 := new bit_vector'("00110011");
assert v_bv_ptr2.all = "00110011";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_bv_ptr1);
deallocate(v_bv_ptr2);
deallocate(v_bv_ptr4);
deallocate(v_bv_ptr5);
deallocate(v_bv_ptr6);
assert NOT(OKtest = 12)
report "***PASSED TEST: c03s03b00x00p03n04i00527"
severity NOTE;
assert (OKtest = 12)
report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00527arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_exe2a4 IS
END TB_exe2a4;
ARCHITECTURE behavior OF TB_btn_led IS
COMPONENT btn_led
PORT(
btn : IN std_logic;
reset : IN std_logic;
ledA : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal btn : std_logic := '0';
signal reset : std_logic := '1';
--Outputs
signal ledA : std_logic_vector(7 downto 0);
constant btn_period : time := 1 ms;
BEGIN
uut: TB_btn_led PORT MAP (
btn => btn,
reset => reset,
ledA => ledA
);
btn_process :process
begin
btn <= '0';
wait for btn_period/2;
btn <= '1';
wait for btn_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
reset <= '0';
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de frecuencia y el controlador
-- de siete segmentos completo para mostrar la hora en una tarjeta Basys2.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/reloj-digital/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reloj is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end reloj;
architecture Behavioral of reloj is
COMPONENT clk1Hz IS
PORT (
entrada: IN STD_LOGIC;
reset : IN STD_LOGIC;
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT contador_reloj IS
PORT (
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT siete_segmentos_completo IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0);
D1 : IN STD_LOGIC_VECTOR(5 downto 0);
D2 : IN STD_LOGIC_VECTOR(5 downto 0);
D3 : IN STD_LOGIC_VECTOR(5 downto 0);
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
signal clk_out : STD_LOGIC := '0';
signal HH1, MM1: STD_LOGIC_VECTOR(2 downto 0);
signal HH0, MM0: STD_LOGIC_VECTOR(3 downto 0);
signal pHH1, pHH0, pMM1, pMM0: STD_LOGIC_VECTOR(5 downto 0);
begin
--PORT MAPs necesarios para habilitar el reloj.
clk_i: clk1Hz PORT MAP(clk, reset, clk_out);
cnt_i: contador_reloj PORT MAP(clk_out, reset, HH1, HH0, MM1, MM0);
seg_i: siete_segmentos_completo PORT MAP(clk, reset, pMM0, pMM1, pHH0, pHH1, salida, MUX);
--Padding de las señales del contador para siete segmentos.
pHH1 <= "000" & HH1;
pHH0 <= "00" & HH0;
pMM1 <= "000" & MM1;
pMM0 <= "00" & MM0;
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de frecuencia y el controlador
-- de siete segmentos completo para mostrar la hora en una tarjeta Basys2.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/reloj-digital/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reloj is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end reloj;
architecture Behavioral of reloj is
COMPONENT clk1Hz IS
PORT (
entrada: IN STD_LOGIC;
reset : IN STD_LOGIC;
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT contador_reloj IS
PORT (
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT siete_segmentos_completo IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0);
D1 : IN STD_LOGIC_VECTOR(5 downto 0);
D2 : IN STD_LOGIC_VECTOR(5 downto 0);
D3 : IN STD_LOGIC_VECTOR(5 downto 0);
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
signal clk_out : STD_LOGIC := '0';
signal HH1, MM1: STD_LOGIC_VECTOR(2 downto 0);
signal HH0, MM0: STD_LOGIC_VECTOR(3 downto 0);
signal pHH1, pHH0, pMM1, pMM0: STD_LOGIC_VECTOR(5 downto 0);
begin
--PORT MAPs necesarios para habilitar el reloj.
clk_i: clk1Hz PORT MAP(clk, reset, clk_out);
cnt_i: contador_reloj PORT MAP(clk_out, reset, HH1, HH0, MM1, MM0);
seg_i: siete_segmentos_completo PORT MAP(clk, reset, pMM0, pMM1, pHH0, pHH1, salida, MUX);
--Padding de las señales del contador para siete segmentos.
pHH1 <= "000" & HH1;
pHH0 <= "00" & HH0;
pMM1 <= "000" & MM1;
pMM0 <= "00" & MM0;
end Behavioral; |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonLX9.vhd
-- /___/ /\ Timestamp : 14/10/2018
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMonLX9
--Device: XC6SLX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Mode jumper, tie low to generate NOPs when paused
mode : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic
);
end Z80CpuMonLX9;
architecture behavioral of Z80CpuMonLX9 is
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal tristate_n : std_logic;
signal tristate_ad_n: std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
-- Tristateable output drivers
MREQ_n <= 'Z' when tristate_n = '0' else MREQ_n_int;
IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
wrapper : entity work.Z80CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map(
clock => clock,
-- Z80 Signals
RESET_n => RESET_n,
CLK_n => CLK_n,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n,
Addr => Addr_int,
Data => Data,
-- Buffer Control Signals
tristate_n => tristate_n,
tristate_ad_n => tristate_ad_n,
DIRD => open,
-- Mode jumper, tie low to generate NOPs when paused
mode => mode,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2,
test3 => test3,
test4 => test4
);
end behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonLX9.vhd
-- /___/ /\ Timestamp : 14/10/2018
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMonLX9
--Device: XC6SLX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Mode jumper, tie low to generate NOPs when paused
mode : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic
);
end Z80CpuMonLX9;
architecture behavioral of Z80CpuMonLX9 is
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal tristate_n : std_logic;
signal tristate_ad_n: std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
-- Tristateable output drivers
MREQ_n <= 'Z' when tristate_n = '0' else MREQ_n_int;
IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
wrapper : entity work.Z80CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map(
clock => clock,
-- Z80 Signals
RESET_n => RESET_n,
CLK_n => CLK_n,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n,
Addr => Addr_int,
Data => Data,
-- Buffer Control Signals
tristate_n => tristate_n,
tristate_ad_n => tristate_ad_n,
DIRD => open,
-- Mode jumper, tie low to generate NOPs when paused
mode => mode,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2,
test3 => test3,
test4 => test4
);
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff09 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rstn : std_logic);
end dff09;
architecture behav of dff09 is
begin
process (clk, rstn) is
constant rval : std_logic := '0';
begin
if rstn = '0' then
q <= rval;
elsif rising_edge (clk) then
q <= d;
end if;
end process;
end behav;
|
--This file is auto-generated by compile_dspip_lib.pl
--Date:06/07/2007
--Time:19:15
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use auk_dspip_lib.auk_dspip_math_pkg.all;
package auk_dspip_lib_pkg is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller
--auk_dspip_avalon_streaming_controller_pe
--auk_dspip_avalon_streaming_sink
--auk_dspip_avalon_streaming_source
--auk_dspip_delay
--auk_dspip_fastadd
--auk_dspip_fastaddsub
--auk_dspip_pipelined_adder
--auk_dspip_fast_accumulator
--auk_dspip_fifo_pfc
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc
--auk_dspip_roundsat
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller is
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller;
component auk_dspip_avalon_streaming_controller_pe is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe;
component auk_dspip_avalon_streaming_sink is
generic(
WIDTH_g : integer := 16;
PACKET_SIZE_g : natural := 4;
FIFO_DEPTH_g : natural := 5; --if PFC mode is selected, this generic
--is used for passing the poly_factor.
MIN_DATA_COUNT_g : natural := 2;
PFC_MODE_g : boolean := false;
SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink;
component auk_dspip_avalon_streaming_source is
generic(
WIDTH_g : integer := 16;
PACKET_SIZE_g : natural := 4;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
MULTI_CHANNEL_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
design_stall : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source;
component auk_dspip_delay is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay;
component auk_dspip_fastadd is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd;
component auk_dspip_fastaddsub is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub;
component auk_dspip_pipelined_adder is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder;
component auk_dspip_fast_accumulator is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator;
component auk_dspip_fifo_pfc is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc;
component auk_dspip_roundsat is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat;
component auk_dspip_avalon_streaming_block_source is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source;
component auk_dspip_avalon_streaming_block_sink is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink;
end package auk_dspip_lib_pkg;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl2
-- File: irqctrl2.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Secondary interrupt controller. Handles up to 32 extra
-- interrupts, which are mapped on one of the 15 standard
-- SPARC interrupts. Filtering is hard-coded in the
-- configuration record.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.iface.all;
use work.macro.orv;
use work.amba.all;
use work.config.all;
entity irqctrl2 is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq2_in_type;
irqo : out irq2_out_type
);
end;
architecture rtl of irqctrl2 is
type irqregs is record
imask : std_logic_vector(IRQ2CHAN-1 downto 0);
ipend : std_logic_vector(IRQ2CHAN-1 downto 0);
ireg : std_logic_vector(IRQ2CHAN-1 downto 0);
irl : std_logic_vector(4 downto 0);
irq : std_logic;
end record;
function priority(v : std_logic_vector(31 downto 0)) return std_logic_vector is
begin
if v(31) = '1' then return("11111");
elsif v(30) = '1' then return("11110");
elsif v(29) = '1' then return("11101");
elsif v(28) = '1' then return("11100");
elsif v(27) = '1' then return("11011");
elsif v(26) = '1' then return("11010");
elsif v(25) = '1' then return("11001");
elsif v(24) = '1' then return("11000");
elsif v(23) = '1' then return("10111");
elsif v(22) = '1' then return("10110");
elsif v(21) = '1' then return("10101");
elsif v(20) = '1' then return("10100");
elsif v(19) = '1' then return("10011");
elsif v(18) = '1' then return("10010");
elsif v(17) = '1' then return("10001");
elsif v(16) = '1' then return("10000");
elsif v(15) = '1' then return("01111");
elsif v(14) = '1' then return("01110");
elsif v(13) = '1' then return("01101");
elsif v(12) = '1' then return("01100");
elsif v(11) = '1' then return("01011");
elsif v(10) = '1' then return("01010");
elsif v( 9) = '1' then return("01001");
elsif v( 8) = '1' then return("01000");
elsif v( 7) = '1' then return("00111");
elsif v( 6) = '1' then return("00110");
elsif v( 5) = '1' then return("00101");
elsif v( 4) = '1' then return("00100");
elsif v( 3) = '1' then return("00011");
elsif v( 2) = '1' then return("00010");
elsif v( 1) = '1' then return("00001");
else return ("00000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable tmp : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
tmp := (others => '0');
for i in 0 to IRQ2CHAN-1 loop
case IRQ2TBL(i) is
when lvl0 => tmp(i) := not irqi.irq(i);
when lvl1 => tmp(i) := irqi.irq(i);
when edge0 => tmp(i) := ir.ireg(i) and not irqi.irq(i);
when edge1 => tmp(i) := (not ir.ireg(i)) and irqi.irq(i);
end case;
end loop;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(IRQ2CHAN-1 downto 0) := ir.imask;
when "01" => rdata(IRQ2CHAN-1 downto 0) := ir.ipend;
when "10" => rdata(5 downto 0) := ir.irq & ir.irl;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.imask := apbi.pwdata(IRQ2CHAN-1 downto 0);
when "01" => irv.ipend := ir.ipend or apbi.pwdata(IRQ2CHAN-1 downto 0);
when "10" => irv.ipend := ir.ipend and not apbi.pwdata(IRQ2CHAN-1 downto 0);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or tmp(IRQ2CHAN-1 downto 0);
tmp(IRQ2CHAN-1 downto 0) := ir.imask and ir.ipend;
irv.irl := priority(tmp);
irv.irq := orv(tmp);
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
irv.ipend := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irq <= ir.irq;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
ir.imask <= irin.imask; ir.ipend <= irin.ipend;
ir.irq <= irin.irq; ir.irl <= irin.irl;
end if;
end process;
-- generate only those registers that are necessary
filt0 : for i in 0 to (IRQ2CHAN -1) generate
filt1 : if (IRQ2TBL(i) > lvl1) generate
regs : process(clk)
begin if rising_edge(clk) then ir.ireg(i) <= irqi.irq(i); end if; end process;
end generate;
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl2
-- File: irqctrl2.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Secondary interrupt controller. Handles up to 32 extra
-- interrupts, which are mapped on one of the 15 standard
-- SPARC interrupts. Filtering is hard-coded in the
-- configuration record.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.iface.all;
use work.macro.orv;
use work.amba.all;
use work.config.all;
entity irqctrl2 is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq2_in_type;
irqo : out irq2_out_type
);
end;
architecture rtl of irqctrl2 is
type irqregs is record
imask : std_logic_vector(IRQ2CHAN-1 downto 0);
ipend : std_logic_vector(IRQ2CHAN-1 downto 0);
ireg : std_logic_vector(IRQ2CHAN-1 downto 0);
irl : std_logic_vector(4 downto 0);
irq : std_logic;
end record;
function priority(v : std_logic_vector(31 downto 0)) return std_logic_vector is
begin
if v(31) = '1' then return("11111");
elsif v(30) = '1' then return("11110");
elsif v(29) = '1' then return("11101");
elsif v(28) = '1' then return("11100");
elsif v(27) = '1' then return("11011");
elsif v(26) = '1' then return("11010");
elsif v(25) = '1' then return("11001");
elsif v(24) = '1' then return("11000");
elsif v(23) = '1' then return("10111");
elsif v(22) = '1' then return("10110");
elsif v(21) = '1' then return("10101");
elsif v(20) = '1' then return("10100");
elsif v(19) = '1' then return("10011");
elsif v(18) = '1' then return("10010");
elsif v(17) = '1' then return("10001");
elsif v(16) = '1' then return("10000");
elsif v(15) = '1' then return("01111");
elsif v(14) = '1' then return("01110");
elsif v(13) = '1' then return("01101");
elsif v(12) = '1' then return("01100");
elsif v(11) = '1' then return("01011");
elsif v(10) = '1' then return("01010");
elsif v( 9) = '1' then return("01001");
elsif v( 8) = '1' then return("01000");
elsif v( 7) = '1' then return("00111");
elsif v( 6) = '1' then return("00110");
elsif v( 5) = '1' then return("00101");
elsif v( 4) = '1' then return("00100");
elsif v( 3) = '1' then return("00011");
elsif v( 2) = '1' then return("00010");
elsif v( 1) = '1' then return("00001");
else return ("00000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable tmp : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
tmp := (others => '0');
for i in 0 to IRQ2CHAN-1 loop
case IRQ2TBL(i) is
when lvl0 => tmp(i) := not irqi.irq(i);
when lvl1 => tmp(i) := irqi.irq(i);
when edge0 => tmp(i) := ir.ireg(i) and not irqi.irq(i);
when edge1 => tmp(i) := (not ir.ireg(i)) and irqi.irq(i);
end case;
end loop;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(IRQ2CHAN-1 downto 0) := ir.imask;
when "01" => rdata(IRQ2CHAN-1 downto 0) := ir.ipend;
when "10" => rdata(5 downto 0) := ir.irq & ir.irl;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.imask := apbi.pwdata(IRQ2CHAN-1 downto 0);
when "01" => irv.ipend := ir.ipend or apbi.pwdata(IRQ2CHAN-1 downto 0);
when "10" => irv.ipend := ir.ipend and not apbi.pwdata(IRQ2CHAN-1 downto 0);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or tmp(IRQ2CHAN-1 downto 0);
tmp(IRQ2CHAN-1 downto 0) := ir.imask and ir.ipend;
irv.irl := priority(tmp);
irv.irq := orv(tmp);
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
irv.ipend := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irq <= ir.irq;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
ir.imask <= irin.imask; ir.ipend <= irin.ipend;
ir.irq <= irin.irq; ir.irl <= irin.irl;
end if;
end process;
-- generate only those registers that are necessary
filt0 : for i in 0 to (IRQ2CHAN -1) generate
filt1 : if (IRQ2TBL(i) > lvl1) generate
regs : process(clk)
begin if rising_edge(clk) then ir.ireg(i) <= irqi.irq(i); end if; end process;
end generate;
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl2
-- File: irqctrl2.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Secondary interrupt controller. Handles up to 32 extra
-- interrupts, which are mapped on one of the 15 standard
-- SPARC interrupts. Filtering is hard-coded in the
-- configuration record.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.iface.all;
use work.macro.orv;
use work.amba.all;
use work.config.all;
entity irqctrl2 is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq2_in_type;
irqo : out irq2_out_type
);
end;
architecture rtl of irqctrl2 is
type irqregs is record
imask : std_logic_vector(IRQ2CHAN-1 downto 0);
ipend : std_logic_vector(IRQ2CHAN-1 downto 0);
ireg : std_logic_vector(IRQ2CHAN-1 downto 0);
irl : std_logic_vector(4 downto 0);
irq : std_logic;
end record;
function priority(v : std_logic_vector(31 downto 0)) return std_logic_vector is
begin
if v(31) = '1' then return("11111");
elsif v(30) = '1' then return("11110");
elsif v(29) = '1' then return("11101");
elsif v(28) = '1' then return("11100");
elsif v(27) = '1' then return("11011");
elsif v(26) = '1' then return("11010");
elsif v(25) = '1' then return("11001");
elsif v(24) = '1' then return("11000");
elsif v(23) = '1' then return("10111");
elsif v(22) = '1' then return("10110");
elsif v(21) = '1' then return("10101");
elsif v(20) = '1' then return("10100");
elsif v(19) = '1' then return("10011");
elsif v(18) = '1' then return("10010");
elsif v(17) = '1' then return("10001");
elsif v(16) = '1' then return("10000");
elsif v(15) = '1' then return("01111");
elsif v(14) = '1' then return("01110");
elsif v(13) = '1' then return("01101");
elsif v(12) = '1' then return("01100");
elsif v(11) = '1' then return("01011");
elsif v(10) = '1' then return("01010");
elsif v( 9) = '1' then return("01001");
elsif v( 8) = '1' then return("01000");
elsif v( 7) = '1' then return("00111");
elsif v( 6) = '1' then return("00110");
elsif v( 5) = '1' then return("00101");
elsif v( 4) = '1' then return("00100");
elsif v( 3) = '1' then return("00011");
elsif v( 2) = '1' then return("00010");
elsif v( 1) = '1' then return("00001");
else return ("00000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable tmp : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
tmp := (others => '0');
for i in 0 to IRQ2CHAN-1 loop
case IRQ2TBL(i) is
when lvl0 => tmp(i) := not irqi.irq(i);
when lvl1 => tmp(i) := irqi.irq(i);
when edge0 => tmp(i) := ir.ireg(i) and not irqi.irq(i);
when edge1 => tmp(i) := (not ir.ireg(i)) and irqi.irq(i);
end case;
end loop;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(IRQ2CHAN-1 downto 0) := ir.imask;
when "01" => rdata(IRQ2CHAN-1 downto 0) := ir.ipend;
when "10" => rdata(5 downto 0) := ir.irq & ir.irl;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.imask := apbi.pwdata(IRQ2CHAN-1 downto 0);
when "01" => irv.ipend := ir.ipend or apbi.pwdata(IRQ2CHAN-1 downto 0);
when "10" => irv.ipend := ir.ipend and not apbi.pwdata(IRQ2CHAN-1 downto 0);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or tmp(IRQ2CHAN-1 downto 0);
tmp(IRQ2CHAN-1 downto 0) := ir.imask and ir.ipend;
irv.irl := priority(tmp);
irv.irq := orv(tmp);
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
irv.ipend := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irq <= ir.irq;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
ir.imask <= irin.imask; ir.ipend <= irin.ipend;
ir.irq <= irin.irq; ir.irl <= irin.irl;
end if;
end process;
-- generate only those registers that are necessary
filt0 : for i in 0 to (IRQ2CHAN -1) generate
filt1 : if (IRQ2TBL(i) > lvl1) generate
regs : process(clk)
begin if rising_edge(clk) then ir.ireg(i) <= irqi.irq(i); end if; end process;
end generate;
end generate;
end;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/02 20:52:44
-- Nombre del módulo: pwm_dc_101 - behavior
-- Descripción:
-- Banco de pruebas para el módulo pwm_dc_101.vhd
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pwm_dc_101_tb IS
END pwm_dc_101_tb;
ARCHITECTURE behavior OF pwm_dc_101_tb IS
-- Declaración del componente de la unidad bajo prueba (UUT).
COMPONENT pwm_dc_101
PORT(
clk : IN std_logic;
reset : IN std_logic;
entrada : IN std_logic_vector(6 downto 0);
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal entrada : std_logic_vector(6 downto 0) := (others => '0');
-- Salidas
signal salida : std_logic;
-- Definición del periodo de reloj.
constant clk_period : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba (UUT).
uut: pwm_dc_101 PORT MAP (
clk => clk,
reset => reset,
entrada => entrada,
salida => salida
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estímulos.
stim_proc: process
begin
-- Estado de reset.
reset <= '1';
wait for 100 ns;
reset <= '0';
-- Simulación.
entrada <= "0000000"; -- Porcentaje en 0%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "0000001"; -- Porcentaje en 1%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "0011110"; -- Porcentaje en 30%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1010000"; -- Porcentaje en 80%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1100011"; -- Porcentaje en 99%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1100100"; -- Porcentaje en 100%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1111000"; -- Porcentaje en 120%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
wait;
end process;
END; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/02 20:52:44
-- Nombre del módulo: pwm_dc_101 - behavior
-- Descripción:
-- Banco de pruebas para el módulo pwm_dc_101.vhd
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pwm_dc_101_tb IS
END pwm_dc_101_tb;
ARCHITECTURE behavior OF pwm_dc_101_tb IS
-- Declaración del componente de la unidad bajo prueba (UUT).
COMPONENT pwm_dc_101
PORT(
clk : IN std_logic;
reset : IN std_logic;
entrada : IN std_logic_vector(6 downto 0);
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal entrada : std_logic_vector(6 downto 0) := (others => '0');
-- Salidas
signal salida : std_logic;
-- Definición del periodo de reloj.
constant clk_period : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba (UUT).
uut: pwm_dc_101 PORT MAP (
clk => clk,
reset => reset,
entrada => entrada,
salida => salida
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estímulos.
stim_proc: process
begin
-- Estado de reset.
reset <= '1';
wait for 100 ns;
reset <= '0';
-- Simulación.
entrada <= "0000000"; -- Porcentaje en 0%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "0000001"; -- Porcentaje en 1%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "0011110"; -- Porcentaje en 30%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1010000"; -- Porcentaje en 80%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1100011"; -- Porcentaje en 99%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1100100"; -- Porcentaje en 100%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
entrada <= "1111000"; -- Porcentaje en 120%.
wait for clk_period * 200; -- Esperamos dos ciclos completos.
wait;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_DECISION is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_DECISION is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_DECISION : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1)
VARIABLE temp : SIGNED(15 downto 0);
begin
temp := SIGNED( INPUT_1(15 downto 0) );
IF temp < TO_SIGNED(0, 16) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( TO_UNSIGNED(0, 32) );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( TO_UNSIGNED(1, 32) );
END IF;
END PROCESS;
-------------------------------------------------------------------------
END; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS_pkg.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE LMS_pkg IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
END LMS_pkg;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS_pkg.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE LMS_pkg IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
END LMS_pkg;
|
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk_wiz_v3_6_tb is
end clk_wiz_v3_6_tb;
architecture test of clk_wiz_v3_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clk_wiz_v3_6_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk_wiz_v3_6_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
debug_out : out STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal shiftreg : std_logic_vector(15 downto 0) := "1111111010110100";
signal counter : std_logic_vector(12 downto 0) := (others => '0');
begin
data_out <= shiftreg(0);
debug_out <= shiftreg(0);
process(clk)
begin
if rising_edge(clk) then
if counter=3332 then
shiftreg <= shiftreg(0) & shiftreg(15 downto 1);
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter
end if; -- rising_edge
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Notas:
-- La idea de este modulo es expandir la cantidad de registros disponibles
-- con 5 bits yo solo tengo 2**5 -1 registros. Las ventanas nos dejar ir moviendonos
-- para tener mas ventanas, en nuestra arquitectura de 40 a 520.
-- Los registros globales siempre van a estar en la misma posicion, los unicos que se mueven son los locales,outs, inputs.
--Basado en https://www.educreations.com/lesson/view/procesador-sparc-v8-soportando-windowing/13230159/
-- analizar el estado del psr en los primeros 5 bits que son cwp
--save: cwp<=cwp-1 >> cwp<='0'
--restore: cwp<=cwp+1 >> cwp<='1'
entity windows_manager_arch is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC;
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC);
end windows_manager_arch;
architecture Behavioral of windows_manager_arch is
begin
process(rs1,rs2,rd,cwp)
begin
--si es locales y salida, usa la logica del video:
-- 10 y 23
if (rs1>="01000" and rs1<="10111") then
nrs1<=conv_std_logic_vector(conv_integer(rs1)+(conv_integer(cwp)*16),6);
end if;
if (rs2>="01000" and rs2<="10111") then
nrs2<=conv_std_logic_vector(conv_integer(rs2)+(conv_integer(cwp)*16),6);
end if;
if (rd>="01000" and rd<="10111") then
nrd<=conv_std_logic_vector(conv_integer(rd)+(conv_integer(cwp)*16),6);
end if;
--si es entrada
if (rs1>="11000" and rs1<="11111") then
nrs1<=conv_std_logic_vector(conv_integer(rs1)-(conv_integer(cwp)*16),6);
end if;
if (rs2>="11000" and rs2<="11111") then
nrs2<=conv_std_logic_vector(conv_integer(rs2)-(conv_integer(cwp)*16),6);
end if;
if (rd>="11000" and rd<="11111") then
nrd<=conv_std_logic_vector(conv_integer(rd)-(conv_integer(cwp)*16),6);
end if;
--si son globales esas siempre van a quedar en la misma parte
if (rs1>="00000" and rs1<="00111") then
nrs1<='0'&rs1;
end if;
if (rs2>="00000" and rs2<="00111") then
nrs2<='0'&rs2;
end if;
if (rd>="00000" and rd<="00111") then
nrd<='0'&rd;
end if;
end process;
process(op,op3,cwp)
begin
if (op="10") and (cwp = '1') then
-- para save
if (op3="111100")then -- save
ncwp<='0';
end if;
if (op3="111101")then --restore
ncwp<='1';
end if;
end if;
if (op="10") and (cwp = '0') then
--restore
if (op3="111101")then --restore
ncwp<='1';
end if;
if (op3="111100")then --save
ncwp<='0';
end if;
end if;
if(op="10")then
if ((op3/="111100") and (op3/="111101"))then
ncwp <= cwp;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with SD feature set
--
-- $Id: chip-sd-a.vhd,v 1.7 2007-08-06 23:31:42 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture sd of chip is
component spi_boot
generic (
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
constant width_img_cnt_c : integer := 2; -- 4 images
constant num_bits_per_img_c : integer := 18; -- 256 kByte per image
constant set_sel_width_c : integer := 31-width_img_cnt_c-num_bits_per_img_c;
signal set_sel_s : std_logic_vector(set_sel_width_c downto 0);
begin
set_sel_s <= (3 => not set_sel_n_i(3),
2 => not set_sel_n_i(2),
1 => not set_sel_n_i(1),
0 => not set_sel_n_i(0),
others => '0');
spi_boot_b : spi_boot
generic map (
width_bit_cnt_g => 12, -- 512 bytes per block
width_img_cnt_g => width_img_cnt_c,
num_bits_per_img_g => num_bits_per_img_c,
sd_init_g => 1, -- SD specific initialization
mmc_compat_clk_div_g => 0, -- no MMC compatibility
width_mmc_clk_div_g => 0 -- no MMC compatibility
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end sd;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:14 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:32 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ps2_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
PS2_Data_I : in std_logic;
PS2_Data_O : out std_logic;
PS2_Data_T : out std_logic;
PS2_Clk_I : in std_logic;
PS2_Clk_O : out std_logic;
PS2_Clk_T : out std_logic;
PS2_interrupt : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
S_AXI_aclk : in std_logic;
S_AXI_aresetn : in std_logic;
S_AXI_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_awprot : in std_logic_vector(2 downto 0);
S_AXI_awvalid : in std_logic;
S_AXI_awready : out std_logic;
S_AXI_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_wvalid : in std_logic;
S_AXI_wready : out std_logic;
S_AXI_bresp : out std_logic_vector(1 downto 0);
S_AXI_bvalid : out std_logic;
S_AXI_bready : in std_logic;
S_AXI_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_arprot : in std_logic_vector(2 downto 0);
S_AXI_arvalid : in std_logic;
S_AXI_arready : out std_logic;
S_AXI_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_rresp : out std_logic_vector(1 downto 0);
S_AXI_rvalid : out std_logic;
S_AXI_rready : in std_logic
);
end axi_ps2_v1_0;
architecture arch_imp of axi_ps2_v1_0 is
-- component declaration
component axi_ps2_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
lTxDataReg : out std_logic_vector (31 downto 0);
lRxDataReg : in std_logic_vector (31 downto 0);
lTxTrig : out std_logic;
lRxAck : out std_logic;
lStatusReg : in std_logic_vector (31 downto 0);
IsrBitTxNoack : in std_logic;
IsrBitTxAck : in std_logic;
IsrBitRxOvf : in std_logic;
IsrBitRxErr : in std_logic;
IsrBitRxFull : in std_logic;
SrstOut : out std_logic;
IntrOut : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_ps2_v1_0_S_AXI;
signal lCtlTxDataReg : std_logic_vector (31 downto 0);
signal lCtlRxDataReg : std_logic_vector (31 downto 0);
signal lCtlTxTrig : std_logic;
signal lCtlRxAck : std_logic;
signal lCtlSrst : std_logic;
signal lCtlStatusReg : std_logic_vector (31 downto 0);
signal lCtlIsrBitTxNoAck : std_logic;
signal lCtlIsrBitTxAck : std_logic;
signal lCtlIsrBitRxOvf : std_logic;
signal lCtlIsrBitRxErr : std_logic;
signal lCtlIsrBitRxFull : std_logic;
begin
axi_ps2_v1_0_S_AXI_inst : axi_ps2_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
lTxDataReg => lCtlTxDataReg,
lRxDataReg => lCtlRxDataReg,
lTxTrig => lCtlTxTrig,
lRxAck => lCtlRxAck,
lStatusReg => lCtlStatusReg,
IsrBitTxNoAck => lCtlIsrBitTxNoack,
IsrBitTxAck => lCtlIsrBitTxAck,
IsrBitRxOvf => lCtlIsrBitRxOvf,
IsrBitRxErr => lCtlIsrBitRxErr,
IsrBitRxFull => lCtlIsrBitRxFull,
SrstOut => lCtlSrst,
IntrOut => PS2_interrupt,
S_AXI_ACLK => S_AXI_aclk,
S_AXI_ARESETN => S_AXI_aresetn,
S_AXI_AWADDR => S_AXI_awaddr,
S_AXI_AWPROT => S_AXI_awprot,
S_AXI_AWVALID => S_AXI_awvalid,
S_AXI_AWREADY => S_AXI_awready,
S_AXI_WDATA => S_AXI_wdata,
S_AXI_WSTRB => S_AXI_wstrb,
S_AXI_WVALID => S_AXI_wvalid,
S_AXI_WREADY => S_AXI_wready,
S_AXI_BRESP => S_AXI_bresp,
S_AXI_BVALID => S_AXI_bvalid,
S_AXI_BREADY => S_AXI_bready,
S_AXI_ARADDR => S_AXI_araddr,
S_AXI_ARPROT => S_AXI_arprot,
S_AXI_ARVALID => S_AXI_arvalid,
S_AXI_ARREADY => S_AXI_arready,
S_AXI_RDATA => S_AXI_rdata,
S_AXI_RRESP => S_AXI_rresp,
S_AXI_RVALID => S_AXI_rvalid,
S_AXI_RREADY => S_AXI_rready
);
-- Add user logic here
Wrapper: entity work.Ps2InterfaceWrapper
port map (
PS2_Data_I => PS2_Data_I,
PS2_Data_O => PS2_Data_O,
PS2_Data_T => PS2_Data_T,
PS2_Clk_I => PS2_Clk_I,
PS2_Clk_O => PS2_Clk_O,
PS2_Clk_T => PS2_Clk_T,
clk => S_AXI_aclk,
rst => S_AXI_aresetn,
lSrst => lCtlSrst,
lTxDataReg => lCtlTxDataReg,
lTxTrig => lCtlTxTrig,
lRxDataReg => lCtlRxDataReg,
lRxAck => lCtlRxAck,
IsrBitTxNoAck => lCtlIsrBitTxNoack,
IsrBitTxAck => lCtlIsrBitTxAck,
IsrBitRxOvf => lCtlIsrBitRxOvf,
IsrBitRxErr => lCtlIsrBitRxErr,
IsrBitRxFull => lCtlIsrBitRxFull,
lStatusReg => lCtlStatusReg
);
-- User logic ends
end arch_imp;
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