content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dma_bus_pkg is
type t_dma_req is record
request : std_logic;
read_writen : std_logic;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
end record;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dma_bus_pkg is
type t_dma_req is record
request : std_logic;
read_writen : std_logic;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
end record;
... |
--------------------------------------------------------------------------------
-- FILE: Mux4
-- DESC: 4 inputs 1 output multiplexer
--
-- Author:
-- Create: 2015-05-28
-- Update: 2015-05-30
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_l... |
-- $Id: sys_conf1_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys... |
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- lpddr2ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic... |
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- lpddr2ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic... |
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- lpddr2ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
-- Fixes follow
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure pro... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
-- Date : Mon Jun 6 23:00:45 2016
-- Host : edinburgh running 64-bit Ubuntu 15.0... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Entity Declaration for di_tnry
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- A DCM block would be more accurate, right?
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity clkdivider is
port (
ticks : in natural;
bigclk : in std_logic;
rst : in std_logic;
smallclk : out std_logic
);
end;
architecture behav of clkdivider is
begi... |
-- Btrace 448
-- Point Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity point_reg is
port(clk, rst, en: in std_logic;
Din: in point;
Dout: out point);
end point_reg;
architecture arch of point_reg is
constant zero_point: point := ((others => '0... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string :=... |
-- Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity shiftregister is
generic
(
NUM_STAGES : natural := 10
);
port
(
clk : in std_logic;
en : in std_logic;
load : in std_logic;
P_S : in std_logic;
D : in std_logic_vector(NUM_STAGES-1 downto 0);
Q : out std_logic_vector(NUM_S... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
-- CONNECTIVITY DEFINITION
entity bigfile is
port (
-- from external pins
sysclk : in std_logic;
g_zaq_in : in std_logic_vector(31 downto 0);
g_aux : in std_logic_vector(31 downto 0);
scanb : in ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity PC is
port(
clock : in vl_logic;
reset : in vl_logic;
PCEn : in vl_logic;
\in\ : in vl_logic_vector(7 downto 0);
\out\ : out vl_logic_vector(7 downto 0)
... |
-- SHA256 Hashing Module - ROM with test data
-- Kristian Klomsten Skordal <kristian.skordal@wafflemail.net>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testrom is
port(
clk : in std_logic;
word_address : in std_logic_vector(5 downto 0);
word_output : out std_logic_vector(31 ... |
-- NEED RESULT: ARCH00121.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00121.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00121.P3: Multi tr... |
-----------------------------------------------------------
-- cos_phase_table.vhd
--
-- Lookup 16bit value from a cos(x) table.
-- Table resolution is 12 bits (4096 entries)
--
-- y = cos(x) -- where x is digital phase Q
--
-- Q = (radian/2*pi)*((2^phase_depth))
-- or if you talk degrees
-- Q = ( degrees/... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at 09/14/16 20:54:53
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 1
-- Master address width: 28
-- Slave address width: 8
-- Port size: ... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:02)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:29 11/22/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
---------------------------------------------------------------------------
-- keyboard_processor.vhd --
-- Sai Koppula --
-- 3-13 --
-- ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief System Top level modules and interconnect declarations.
----------------------------------------... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_G... |
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port ( i: in std_logic_vector(1 downto 0);
o: out std_logic_vector(1 downto 0));
end inverter;
architecture inverter_beh of inverter is
begin
o <= not i;
end architecture;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BusRouter is
PORT(
SW: IN std_logic_vector(9 downto 0);
KEY: IN std_logic_vector(3 downto 0);
LEDR: OUT std_logic_vector(9 downto 0) := (others => '0');
LEDG: OUT std_logic_vector(7 downto 0) := (others => '0... |
--------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organizat... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal AWADDR : std_logic_vector(6 downto 0);
signal AWPROT : std_logic_vector(2 downto 0);
signal AWVALID : std_logic;
signal AWREADY : std_... |
--------------------------------------------------------------------------------
-- File Name: conversions.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity sub_rng1 is
port (
clk : in std_logic;
a : in natural range 0 to 7;
b : out natural range 0 to 7
);
end sub_rng1;
architecture rtl of sub_rng1 is
begin
process(clk)
begin
if rising_edge(clk) then
b <= a;
end if;
end process;
end rtl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:23 12/19/2013
-- Design Name:
-- Module Name: virtual_top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:23 12/19/2013
-- Design Name:
-- Module Name: virtual_top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue2 is
end issue2;
architecture beh of issue2 is
begin
assert (unsigned'("1111") > unsigned'("0111"));
assert (unsigned'("1111") >= unsigned'("0111"));
assert (unsigned'("0111") < unsigned'("1111"));
assert (unsigned'("01... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:40 2014
-- Host : CE-2013-124 running 64-bit Service Pa... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
use work.c.all;
package b is
end package;
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is ... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is ... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is ... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is ... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register7 is
Port (
rst_n : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 6 DOWNTO 0 );
dout : out STD_LOGIC_VECTOR ( 6 DOWNTO 0 )
);
end Register7;
architecture... |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0));
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 do... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:26:55 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
library verilog;
use verilog.vl_types.all;
entity mss_clockgen is
generic(
CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
SYSCLK : in vl_logic;
F2MRESETN : in vl_logic;
MSSRESETN : in vl_logi... |
library verilog;
use verilog.vl_types.all;
entity mss_clockgen is
generic(
CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
SYSCLK : in vl_logic;
F2MRESETN : in vl_logic;
MSSRESETN : in vl_logi... |
library verilog;
use verilog.vl_types.all;
entity mss_clockgen is
generic(
CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
SYSCLK : in vl_logic;
F2MRESETN : in vl_logic;
MSSRESETN : in vl_logi... |
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 08.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED... |
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 08.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:48:40 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/Tester_tb.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool version... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Internal SRAM implementation with the byte access.
------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Internal SRAM implementation with the byte access.
------------------------------------------------------------------... |
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