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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package dma_bus_pkg is type t_dma_req is record request : std_logic; read_writen : std_logic; address : unsigned(15 downto 0); data : std_logic_vector(7 downto 0); end record; type t_dma_resp is record data : std_logic_vector(7 downto 0); rack : std_logic; dack : std_logic; end record; constant c_dma_req_init : t_dma_req := ( request => '0', read_writen => '1', address => (others => '0'), data => X"00" ); constant c_dma_resp_init : t_dma_resp := ( data => X"00", rack => '0', dack => '0' ); type t_dma_req_array is array(natural range <>) of t_dma_req; type t_dma_resp_array is array(natural range <>) of t_dma_resp; end package; package body dma_bus_pkg is end package body;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package dma_bus_pkg is type t_dma_req is record request : std_logic; read_writen : std_logic; address : unsigned(15 downto 0); data : std_logic_vector(7 downto 0); end record; type t_dma_resp is record data : std_logic_vector(7 downto 0); rack : std_logic; dack : std_logic; end record; constant c_dma_req_init : t_dma_req := ( request => '0', read_writen => '1', address => (others => '0'), data => X"00" ); constant c_dma_resp_init : t_dma_resp := ( data => X"00", rack => '0', dack => '0' ); type t_dma_req_array is array(natural range <>) of t_dma_req; type t_dma_resp_array is array(natural range <>) of t_dma_resp; end package; package body dma_bus_pkg is end package body;
-------------------------------------------------------------------------------- -- FILE: Mux4 -- DESC: 4 inputs 1 output multiplexer -- -- Author: -- Create: 2015-05-28 -- Update: 2015-05-30 -- Status: TESTED -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.Consts.all; -------------------------------------------------------------------------------- -- ENTITY -------------------------------------------------------------------------------- entity Mux4 is generic( DATA_SIZE: integer := C_SYS_DATA_SIZE ); port( sel: in std_logic_vector(1 downto 0); din0: in std_logic_vector(DATA_SIZE-1 downto 0); din1: in std_logic_vector(DATA_SIZE-1 downto 0); din2: in std_logic_vector(DATA_SIZE-1 downto 0); din3: in std_logic_vector(DATA_SIZE-1 downto 0); dout: out std_logic_vector(DATA_SIZE-1 downto 0) ); end Mux4; -------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------- architecture mux4_arch of Mux4 is begin dout <= din0 when sel="00" else din1 when sel="01" else din2 when sel="10" else din3 when sel="11"; end mux4_arch;
-- $Id: sys_conf1_sim.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- ------------------------------------------------------------------------------ -- Package Name: sys_conf -- Description: Definitions for sys_tst_serloop1_n3 (for test bench) -- -- Dependencies: - -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-11 438 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; package sys_conf is -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec -- to 100 cycles (1 usec). This affects the pulse generators (usec) and -- mainly the autobauder. A break will be detected after 128 msec periods, -- this in simulation after 128 usec or 6400 cycles. This is compatible with -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! constant sys_conf_hio_debounce : boolean := false; -- no debouncers constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim end package sys_conf;
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0% -- GENERATION: XML -- lpddr2ctrl1.vhd -- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity lpddr2ctrl1 is port ( pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk global_reset_n : in std_logic := '0'; -- global_reset.reset_n soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n afi_clk : out std_logic; -- afi_clk.clk afi_half_clk : out std_logic; -- afi_half_clk.clk afi_reset_n : out std_logic; -- afi_reset.reset_n afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n mem_ca : out std_logic_vector(9 downto 0); -- memory.mem_ca mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n avl_ready : out std_logic; -- avl.waitrequest_n avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address avl_rdata_valid : out std_logic; -- .readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- .readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata avl_be : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail oct_rzqin : in std_logic := '0'; -- oct.rzqin pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk pll_write_clk : out std_logic; -- .pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk pll_locked : out std_logic; -- .pll_locked pll_avl_clk : out std_logic; -- .pll_avl_clk pll_config_clk : out std_logic; -- .pll_config_clk pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk afi_phy_clk : out std_logic; -- .afi_phy_clk pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk ); end entity lpddr2ctrl1; architecture rtl of lpddr2ctrl1 is component lpddr2ctrl1_0002 is port ( pll_ref_clk : in std_logic := 'X'; -- clk global_reset_n : in std_logic := 'X'; -- reset_n soft_reset_n : in std_logic := 'X'; -- reset_n afi_clk : out std_logic; -- clk afi_half_clk : out std_logic; -- clk afi_reset_n : out std_logic; -- reset_n afi_reset_export_n : out std_logic; -- reset_n mem_ca : out std_logic_vector(9 downto 0); -- mem_ca mem_ck : out std_logic_vector(0 downto 0); -- mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n avl_ready : out std_logic; -- waitrequest_n avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address avl_rdata_valid : out std_logic; -- readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable avl_read_req : in std_logic := 'X'; -- read avl_write_req : in std_logic := 'X'; -- write avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail oct_rzqin : in std_logic := 'X'; -- rzqin pll_mem_clk : out std_logic; -- pll_mem_clk pll_write_clk : out std_logic; -- pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk pll_locked : out std_logic; -- pll_locked pll_avl_clk : out std_logic; -- pll_avl_clk pll_config_clk : out std_logic; -- pll_config_clk pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk afi_phy_clk : out std_logic; -- afi_phy_clk pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk ); end component lpddr2ctrl1_0002; begin lpddr2ctrl1_inst : component lpddr2ctrl1_0002 port map ( pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk global_reset_n => global_reset_n, -- global_reset.reset_n soft_reset_n => soft_reset_n, -- soft_reset.reset_n afi_clk => afi_clk, -- afi_clk.clk afi_half_clk => afi_half_clk, -- afi_half_clk.clk afi_reset_n => afi_reset_n, -- afi_reset.reset_n afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n mem_ca => mem_ca, -- memory.mem_ca mem_ck => mem_ck, -- .mem_ck mem_ck_n => mem_ck_n, -- .mem_ck_n mem_cke => mem_cke, -- .mem_cke mem_cs_n => mem_cs_n, -- .mem_cs_n mem_dm => mem_dm, -- .mem_dm mem_dq => mem_dq, -- .mem_dq mem_dqs => mem_dqs, -- .mem_dqs mem_dqs_n => mem_dqs_n, -- .mem_dqs_n avl_ready => avl_ready, -- avl.waitrequest_n avl_burstbegin => avl_burstbegin, -- .beginbursttransfer avl_addr => avl_addr, -- .address avl_rdata_valid => avl_rdata_valid, -- .readdatavalid avl_rdata => avl_rdata, -- .readdata avl_wdata => avl_wdata, -- .writedata avl_be => avl_be, -- .byteenable avl_read_req => avl_read_req, -- .read avl_write_req => avl_write_req, -- .write avl_size => avl_size, -- .burstcount local_init_done => local_init_done, -- status.local_init_done local_cal_success => local_cal_success, -- .local_cal_success local_cal_fail => local_cal_fail, -- .local_cal_fail oct_rzqin => oct_rzqin, -- oct.rzqin pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk pll_write_clk => pll_write_clk, -- .pll_write_clk pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk pll_locked => pll_locked, -- .pll_locked pll_avl_clk => pll_avl_clk, -- .pll_avl_clk pll_config_clk => pll_config_clk, -- .pll_config_clk pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk afi_phy_clk => afi_phy_clk, -- .afi_phy_clk pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk ); end architecture rtl; -- of lpddr2ctrl1 -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1991-2013 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_mem_if_lpddr2_emif" version="13.0" > -- Retrieval info: <generic name="MEM_VENDOR" value="Micron" /> -- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" /> -- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" /> -- Retrieval info: <generic name="DEVICE_DEPTH" value="1" /> -- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" /> -- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" /> -- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" /> -- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" /> -- Retrieval info: <generic name="MEM_DQ_WIDTH" value="16" /> -- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" /> -- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" /> -- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" 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name="WEIGHT_PORT" value="0,0,0,0,0,0" /> -- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" /> -- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" /> -- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" /> -- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ" value="125.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" /> -- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" /> -- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" /> -- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" /> -- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" /> -- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" /> -- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" /> -- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> -- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="USE_FAKE_PHY" value="false" /> -- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" /> -- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" /> -- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" /> -- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" /> -- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" /> -- Retrieval info: <generic name="EXTRA_SETTINGS" value="" /> -- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" /> -- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" /> -- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" /> -- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" /> -- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" /> -- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" /> -- Retrieval info: <generic name="PHY_ONLY" value="false" /> -- Retrieval info: <generic name="SEQ_MODE" value="0" /> -- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" /> -- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" /> -- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" /> -- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" /> -- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" /> -- Retrieval info: <generic name="SKIP_MEM_INIT" value="false" /> -- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" /> -- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" /> -- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" /> -- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" /> -- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" /> -- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" /> -- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" /> -- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" /> -- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" /> -- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" /> -- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" /> -- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" /> -- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" /> -- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" /> -- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" /> -- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" /> -- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" /> -- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" /> -- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" /> -- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" /> -- Retrieval info: </instance> -- IPFS_FILES : lpddr2ctrl1.vho -- RELATED_FILES: lpddr2ctrl1.vhd, lpddr2ctrl1_0002.v, lpddr2ctrl1_pll0.sv, lpddr2ctrl1_p0_clock_pair_generator.v, lpddr2ctrl1_p0_read_valid_selector.v, lpddr2ctrl1_p0_addr_cmd_datapath.v, lpddr2ctrl1_p0_reset.v, lpddr2ctrl1_p0_acv_ldc.v, lpddr2ctrl1_p0_memphy.sv, lpddr2ctrl1_p0_reset_sync.v, lpddr2ctrl1_p0_new_io_pads.v, lpddr2ctrl1_p0_fr_cycle_shifter.v, lpddr2ctrl1_p0_fr_cycle_extender.v, lpddr2ctrl1_p0_read_datapath.sv, lpddr2ctrl1_p0_write_datapath.v, lpddr2ctrl1_p0_simple_ddio_out.sv, lpddr2ctrl1_p0_phy_csr.sv, lpddr2ctrl1_p0_iss_probe.v, lpddr2ctrl1_p0_flop_mem.v, lpddr2ctrl1_p0_addr_cmd_pads.v, lpddr2ctrl1_p0.sv, lpddr2ctrl1_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev_lpddr2.sv, afi_mux_lpddr2.v, lpddr2ctrl1_s0.v, rw_manager_bitcheck.v, rw_manager_datamux.v, lpddr2ctrl1_s0_id_router.sv, altera_merlin_traffic_limiter.sv, lpddr2ctrl1_s0_cmd_xbar_demux_001.sv, sequencer_trk_mgr.sv, lpddr2ctrl1_s0_addr_router_002.sv, sequencer_scc_sv_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_demux_003.sv, rw_manager_ac_ROM_reg.v, altera_merlin_burst_uncompressor.sv, rw_manager_read_datapath.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_data_broadcast.v, altera_avalon_mm_bridge.v, lpddr2ctrl1_s0_irq_mapper.sv, rw_manager_lfsr72.v, sequencer_reg_file.sv, rw_manager_di_buffer_wrap.v, rw_manager_jumplogic.v, altera_merlin_slave_agent.sv, altera_merlin_slave_translator.sv, altera_mem_if_sequencer_mem_no_ifdef_params.sv, lpddr2ctrl1_s0_cmd_xbar_mux.sv, sequencer_data_mgr.sv, sequencer_scc_reg_file.v, rw_manager_ram.v, rw_manager_lpddr2.v, rw_manager_ram_csr.v, rw_manager_generic.sv, altera_avalon_sc_fifo.v, altera_avalon_st_pipeline_base.v, lpddr2ctrl1_s0_id_router_003.sv, lpddr2ctrl1_s0_rsp_xbar_mux_003.sv, rw_manager_write_decoder.v, sequencer_scc_acv_wrapper.sv, rw_manager_ac_ROM_no_ifdef_params.v, lpddr2ctrl1_s0_id_router_001.sv, rw_manager_core.sv, sequencer_phy_mgr.sv, lpddr2ctrl1_s0_cmd_xbar_demux_003.sv, sequencer_scc_acv_phase_decode.v, lpddr2ctrl1_s0_addr_router.sv, sequencer_scc_siii_phase_decode.v, lpddr2ctrl1_s0_cmd_xbar_demux.sv, lpddr2ctrl1_s0_rsp_xbar_demux.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, rw_manager_dm_decoder.v, lpddr2ctrl1_s0_addr_router_001.sv, rw_manager_inst_ROM_reg.v, rw_manager_data_decoder.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_mux.sv, altera_merlin_master_translator.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, lpddr2ctrl1_s0_addr_router_003.sv, lpddr2ctrl1_s0_id_router_002.sv, rw_manager_di_buffer.v, rw_manager_pattern_fifo.v, altera_merlin_master_agent.sv, altera_merlin_arbitrator.sv, sequencer_scc_sv_phase_decode.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_rst.sv, lpddr2ctrl1_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_lpddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0% -- GENERATION: XML -- lpddr2ctrl1.vhd -- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity lpddr2ctrl1 is port ( pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk global_reset_n : in std_logic := '0'; -- global_reset.reset_n soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n afi_clk : out std_logic; -- afi_clk.clk afi_half_clk : out std_logic; -- afi_half_clk.clk afi_reset_n : out std_logic; -- afi_reset.reset_n afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n mem_ca : out std_logic_vector(9 downto 0); -- memory.mem_ca mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n avl_ready : out std_logic; -- avl.waitrequest_n avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address avl_rdata_valid : out std_logic; -- .readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- .readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata avl_be : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail oct_rzqin : in std_logic := '0'; -- oct.rzqin pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk pll_write_clk : out std_logic; -- .pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk pll_locked : out std_logic; -- .pll_locked pll_avl_clk : out std_logic; -- .pll_avl_clk pll_config_clk : out std_logic; -- .pll_config_clk pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk afi_phy_clk : out std_logic; -- .afi_phy_clk pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk ); end entity lpddr2ctrl1; architecture rtl of lpddr2ctrl1 is component lpddr2ctrl1_0002 is port ( pll_ref_clk : in std_logic := 'X'; -- clk global_reset_n : in std_logic := 'X'; -- reset_n soft_reset_n : in std_logic := 'X'; -- reset_n afi_clk : out std_logic; -- clk afi_half_clk : out std_logic; -- clk afi_reset_n : out std_logic; -- reset_n afi_reset_export_n : out std_logic; -- reset_n mem_ca : out std_logic_vector(9 downto 0); -- mem_ca mem_ck : out std_logic_vector(0 downto 0); -- mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n avl_ready : out std_logic; -- waitrequest_n avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address avl_rdata_valid : out std_logic; -- readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable avl_read_req : in std_logic := 'X'; -- read avl_write_req : in std_logic := 'X'; -- write avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail oct_rzqin : in std_logic := 'X'; -- rzqin pll_mem_clk : out std_logic; -- pll_mem_clk pll_write_clk : out std_logic; -- pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk pll_locked : out std_logic; -- pll_locked pll_avl_clk : out std_logic; -- pll_avl_clk pll_config_clk : out std_logic; -- pll_config_clk pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk afi_phy_clk : out std_logic; -- afi_phy_clk pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk ); end component lpddr2ctrl1_0002; begin lpddr2ctrl1_inst : component lpddr2ctrl1_0002 port map ( pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk global_reset_n => global_reset_n, -- global_reset.reset_n soft_reset_n => soft_reset_n, -- soft_reset.reset_n afi_clk => afi_clk, -- afi_clk.clk afi_half_clk => afi_half_clk, -- afi_half_clk.clk afi_reset_n => afi_reset_n, -- afi_reset.reset_n afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n mem_ca => mem_ca, -- memory.mem_ca mem_ck => mem_ck, -- .mem_ck mem_ck_n => mem_ck_n, -- .mem_ck_n mem_cke => mem_cke, -- .mem_cke mem_cs_n => mem_cs_n, -- .mem_cs_n mem_dm => mem_dm, -- .mem_dm mem_dq => mem_dq, -- .mem_dq mem_dqs => mem_dqs, -- .mem_dqs mem_dqs_n => mem_dqs_n, -- .mem_dqs_n avl_ready => avl_ready, -- avl.waitrequest_n avl_burstbegin => avl_burstbegin, -- .beginbursttransfer avl_addr => avl_addr, -- .address avl_rdata_valid => avl_rdata_valid, -- .readdatavalid avl_rdata => avl_rdata, -- .readdata avl_wdata => avl_wdata, -- .writedata avl_be => avl_be, -- .byteenable avl_read_req => avl_read_req, -- .read avl_write_req => avl_write_req, -- .write avl_size => avl_size, -- .burstcount local_init_done => local_init_done, -- status.local_init_done local_cal_success => local_cal_success, -- .local_cal_success local_cal_fail => local_cal_fail, -- .local_cal_fail oct_rzqin => oct_rzqin, -- oct.rzqin pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk pll_write_clk => pll_write_clk, -- .pll_write_clk pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk pll_locked => pll_locked, -- .pll_locked pll_avl_clk => pll_avl_clk, -- .pll_avl_clk pll_config_clk => pll_config_clk, -- .pll_config_clk pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk afi_phy_clk => afi_phy_clk, -- .afi_phy_clk pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk ); end architecture rtl; -- of lpddr2ctrl1 -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1991-2013 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. 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No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_mem_if_lpddr2_emif" version="13.0" > -- Retrieval info: <generic name="MEM_VENDOR" value="Micron" /> -- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" /> -- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" /> -- Retrieval info: <generic name="DEVICE_DEPTH" value="1" /> -- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" /> -- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" /> -- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" /> -- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" /> -- Retrieval info: <generic name="MEM_DQ_WIDTH" value="16" /> -- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" /> -- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" /> -- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" /> -- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" /> -- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" /> -- Retrieval info: <generic name="MEM_CK_WIDTH" value="1" /> -- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" /> -- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" /> -- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" /> -- Retrieval info: <generic name="NEXTGEN" value="true" /> -- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" /> -- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" /> -- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" /> -- Retrieval info: <generic name="MEM_VERBOSE" value="true" /> -- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" /> -- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" /> -- Retrieval info: <generic name="MEM_BL" value="8" /> -- Retrieval info: <generic name="MEM_BT" value="Sequential" /> -- Retrieval info: <generic name="MEM_DRV_STR" value="40" /> -- Retrieval info: <generic name="MEM_DLL_EN" value="true" /> -- Retrieval info: <generic name="MEM_ATCL" value="0" /> -- Retrieval info: <generic name="MEM_TCL" value="7" /> -- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" /> -- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" /> -- Retrieval info: <generic name="MEM_INIT_EN" value="false" /> -- Retrieval info: <generic name="MEM_INIT_FILE" value="" /> -- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" /> -- Retrieval info: <generic name="TIMING_TIS" value="290" /> -- Retrieval info: <generic name="TIMING_TIH" value="290" /> -- Retrieval info: <generic name="TIMING_TDS" value="270" /> -- Retrieval info: <generic name="TIMING_TDH" value="270" /> -- Retrieval info: <generic name="TIMING_TDQSQ" value="240" /> -- Retrieval info: <generic name="TIMING_TQHS" value="280" /> -- Retrieval info: <generic name="TIMING_TDQSCK" value="5500" /> -- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" /> -- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" /> -- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" /> -- Retrieval info: <generic name="TIMING_TDQSS" value="1.0" /> -- Retrieval info: <generic name="TIMING_TDQSH" value="0.4" /> -- Retrieval info: <generic name="TIMING_TDSH" value="0.2" /> -- Retrieval info: <generic name="TIMING_TDSS" value="0.2" /> -- Retrieval info: <generic name="MEM_TINIT_US" value="200" /> -- Retrieval info: <generic name="MEM_TMRD_CK" value="2" /> -- Retrieval info: <generic name="MEM_TRAS_NS" value="70.0" /> -- Retrieval info: <generic name="MEM_TRCD_NS" value="18.0" /> -- Retrieval info: <generic name="MEM_TRP_NS" value="18.0" /> -- Retrieval info: <generic name="MEM_TREFI_US" value="3.9" /> -- Retrieval info: <generic name="MEM_TRFC_NS" value="60.0" /> -- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" /> -- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" /> -- Retrieval info: <generic name="MEM_TWTR" value="2" /> -- Retrieval info: <generic name="MEM_TFAW_NS" value="50.0" /> -- Retrieval info: <generic name="MEM_TRRD_NS" value="10.0" /> -- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" /> -- Retrieval info: <generic name="RATE" value="Half" /> -- Retrieval info: <generic name="MEM_CLK_FREQ" value="300.0" /> -- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" /> -- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" /> -- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" /> -- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" /> -- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" /> -- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" /> -- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" /> -- Retrieval info: <generic name="SPEED_GRADE" value="7" /> -- Retrieval info: <generic name="IS_ES_DEVICE" value="false" /> -- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" /> -- Retrieval info: <generic name="HARD_EMIF" value="false" /> -- Retrieval info: <generic name="HHP_HPS" value="false" /> -- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" /> -- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" /> -- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" /> -- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" /> -- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" /> -- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" /> -- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" /> -- Retrieval info: <generic name="BYTE_ENABLE" value="true" /> -- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" /> -- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" /> -- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" /> -- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" /> -- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" /> -- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" /> -- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" /> -- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" /> -- Retrieval info: <generic name="ADDR_ORDER" value="0" /> -- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" /> -- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" /> -- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" /> -- Retrieval info: <generic name="STARVE_LIMIT" value="10" /> -- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" /> -- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" /> -- Retrieval info: <generic name="MULTICAST_EN" value="false" /> -- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" /> -- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" /> -- Retrieval info: <generic name="DEBUG_MODE" value="false" /> -- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" /> -- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" /> -- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" /> -- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" /> -- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" /> -- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" /> -- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" /> -- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" /> -- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" /> -- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" /> -- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" /> -- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" /> -- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" /> -- Retrieval info: <generic name="NUM_OF_PORTS" value="1" /> -- Retrieval info: <generic name="ENABLE_BONDING" value="false" /> -- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" /> -- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" /> -- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" /> -- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" /> -- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" /> -- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" /> -- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" /> -- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ" value="125.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" /> -- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" /> -- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" /> -- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" /> -- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" /> -- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" /> -- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" /> -- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> -- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="USE_FAKE_PHY" value="false" /> -- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" /> -- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" /> -- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" /> -- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" /> -- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" /> -- Retrieval info: <generic name="EXTRA_SETTINGS" value="" /> -- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" /> -- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" /> -- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" /> -- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" /> -- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" /> -- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" /> -- Retrieval info: <generic name="PHY_ONLY" value="false" /> -- Retrieval info: <generic name="SEQ_MODE" value="0" /> -- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" /> -- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" /> -- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" /> -- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" /> -- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" /> -- Retrieval info: <generic name="SKIP_MEM_INIT" value="false" /> -- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" /> -- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" /> -- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" /> -- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" /> -- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" /> -- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" /> -- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" /> -- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" /> -- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" /> -- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" /> -- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" /> -- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" /> -- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" /> -- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" /> -- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" /> -- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" /> -- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" /> -- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" /> -- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" /> -- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" /> -- Retrieval info: </instance> -- IPFS_FILES : lpddr2ctrl1.vho -- RELATED_FILES: lpddr2ctrl1.vhd, lpddr2ctrl1_0002.v, lpddr2ctrl1_pll0.sv, lpddr2ctrl1_p0_clock_pair_generator.v, lpddr2ctrl1_p0_read_valid_selector.v, lpddr2ctrl1_p0_addr_cmd_datapath.v, lpddr2ctrl1_p0_reset.v, lpddr2ctrl1_p0_acv_ldc.v, lpddr2ctrl1_p0_memphy.sv, lpddr2ctrl1_p0_reset_sync.v, lpddr2ctrl1_p0_new_io_pads.v, lpddr2ctrl1_p0_fr_cycle_shifter.v, lpddr2ctrl1_p0_fr_cycle_extender.v, lpddr2ctrl1_p0_read_datapath.sv, lpddr2ctrl1_p0_write_datapath.v, lpddr2ctrl1_p0_simple_ddio_out.sv, lpddr2ctrl1_p0_phy_csr.sv, lpddr2ctrl1_p0_iss_probe.v, lpddr2ctrl1_p0_flop_mem.v, lpddr2ctrl1_p0_addr_cmd_pads.v, lpddr2ctrl1_p0.sv, lpddr2ctrl1_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev_lpddr2.sv, afi_mux_lpddr2.v, lpddr2ctrl1_s0.v, rw_manager_bitcheck.v, rw_manager_datamux.v, lpddr2ctrl1_s0_id_router.sv, altera_merlin_traffic_limiter.sv, lpddr2ctrl1_s0_cmd_xbar_demux_001.sv, sequencer_trk_mgr.sv, lpddr2ctrl1_s0_addr_router_002.sv, sequencer_scc_sv_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_demux_003.sv, rw_manager_ac_ROM_reg.v, altera_merlin_burst_uncompressor.sv, rw_manager_read_datapath.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_data_broadcast.v, altera_avalon_mm_bridge.v, lpddr2ctrl1_s0_irq_mapper.sv, rw_manager_lfsr72.v, sequencer_reg_file.sv, rw_manager_di_buffer_wrap.v, rw_manager_jumplogic.v, altera_merlin_slave_agent.sv, altera_merlin_slave_translator.sv, altera_mem_if_sequencer_mem_no_ifdef_params.sv, lpddr2ctrl1_s0_cmd_xbar_mux.sv, sequencer_data_mgr.sv, sequencer_scc_reg_file.v, rw_manager_ram.v, rw_manager_lpddr2.v, rw_manager_ram_csr.v, rw_manager_generic.sv, altera_avalon_sc_fifo.v, altera_avalon_st_pipeline_base.v, lpddr2ctrl1_s0_id_router_003.sv, lpddr2ctrl1_s0_rsp_xbar_mux_003.sv, rw_manager_write_decoder.v, sequencer_scc_acv_wrapper.sv, rw_manager_ac_ROM_no_ifdef_params.v, lpddr2ctrl1_s0_id_router_001.sv, rw_manager_core.sv, sequencer_phy_mgr.sv, lpddr2ctrl1_s0_cmd_xbar_demux_003.sv, sequencer_scc_acv_phase_decode.v, lpddr2ctrl1_s0_addr_router.sv, sequencer_scc_siii_phase_decode.v, lpddr2ctrl1_s0_cmd_xbar_demux.sv, lpddr2ctrl1_s0_rsp_xbar_demux.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, rw_manager_dm_decoder.v, lpddr2ctrl1_s0_addr_router_001.sv, rw_manager_inst_ROM_reg.v, rw_manager_data_decoder.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_mux.sv, altera_merlin_master_translator.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, lpddr2ctrl1_s0_addr_router_003.sv, lpddr2ctrl1_s0_id_router_002.sv, rw_manager_di_buffer.v, rw_manager_pattern_fifo.v, altera_merlin_master_agent.sv, altera_merlin_arbitrator.sv, sequencer_scc_sv_phase_decode.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_rst.sv, lpddr2ctrl1_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_lpddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0% -- GENERATION: XML -- lpddr2ctrl1.vhd -- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity lpddr2ctrl1 is port ( pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk global_reset_n : in std_logic := '0'; -- global_reset.reset_n soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n afi_clk : out std_logic; -- afi_clk.clk afi_half_clk : out std_logic; -- afi_half_clk.clk afi_reset_n : out std_logic; -- afi_reset.reset_n afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n mem_ca : out std_logic_vector(9 downto 0); -- memory.mem_ca mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n avl_ready : out std_logic; -- avl.waitrequest_n avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address avl_rdata_valid : out std_logic; -- .readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- .readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata avl_be : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail oct_rzqin : in std_logic := '0'; -- oct.rzqin pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk pll_write_clk : out std_logic; -- .pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk pll_locked : out std_logic; -- .pll_locked pll_avl_clk : out std_logic; -- .pll_avl_clk pll_config_clk : out std_logic; -- .pll_config_clk pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk afi_phy_clk : out std_logic; -- .afi_phy_clk pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk ); end entity lpddr2ctrl1; architecture rtl of lpddr2ctrl1 is component lpddr2ctrl1_0002 is port ( pll_ref_clk : in std_logic := 'X'; -- clk global_reset_n : in std_logic := 'X'; -- reset_n soft_reset_n : in std_logic := 'X'; -- reset_n afi_clk : out std_logic; -- clk afi_half_clk : out std_logic; -- clk afi_reset_n : out std_logic; -- reset_n afi_reset_export_n : out std_logic; -- reset_n mem_ca : out std_logic_vector(9 downto 0); -- mem_ca mem_ck : out std_logic_vector(0 downto 0); -- mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- mem_dm mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n avl_ready : out std_logic; -- waitrequest_n avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address avl_rdata_valid : out std_logic; -- readdatavalid avl_rdata : out std_logic_vector(63 downto 0); -- readdata avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable avl_read_req : in std_logic := 'X'; -- read avl_write_req : in std_logic := 'X'; -- write avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail oct_rzqin : in std_logic := 'X'; -- rzqin pll_mem_clk : out std_logic; -- pll_mem_clk pll_write_clk : out std_logic; -- pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk pll_locked : out std_logic; -- pll_locked pll_avl_clk : out std_logic; -- pll_avl_clk pll_config_clk : out std_logic; -- pll_config_clk pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk afi_phy_clk : out std_logic; -- afi_phy_clk pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk ); end component lpddr2ctrl1_0002; begin lpddr2ctrl1_inst : component lpddr2ctrl1_0002 port map ( pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk global_reset_n => global_reset_n, -- global_reset.reset_n soft_reset_n => soft_reset_n, -- soft_reset.reset_n afi_clk => afi_clk, -- afi_clk.clk afi_half_clk => afi_half_clk, -- afi_half_clk.clk afi_reset_n => afi_reset_n, -- afi_reset.reset_n afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n mem_ca => mem_ca, -- memory.mem_ca mem_ck => mem_ck, -- .mem_ck mem_ck_n => mem_ck_n, -- .mem_ck_n mem_cke => mem_cke, -- .mem_cke mem_cs_n => mem_cs_n, -- .mem_cs_n mem_dm => mem_dm, -- .mem_dm mem_dq => mem_dq, -- .mem_dq mem_dqs => mem_dqs, -- .mem_dqs mem_dqs_n => mem_dqs_n, -- .mem_dqs_n avl_ready => avl_ready, -- avl.waitrequest_n avl_burstbegin => avl_burstbegin, -- .beginbursttransfer avl_addr => avl_addr, -- .address avl_rdata_valid => avl_rdata_valid, -- .readdatavalid avl_rdata => avl_rdata, -- .readdata avl_wdata => avl_wdata, -- .writedata avl_be => avl_be, -- .byteenable avl_read_req => avl_read_req, -- .read avl_write_req => avl_write_req, -- .write avl_size => avl_size, -- .burstcount local_init_done => local_init_done, -- status.local_init_done local_cal_success => local_cal_success, -- .local_cal_success local_cal_fail => local_cal_fail, -- .local_cal_fail oct_rzqin => oct_rzqin, -- oct.rzqin pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk pll_write_clk => pll_write_clk, -- .pll_write_clk pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk pll_locked => pll_locked, -- .pll_locked pll_avl_clk => pll_avl_clk, -- .pll_avl_clk pll_config_clk => pll_config_clk, -- .pll_config_clk pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk afi_phy_clk => afi_phy_clk, -- .afi_phy_clk pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk ); end architecture rtl; -- of lpddr2ctrl1 -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1991-2013 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_mem_if_lpddr2_emif" version="13.0" > -- Retrieval info: <generic name="MEM_VENDOR" value="Micron" /> -- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" /> -- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" /> -- Retrieval info: <generic name="DEVICE_DEPTH" value="1" /> -- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" /> -- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" /> -- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" /> -- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" /> -- Retrieval info: <generic name="MEM_DQ_WIDTH" value="16" /> -- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" /> -- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" /> -- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" /> -- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" /> -- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" /> -- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" /> -- Retrieval info: <generic name="MEM_CK_WIDTH" value="1" /> -- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" /> -- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" /> -- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" /> -- Retrieval info: <generic name="NEXTGEN" value="true" /> -- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" /> -- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" /> -- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" /> -- Retrieval info: <generic name="MEM_VERBOSE" value="true" /> -- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" /> -- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" /> -- Retrieval info: <generic name="MEM_BL" value="8" /> -- Retrieval info: <generic name="MEM_BT" value="Sequential" /> -- Retrieval info: <generic name="MEM_DRV_STR" value="40" /> -- Retrieval info: <generic name="MEM_DLL_EN" value="true" /> -- Retrieval info: <generic name="MEM_ATCL" value="0" /> -- Retrieval info: <generic name="MEM_TCL" value="7" /> -- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" /> -- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" /> -- Retrieval info: <generic name="MEM_INIT_EN" value="false" /> -- Retrieval info: <generic name="MEM_INIT_FILE" value="" /> -- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" /> -- Retrieval info: <generic name="TIMING_TIS" value="290" /> -- Retrieval info: <generic name="TIMING_TIH" value="290" /> -- Retrieval info: <generic name="TIMING_TDS" value="270" /> -- Retrieval info: <generic name="TIMING_TDH" value="270" /> -- Retrieval info: <generic name="TIMING_TDQSQ" value="240" /> -- Retrieval info: <generic name="TIMING_TQHS" value="280" /> -- Retrieval info: <generic name="TIMING_TDQSCK" value="5500" /> -- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" /> -- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" /> -- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" /> -- Retrieval info: <generic name="TIMING_TDQSS" value="1.0" /> -- Retrieval info: <generic name="TIMING_TDQSH" value="0.4" /> -- Retrieval info: <generic name="TIMING_TDSH" value="0.2" /> -- Retrieval info: <generic name="TIMING_TDSS" value="0.2" /> -- Retrieval info: <generic name="MEM_TINIT_US" value="200" /> -- Retrieval info: <generic name="MEM_TMRD_CK" value="2" /> -- Retrieval info: <generic name="MEM_TRAS_NS" value="70.0" /> -- Retrieval info: <generic name="MEM_TRCD_NS" value="18.0" /> -- Retrieval info: <generic name="MEM_TRP_NS" value="18.0" /> -- Retrieval info: <generic name="MEM_TREFI_US" value="3.9" /> -- Retrieval info: <generic name="MEM_TRFC_NS" value="60.0" /> -- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" /> -- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" /> -- Retrieval info: <generic name="MEM_TWTR" value="2" /> -- Retrieval info: <generic name="MEM_TFAW_NS" value="50.0" /> -- Retrieval info: <generic name="MEM_TRRD_NS" value="10.0" /> -- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" /> -- Retrieval info: <generic name="RATE" value="Half" /> -- Retrieval info: <generic name="MEM_CLK_FREQ" value="300.0" /> -- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" /> -- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" /> -- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" /> -- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" /> -- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" /> -- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" /> -- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" /> -- Retrieval info: <generic name="SPEED_GRADE" value="7" /> -- Retrieval info: <generic name="IS_ES_DEVICE" value="false" /> -- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" /> -- Retrieval info: <generic name="HARD_EMIF" value="false" /> -- Retrieval info: <generic name="HHP_HPS" value="false" /> -- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" /> -- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" /> -- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" /> -- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" /> -- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" /> -- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" /> -- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" /> -- Retrieval info: <generic name="BYTE_ENABLE" value="true" /> -- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" /> -- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" /> -- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" /> -- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" /> -- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" /> -- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" /> -- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" /> -- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" /> -- Retrieval info: <generic name="ADDR_ORDER" value="0" /> -- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" /> -- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" /> -- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" /> -- Retrieval info: <generic name="STARVE_LIMIT" value="10" /> -- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" /> -- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" /> -- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" /> -- Retrieval info: <generic name="MULTICAST_EN" value="false" /> -- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" /> -- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" /> -- Retrieval info: <generic name="DEBUG_MODE" value="false" /> -- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" /> -- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" /> -- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" /> -- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" /> -- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" /> -- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" /> -- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" /> -- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" /> -- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" /> -- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" /> -- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" /> -- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" /> -- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" /> -- Retrieval info: <generic name="NUM_OF_PORTS" value="1" /> -- Retrieval info: <generic name="ENABLE_BONDING" value="false" /> -- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" /> -- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" /> -- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" /> -- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" /> -- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" /> -- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" /> -- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" /> -- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ" value="125.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" /> -- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" /> -- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" /> -- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" /> -- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" /> -- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" /> -- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" /> -- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" /> -- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" /> -- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" /> -- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> -- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" /> -- Retrieval info: <generic name="USE_FAKE_PHY" value="false" /> -- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" /> -- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" /> -- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" /> -- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" /> -- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" /> -- Retrieval info: <generic name="EXTRA_SETTINGS" value="" /> -- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" /> -- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" /> -- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" /> -- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" /> -- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" /> -- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" /> -- Retrieval info: <generic name="PHY_ONLY" value="false" /> -- Retrieval info: <generic name="SEQ_MODE" value="0" /> -- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" /> -- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" /> -- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" /> -- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" /> -- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" /> -- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" /> -- Retrieval info: <generic name="SKIP_MEM_INIT" value="false" /> -- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" /> -- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" /> -- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" /> -- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" /> -- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" /> -- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" /> -- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" /> -- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" /> -- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" /> -- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" /> -- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" /> -- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" /> -- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" /> -- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" /> -- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" /> -- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" /> -- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" /> -- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" /> -- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" /> -- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" /> -- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" /> -- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" /> -- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" /> -- Retrieval info: </instance> -- IPFS_FILES : lpddr2ctrl1.vho -- RELATED_FILES: lpddr2ctrl1.vhd, lpddr2ctrl1_0002.v, lpddr2ctrl1_pll0.sv, lpddr2ctrl1_p0_clock_pair_generator.v, lpddr2ctrl1_p0_read_valid_selector.v, lpddr2ctrl1_p0_addr_cmd_datapath.v, lpddr2ctrl1_p0_reset.v, lpddr2ctrl1_p0_acv_ldc.v, lpddr2ctrl1_p0_memphy.sv, lpddr2ctrl1_p0_reset_sync.v, lpddr2ctrl1_p0_new_io_pads.v, lpddr2ctrl1_p0_fr_cycle_shifter.v, lpddr2ctrl1_p0_fr_cycle_extender.v, lpddr2ctrl1_p0_read_datapath.sv, lpddr2ctrl1_p0_write_datapath.v, lpddr2ctrl1_p0_simple_ddio_out.sv, lpddr2ctrl1_p0_phy_csr.sv, lpddr2ctrl1_p0_iss_probe.v, lpddr2ctrl1_p0_flop_mem.v, lpddr2ctrl1_p0_addr_cmd_pads.v, lpddr2ctrl1_p0.sv, lpddr2ctrl1_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev_lpddr2.sv, afi_mux_lpddr2.v, lpddr2ctrl1_s0.v, rw_manager_bitcheck.v, rw_manager_datamux.v, lpddr2ctrl1_s0_id_router.sv, altera_merlin_traffic_limiter.sv, lpddr2ctrl1_s0_cmd_xbar_demux_001.sv, sequencer_trk_mgr.sv, lpddr2ctrl1_s0_addr_router_002.sv, sequencer_scc_sv_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_demux_003.sv, rw_manager_ac_ROM_reg.v, altera_merlin_burst_uncompressor.sv, rw_manager_read_datapath.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_data_broadcast.v, altera_avalon_mm_bridge.v, lpddr2ctrl1_s0_irq_mapper.sv, rw_manager_lfsr72.v, sequencer_reg_file.sv, rw_manager_di_buffer_wrap.v, rw_manager_jumplogic.v, altera_merlin_slave_agent.sv, altera_merlin_slave_translator.sv, altera_mem_if_sequencer_mem_no_ifdef_params.sv, lpddr2ctrl1_s0_cmd_xbar_mux.sv, sequencer_data_mgr.sv, sequencer_scc_reg_file.v, rw_manager_ram.v, rw_manager_lpddr2.v, rw_manager_ram_csr.v, rw_manager_generic.sv, altera_avalon_sc_fifo.v, altera_avalon_st_pipeline_base.v, lpddr2ctrl1_s0_id_router_003.sv, lpddr2ctrl1_s0_rsp_xbar_mux_003.sv, rw_manager_write_decoder.v, sequencer_scc_acv_wrapper.sv, rw_manager_ac_ROM_no_ifdef_params.v, lpddr2ctrl1_s0_id_router_001.sv, rw_manager_core.sv, sequencer_phy_mgr.sv, lpddr2ctrl1_s0_cmd_xbar_demux_003.sv, sequencer_scc_acv_phase_decode.v, lpddr2ctrl1_s0_addr_router.sv, sequencer_scc_siii_phase_decode.v, lpddr2ctrl1_s0_cmd_xbar_demux.sv, lpddr2ctrl1_s0_rsp_xbar_demux.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, rw_manager_dm_decoder.v, lpddr2ctrl1_s0_addr_router_001.sv, rw_manager_inst_ROM_reg.v, rw_manager_data_decoder.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_mux.sv, altera_merlin_master_translator.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, lpddr2ctrl1_s0_addr_router_003.sv, lpddr2ctrl1_s0_id_router_002.sv, rw_manager_di_buffer.v, rw_manager_pattern_fifo.v, altera_merlin_master_agent.sv, altera_merlin_arbitrator.sv, sequencer_scc_sv_phase_decode.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_rst.sv, lpddr2ctrl1_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_lpddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Author: Andrzej Paluch -- -- Create Date: 23:21:05 10/21/2011 -- Design Name: -- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd -- Project Name: usbToHpib -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: gpibInterface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use work.gpibComponents.all; use work.helperComponents.all; ENTITY gpibReaderTest IS END gpibReaderTest; ARCHITECTURE behavior OF gpibReaderTest IS -- Component Declaration for the Unit Under Test (UUT) component gpibCableEmulator is port ( -- interface signals DIO_1 : in std_logic_vector (7 downto 0); output_valid_1 : in std_logic; DIO_2 : in std_logic_vector (7 downto 0); output_valid_2 : in std_logic; DIO : out std_logic_vector (7 downto 0); -- attention ATN_1 : in std_logic; ATN_2 : in std_logic; ATN : out std_logic; -- data valid DAV_1 : in std_logic; DAV_2 : in std_logic; DAV : out std_logic; -- not ready for data NRFD_1 : in std_logic; NRFD_2 : in std_logic; NRFD : out std_logic; -- no data accepted NDAC_1 : in std_logic; NDAC_2 : in std_logic; NDAC : out std_logic; -- end or identify EOI_1 : in std_logic; EOI_2 : in std_logic; EOI : out std_logic; -- service request SRQ_1 : in std_logic; SRQ_2 : in std_logic; SRQ : out std_logic; -- interface clear IFC_1 : in std_logic; IFC_2 : in std_logic; IFC : out std_logic; -- remote enable REN_1 : in std_logic; REN_2 : in std_logic; REN : out std_logic ); end component; -- inputs common signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal T1 : std_logic_vector(7 downto 0) := "00000100"; -- inputs 1 signal data_1 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_1 : std_logic := '0'; signal nba_1 : std_logic := '0'; signal ltn_1 : std_logic := '0'; signal lun_1 : std_logic := '0'; signal lon_1 : std_logic := '0'; signal ton_1 : std_logic := '0'; signal endOf_1 : std_logic := '0'; signal gts_1 : std_logic := '0'; signal rpp_1 : std_logic := '0'; signal tcs_1 : std_logic := '0'; signal tca_1 : std_logic := '0'; signal sic_1 : std_logic := '0'; signal rsc_1 : std_logic := '0'; signal sre_1 : std_logic := '0'; signal rtl_1 : std_logic := '0'; signal rsv_1 : std_logic := '0'; signal ist_1 : std_logic := '0'; signal lpe_1 : std_logic := '0'; -- inputs 2 signal data_2 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_2 : std_logic := '0'; signal nba_2 : std_logic := '0'; signal ltn_2 : std_logic := '0'; signal lun_2 : std_logic := '0'; signal lon_2 : std_logic := '0'; signal ton_2 : std_logic := '0'; signal endOf_2 : std_logic := '0'; signal gts_2 : std_logic := '0'; signal rpp_2 : std_logic := '0'; signal tcs_2 : std_logic := '0'; signal tca_2 : std_logic := '0'; signal sic_2 : std_logic := '0'; signal rsc_2 : std_logic := '0'; signal sre_2 : std_logic := '0'; signal rtl_2 : std_logic := '0'; signal rsv_2 : std_logic := '0'; signal ist_2 : std_logic := '0'; signal lpe_2 : std_logic := '0'; -- outputs 1 signal dvd_1 : std_logic; signal wnc_1 : std_logic; signal tac_1 : std_logic; signal cwrc_1 : std_logic; signal cwrd_1 : std_logic; signal clr_1 : std_logic; signal trg_1 : std_logic; signal atl_1 : std_logic; signal att_1 : std_logic; signal mla_1 : std_logic; signal lsb_1 : std_logic; signal spa_1 : std_logic; signal ppr_1 : std_logic; signal sreq_1 : std_logic; signal isLocal_1 : std_logic; signal currentSecAddr_1 : std_logic_vector (4 downto 0); -- outputs 2 signal dvd_2 : std_logic; signal wnc_2 : std_logic; signal tac_2 : std_logic; signal cwrc_2 : std_logic; signal cwrd_2 : std_logic; signal clr_2 : std_logic; signal trg_2 : std_logic; signal atl_2 : std_logic; signal att_2 : std_logic; signal mla_2 : std_logic; signal lsb_2 : std_logic; signal spa_2 : std_logic; signal ppr_2 : std_logic; signal sreq_2 : std_logic; signal isLocal_2 : std_logic; signal currentSecAddr_2 : std_logic_vector (4 downto 0); -- common signal DO : std_logic_vector (7 downto 0); signal DI_1 : std_logic_vector (7 downto 0); signal output_valid_1 : std_logic; signal DI_2 : std_logic_vector (7 downto 0); signal output_valid_2 : std_logic; signal ATN_1, ATN_2, ATN : std_logic; signal DAV_1, DAV_2, DAV : std_logic; signal NRFD_1, NRFD_2, NRFD : std_logic; signal NDAC_1, NDAC_2, NDAC : std_logic; signal EOI_1, EOI_2, EOI : std_logic; signal SRQ_1, SRQ_2, SRQ : std_logic; signal IFC_1, IFC_2, IFC : std_logic; signal REN_1, REN_2, REN : std_logic; -- gpib reader signal buf_interrupt : std_logic; signal data_available : std_logic; signal last_byte_addr : std_logic_vector (3 downto 0); signal end_of_stream : std_logic; signal byte_addr : std_logic_vector (3 downto 0); signal data_out : std_logic_vector (7 downto 0); signal reset_buffer : std_logic := '0'; signal dataSecAddr : std_logic_vector (4 downto 0); -- Clock period definitions constant clk_period : time := 2ps; BEGIN -- Instantiate the Unit Under Test (UUT) gpib1: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00001", myTalkAddr => "00001", secAddrMask => (others => '0'), data => data_1, status_byte => status_byte_1, T1 => T1, rdy => rdy_1, nba => nba_1, ltn => ltn_1, lun => lun_1, lon => lon_1, ton => ton_1, endOf => endOf_1, gts => gts_1, rpp => rpp_1, tcs => tcs_1, tca => tca_1, sic => sic_1, rsc => rsc_1, sre => sre_1, rtl => rtl_1, rsv => rsv_1, ist => ist_1, lpe => lpe_1, dvd => dvd_1, wnc => wnc_1, tac => tac_1, cwrc => cwrc_1, cwrd => cwrd_1, clr => clr_1, trg => trg_1, atl => atl_1, att => att_1, mla => mla_1, lsb => lsb_1, spa => spa_1, ppr => ppr_1, sreq => sreq_1, isLocal => isLocal_1, currentSecAddr => currentSecAddr_1, DI => DO, DO => DI_1, output_valid => output_valid_1, ATN_in => ATN, ATN_out => ATN_1, DAV_in => DAV, DAV_out => DAV_1, NRFD_in => NRFD, NRFD_out => NRFD_1, NDAC_in => NDAC, NDAC_out => NDAC_1, EOI_in => EOI, EOI_out => EOI_1, SRQ_in => SRQ, SRQ_out => SRQ_1, IFC_in => IFC, IFC_out => IFC_1, REN_in => REN, REN_out => REN_1 ); -- Instantiate the Unit Under Test (UUT) gpib2: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00010", myTalkAddr => "00010", secAddrMask => (others => '0'), data => data_2, status_byte => status_byte_2, T1 => T1, rdy => rdy_2, nba => nba_2, ltn => ltn_2, lun => lun_2, lon => lon_2, ton => ton_2, endOf => endOf_2, gts => gts_2, rpp => rpp_2, tcs => tcs_2, tca => tca_2, sic => sic_2, rsc => rsc_2, sre => sre_2, rtl => rtl_2, rsv => rsv_2, ist => ist_2, lpe => lpe_2, dvd => dvd_2, wnc => wnc_2, tac => tac_2, cwrc => cwrc_2, cwrd => cwrd_2, clr => clr_2, trg => trg_2, atl => atl_2, att => att_2, mla => mla_2, lsb => lsb_2, spa => spa_2, ppr => ppr_2, sreq => sreq_2, isLocal => isLocal_2, currentSecAddr => currentSecAddr_2, DI => DO, DO => DI_2, output_valid => output_valid_2, ATN_in => ATN, ATN_out => ATN_2, DAV_in => DAV, DAV_out => DAV_2, NRFD_in => NRFD, NRFD_out => NRFD_2, NDAC_in => NDAC, NDAC_out => NDAC_2, EOI_in => EOI, EOI_out => EOI_2, SRQ_in => SRQ, SRQ_out => SRQ_2, IFC_in => IFC, IFC_out => IFC_2, REN_in => REN, REN_out => REN_2 ); ce: gpibCableEmulator port map ( -- interface signals DIO_1 => DI_1, output_valid_1 => output_valid_1, DIO_2 => DI_2, output_valid_2 => output_valid_2, DIO => DO, -- attention ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN, DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV, NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD, NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC, EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI, SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ, IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC, REN_1 => REN_1, REN_2 => REN_2, REN => REN ); gr: gpibReader generic map(ADDR_WIDTH => 4) port map( clk => clk, reset => reset, ------------------------------------------------------------------------ ------ GPIB interface -------------------------------------------------- ------------------------------------------------------------------------ data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2, ------------------------------------------------------------------------ ------ external interface ---------------------------------------------- ------------------------------------------------------------------------ isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr, buf_interrupt => buf_interrupt, data_available => data_available, last_byte_addr => last_byte_addr, end_of_stream => end_of_stream, byte_addr => byte_addr, data_out => data_out, reset_buffer => reset_buffer ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 10 clock periods. reset <= '1'; wait for clk_period*10; reset <= '0'; wait for clk_period*10; -- requests system control rsc_1 <= '1'; -- interface clear sic_1 <= '1'; wait until IFC_1 = '1'; sic_1 <= '0'; wait until IFC_1 = '0'; -- address gpib2 to listen data_1 <= "00100010"; nba_1 <= '1'; wait until DAV='1'; nba_1 <= '0'; wait for clk_period*20; -- address gpib1 to talk data_1 <= "01000001"; wait for clk_period*1; nba_1 <= '1'; wait until DAV='1'; nba_1 <= '0'; wait for clk_period*30; gts_1 <= '1'; wait until ATN='0'; -- send data to gpib2 data_1 <= "10101010"; nba_1 <= '1'; wait until wnc_1='1'; nba_1 <= '0'; wait for clk_period*3; -- send end data to gpib2 data_1 <= "10101010"; endOf_1 <= '1'; nba_1 <= '1'; wait until wnc_1='1'; nba_1 <= '0'; --wait until wnc_1='0'; wait until buf_interrupt = '1'; byte_addr <= "0000"; wait for clk_period*1; assert data_out = "10101010"; byte_addr <= "0001"; wait for clk_period*1; assert data_out = "10101010"; report "$$$ END OF TEST - reader $$$"; wait; end process; END;
architecture RTL of FIFO is procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; -- Fixes follow procedure proc1 is begin end procedure proc1; procedure proc1 is begin end procedure proc1; procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; begin end architecture RTL;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: Chip-Specific DDR Input and Output Registers -- -- Description: -- ------------------------------------ -- Instantiates chip-specific DDR input and output registers. -- -- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if -- necessary. If an output enable is not required, you may save some logic by -- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'. -- -- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with -- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought -- out with this rising edge. "DataOut_low" is brought out with the falling -- edge. -- -- "Pad" must be connected to a PAD because FPGAs only have these registers in -- IOBs. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.config.all; use PoC.ddrio.all; entity ddrio_out is generic ( NO_OUTPUT_ENABLE : BOOLEAN := false; BITS : POSITIVE; INIT_VALUE_OUT : BIT_VECTOR := "1"; INIT_VALUE_IN_HIGH : BIT_VECTOR := "1"; INIT_VALUE_IN_LOW : BIT_VECTOR := "1" ); port ( Clock : in STD_LOGIC; ClockEnable : in STD_LOGIC; OutputEnable : in STD_LOGIC; DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0) ); end entity; architecture rtl of ddrio_out is begin assert (VENDOR = VENDOR_XILINX) or (VENDOR = VENDOR_ALTERA) report "PoC.io.ddrio.inout is not implemented for given DEVICE." severity FAILURE; genXilinx : if (VENDOR = VENDOR_XILINX) generate inst : ddrio_inout_xilinx generic map ( NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE, BITS => BITS, INIT_VALUE_OUT => INIT_VALUE_OUT, INIT_VALUE_IN_HIGH => INIT_VALUE_IN_HIGH, INIT_VALUE_IN_LOW => INIT_VALUE_IN_LOW ) port map ( Clock => Clock, ClockEnable => ClockEnable, OutputEnable => OutputEnable, DataOut_high => DataOut_high, DataOut_low => DataOut_low, DataIn_high => DataIn_high, DataIn_low => DataIn_low, Pad => Pad ); end generate; genAltera : if (VENDOR = VENDOR_ALTERA) generate inst : ddrio_inout_altera generic map ( BITS => BITS ) port map ( Clock => Clock, ClockEnable => ClockEnable, OutputEnable => OutputEnable, DataOut_high => DataOut_high, DataOut_low => DataOut_low, DataIn_high => DataIn_high, DataIn_low => DataIn_low, Pad => Pad ); end generate; end architecture;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: Chip-Specific DDR Input and Output Registers -- -- Description: -- ------------------------------------ -- Instantiates chip-specific DDR input and output registers. -- -- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if -- necessary. If an output enable is not required, you may save some logic by -- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'. -- -- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with -- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought -- out with this rising edge. "DataOut_low" is brought out with the falling -- edge. -- -- "Pad" must be connected to a PAD because FPGAs only have these registers in -- IOBs. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.config.all; use PoC.ddrio.all; entity ddrio_out is generic ( NO_OUTPUT_ENABLE : BOOLEAN := false; BITS : POSITIVE; INIT_VALUE_OUT : BIT_VECTOR := "1"; INIT_VALUE_IN_HIGH : BIT_VECTOR := "1"; INIT_VALUE_IN_LOW : BIT_VECTOR := "1" ); port ( Clock : in STD_LOGIC; ClockEnable : in STD_LOGIC; OutputEnable : in STD_LOGIC; DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0) ); end entity; architecture rtl of ddrio_out is begin assert (VENDOR = VENDOR_XILINX) or (VENDOR = VENDOR_ALTERA) report "PoC.io.ddrio.inout is not implemented for given DEVICE." severity FAILURE; genXilinx : if (VENDOR = VENDOR_XILINX) generate inst : ddrio_inout_xilinx generic map ( NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE, BITS => BITS, INIT_VALUE_OUT => INIT_VALUE_OUT, INIT_VALUE_IN_HIGH => INIT_VALUE_IN_HIGH, INIT_VALUE_IN_LOW => INIT_VALUE_IN_LOW ) port map ( Clock => Clock, ClockEnable => ClockEnable, OutputEnable => OutputEnable, DataOut_high => DataOut_high, DataOut_low => DataOut_low, DataIn_high => DataIn_high, DataIn_low => DataIn_low, Pad => Pad ); end generate; genAltera : if (VENDOR = VENDOR_ALTERA) generate inst : ddrio_inout_altera generic map ( BITS => BITS ) port map ( Clock => Clock, ClockEnable => ClockEnable, OutputEnable => OutputEnable, DataOut_high => DataOut_high, DataOut_low => DataOut_low, DataIn_high => DataIn_high, DataIn_low => DataIn_low, Pad => Pad ); end generate; end architecture;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Utc5kfC8dHAthzGiZhK+EkRLNpyg0Lza9cYpbOEhuKm1S1DCJTw3bb4WfQh8VnyRIjmu4YzA9dNZ C1+tgMHDIw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UkTKhUcw2aFCr8GHnbhH4t8fFVk5hP4ibz9GuIpU21sLKWutytxTtXgH078XIEmWCB0weHxd3AN7 hLd907jBumFh9BsOpWm58KfYaQc0ervcwjIEM/Nn2eRieKTP56FGsEXJ6vZyYjhltbQ52OTIyZuA +Q0oICPtaPEOew1vpLQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Utc5kfC8dHAthzGiZhK+EkRLNpyg0Lza9cYpbOEhuKm1S1DCJTw3bb4WfQh8VnyRIjmu4YzA9dNZ C1+tgMHDIw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UkTKhUcw2aFCr8GHnbhH4t8fFVk5hP4ibz9GuIpU21sLKWutytxTtXgH078XIEmWCB0weHxd3AN7 hLd907jBumFh9BsOpWm58KfYaQc0ervcwjIEM/Nn2eRieKTP56FGsEXJ6vZyYjhltbQ52OTIyZuA +Q0oICPtaPEOew1vpLQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016 -- Date : Mon Jun 6 23:00:45 2016 -- Host : edinburgh running 64-bit Ubuntu 15.04 -- Command : write_vhdl -force -mode synth_stub -- /home/greg/opl3_fpga_vivado_project/opl3_fpga_vivado_project.srcs/sources_1/ip/clk_gen/clk_gen_stub.vhdl -- Design : clk_gen -- Purpose : Stub declaration of top-level module interface -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity clk_gen is Port ( clk125 : in STD_LOGIC; clk : out STD_LOGIC; clk_locked : out STD_LOGIC ); end clk_gen; architecture stub of clk_gen is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clk125,clk,clk_locked"; begin end;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block G3EuaHQZLi0S9F1wV58kMElN5yhKaWd7yzlj9BZlgBFFCASuE2JxnLB4YmHXzsUa77Y5YXOEXopa 3yFviI+bKQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jj028VYEFhpZg/r5Lq9ZdstZ7t3GnRx8eNwauMobdqqp99WMd22R7spBkd9MDl76KLKL3qaVpdmG a7ZtI11qoXyksX3lOg3zdkuNiGP+NPvc3YZeMv6bOyH+gIFNzKqV7mgyqkCBYn+YMa9Q1rUfivKg Bcz+4oytMDdXTbbYNOI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- ------------------------------------------------------------- -- -- Entity Declaration for di_tnry -- -- Generated -- by: lutscher -- on: Tue Jun 23 14:19:39 2009 -- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author$ -- $Id$ -- $Date$ -- $Log$ -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp -- -- Generator: mix_1.pl Version: Revision: 1.3 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity di_tnry -- entity di_tnry is -- Generics: -- No Generated Generics for Entity di_tnry -- Generated Port Declaration: port( -- Generated Port for Entity di_tnry af_c0_i : in std_ulogic ; al_c0_i : in std_ulogic; al_c1_i : in std_ulogic; ap_c0_i : in std_ulogic; ap_p0_i : in std_ulogic; asresi_n : in std_ulogic; clkin : in std_ulogic; hsync_c_i : in std_ulogic; nr_dis_c_i : in std_ulogic; nron_iic_i : in std_ulogic; tnrabs_iic_i : in std_ulogic; tnrcly_iic_i : in std_ulogic_vector(3 downto 0); tnrkvaly_p_o : out std_ulogic_vector(3 downto 0); tnrmd4y_iic_i : in std_ulogic; tnrnr4y_iic_i : in std_ulogic; tnrs0y_iic_i : in std_ulogic_vector(3 downto 0); tnrs1y_iic_i : in std_ulogic_vector(3 downto 0); tnrs2y_iic_i : in std_ulogic_vector(3 downto 0); tnrs3y_iic_i : in std_ulogic_vector(3 downto 0); tnrs4y_iic_i : in std_ulogic_vector(3 downto 0); tnrs5y_iic_i : in std_ulogic_vector(3 downto 0); tnrs6y_iic_i : in std_ulogic_vector(3 downto 0); tnrs7y_iic_i : in std_ulogic_vector(3 downto 0); tnrssy_iic_i : in std_ulogic_vector(3 downto 0); y0_p1_i : in std_ulogic_vector(7 downto 0); y0_p1_o : out std_ulogic_vector(7 downto 0); y1_p1_i : in std_ulogic_vector(7 downto 0); y1_p1_o : out std_ulogic_vector(7 downto 0); y_p0_i : in std_ulogic_vector(7 downto 0); y_p0_o : out std_ulogic_vector(7 downto 0); yblack_p_i : in std_ulogic_vector(7 downto 0) -- End of Generated Port for Entity di_tnry ); end di_tnry; -- -- End of Generated Entity di_tnry -- -- --!End of Entity/ies -- --------------------------------------------------------------
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- -- Filename: blk_mem_gen_v7_3_prod.vhd -- -- Description: -- This is the top-level BMG wrapper (over BMG core). -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: August 31, 2005 - First Release -------------------------------------------------------------------------------- -- -- Configured Core Parameter Values: -- (Refer to the SIM Parameters table in the datasheet for more information on -- the these parameters.) -- C_FAMILY : spartan6 -- C_XDEVICEFAMILY : spartan6 -- C_INTERFACE_TYPE : 0 -- C_ENABLE_32BIT_ADDRESS : 0 -- C_AXI_TYPE : 1 -- C_AXI_SLAVE_TYPE : 0 -- C_AXI_ID_WIDTH : 4 -- C_MEM_TYPE : 3 -- C_BYTE_SIZE : 9 -- C_ALGORITHM : 1 -- C_PRIM_TYPE : 1 -- C_LOAD_INIT_FILE : 1 -- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif -- C_USE_DEFAULT_DATA : 1 -- C_DEFAULT_DATA : 0 -- C_RST_TYPE : SYNC -- C_HAS_RSTA : 0 -- C_RST_PRIORITY_A : CE -- C_RSTRAM_A : 0 -- C_INITA_VAL : 0 -- C_HAS_ENA : 1 -- C_HAS_REGCEA : 0 -- C_USE_BYTE_WEA : 0 -- C_WEA_WIDTH : 1 -- C_WRITE_MODE_A : WRITE_FIRST -- C_WRITE_WIDTH_A : 16 -- C_READ_WIDTH_A : 16 -- C_WRITE_DEPTH_A : 256 -- C_READ_DEPTH_A : 256 -- C_ADDRA_WIDTH : 8 -- C_HAS_RSTB : 0 -- C_RST_PRIORITY_B : CE -- C_RSTRAM_B : 0 -- C_INITB_VAL : 0 -- C_HAS_ENB : 0 -- C_HAS_REGCEB : 0 -- C_USE_BYTE_WEB : 0 -- C_WEB_WIDTH : 1 -- C_WRITE_MODE_B : WRITE_FIRST -- C_WRITE_WIDTH_B : 16 -- C_READ_WIDTH_B : 16 -- C_WRITE_DEPTH_B : 256 -- C_READ_DEPTH_B : 256 -- C_ADDRB_WIDTH : 8 -- C_HAS_MEM_OUTPUT_REGS_A : 0 -- C_HAS_MEM_OUTPUT_REGS_B : 0 -- C_HAS_MUX_OUTPUT_REGS_A : 0 -- C_HAS_MUX_OUTPUT_REGS_B : 0 -- C_HAS_SOFTECC_INPUT_REGS_A : 0 -- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 -- C_MUX_PIPELINE_STAGES : 0 -- C_USE_ECC : 0 -- C_USE_SOFTECC : 0 -- C_HAS_INJECTERR : 0 -- C_SIM_COLLISION_CHECK : ALL -- C_COMMON_CLK : 0 -- C_DISABLE_WARN_BHV_COLL : 0 -- C_DISABLE_WARN_BHV_RANGE : 0 -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY blk_mem_gen_v7_3_prod IS PORT ( --Port A CLKA : IN STD_LOGIC; RSTA : IN STD_LOGIC; --opt port ENA : IN STD_LOGIC; --optional port REGCEA : IN STD_LOGIC; --optional port WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --Port B CLKB : IN STD_LOGIC; RSTB : IN STD_LOGIC; --opt port ENB : IN STD_LOGIC; --optional port REGCEB : IN STD_LOGIC; --optional port WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --ECC INJECTSBITERR : IN STD_LOGIC; --optional port INJECTDBITERR : IN STD_LOGIC; --optional port SBITERR : OUT STD_LOGIC; --optional port DBITERR : OUT STD_LOGIC; --optional port RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_ACLK : IN STD_LOGIC; S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_AWVALID : IN STD_LOGIC; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); S_AXI_WLAST : IN STD_LOGIC; S_AXI_WVALID : IN STD_LOGIC; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_ARVALID : IN STD_LOGIC; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC; S_AXI_INJECTDBITERR : IN STD_LOGIC; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); S_ARESETN : IN STD_LOGIC ); END blk_mem_gen_v7_3_prod; ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS COMPONENT blk_mem_gen_v7_3_exdes IS PORT ( --Port A ENA : IN STD_LOGIC; --opt port ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; BEGIN bmg0 : blk_mem_gen_v7_3_exdes PORT MAP ( --Port A ENA => ENA, ADDRA => ADDRA, DOUTA => DOUTA, CLKA => CLKA ); END xilinx;
-- A DCM block would be more accurate, right? library ieee; use ieee.std_logic_1164.all; use work.arch_defs.all; entity clkdivider is port ( ticks : in natural; bigclk : in std_logic; rst : in std_logic; smallclk : out std_logic ); end; architecture behav of clkdivider is begin clkdivider: process(bigclk, rst, ticks) variable i : natural := 0; variable pulse : std_logic := '0'; begin if rst = '1' then i := 0; pulse := '0'; elsif rising_edge(bigclk) then i := i + 1; if i >= ticks then pulse := not pulse; i := 0; end if; end if; smallclk <= pulse; end process; end behav;
-- Btrace 448 -- Point Register -- -- Bradley Boccuzzi -- 2016 library ieee; use ieee.std_logic_1164.all; use work.btrace_pack.all; entity point_reg is port(clk, rst, en: in std_logic; Din: in point; Dout: out point); end point_reg; architecture arch of point_reg is constant zero_point: point := ((others => '0'), (others => '0'), (others => '0')); begin process(clk, rst) begin if rst = '1' then Dout <= zero_point; elsif rising_edge(clk) then if en = '1' then Dout <= Din; end if; end if; end process; end arch;
library IEEE; use IEEE.STD_LOGIC_1164.all; library work; use work.abb64Package.all; library UNISIM; use UNISIM.VComponents.all; entity top is generic ( SIMULATION : string := "FALSE"; -- **** -- PCIe core parameters -- **** constant pcieLanes : integer := 4; PL_FAST_TRAIN : string := "FALSE"; PIPE_SIM_MODE : string := "FALSE"; --*************************************************************************** -- Necessary parameters for DDR core support -- (dependent on memory chip connected to FPGA, not to be modified at will) --*************************************************************************** constant DDR_DQ_WIDTH : integer := 64; constant DDR_PAYLOAD_WIDTH : integer := 512; constant DDR_DQS_WIDTH : integer := 8; constant DDR_DM_WIDTH : integer := 8; constant DDR_ROW_WIDTH : integer := 14; constant DDR_BANK_WIDTH : integer := 3; constant DDR_CK_WIDTH : integer := 1; constant DDR_CKE_WIDTH : integer := 1; constant DDR_ODT_WIDTH : integer := 1 ); port ( --DDR3 memory pins ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0); ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0); ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0); ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0); ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0); -- PCIe transceivers pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0); pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0); pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0); pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0); -- Necessity signals ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) sys_clk_n : in std_logic; --100 MHz PCIe Clock sys_rst_n : in std_logic --Reset to PCIe core ); end entity top; architecture arch of top is component bpm_pcie_k7 is generic ( SIMULATION : string := "FALSE"; -- **** -- PCIe core parameters -- **** constant pcieLanes : integer := 4; PL_FAST_TRAIN : string := "FALSE"; PIPE_SIM_MODE : string := "FALSE" ); port ( --DDR3 memory pins ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0); ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0); ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0); ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0); ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0); -- PCIe transceivers pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0); pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0); pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0); pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0); -- Necessity signals ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) sys_clk_n : in std_logic; --100 MHz PCIe Clock sys_rst_n : in std_logic; --Reset to PCIe core -- DDR memory controller interface -- -- uncomment when instantiating in another project ddr_core_rst : in std_logic; memc_ui_clk : out std_logic; memc_ui_rst : out std_logic; memc_cmd_rdy : out std_logic; memc_cmd_en : in std_logic; memc_cmd_instr : in std_logic_vector(2 downto 0); memc_cmd_addr : in std_logic_vector(31 downto 0); memc_wr_en : in std_logic; memc_wr_end : in std_logic; memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0); memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); memc_wr_rdy : out std_logic; memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); memc_rd_valid : out std_logic; ---- memory arbiter interface memarb_acc_req : in std_logic; memarb_acc_gnt : out std_logic; --/ DDR memory controller interface -- Wishbone interface -- -- uncomment when instantiating in another project CLK_I : in std_logic; RST_I : in std_logic; ACK_I : in std_logic; DAT_I : in std_logic_vector(63 downto 0); ADDR_O : out std_logic_vector(28 downto 0); DAT_O : out std_logic_vector(63 downto 0); WE_O : out std_logic; STB_O : out std_logic; SEL_O : out std_logic; CYC_O : out std_logic; --/ Wishbone interface -- Additional exported signals for instantiation ext_rst_o : out std_logic ); end component bpm_pcie_k7; -- WISHBONE SLAVE interface: -- Single-Port RAM with Asynchronous Read -- component WB_MEM is generic( AWIDTH : natural range 2 to 29 := 7; DWIDTH : natural range 8 to 128 := 64 ); port( CLK_I : in std_logic; ACK_O : out std_logic; ADR_I : in std_logic_vector(AWIDTH-1 downto 0); DAT_I : in std_logic_vector(DWIDTH-1 downto 0); DAT_O : out std_logic_vector(DWIDTH-1 downto 0); STB_I : in std_logic; WE_I : in std_logic ); end component; signal ddr_sys_rst_i : std_logic; signal ddr_ui_clk : std_logic; signal pll_clkin : std_logic; signal pll_clkfbout : std_logic; signal pll_clkout0 : std_logic; signal pll_locked : std_logic; signal wbone_clk : std_logic; signal wbone_addr : std_logic_vector(31 downto 0); signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0); signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0); signal wbone_we : std_logic; signal wbone_sel : std_logic_vector(0 downto 0); signal wbone_stb : std_logic; signal wbone_ack : std_logic; signal wbone_cyc : std_logic; signal wbone_rst : std_logic; begin bpm_pcie : bpm_pcie_k7 generic map( SIMULATION => SIMULATION, -- **** -- PCIe core parameters -- **** pcieLanes => pcieLanes, PL_FAST_TRAIN => PL_FAST_TRAIN, PIPE_SIM_MODE => PIPE_SIM_MODE ) port map( --DDR3 memory pins ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cs_n => ddr3_cs_n, ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n, ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, -- PCIe transceivers pci_exp_rxp => pci_exp_rxp, pci_exp_rxn => pci_exp_rxn, pci_exp_txp => pci_exp_txp, pci_exp_txn => pci_exp_txn, -- Necessity signals ddr_sys_clk_p => ddr_sys_clk_p, ddr_sys_clk_n => ddr_sys_clk_n, sys_clk_p => sys_clk_p, sys_clk_n => sys_clk_n, sys_rst_n => sys_rst_n, -- DDR memory controller interface -- -- uncomment when instantiating in another project ddr_core_rst => ddr_sys_rst_i, memc_ui_clk => ddr_ui_clk, memc_ui_rst => open, memc_cmd_rdy => open, memc_cmd_en => '0', memc_cmd_instr => (others => '0'), memc_cmd_addr => (others => '0'), memc_wr_en => '0', memc_wr_end => '0', memc_wr_mask => (others => '0'), memc_wr_data => (others => '0'), memc_wr_rdy => open, memc_rd_data => open, memc_rd_valid => open, ---- memory arbiter interface memarb_acc_req => '0', memarb_acc_gnt => open, --/ DDR memory controller interface -- Wishbone interface -- -- uncomment when instantiating in another project CLK_I => wbone_clk, RST_I => wbone_rst, ACK_I => wbone_ack, DAT_I => wbone_mdin, ADDR_O => wbone_addr(28 downto 0), DAT_O => wbone_mdout, WE_O => wbone_we, STB_O => wbone_stb, SEL_O => wbone_sel(0), CYC_O => wbone_cyc, --/ Wishbone interface -- Additional exported signals for instantiation ext_rst_o => wbone_rst ); Wishbone_mem_large: if (SIMULATION = "TRUE") generate wb_mem_sim : wb_mem generic map( AWIDTH => 16, DWIDTH => 64 ) port map( CLK_I => wbone_clk, --in std_logic; ACK_O => wbone_ack, --out std_logic; ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); STB_I => wbone_stb, --in std_logic; WE_I => wbone_we --in std_logic ); end generate; Wishbone_mem_sample: if (SIMULATION = "FALSE") generate wb_mem_syn : wb_mem generic map( AWIDTH => 7, DWIDTH => 64 ) port map( CLK_I => wbone_clk, --in std_logic; ACK_O => wbone_ack, --out std_logic; ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); STB_I => wbone_stb, --in std_logic; WE_I => wbone_we --in std_logic ); end generate; --temporary clock assignment wbone_clk <= ddr_ui_clk; end architecture;
-- Shift Register library ieee; use ieee.std_logic_1164.all; entity shiftregister is generic ( NUM_STAGES : natural := 10 ); port ( clk : in std_logic; en : in std_logic; load : in std_logic; P_S : in std_logic; D : in std_logic_vector(NUM_STAGES-1 downto 0); Q : out std_logic_vector(NUM_STAGES-1 downto 0) ); end entity; architecture rtl of shiftregister is signal sr : std_logic_vector(NUM_STAGES-1 downto 0) := (others => '0'); begin process (clk) begin if (rising_edge(clk)) then if (en = '1') then if (P_S = '1') and (load = '1') then sr <= D; elsif (P_S = '0') then -- Shift data by one stage; data from last stage is lost sr((NUM_STAGES-1) downto 1) <= sr((NUM_STAGES-2) downto 0); -- Load new data into the first stage sr(0) <= D(0); end if; end if; end if; end process; Q <= sr; end rtl;
library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.numeric_std.all; -- CONNECTIVITY DEFINITION entity bigfile is port ( -- from external pins sysclk : in std_logic; g_zaq_in : in std_logic_vector(31 downto 0); g_aux : in std_logic_vector(31 downto 0); scanb : in std_logic; g_wrb : in std_logic; g_rdb : in std_logic; g_noop_clr : in std_logic_vector(31 downto 0); swe_ed : in std_logic; swe_lv : in std_logic; din : in std_logic_vector(63 downto 0); g_dout_w0x0f : in std_logic_vector(4 downto 0); n9_bit_write : in std_logic; -- from reset_gen block reset : in std_logic; alu_u : in std_logic_vector(31 downto 0); debct_ping : in std_logic; g_sys_in : out std_logic_vector(31 downto 0); g_zaq_in_rst_hold : out std_logic_vector(31 downto 0); g_zaq_hhh_enb : out std_logic_vector(31 downto 0); g_zaq_out : out std_logic_vector(31 downto 0); g_dout : out std_logic_vector(31 downto 0); g_zaq_ctl : out std_logic_vector(31 downto 0); g_zaq_qaz_hb : out std_logic_vector(31 downto 0); g_zaq_qaz_lb : out std_logic_vector(31 downto 0); gwerth : out std_logic_vector(31 downto 0); g_noop : out std_logic_vector(31 downto 0); g_vector : out std_logic_vector(8*32-1 downto 0); swe_qaz1 : out std_logic_vector(31 downto 0) ); end bigfile; -- IMPLEMENTATION architecture rtl of bigfile is -- constants constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000"; constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001"; constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010"; constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011"; constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100"; constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101"; constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110"; constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111"; constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000"; constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001"; constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010"; constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011"; constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100"; constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101"; constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110"; constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111"; constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000"; constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001"; constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010"; constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011"; constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100"; constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101"; constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110"; constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111"; -- comment signal g_t_klim_dout : std_logic_vector(31 downto 0); signal g_t_u_dout : std_logic_vector(31 downto 0); signal g_t_l_dout : std_logic_vector(31 downto 0); signal g_t_hhh_l_dout : std_logic_vector(31 downto 0); signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0); signal g_secondary_t_l_dout : std_logic_vector(31 downto 0); signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used signal g_e_z_dout : std_logic_vector(31 downto 0); signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0); signal g_style_vfr_dout : std_logic_vector(31 downto 0); signal g_style_klim_dout : std_logic_vector(31 downto 0); signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0); signal g_style_t_y_dout : std_logic_vector(31 downto 0); signal g_n_l_dout : std_logic_vector(31 downto 0); signal g_n_vfr_dout : std_logic_vector(31 downto 0); signal g_e_n_r_dout : std_logic_vector(31 downto 0); signal g_n_r_bne_dout : std_logic; signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0); signal g_alu_l_dout : std_logic_vector(31 downto 0); signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0); signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0); signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0); signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0); signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0); -- other signal q_g_zaq_in : std_logic_vector(31 downto 0); signal q2_g_zaq_in : std_logic_vector(31 downto 0); signal q3_g_zaq_in : std_logic_vector(31 downto 0); signal q_g_zaq_in_cd : std_logic_vector(3 downto 0); signal q_g_style_vfr_dout : std_logic_vector(31 downto 0); signal q_g_unzq : std_logic_vector(3 downto 0); -- i signal g_n_active : std_logic_vector(31 downto 0); -- inter signal g_zaq_in_y : std_logic_vector(31 downto 0); signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0); signal g_zaq_out_i : std_logic_vector(31 downto 0); signal g_zaq_ctl_i : std_logic_vector(31 downto 0); signal g_sys_in_i : std_logic_vector(31 downto 0); signal g_sys_in_ii : std_logic_vector(31 downto 0); signal g_dout_i : std_logic_vector(31 downto 0); begin -- qaz out g_zaq_out_i <= -- if secondary (g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or -- if alu (g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or -- otherwise (not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout); -- Changed g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout; -- qaz -- JLB g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or (g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i)); -- mux --vnavigatoroff g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000"; --vnavigatoron g_zaq_hhh_enb <= not(g_t_hhh_l_dout); g_zaq_qaz_hb <= g_t_qaz_mult_high_dout; g_zaq_qaz_lb <= g_t_qaz_mult_low_dout; -- Dout g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else ("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else ("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else "00000000000000000000000000000000"; g_dout <= g_dout_i when g_rdb = '0' else (others => '1'); -- this can be used to use zzz1 g_style_main_reset_hold_dout_proc : process(sysclk) begin if( sysclk'event and sysclk = '1' ) then if( scanb = '1' ) then if( reset = '1' ) then g_style_main_reset_hold_dout <= g_zaq_in; end if; --vnavigatoroff else g_style_main_reset_hold_dout <= q2_g_zaq_in; end if; --vnavigatoron end if; end process; -- qaz g_zaq_in_rst_hold <= g_style_main_reset_hold_dout; -- Din g_doutister_proc : process(reset, sysclk) variable g_dout_w0x0f_v : std_logic_vector(4 downto 0); begin if( reset /= '0' ) then g_t_klim_dout <= (others => '0'); g_t_u_dout <= (others => '0'); g_t_l_dout <= (others => '0'); g_t_hhh_l_dout <= (others => '0'); g_t_jkl_sink_l_dout <= (others => '0'); g_secondary_t_l_dout <= (others => '0'); g_style_c_l_dout <= (others => '0'); g_e_z_dout <= (others => '0'); g_n_both_qbars_l_dout <= (others => '0'); g_style_klim_dout <= (others => '0'); g_style_t_y_dout <= (others => '0'); g_n_l_dout <= (others => '0'); g_e_n_r_dout <= (others => '0'); g_n_r_bne_dout <= '0'; g_n_div_rebeq_dout <= (others => '1'); g_alu_l_dout <= (others => '0'); g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low g_t_qaz_mult_high_dout <= (others => '0'); gwerthernal_style_u_dout <= (others => '0'); gwerthernal_style_l_dout <= (others => '0'); elsif( sysclk'event and sysclk = '1' ) then -- clear g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr; if( g_wrb = '0' ) then -- because we now... for i in 0 to 1 loop if( i = 0 ) then g_dout_w0x0f_v := g_dout_w0x0f; elsif( i = 1 ) then if( n9_bit_write = '1' ) then -- set g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1'; else exit; end if; --vnavigatoroff else -- not possible but added for code coverage's sake end if; --vnavigatoron case g_dout_w0x0f_v is when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32); when g_t_u_w0x0f => -- output klim for j in 0 to 31 loop if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then g_t_u_dout(j) <= din(32*i+j); end if; end loop; when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32); when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32); when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32); when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32); when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32); when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32); when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32); when g_style_vfr_w0x0f => null; -- read-only register when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32); when g_unklimed_style_vfr_w0x0f => null; -- read-only register when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32); when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32); when g_n_vfr_w0x0f => null; -- writes when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32); when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32); when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or g_n_div_rebeq_dout; -- a '1' writes when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32); when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32); when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32); when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32); when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32); --vnavigatoroff when others => null; --vnavigatoron end case; end loop; end if; end if; end process; -- sample g_zaq_in_sample_proc : process(reset, sysclk) begin if( reset /= '0' ) then q_g_zaq_in <= (others => '0'); q2_g_zaq_in <= (others => '0'); q3_g_zaq_in <= (others => '0'); elsif( sysclk'event and sysclk = '1' ) then q_g_zaq_in <= g_zaq_in; q2_g_zaq_in <= q_g_zaq_in; q3_g_zaq_in <= g_zaq_in_y; end if; end process; -- vfr register g_unklimed_style_vfr_dout <= q2_g_zaq_in; -- switch g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in; -- qaz g_style_vfr_dout <= -- top 2 (g_zaq_in_y(31 downto 4) & -- FSM (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or -- otherwise just use (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0)))); -- in scan mode g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1' --vnavigatoroff else g_style_t_y_dout; --vnavigatoron g_sys_in_i <= (-- top 28 (g_zaq_in_y_no_dout(31 downto 4) & -- is enabled (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or -- otherwise just use (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0))))); g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout ); g_sys_in <= g_sys_in_ii; lpq_proc : process(reset, sysclk) begin if( reset /= '0' ) then q_g_zaq_in_cd <= (others => '0'); q_g_unzq <= (others => '1'); elsif( sysclk'event and sysclk = '1' ) then -- sample if( debct_ping = '1') then -- taken for i in 0 to 3 loop if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then q_g_unzq(i) <= '1'; else if( q_g_unzq(i) = '0' ) then q_g_zaq_in_cd(i) <= g_zaq_in_y(i); else q_g_unzq(i) <= '0'; end if; end if; end loop; else for i in 0 to 3 loop if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then q_g_unzq(i) <= '1'; end if; end loop; end if; end if; end process; -- generate lqqs sample_forwerth_proc : process(reset, sysclk) begin if( reset /= '0' ) then q_g_style_vfr_dout <= (others => '0'); elsif( sysclk'event and sysclk = '1' ) then if( scanb = '1' ) then q_g_style_vfr_dout <= g_style_vfr_dout; --vnavigatoroff else -- in scan q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii; end if; --vnavigatoron end if; end process; -- generate g_n_active <= -- 1 to 0 (((q_g_style_vfr_dout and not g_style_vfr_dout) or -- get this (not q_g_style_vfr_dout and g_style_vfr_dout and g_n_both_qbars_l_dout))) and -- must be g_n_l_dout; -- check for lqq active and set lqq vfr register -- also clear n_proc : process(reset, sysclk) begin if( reset /= '0' ) then g_n_vfr_dout <= (others => '0'); gwerth <= (others => '0'); elsif( sysclk'event and sysclk = '1' ) then for i in 0 to 31 loop -- lqq -- vfr matches if( g_n_active(i) = '1' ) then gwerth(i) <= '1'; if( g_e_z_dout(i) = '1' ) then -- lqq g_n_vfr_dout(i) <= '1'; else g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); end if; else -- clear if( g_e_z_dout(i) = '0' ) then g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign -- in both if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then gwerth(i) <= '0'; end if; else -- write if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then gwerth(i) <= '0'; g_n_vfr_dout(i) <= '0'; end if; end if; end if; end loop; end if; end process; ---- -- Create the Lqq createwerth_vec_proc : process( g_n_r_bne_dout, g_e_n_r_dout) variable imod8, idiv8 : integer; begin for i in 0 to 31 loop imod8 := i mod 8; idiv8 := i / 8; if( g_n_r_bne_dout = '0' ) then -- non-unique g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); else -- unique if( imod8 = 0 ) then g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); else g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) + to_unsigned(imod8, 8)); end if; end if; end loop; end process; ---- -- Qaz g_noop <= g_n_div_rebeq_dout; create_g_ack_bne_proc : process( swe_ed,swe_lv,g_e_z_dout) begin for i in 0 to 31 loop if( g_e_z_dout(i) = '1') then swe_qaz1(i) <= swe_ed; else swe_qaz1(i) <= swe_lv; end if; end loop; end process; end rtl;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:mutex:2.1 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY mutex_v2_1_8; USE mutex_v2_1_8.mutex; ENTITY DemoInterconnect_mutex_0_0 IS PORT ( S0_AXI_ACLK : IN STD_LOGIC; S0_AXI_ARESETN : IN STD_LOGIC; S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_AWVALID : IN STD_LOGIC; S0_AXI_AWREADY : OUT STD_LOGIC; S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S0_AXI_WVALID : IN STD_LOGIC; S0_AXI_WREADY : OUT STD_LOGIC; S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S0_AXI_BVALID : OUT STD_LOGIC; S0_AXI_BREADY : IN STD_LOGIC; S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_ARVALID : IN STD_LOGIC; S0_AXI_ARREADY : OUT STD_LOGIC; S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S0_AXI_RVALID : OUT STD_LOGIC; S0_AXI_RREADY : IN STD_LOGIC; S1_AXI_ACLK : IN STD_LOGIC; S1_AXI_ARESETN : IN STD_LOGIC; S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_AWVALID : IN STD_LOGIC; S1_AXI_AWREADY : OUT STD_LOGIC; S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S1_AXI_WVALID : IN STD_LOGIC; S1_AXI_WREADY : OUT STD_LOGIC; S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S1_AXI_BVALID : OUT STD_LOGIC; S1_AXI_BREADY : IN STD_LOGIC; S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_ARVALID : IN STD_LOGIC; S1_AXI_ARREADY : OUT STD_LOGIC; S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S1_AXI_RVALID : OUT STD_LOGIC; S1_AXI_RREADY : IN STD_LOGIC; S2_AXI_ACLK : IN STD_LOGIC; S2_AXI_ARESETN : IN STD_LOGIC; S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_AWVALID : IN STD_LOGIC; S2_AXI_AWREADY : OUT STD_LOGIC; S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S2_AXI_WVALID : IN STD_LOGIC; S2_AXI_WREADY : OUT STD_LOGIC; S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S2_AXI_BVALID : OUT STD_LOGIC; S2_AXI_BREADY : IN STD_LOGIC; S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_ARVALID : IN STD_LOGIC; S2_AXI_ARREADY : OUT STD_LOGIC; S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S2_AXI_RVALID : OUT STD_LOGIC; S2_AXI_RREADY : IN STD_LOGIC ); END DemoInterconnect_mutex_0_0; ARCHITECTURE DemoInterconnect_mutex_0_0_arch OF DemoInterconnect_mutex_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT mutex IS GENERIC ( C_FAMILY : STRING; C_NUM_AXI : INTEGER; C_S0_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S0_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S0_AXI_ADDR_WIDTH : INTEGER; C_S0_AXI_DATA_WIDTH : INTEGER; C_S1_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S1_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S1_AXI_ADDR_WIDTH : INTEGER; C_S1_AXI_DATA_WIDTH : INTEGER; C_S2_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S2_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S2_AXI_ADDR_WIDTH : INTEGER; C_S2_AXI_DATA_WIDTH : INTEGER; C_S3_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S3_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S3_AXI_ADDR_WIDTH : INTEGER; C_S3_AXI_DATA_WIDTH : INTEGER; C_S4_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S4_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S4_AXI_ADDR_WIDTH : INTEGER; C_S4_AXI_DATA_WIDTH : INTEGER; C_S5_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S5_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S5_AXI_ADDR_WIDTH : INTEGER; C_S5_AXI_DATA_WIDTH : INTEGER; C_S6_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S6_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S6_AXI_ADDR_WIDTH : INTEGER; C_S6_AXI_DATA_WIDTH : INTEGER; C_S7_AXI_BASEADDR : STD_LOGIC_VECTOR; C_S7_AXI_HIGHADDR : STD_LOGIC_VECTOR; C_S7_AXI_ADDR_WIDTH : INTEGER; C_S7_AXI_DATA_WIDTH : INTEGER; C_ASYNC_CLKS : INTEGER; C_NUM_SYNC_FF : INTEGER; C_ENABLE_USER : INTEGER; C_OWNER_ID_WIDTH : INTEGER; C_ENABLE_HW_PROT : INTEGER; C_NUM_MUTEX : INTEGER ); PORT ( S0_AXI_ACLK : IN STD_LOGIC; S0_AXI_ARESETN : IN STD_LOGIC; S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_AWVALID : IN STD_LOGIC; S0_AXI_AWREADY : OUT STD_LOGIC; S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S0_AXI_WVALID : IN STD_LOGIC; S0_AXI_WREADY : OUT STD_LOGIC; S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S0_AXI_BVALID : OUT STD_LOGIC; S0_AXI_BREADY : IN STD_LOGIC; S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_ARVALID : IN STD_LOGIC; S0_AXI_ARREADY : OUT STD_LOGIC; S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S0_AXI_RVALID : OUT STD_LOGIC; S0_AXI_RREADY : IN STD_LOGIC; S1_AXI_ACLK : IN STD_LOGIC; S1_AXI_ARESETN : IN STD_LOGIC; S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_AWVALID : IN STD_LOGIC; S1_AXI_AWREADY : OUT STD_LOGIC; S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S1_AXI_WVALID : IN STD_LOGIC; S1_AXI_WREADY : OUT STD_LOGIC; S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S1_AXI_BVALID : OUT STD_LOGIC; S1_AXI_BREADY : IN STD_LOGIC; S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_ARVALID : IN STD_LOGIC; S1_AXI_ARREADY : OUT STD_LOGIC; S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S1_AXI_RVALID : OUT STD_LOGIC; S1_AXI_RREADY : IN STD_LOGIC; S2_AXI_ACLK : IN STD_LOGIC; S2_AXI_ARESETN : IN STD_LOGIC; S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_AWVALID : IN STD_LOGIC; S2_AXI_AWREADY : OUT STD_LOGIC; S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S2_AXI_WVALID : IN STD_LOGIC; S2_AXI_WREADY : OUT STD_LOGIC; S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S2_AXI_BVALID : OUT STD_LOGIC; S2_AXI_BREADY : IN STD_LOGIC; S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_ARVALID : IN STD_LOGIC; S2_AXI_ARREADY : OUT STD_LOGIC; S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S2_AXI_RVALID : OUT STD_LOGIC; S2_AXI_RREADY : IN STD_LOGIC; S3_AXI_ACLK : IN STD_LOGIC; S3_AXI_ARESETN : IN STD_LOGIC; S3_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S3_AXI_AWVALID : IN STD_LOGIC; S3_AXI_AWREADY : OUT STD_LOGIC; S3_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S3_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S3_AXI_WVALID : IN STD_LOGIC; S3_AXI_WREADY : OUT STD_LOGIC; S3_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S3_AXI_BVALID : OUT STD_LOGIC; S3_AXI_BREADY : IN STD_LOGIC; S3_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S3_AXI_ARVALID : IN STD_LOGIC; S3_AXI_ARREADY : OUT STD_LOGIC; S3_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S3_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S3_AXI_RVALID : OUT STD_LOGIC; S3_AXI_RREADY : IN STD_LOGIC; S4_AXI_ACLK : IN STD_LOGIC; S4_AXI_ARESETN : IN STD_LOGIC; S4_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S4_AXI_AWVALID : IN STD_LOGIC; S4_AXI_AWREADY : OUT STD_LOGIC; S4_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S4_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S4_AXI_WVALID : IN STD_LOGIC; S4_AXI_WREADY : OUT STD_LOGIC; S4_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S4_AXI_BVALID : OUT STD_LOGIC; S4_AXI_BREADY : IN STD_LOGIC; S4_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S4_AXI_ARVALID : IN STD_LOGIC; S4_AXI_ARREADY : OUT STD_LOGIC; S4_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S4_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S4_AXI_RVALID : OUT STD_LOGIC; S4_AXI_RREADY : IN STD_LOGIC; S5_AXI_ACLK : IN STD_LOGIC; S5_AXI_ARESETN : IN STD_LOGIC; S5_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S5_AXI_AWVALID : IN STD_LOGIC; S5_AXI_AWREADY : OUT STD_LOGIC; S5_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S5_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S5_AXI_WVALID : IN STD_LOGIC; S5_AXI_WREADY : OUT STD_LOGIC; S5_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S5_AXI_BVALID : OUT STD_LOGIC; S5_AXI_BREADY : IN STD_LOGIC; S5_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S5_AXI_ARVALID : IN STD_LOGIC; S5_AXI_ARREADY : OUT STD_LOGIC; S5_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S5_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S5_AXI_RVALID : OUT STD_LOGIC; S5_AXI_RREADY : IN STD_LOGIC; S6_AXI_ACLK : IN STD_LOGIC; S6_AXI_ARESETN : IN STD_LOGIC; S6_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S6_AXI_AWVALID : IN STD_LOGIC; S6_AXI_AWREADY : OUT STD_LOGIC; S6_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S6_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S6_AXI_WVALID : IN STD_LOGIC; S6_AXI_WREADY : OUT STD_LOGIC; S6_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S6_AXI_BVALID : OUT STD_LOGIC; S6_AXI_BREADY : IN STD_LOGIC; S6_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S6_AXI_ARVALID : IN STD_LOGIC; S6_AXI_ARREADY : OUT STD_LOGIC; S6_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S6_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S6_AXI_RVALID : OUT STD_LOGIC; S6_AXI_RREADY : IN STD_LOGIC; S7_AXI_ACLK : IN STD_LOGIC; S7_AXI_ARESETN : IN STD_LOGIC; S7_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S7_AXI_AWVALID : IN STD_LOGIC; S7_AXI_AWREADY : OUT STD_LOGIC; S7_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S7_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S7_AXI_WVALID : IN STD_LOGIC; S7_AXI_WREADY : OUT STD_LOGIC; S7_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S7_AXI_BVALID : OUT STD_LOGIC; S7_AXI_BREADY : IN STD_LOGIC; S7_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S7_AXI_ARVALID : IN STD_LOGIC; S7_AXI_ARREADY : OUT STD_LOGIC; S7_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S7_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S7_AXI_RVALID : OUT STD_LOGIC; S7_AXI_RREADY : IN STD_LOGIC ); END COMPONENT mutex; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "mutex,Vivado 2017.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_mutex_0_0_arch : ARCHITECTURE IS "DemoInterconnect_mutex_0_0,mutex,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "DemoInterconnect_mutex_0_0,mutex,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mutex,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_AXI=3,C_S0_AXI_BASEADDR=0x00100000,C_S0_AXI_HIGHADDR=0x0010FFFF,C_S0_AXI_ADDR_WIDTH=32,C_S0_AXI_DATA_WIDTH=32,C_S1_AXI_BASEADDR=0x00200000,C_S1_AXI_HIGHADDR=0x0020FFFF,C_S1_AXI_ADDR_WIDTH=32,C_S1_AXI_DATA_WIDTH=32,C_S2_AXI_BASEADDR=0x00300000,C_S2_AXI_HIGHADDR=0x0030FFFF,C_S2_AXI_ADDR_WIDTH" & "=32,C_S2_AXI_DATA_WIDTH=32,C_S3_AXI_BASEADDR=0xFFFFFFFF,C_S3_AXI_HIGHADDR=0x00000000,C_S3_AXI_ADDR_WIDTH=32,C_S3_AXI_DATA_WIDTH=32,C_S4_AXI_BASEADDR=0xFFFFFFFF,C_S4_AXI_HIGHADDR=0x00000000,C_S4_AXI_ADDR_WIDTH=32,C_S4_AXI_DATA_WIDTH=32,C_S5_AXI_BASEADDR=0xFFFFFFFF,C_S5_AXI_HIGHADDR=0x00000000,C_S5_AXI_ADDR_WIDTH=32,C_S5_AXI_DATA_WIDTH=32,C_S6_AXI_BASEADDR=0xFFFFFFFF,C_S6_AXI_HIGHADDR=0x00000000,C_S6_AXI_ADDR_WIDTH=32,C_S6_AXI_DATA_WIDTH=32,C_S7_AXI_BASEADDR=0xFFFFFFFF,C_S7_AXI_HIGHADDR=0x00000000" & ",C_S7_AXI_ADDR_WIDTH=32,C_S7_AXI_DATA_WIDTH=32,C_ASYNC_CLKS=0,C_NUM_SYNC_FF=2,C_ENABLE_USER=1,C_OWNER_ID_WIDTH=8,C_ENABLE_HW_PROT=1,C_NUM_MUTEX=16}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S2_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S2_AXI_ARESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S2_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S2_AXI_ACLK, ASSOCIATED_BUSIF S2_AXI, ASSOCIATED_RESET S2_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1"; ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S2_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S1_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S1_AXI_ARESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S1_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S1_AXI_ACLK, ASSOCIATED_BUSIF S1_AXI, ASSOCIATED_RESET S1_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1"; ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S1_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S0_AXI_ARESETN, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S0_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S0_AXI_ACLK, ASSOCIATED_BUSIF S0_AXI, ASSOCIATED_RESET S0_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1"; ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S0_AXI_ACLK CLK"; BEGIN U0 : mutex GENERIC MAP ( C_FAMILY => "artix7", C_NUM_AXI => 3, C_S0_AXI_BASEADDR => X"00100000", C_S0_AXI_HIGHADDR => X"0010FFFF", C_S0_AXI_ADDR_WIDTH => 32, C_S0_AXI_DATA_WIDTH => 32, C_S1_AXI_BASEADDR => X"00200000", C_S1_AXI_HIGHADDR => X"0020FFFF", C_S1_AXI_ADDR_WIDTH => 32, C_S1_AXI_DATA_WIDTH => 32, C_S2_AXI_BASEADDR => X"00300000", C_S2_AXI_HIGHADDR => X"0030FFFF", C_S2_AXI_ADDR_WIDTH => 32, C_S2_AXI_DATA_WIDTH => 32, C_S3_AXI_BASEADDR => X"FFFFFFFF", C_S3_AXI_HIGHADDR => X"00000000", C_S3_AXI_ADDR_WIDTH => 32, C_S3_AXI_DATA_WIDTH => 32, C_S4_AXI_BASEADDR => X"FFFFFFFF", C_S4_AXI_HIGHADDR => X"00000000", C_S4_AXI_ADDR_WIDTH => 32, C_S4_AXI_DATA_WIDTH => 32, C_S5_AXI_BASEADDR => X"FFFFFFFF", C_S5_AXI_HIGHADDR => X"00000000", C_S5_AXI_ADDR_WIDTH => 32, C_S5_AXI_DATA_WIDTH => 32, C_S6_AXI_BASEADDR => X"FFFFFFFF", C_S6_AXI_HIGHADDR => X"00000000", C_S6_AXI_ADDR_WIDTH => 32, C_S6_AXI_DATA_WIDTH => 32, C_S7_AXI_BASEADDR => X"FFFFFFFF", C_S7_AXI_HIGHADDR => X"00000000", C_S7_AXI_ADDR_WIDTH => 32, C_S7_AXI_DATA_WIDTH => 32, C_ASYNC_CLKS => 0, C_NUM_SYNC_FF => 2, C_ENABLE_USER => 1, C_OWNER_ID_WIDTH => 8, C_ENABLE_HW_PROT => 1, C_NUM_MUTEX => 16 ) PORT MAP ( S0_AXI_ACLK => S0_AXI_ACLK, S0_AXI_ARESETN => S0_AXI_ARESETN, S0_AXI_AWADDR => S0_AXI_AWADDR, S0_AXI_AWVALID => S0_AXI_AWVALID, S0_AXI_AWREADY => S0_AXI_AWREADY, S0_AXI_WDATA => S0_AXI_WDATA, S0_AXI_WSTRB => S0_AXI_WSTRB, S0_AXI_WVALID => S0_AXI_WVALID, S0_AXI_WREADY => S0_AXI_WREADY, S0_AXI_BRESP => S0_AXI_BRESP, S0_AXI_BVALID => S0_AXI_BVALID, S0_AXI_BREADY => S0_AXI_BREADY, S0_AXI_ARADDR => S0_AXI_ARADDR, S0_AXI_ARVALID => S0_AXI_ARVALID, S0_AXI_ARREADY => S0_AXI_ARREADY, S0_AXI_RDATA => S0_AXI_RDATA, S0_AXI_RRESP => S0_AXI_RRESP, S0_AXI_RVALID => S0_AXI_RVALID, S0_AXI_RREADY => S0_AXI_RREADY, S1_AXI_ACLK => S1_AXI_ACLK, S1_AXI_ARESETN => S1_AXI_ARESETN, S1_AXI_AWADDR => S1_AXI_AWADDR, S1_AXI_AWVALID => S1_AXI_AWVALID, S1_AXI_AWREADY => S1_AXI_AWREADY, S1_AXI_WDATA => S1_AXI_WDATA, S1_AXI_WSTRB => S1_AXI_WSTRB, S1_AXI_WVALID => S1_AXI_WVALID, S1_AXI_WREADY => S1_AXI_WREADY, S1_AXI_BRESP => S1_AXI_BRESP, S1_AXI_BVALID => S1_AXI_BVALID, S1_AXI_BREADY => S1_AXI_BREADY, S1_AXI_ARADDR => S1_AXI_ARADDR, S1_AXI_ARVALID => S1_AXI_ARVALID, S1_AXI_ARREADY => S1_AXI_ARREADY, S1_AXI_RDATA => S1_AXI_RDATA, S1_AXI_RRESP => S1_AXI_RRESP, S1_AXI_RVALID => S1_AXI_RVALID, S1_AXI_RREADY => S1_AXI_RREADY, S2_AXI_ACLK => S2_AXI_ACLK, S2_AXI_ARESETN => S2_AXI_ARESETN, S2_AXI_AWADDR => S2_AXI_AWADDR, S2_AXI_AWVALID => S2_AXI_AWVALID, S2_AXI_AWREADY => S2_AXI_AWREADY, S2_AXI_WDATA => S2_AXI_WDATA, S2_AXI_WSTRB => S2_AXI_WSTRB, S2_AXI_WVALID => S2_AXI_WVALID, S2_AXI_WREADY => S2_AXI_WREADY, S2_AXI_BRESP => S2_AXI_BRESP, S2_AXI_BVALID => S2_AXI_BVALID, S2_AXI_BREADY => S2_AXI_BREADY, S2_AXI_ARADDR => S2_AXI_ARADDR, S2_AXI_ARVALID => S2_AXI_ARVALID, S2_AXI_ARREADY => S2_AXI_ARREADY, S2_AXI_RDATA => S2_AXI_RDATA, S2_AXI_RRESP => S2_AXI_RRESP, S2_AXI_RVALID => S2_AXI_RVALID, S2_AXI_RREADY => S2_AXI_RREADY, S3_AXI_ACLK => '0', S3_AXI_ARESETN => '0', S3_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S3_AXI_AWVALID => '0', S3_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S3_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S3_AXI_WVALID => '0', S3_AXI_BREADY => '0', S3_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S3_AXI_ARVALID => '0', S3_AXI_RREADY => '0', S4_AXI_ACLK => '0', S4_AXI_ARESETN => '0', S4_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S4_AXI_AWVALID => '0', S4_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S4_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S4_AXI_WVALID => '0', S4_AXI_BREADY => '0', S4_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S4_AXI_ARVALID => '0', S4_AXI_RREADY => '0', S5_AXI_ACLK => '0', S5_AXI_ARESETN => '0', S5_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S5_AXI_AWVALID => '0', S5_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S5_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S5_AXI_WVALID => '0', S5_AXI_BREADY => '0', S5_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S5_AXI_ARVALID => '0', S5_AXI_RREADY => '0', S6_AXI_ACLK => '0', S6_AXI_ARESETN => '0', S6_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S6_AXI_AWVALID => '0', S6_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S6_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S6_AXI_WVALID => '0', S6_AXI_BREADY => '0', S6_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S6_AXI_ARVALID => '0', S6_AXI_RREADY => '0', S7_AXI_ACLK => '0', S7_AXI_ARESETN => '0', S7_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S7_AXI_AWVALID => '0', S7_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S7_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S7_AXI_WVALID => '0', S7_AXI_BREADY => '0', S7_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S7_AXI_ARVALID => '0', S7_AXI_RREADY => '0' ); END DemoInterconnect_mutex_0_0_arch;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WaUMYyOCrJ3+e0D+IgKRm7y7D8B3zV49qiAzywvvZnM+iiPmkjv6jaaleJhuUHr/VVbJ0WVREsFN C3aocuAIZQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vg4kt+0MRKUFDd786MB334oscjgqOf0zx5x6X9lD5FSNEePK+/Ljwwf4Tg5LDl6RNtM6Wjqch9qW bZos/OTOGWCccZ7THphoHP82pYF+16K4OALfhXWSVLkx3LM/Ee80BPMDNyNr7APabTz8t/B2zYqn gE2Fzu+5KZhSDvDOuQY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WaUMYyOCrJ3+e0D+IgKRm7y7D8B3zV49qiAzywvvZnM+iiPmkjv6jaaleJhuUHr/VVbJ0WVREsFN C3aocuAIZQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vg4kt+0MRKUFDd786MB334oscjgqOf0zx5x6X9lD5FSNEePK+/Ljwwf4Tg5LDl6RNtM6Wjqch9qW bZos/OTOGWCccZ7THphoHP82pYF+16K4OALfhXWSVLkx3LM/Ee80BPMDNyNr7APabTz8t/B2zYqn gE2Fzu+5KZhSDvDOuQY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WaUMYyOCrJ3+e0D+IgKRm7y7D8B3zV49qiAzywvvZnM+iiPmkjv6jaaleJhuUHr/VVbJ0WVREsFN C3aocuAIZQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vg4kt+0MRKUFDd786MB334oscjgqOf0zx5x6X9lD5FSNEePK+/Ljwwf4Tg5LDl6RNtM6Wjqch9qW bZos/OTOGWCccZ7THphoHP82pYF+16K4OALfhXWSVLkx3LM/Ee80BPMDNyNr7APabTz8t/B2zYqn gE2Fzu+5KZhSDvDOuQY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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library verilog; use verilog.vl_types.all; entity PC is port( clock : in vl_logic; reset : in vl_logic; PCEn : in vl_logic; \in\ : in vl_logic_vector(7 downto 0); \out\ : out vl_logic_vector(7 downto 0) ); end PC;
-- SHA256 Hashing Module - ROM with test data -- Kristian Klomsten Skordal <kristian.skordal@wafflemail.net> library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity testrom is port( clk : in std_logic; word_address : in std_logic_vector(5 downto 0); word_output : out std_logic_vector(31 downto 0) ); end entity testrom; architecture behaviour of testrom is type testdata2_array is array(0 to 31) of std_logic_vector(31 downto 0); constant testdata2 : testdata2_array := ( x"61626364", x"62636465", x"63646566", x"64656667", x"65666768", x"66676869", x"6768696a", x"68696a6b", x"696a6b6c", x"6a6b6c6d", x"6b6c6d6e", x"6c6d6e6f", x"6d6e6f70", x"6e6f7071", x"80000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"00000000", x"000001c0"); begin readproc: process(clk) begin if falling_edge(clk) then -- FIXME if word_address(5 downto 4) = b"00" then -- Test set 1, "abc" if word_address = b"000000" then word_output <= x"61626380"; -- "abc" and a 1 bit at the end elsif word_address = b"001111" then word_output <= x"00000018"; -- message length is 24 bits else word_output <= (others => '0'); end if; else -- Test set 2, "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" if word_address(5) = '1' then word_output <= testdata2(16 + to_integer(unsigned(word_address(3 downto 0)))); else word_output <= testdata2(to_integer(unsigned(word_address(3 downto 0)))); end if; end if; end if; end process readproc; end architecture behaviour;
-- NEED RESULT: ARCH00121.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00121 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00121 -- PKG00121/BODY -- ENT00121(ARCH00121) -- ENT00121_Test_Bench(ARCH00121_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00121 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00121 ; -- package body PKG00121 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00121 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00121.all ; entity ENT00121 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_r_st_arr1_vector : inout r_st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_r_st_arr2_vector : inout r_st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_r_st_arr3_vector : inout r_st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_r_st_rec1_vector : inout r_st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_r_st_rec2_vector : inout r_st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_r_st_rec3_vector : inout r_st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- -- end ENT00121 ; -- architecture ARCH00121 of ENT00121 is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_r_st_arr1_vector, counter, correct, savtime, chk_r_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_r_st_arr2_vector, counter, correct, savtime, chk_r_st_arr2_vector ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_r_st_arr3_vector, counter, correct, savtime, chk_r_st_arr3_vector ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_r_st_rec1_vector, counter, correct, savtime, chk_r_st_rec1_vector ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_r_st_rec2_vector, counter, correct, savtime, chk_r_st_rec2_vector ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_r_st_rec3_vector, counter, correct, savtime, chk_r_st_rec3_vector ) ; end process P6 ; -- -- end ARCH00121 ; -- entity ENT00121_Test_Bench is end ENT00121_Test_Bench ; -- architecture ARCH00121_Test_Bench of ENT00121_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00121 ( ARCH00121 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00121_Test_Bench ;
----------------------------------------------------------- -- cos_phase_table.vhd -- -- Lookup 16bit value from a cos(x) table. -- Table resolution is 12 bits (4096 entries) -- -- y = cos(x) -- where x is digital phase Q -- -- Q = (radian/2*pi)*((2^phase_depth)) -- or if you talk degrees -- Q = ( degrees/360)*((2^phase_depth)) -- -- -- Peter Fetterer (KB3GTN) ----------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; entity cos_phase_table is generic ( constant sample_depth : integer := 16; -- number of bits in output sample (1->N) constant phase_depth : integer := 12 -- number of bits for phase input value (1->N) ); port ( i_clk : in std_logic; -- input DSP clock i_srst : in std_logic; -- input sync reset to dsp clock --------------------------------------------------------- x : in unsigned( phase_depth-1 downto 0 ); -- digital normalized phase input (0->2*pi) y : out signed( sample_depth-1 downto 0 ) -- output value signed 16b ); end entity cos_phase_table; architecture system of cos_phase_table is ---------------------------------- -- lookup table -- pre-compute at compile time.. ---------------------------------- constant memory_depth : integer := 2**phase_depth; -- how many memory entries do we need. constant SCALE : real := real((2**(real(sample_depth)-1.0))-1.0); -- cos is normal 1.0 we want 2^(N-1)-1 (will all be positive values) constant STEP : real := 1.0/(real(2**phase_depth)); -- phase increment per table entry (0->90 degrees) -- memory table is 1/4 cos period, 1024 phase enteries of 16 bit samples -- taking advantage of cos symmetry for the other 3/4 of the period. type cos_table_mem is array ( 0 to memory_depth ) of signed( sample_depth-1 downto 0); -- function to fill in cos_table_mem function init_lookuptable return cos_table_mem is variable tmp_mem : cos_table_mem; begin -- phase table is only 0.25 + 1 sample of the total period. (0 -> 1024, 1025 entries) for i in 0 to integer((2**real(phase_depth))) loop tmp_mem(i) := to_signed( integer( round( cos(real(MATH_2_PI*(real(i)*STEP)))*SCALE)), 16 ); end loop; return tmp_mem; end; -- This is the lookup table, should synth into 1 blockram on Xilinx parts. constant cos_lookup : cos_table_mem := init_lookuptable; ---------------------------- -- Design Signals ---------------------------- signal ref_phase : unsigned(9 downto 0); -- lower 10 bits of X signal base_phase : unsigned(10 downto 0); -- base phase 0 -> 90 degrees signal inv_sample_out : std_logic; -- output sample needs to be inverted. signal quadrant : unsigned(1 downto 0); -- phase quadrant requested begin quadrant <= x(11 downto 10); -- upper 2 bits of phase give's us quadrant ref_phase <= x(9 downto 0); -- phase within quadrant compute_base_phase : process( i_clk ) begin if ( rising_edge( i_clk ) ) then if ( i_srst = '1' ) then base_phase <= (others=>'0'); inv_sample_out <= '0'; else case quadrant is when "00" => -- requested direct entry in table. -- 0 -> >90 degrees base_phase <= ("0" & ref_phase); inv_sample_out <= '0'; when "01" => -- request second quadrante -- 90 -> >180 degrees -- map 2nd quad phase to 1st quad phase base_phase <= "10000000000" - ("0" & ref_phase); -- 180 degrees - ref_phase => phase in quad 1. inv_sample_out <= '1'; -- invert the base_base from quad1 to get quad2's value. when "10" => -- request third quad -- 180 -> >270 -- map 3rd quad phase to 1st quad phase base_phase <= ("1" & ref_phase) - "10000000000"; -- just subtract 180 degrees inv_sample_out <= '1'; -- invert magnatude when "11" => -- request forth quad -- 270 -> >360 (360 is zero) -- map 4th quad to 1st quad phase base_phase <= "10000000000" - ( "0" & ref_phase); inv_sample_out <= '0'; when others => null; end case; end if; end if; end process; generate_sample : process( i_clk ) begin if ( rising_edge( i_clk ) ) then if ( inv_sample_out = '1' ) then -- invert sample before outputing ( invert and add 1 ) y <= not cos_lookup( to_integer(base_phase) ) + 1; else -- normal output y <= cos_lookup( to_integer(base_phase) ); end if; end if; end process; end architecture system;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2863.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c02s01b00x00p03n01i02863ent IS END c02s01b00x00p03n01i02863ent; ARCHITECTURE c02s01b00x00p03n01i02863arch OF c02s01b00x00p03n01i02863ent IS BEGIN TESTING: PROCESS procedure mytest (fpl:integer); procedure mytest (fpl:integer) is begin assert NOT( fpl = 5 ) report "***PASSED TEST: c02s01b00x00p03n01i02863" severity NOTE; assert ( fpl = 5 ) report "***FAILED TEST: c02s01b00x00p03n01i02863 - Subprogram syntax test failed." severity ERROR; end mytest; BEGIN mytest(5); wait; END PROCESS TESTING; END c02s01b00x00p03n01i02863arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2863.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c02s01b00x00p03n01i02863ent IS END c02s01b00x00p03n01i02863ent; ARCHITECTURE c02s01b00x00p03n01i02863arch OF c02s01b00x00p03n01i02863ent IS BEGIN TESTING: PROCESS procedure mytest (fpl:integer); procedure mytest (fpl:integer) is begin assert NOT( fpl = 5 ) report "***PASSED TEST: c02s01b00x00p03n01i02863" severity NOTE; assert ( fpl = 5 ) report "***FAILED TEST: c02s01b00x00p03n01i02863 - Subprogram syntax test failed." severity ERROR; end mytest; BEGIN mytest(5); wait; END PROCESS TESTING; END c02s01b00x00p03n01i02863arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2863.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c02s01b00x00p03n01i02863ent IS END c02s01b00x00p03n01i02863ent; ARCHITECTURE c02s01b00x00p03n01i02863arch OF c02s01b00x00p03n01i02863ent IS BEGIN TESTING: PROCESS procedure mytest (fpl:integer); procedure mytest (fpl:integer) is begin assert NOT( fpl = 5 ) report "***PASSED TEST: c02s01b00x00p03n01i02863" severity NOTE; assert ( fpl = 5 ) report "***FAILED TEST: c02s01b00x00p03n01i02863 - Subprogram syntax test failed." severity ERROR; end mytest; BEGIN mytest(5); wait; END PROCESS TESTING; END c02s01b00x00p03n01i02863arch;
--------------------------------------------------------------------- -- Simple WISHBONE interconnect -- -- Generated by wigen at 09/14/16 20:54:53 -- -- Configuration: -- Number of masters: 1 -- Number of slaves: 1 -- Master address width: 28 -- Slave address width: 8 -- Port size: 8 -- Port granularity: 8 -- Entity name: lpcbus -- Pipelined arbiter: no -- Registered feedback: no -- Unsafe slave decoder: no -- -- Command line: -- wigen -e lpcbus 1 1 28 8 8 8 --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity lpcbus is port( clk_i: in std_logic; rst_i: in std_logic; s0_cyc_i: in std_logic; s0_stb_i: in std_logic; s0_we_i: in std_logic; s0_ack_o: out std_logic; s0_adr_i: in std_logic_vector(27 downto 0); s0_dat_i: in std_logic_vector(7 downto 0); s0_dat_o: out std_logic_vector(7 downto 0); m0_cyc_o: out std_logic; m0_stb_o: out std_logic; m0_we_o: out std_logic; m0_ack_i: in std_logic; m0_adr_o: out std_logic_vector(7 downto 0); m0_dat_o: out std_logic_vector(7 downto 0); m0_dat_i: in std_logic_vector(7 downto 0) ); end entity; architecture rtl of lpcbus is signal cyc_mux: std_logic; signal stb_mux: std_logic; signal we_mux: std_logic; signal adr_mux: std_logic_vector(27 downto 0); signal wdata_mux: std_logic_vector(7 downto 0); signal ack_mux: std_logic; signal rdata_mux: std_logic_vector(7 downto 0); begin -- MASTER->SLAVE MUX cyc_mux<=s0_cyc_i; stb_mux<=s0_stb_i; we_mux<=s0_we_i; adr_mux<=s0_adr_i; wdata_mux<=s0_dat_i; -- MASTER->SLAVE DEMUX m0_cyc_o<=cyc_mux; m0_stb_o<=stb_mux; m0_we_o<=we_mux; m0_adr_o<=adr_mux(m0_adr_o'range); m0_dat_o<=wdata_mux; -- SLAVE->MASTER MUX ack_mux<=m0_ack_i; rdata_mux<=m0_dat_i; -- SLAVE->MASTER DEMUX s0_ack_o<=ack_mux; s0_dat_o<=rdata_mux; end architecture;
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:02) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; ENTITY mpegmv_asap_entity IS PORT ( reset, clk: IN std_logic; input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30); output1, output2, output3: OUT unsigned(0 TO 31)); END mpegmv_asap_entity; ARCHITECTURE mpegmv_asap_description OF mpegmv_asap_entity IS SIGNAL current_state : unsigned(0 TO 7) := "00000000"; SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register10: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register11: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register12: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register13: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register14: unsigned(0 TO 31) := "00000000000000000000000000000000"; BEGIN moore_machine: PROCESS(clk, reset) BEGIN IF reset = '0' THEN current_state <= "00000000"; ELSIF clk = '1' AND clk'event THEN IF current_state < 4 THEN current_state <= current_state + 1; END IF; END IF; END PROCESS moore_machine; operations: PROCESS(current_state) BEGIN CASE current_state IS WHEN "00000001" => register1 := input1 * 1; register2 := input2 * 2; register3 := input3 * 3; register4 := input4 * 4; register5 := input5 * 5; register6 := input6 * 6; register7 := input7 * 7; register8 := input8 * 8; register9 := input9 * 9; register10 := input10 * 10; register11 := input11 * 11; register12 := input12 * 12; register13 := input13 * 13; register14 := input14 * 14; WHEN "00000010" => register1 := register1 + 16; register6 := register6 + 18; register7 := register7 + 20; register9 := register9 + 22; register13 := register13 + 24; WHEN "00000011" => register1 := register2 + register1; register2 := register4 + register6; output1 <= register3 + register7; register3 := register8 + register9; register4 := register12 + register13; WHEN "00000100" => register1 := register14 + register1; register2 := register5 + register2; register3 := register10 + register3; register4 := register11 + register4; WHEN "00000101" => register1 := ((NOT register1) + 1) XOR register1; register4 := ((NOT register4) + 1) XOR register4; WHEN "00000110" => output2 <= register1(0 TO 15) & register3(0 TO 15); output3 <= register4(0 TO 15) & register2(0 TO 15); WHEN OTHERS => NULL; END CASE; END PROCESS operations; END mpegmv_asap_description;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:58:29 11/22/2015 -- Design Name: -- Module Name: Ultrasonic - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library work; use work.PKG_ROBOT_SUMO.all; entity Ultrasonic is Port ( in_Clk : in STD_LOGIC; --Clock in_Rst : in STD_LOGIC; in_Rx : in STD_LOGIC; --Entrada FSM out_Tx : out STD_LOGIC; in_Tin : in STD_LOGIC; out_Tin : out STD_LOGIC; --Counter end Ultrasonic; architecture Behavioral of Ultrasonic is -- Componentes del modulo -- Comp: U1 Divisor de frequencia 100/1 component Freq_Div port ( in_Rst : in STD_LOGIC; in_Clk : in STD_LOGIC; out_time_base : out STD_LOGIC); end component; -- Comp: U2 State Register for motor component State_Reg_Ultrasonic port ( in_clk : in STD_LOGIC; in_time_base : in STD_LOGIC; in_rst : in STD_LOGIC; in_next_state : in ultrasonic_state_values; in_state_duration : in integer; out_pres_state : out ultrasonic_state_values); end component; -- Comp: U3 Finite State Machine motor component FSM_Ultrasonic port ( in_pres_state : in ultrasonic_state_values; in_Rx : in integer; out_next_state: out ultrasonic_state_values; state_duration : out integer); end component; -- Comp : U4 Output component Output_Ultrasonic port ( in_pres_state : in ultrasonic_state_values; out_Tx : out STD_LOGIC); end component; -- Comp : U5 Tin_Counter component Tin_Counter port ( in_clk : in STD_LOGIC; in_time_base : in STD_LOGIC; in_rst : in STD_LOGIC; out_tin : out integer); end component; -- seniales embebidas -- 1 bit signal time_base : STD_LOGIC; -- 2 o mas bits -- of types signal pres_state, next_state: ultrasonic_state_values; -- integers signal tin : integer range 0 to ULTRASONIC_MAX; signal curr_state_duration : integer range 0 to ULTRASONIC_MAX; begin -- Instanciar componentes U4_1 : Freq_Div port map(in_rst, in_clk, time_base); U4_2 : State_Reg_Ultrasonic port map( in_clk, time_base, in_rst_U, next_state, curr_state_duration, pres_state); U4_5 : Tin_Counter port map(in_clk, time_base, in_rst, tin); U4_3 : FSM_Ultrasonic port map(pres_state,in_Rx, next_state, curr_state_duration); U4_4 : Output_motor port map(pres_state, out_Tx); end Behavioral;
--------------------------------------------------------------------------- -- keyboard_processor.vhd -- -- Sai Koppula -- -- 3-13 -- -- -- -- Purpose/Description -- -- Takes in ps2data and outputs the right make codes -- -- -- -- -- -- Final Modifications by Raj Vinjamuri and Sai Koppula -- -- -- -- -- --Updates -- -- -- -- >changed A/B_out to just A/B -- -- >condensed signals for clearer reading -- -- >changed re buses from 7 downto 0 to 10 downto 0 -- -- >changed name of data bits in for uniformity -- --------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keyboard_processor is Port ( Clk : in std_logic; --takes in modified clock Status : in std_logic_vector(1 downto 0); ps2data : in std_logic; --from keyboard Reset : in std_logic; SR_Out : out std_logic_vector(10 downto 0); --one code PR_Out : out std_logic_vector(10 downto 0) --prev code ); end keyboard_processor; architecture Behavioral of keyboard_processor is component reg_unit is Port ( Clk : in std_logic; ClrSR, ClrPR : in std_logic; D_In : in std_logic_vector(10 downto 0); SR_In : in std_logic; Ld_SR : in std_logic; Ld_PR : in std_logic; Shift_En : in std_logic; SR_out : out std_logic; PR_out : out std_logic; SR : out std_logic_vector(10 downto 0); PR : out std_logic_vector(10 downto 0)); end component reg_unit; signal ClrSR, ClrPR : std_logic; signal SR_In, Ld_SR, Ld_PR, Shift_En : std_logic; signal D_In : std_logic_vector(10 downto 0); signal nreset, data: std_logic; begin nreset <= Reset; data <= ps2data; Registers : reg_unit port map( Clk => Clk, ClrSR => ClrSR, ClrPR => ClrPR, D_In => D_In, SR_In => SR_In, Ld_SR => Ld_SR, Ld_PR => Ld_PR, Shift_En => Shift_En, SR => SR_Out, PR => PR_Out); pass_Data: process(Status, data) --shift data from prev code into another register begin if (Status = "10") then Shift_En <= '1'; else Shift_En <= '0'; end if; ClrSR <= nreset; ClrPr <= nreset; SR_In <= data; Ld_SR <= '0'; Ld_PR <= '0'; end process; end Behavioral;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity agito_registers_V_ram is generic( mem_type : string := "distributed"; dwidth : integer := 32; awidth : integer := 4; mem_size : integer := 11 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; d1 : in std_logic_vector(dwidth-1 downto 0); we1 : in std_logic; clk : in std_logic ); end entity; architecture rtl of agito_registers_V_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array := ( 0 => "00000000000000000000000000100000", 1 => "00000000000000000000000000100101", 2 to 10=> "00000000000000000000000000000000" ); attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "select_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then if (we1 = '1') then ram(CONV_INTEGER(addr1)) := d1; end if; end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity agito_registers_V is generic ( DataWidth : INTEGER := 32; AddressRange : INTEGER := 11; AddressWidth : INTEGER := 4); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; we1 : IN STD_LOGIC; d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of agito_registers_V is component agito_registers_V_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; d1 : IN STD_LOGIC_VECTOR; we1 : IN STD_LOGIC); end component; begin agito_registers_V_ram_U : component agito_registers_V_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, q0 => q0, addr1 => address1, ce1 => ce1, d1 => d1, we1 => we1); end architecture;
----------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov - sergeykhbr@gmail.com --! @brief System Top level modules and interconnect declarations. ----------------------------------------------------------------------------- --! Standard library. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library commonlib; use commonlib.types_common.all; --! Technology definition library. library techmap; use techmap.gencomp.all; --! CPU, System Bus and common peripheries library. library ambalib; use ambalib.types_amba4.all; --! @brief Declaration of components visible on SoC top level. package types_rocket is --! @name Scala inherited constants. --! @brief The following constants were define in Rocket-chip generator. --! @{ --! @brief Bits allocated for the memory tag value. --! @details This value is defined \i Config.scala and depends of others --! configuration paramters, like number of master, clients, channels --! and so on. It is not used in VHDL implemenation. constant MEM_TAG_BITS : integer := 6; --! @brief SCALA generated value. Not used in VHDL. constant MEM_ADDR_BITS : integer := 26; --! @brief Multiplexing HTIF bus data width. --! @details Not used in a case of disabled L2 cache. --! If L2 cached is enabled this value defines bitwise of the bus --! between \i Uncore module and external transievers. --! Standard message size for the HTID request is 128 bits, so this --! value defines number of beats required to transmit/recieve such --! message. constant HTIF_WIDTH : integer := 16; --! @} --! @name HostIO modules unique IDs. --! @{ --! Interrupt controller constant CFG_HTIF_SRC_IRQCTRL : integer := 0; --! Debug Support Unit (DSU) constant CFG_HTIF_SRC_DSU : integer := CFG_HTIF_SRC_IRQCTRL + 1; --! Total number of HostIO initiators. constant CFG_HTIF_SRC_TOTAL : integer := CFG_HTIF_SRC_DSU + 1; --! @} --! @name Memory Transaction types. --! @details TileLinkIO interface uses these constant to identify the payload --! size of the transaction. --! @{ constant MT_B : integer := 0; --! int8_t Memory Transaction. constant MT_H : integer := 1; --! int16_t Memory Transaction. constant MT_W : integer := 2; --! int32_t Memory Transaction. constant MT_D : integer := 3; --! int64_t Memory Transaction. constant MT_BU : integer := 4; --! uint8_t Memory Transaction. constant MT_HU : integer := 5; --! uint16_t Memory Transaction. constant MT_WU : integer := 6; --! uint32_t Memory Transaction. constant MT_Q : integer := 7; --! AXI data-width Memory Transaction (default 128-bits). --! @} --! @brief Memory operation types --! @details The union bits [5:1] contains information about current transaction constant M_XRD : std_logic_vector(4 downto 0) := "00000"; --! int load constant M_XWR : std_logic_vector(4 downto 0) := "00001"; --! int store constant M_PFR : std_logic_vector(4 downto 0) := "00010"; --! prefetch with intent to read constant M_PFW : std_logic_vector(4 downto 0) := "00011"; --! prefetch with intent to write constant M_XA_SWAP : std_logic_vector(4 downto 0) := "00100"; constant M_NOP : std_logic_vector(4 downto 0) := "00101"; constant M_XLR : std_logic_vector(4 downto 0) := "00110"; constant M_XSC : std_logic_vector(4 downto 0) := "00111"; constant M_XA_ADD : std_logic_vector(4 downto 0) := "01000"; constant M_XA_XOR : std_logic_vector(4 downto 0) := "01001"; constant M_XA_OR : std_logic_vector(4 downto 0) := "01010"; constant M_XA_AND : std_logic_vector(4 downto 0) := "01011"; constant M_XA_MIN : std_logic_vector(4 downto 0) := "01100"; constant M_XA_MAX : std_logic_vector(4 downto 0) := "01101"; constant M_XA_MINU : std_logic_vector(4 downto 0) := "01110"; constant M_XA_MAXU : std_logic_vector(4 downto 0) := "01111"; constant M_FLUSH : std_logic_vector(4 downto 0) := "10000"; --! write back dirty data and cede R/W permissions constant M_PRODUCE : std_logic_vector(4 downto 0) := "10001"; --! write back dirty data and cede W permissions constant M_CLEAN : std_logic_vector(4 downto 0) := "10011"; --! write back dirty data and retain R/W permissions function isAMO(cmd : std_logic_vector(4 downto 0)) return std_logic; --def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW --def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd) function isWrite(cmd : std_logic_vector(4 downto 0)) return std_logic; --def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR --! <tilelink.scala> Object Acquire {} constant ACQUIRE_GET_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "000"; constant ACQUIRE_GET_BLOCK_DATA : std_logic_vector(2 downto 0) := "001"; -- constant ACQUIRE_PUT_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "010"; -- Single beat data. constant ACQUIRE_PUT_BLOCK_DATA : std_logic_vector(2 downto 0) := "011"; -- For acMultibeat data. constant ACQUIRE_PUT_ATOMIC_DATA : std_logic_vector(2 downto 0) := "100"; -- Single beat data. 64 bits width constant ACQUIRE_PREFETCH_BLOCK : std_logic_vector(2 downto 0) := "101"; --! <tilelink.scala> Object Grant {} constant GRANT_ACK_RELEASE : std_logic_vector(3 downto 0) := "0000"; -- For acking Releases constant GRANT_ACK_PREFETCH : std_logic_vector(3 downto 0) := "0001"; -- For acking any kind of Prefetch constant GRANT_ACK_NON_PREFETCH_PUT : std_logic_vector(3 downto 0) := "0011"; -- For acking any kind of non-prfetch Put constant GRANT_SINGLE_BEAT_GET : std_logic_vector(3 downto 0) := "0100"; -- Supplying a single beat of Get constant GRANT_BLOCK_GET : std_logic_vector(3 downto 0) := "0101"; -- Supplying all beats of a GetBlock --! MESI coherence constant CACHED_ACQUIRE_SHARED : std_logic_vector(2 downto 0) := "000"; -- get constant CACHED_ACQUIRE_EXCLUSIVE : std_logic_vector(2 downto 0) := "001"; -- put constant CACHED_GRANT_SHARED : std_logic_vector(3 downto 0) := "0000"; constant CACHED_GRANT_EXCLUSIVE : std_logic_vector(3 downto 0) := "0001"; constant CACHED_GRANT_EXCLUSIVE_ACK : std_logic_vector(3 downto 0) := "0010"; --! @brief Memory Operation size decoder --! @details TileLink bus has encoded Memory Operation size --! in the union[8:6] bits of the acquire request. constant MEMOP_XSIZE_TOTAL : integer := 8; type memop_xsize_type is array (0 to MEMOP_XSIZE_TOTAL-1) of std_logic_vector(2 downto 0); constant opSizeToXSize : memop_xsize_type := ( MT_B => "000", MT_BU => "000", MT_H => "001", MT_HU => "001", MT_W => "010", MT_WU => "010", --! unimplemented in scala MT_D => "011", MT_Q => conv_std_logic_vector(log2(CFG_NASTI_DATA_BYTES),3) ); type tile_cached_in_type is record acquire_ready : std_logic; grant_valid : std_logic; grant_bits_addr_beat : std_logic_vector(1 downto 0); --! client's transaction id grant_bits_client_xact_id : std_logic_vector(1 downto 0); grant_bits_manager_xact_id : std_logic_vector(3 downto 0); grant_bits_is_builtin_type : std_logic; grant_bits_g_type : std_logic_vector(3 downto 0); grant_bits_data : std_logic_vector(127 downto 0); probe_valid : std_logic; probe_bits_addr_block : std_logic_vector(25 downto 0); probe_bits_p_type : std_logic_vector(1 downto 0); release_ready : std_logic; end record; type tile_cached_out_type is record acquire_valid : std_logic; acquire_bits_addr_block : std_logic_vector(25 downto 0); acquire_bits_client_xact_id : std_logic_vector(1 downto 0); acquire_bits_addr_beat : std_logic_vector(1 downto 0); acquire_bits_is_builtin_type : std_logic; acquire_bits_a_type : std_logic_vector(2 downto 0); acquire_bits_union : std_logic_vector(16 downto 0); acquire_bits_data : std_logic_vector(127 downto 0); grant_ready : std_logic; probe_ready : std_logic; release_valid : std_logic; release_bits_addr_beat : std_logic_vector(1 downto 0); release_bits_addr_block : std_logic_vector(25 downto 0); release_bits_client_xact_id : std_logic_vector(1 downto 0); release_bits_r_type : std_logic_vector(2 downto 0); release_bits_voluntary : std_logic; release_bits_data : std_logic_vector(127 downto 0); end record; --! HostIO tile input signals type host_in_type is record grant : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0); csr_req_ready : std_logic; csr_resp_valid : std_logic; csr_resp_bits : std_logic_vector(63 downto 0); debug_stats_csr : std_logic; end record; --! HostIO tile output signals type host_out_type is record reset : std_logic; id : std_logic; csr_req_valid : std_logic; csr_req_bits_rw : std_logic; csr_req_bits_addr : std_logic_vector(11 downto 0); csr_req_bits_data : std_logic_vector(63 downto 0); csr_resp_ready : std_logic; end record; --! Full stack of HostIO output signals from all devices. type host_out_vector is array (0 to CFG_HTIF_SRC_TOTAL-1) of host_out_type; --! @brief Empty output signals of HostIO interface. --! @details If device was included in the owners of the HostIO interface and --! was disabled by configuration parameter (for example) then its --! outputs must be assigned to this empty signals otherwise --! RTL simulation will fail with undefined states of the processor. constant host_out_none : host_out_type := ( '0', '0', '0', '0', (others => '0'), (others => '0'), '0'); --! @brief Decode Acquire request from the Cached/Uncached TileLink --! @param[in] a_type Request type depends of the built_in flag --! @param[in] built_in This flag defines cached or uncached request. For --! the uncached this value is set to 1. --! @param[in] u Union bits. This value is decoding depending of --! types operation (rd/wr) and cached/uncached. procedure procedureDecodeTileAcquire ( a_type : in std_logic_vector(2 downto 0); built_in : in std_logic; u : in std_logic_vector(16 downto 0); write : out std_logic; wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); axi_sz : out std_logic_vector(2 downto 0); byte_addr : out std_logic_vector(3 downto 0); beat_cnt : out integer ); --! @brief HostIO (HTIF) controller declaration. --! @details This device provides multiplexing of the Host messages --! from several sources (interrupt controller, ethernet MAC, --! Debug Support Unit and others) on HostIO bus that is --! specific for Rocket-chip implementation of RISC-V. --! @todo Make htifii as a vector to support multi-cores --! configuration. component htifctrl is port ( clk : in std_logic; nrst : in std_logic; srcsi : in host_out_vector; srcso : out host_out_type; htifii : in host_in_type; htifio : out host_in_type ); end component; --! @brief HTIF serializer input. --! @details In a case of using L2-cache, 'Uncore' module implements --! additional layer of the transformation of 128-bits HTIF --! messages into chunks of HTIF_WIDTH. So we have to --! implement the same serdes on upper level. type htif_serdes_in_type is record --! Chunk was accepted by Uncore subsytem. ready : std_logic; --! Current chunk output is valid valid : std_logic; --! Chunk bits itself. bits : std_logic_vector(HTIF_WIDTH-1 downto 0); end record; --! @brief HTIF serializer output. type htif_serdes_out_type is record valid : std_logic; bits : std_logic_vector(HTIF_WIDTH-1 downto 0); ready : std_logic; end record; --! @brief RocketTile component declaration. --! @details This module implements Risc-V Core with L1-cache, --! branch predictor and other stuffs of the RocketTile. --! @param[in] xindex1 Cached Tile AXI master index --! @param[in] xindex2 Uncached Tile AXI master index --! @param[in] rst Reset signal with active HIGH level. --! @param[in] soft_rst Software Reset via DSU --! @param[in] clk_sys System clock (BUS/CPU clock). --! @param[in] slvo Bus-to-Slave device signals. --! @param[in] msti Bus-to-Master device signals. --! @param[out] msto1 CachedTile-to-Bus request signals. --! @param[out] msto2 UncachedTile-to-Bus request signals. --! @param[in] htifoi Requests from the HostIO-connected devices. --! @param[out] htifio Response to HostIO-connected devices. component rocket_l1only is generic ( xindex1 : integer := 0; xindex2 : integer := 1 ); port ( rst : in std_logic; soft_rst : in std_logic; clk_sys : in std_logic; slvo : in nasti_slave_in_type; msti : in nasti_master_in_type; msto1 : out nasti_master_out_type; mstcfg1 : out nasti_master_config_type; msto2 : out nasti_master_out_type; mstcfg2 : out nasti_master_config_type; htifoi : in host_out_type; htifio : out host_in_type ); end component; --! @brief RocketTile + Uncore component declaration. --! @details This module implements Risc-V Core with L1-cache, --! branch predictor and other stuffs of the RocketTile. --! @param[in] xindex1 Cached Tile AXI master index --! @param[in] xindex2 Uncached Tile AXI master index --! @param[in] rst Reset signal with active HIGH level. --! @param[in] soft_rst Software Reset via DSU --! @param[in] clk_sys System clock (BUS/CPU clock). --! @param[in] slvo Bus-to-Slave device signals. --! @param[in] msti Bus-to-Master device signals. --! @param[out] msto1 CachedTile-to-Bus request signals. --! @param[out] msto2 UncachedTile-to-Bus request signals. --! @param[in] htifoi Requests from the HostIO-connected devices. --! @param[out] htifio Response to HostIO-connected devices. component rocket_l2cache is generic ( xindex1 : integer := 0; xindex2 : integer := 1 ); port ( rst : in std_logic; soft_rst : in std_logic; clk_sys : in std_logic; slvo : in nasti_slave_in_type; msti : in nasti_master_in_type; msto1 : out nasti_master_out_type; mstcfg1 : out nasti_master_config_type; msto2 : out nasti_master_out_type; mstcfg2 : out nasti_master_config_type; htifoi : in host_out_type; htifio : out host_in_type ); end component; --! @brief SOC global reset former. --! @details This module produces output reset signal in a case if --! button 'Reset' was pushed or PLL isn't a 'lock' state. --! param[in] inSysReset Button generated signal --! param[in] inSysClk Clock from the PLL. Bus clock. --! param[in] inPllLock PLL status. --! param[out] outReset Output reset signal with active 'High' (1 = reset). component reset_global port ( inSysReset : in std_ulogic; inSysClk : in std_ulogic; inPllLock : in std_ulogic; outReset : out std_ulogic ); end component; --! Boot ROM with AXI4 interface declaration. component nasti_bootrom is generic ( memtech : integer := inferred; xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; sim_hexfile : string ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i : in nasti_slave_in_type; o : out nasti_slave_out_type ); end component; --! AXI4 ROM with the default FW version declaration. component nasti_romimage is generic ( memtech : integer := inferred; xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; sim_hexfile : string ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i : in nasti_slave_in_type; o : out nasti_slave_out_type ); end component; --! Internal RAM with AXI4 interface declaration. component nasti_sram is generic ( memtech : integer := inferred; xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; abits : integer := 17; init_file : string := "" -- only for 'inferred' ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i : in nasti_slave_in_type; o : out nasti_slave_out_type ); end component; --! @brief NASTI (AXI4) GPIO controller component nasti_gpio is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff# ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i : in nasti_slave_in_type; o : out nasti_slave_out_type; i_dip : in std_logic_vector(3 downto 0); o_led : out std_logic_vector(7 downto 0) ); end component; type uart_in_type is record rd : std_ulogic; cts : std_ulogic; end record; type uart_out_type is record td : std_ulogic; rts : std_ulogic; end record; --! UART with the AXI4 interface declaration. component nasti_uart is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; fifosz : integer := 16 ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i_uart : in uart_in_type; o_uart : out uart_out_type; i_axi : in nasti_slave_in_type; o_axi : out nasti_slave_out_type; o_irq : out std_logic); end component; --! @brief Interrupt controller with the AXI4 interface declaration. --! @details To rise interrupt on certain CPU HostIO interface is used. component nasti_irqctrl is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; htif_index : integer := 0 ); port ( clk : in std_logic; nrst : in std_logic; i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 0); o_cfg : out nasti_slave_config_type; i_axi : in nasti_slave_in_type; o_axi : out nasti_slave_out_type; i_host : in host_in_type; o_host : out host_out_type ); end component; --! @brief Declaration of the Debug Support Unit with the AXI interface. --! @details This module provides access to processors CSRs via HostIO bus. component nasti_dsu is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; htif_index : integer := 0 ); port ( clk : in std_logic; nrst : in std_logic; o_cfg : out nasti_slave_config_type; i_axi : in nasti_slave_in_type; o_axi : out nasti_slave_out_type; i_host : in host_in_type; o_host : out host_out_type; o_soft_reset : out std_logic ); end component; --! @brief General Purpose Timers with the AXI interface. --! @details This module provides high precision counter and --! generic number of GP timers. component nasti_gptimers is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; tmr_total : integer := 2 ); port ( clk : in std_logic; nrst : in std_logic; cfg : out nasti_slave_config_type; i_axi : in nasti_slave_in_type; o_axi : out nasti_slave_out_type; o_irq : out std_logic ); end component; --! @brief Plug-n-Play support module with AXI4 interface declaration. --! @details Each device in a system hase to implements sideband signal --! structure 'nasti_slave_config_type' that allows FW to --! detect Hardware configuration in a run-time. --! @todo Implements PnP signals for all Masters devices. component nasti_pnp is generic ( xindex : integer := 0; xaddr : integer := 0; xmask : integer := 16#fffff#; tech : integer := 0 ); port ( sys_clk : in std_logic; adc_clk : in std_logic; nrst : in std_logic; mstcfg : in nasti_master_cfg_vector; slvcfg : in nasti_slave_cfg_vector; cfg : out nasti_slave_config_type; i : in nasti_slave_in_type; o : out nasti_slave_out_type ); end component; end; -- package declaration --! ----------------- package body types_rocket is function isAMO(cmd : std_logic_vector(4 downto 0)) return std_logic is variable t1 : std_logic; begin t1 := '0'; if cmd = M_XA_SWAP then t1 := '1'; end if; return (cmd(3) or t1); end; function isWrite(cmd : std_logic_vector(4 downto 0)) return std_logic is variable ret : std_logic; begin ret := isAMO(cmd); if cmd = M_XWR then ret := '1'; end if; if cmd = M_XSC then ret := '1'; end if; return (ret); end; --! @brief Decode Acquire request from the Cached/Uncached TileLink --! @param[in] a_type Request type depends of the built_in flag --! @param[in] built_in This flag defines cached or uncached request. For --! the uncached this value is set to 1. --! @param[in] u Union bits. This value is decoding depending of --! types operation (rd/wr) and cached/uncached. procedure procedureDecodeTileAcquire( a_type : in std_logic_vector(2 downto 0); built_in : in std_logic; u : in std_logic_vector(16 downto 0); write : out std_logic; wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); axi_sz : out std_logic_vector(2 downto 0); byte_addr : out std_logic_vector(3 downto 0); beat_cnt : out integer ) is begin if built_in = '1' then -- Cached request case a_type is when ACQUIRE_GET_SINGLE_DATA_BEAT => write := '0'; wmask := (others => '0'); byte_addr := u(12 downto 9);--tst.block.byte_addr; axi_sz := opSizeToXSize(conv_integer(u(8 downto 6))); beat_cnt := 0; when ACQUIRE_PREFETCH_BLOCK | ACQUIRE_GET_BLOCK_DATA => -- cache line size / data bits width write := '0'; wmask := (others => '0'); byte_addr := (others => '0'); axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3); beat_cnt := 3;--tlDataBeats-1; when ACQUIRE_PUT_SINGLE_DATA_BEAT => -- Single beat data. write := '1'; wmask := u(CFG_NASTI_DATA_BYTES downto 1); byte_addr := (others => '0'); axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3); beat_cnt := 0; when ACQUIRE_PUT_BLOCK_DATA => -- Multibeat data. write := '1'; wmask := (others => '1'); byte_addr := (others => '0'); axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3); beat_cnt := 3;--tlDataBeats-1; when ACQUIRE_PUT_ATOMIC_DATA => -- Single beat data. 64 bits width write := '1'; if CFG_NASTI_DATA_BITS = 128 then if u(12) = '0' then wmask(7 downto 0) := (others => '1'); wmask(15 downto 8) := (others => '0'); else wmask(7 downto 0) := (others => '0'); wmask(15 downto 8) := (others => '1'); end if; else wmask := (others => '1'); end if; byte_addr := (others => '0'); axi_sz := opSizeToXSize(conv_integer(u(8 downto 6))); beat_cnt := 0; when others => write := '0'; wmask := (others => '0'); byte_addr := (others => '0'); axi_sz := (others => '0'); beat_cnt := 0; end case; else --! built_in = '0' -- Cached request case a_type is when CACHED_ACQUIRE_SHARED => write := '0'; wmask := (others => '0'); byte_addr := u(12 downto 9);--tst.block.byte_addr; axi_sz := opSizeToXSize(conv_integer(u(8 downto 6))); beat_cnt := 0; when CACHED_ACQUIRE_EXCLUSIVE => -- Single beat data. write := '1'; wmask := u(CFG_NASTI_DATA_BYTES downto 1); byte_addr := (others => '0'); axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3); beat_cnt := 0; when others => write := '0'; wmask := (others => '0'); byte_addr := (others => '0'); axi_sz := (others => '0'); beat_cnt := 0; end case; end if; end procedure; end; -- package body
entity FIFO is generic ( G_WIDTH : integer := 256; G_DEPTH : integer := 32; prefix_GENERIC_suffix : integer := 20 ); port ( I_PORT1 : in std_logic; I_PORT2 : out std_logic ); end entity FIFO; entity FIFO is generic ( G_WIDTH : integer := 256; G_DEPTH : integer := 32; PREFIX_GENERIC_suffix : integer := 20 ); port ( I_PORT1 : in std_logic; I_PORT2 : out std_logic ); end entity FIFO; entity FIFO is generic ( G_WIDTH : integer := 256; G_DEPTH : integer := 32; prefix_GENERIC_SUFFIX : integer := 20 ); port ( I_PORT1 : in std_logic; I_PORT2 : out std_logic ); end entity FIFO; entity FIFO is generic ( G_WIDTH : integer := 256; G_DEPTH : integer := 32; PREFIX_GENERIC_SUFFIX : integer := 20 ); port ( I_PORT1 : in std_logic; I_PORT2 : out std_logic ); end entity FIFO; entity FIFO is generic(g_size : integer := 10; g_width : integer := 256; g_depth : integer := 32; prefix_generic_suffix : integer := 20 ); port ( i_port1 : in std_logic := '0'; i_port2 : out std_logic :='1' ); end entity FIFO; entity FIFO is generic(g_size : integer := 10; g_width : integer := 256; g_depth : integer := 32; PREFIX_generic_suffix : integer := 20 ); port ( i_port1 : in std_logic := '0'; i_port2 : out std_logic :='1' ); end entity FIFO; entity FIFO is generic(g_size : integer := 10; g_width : integer := 256; g_depth : integer := 32; prefix_generic_SUFFIX : integer := 20 ); port ( i_port1 : in std_logic := '0'; i_port2 : out std_logic :='1' ); end entity FIFO; entity FIFO is generic(g_size : integer := 10; g_width : integer := 256; g_depth : integer := 32; PREFIX_generic_SUFFIX : integer := 20 ); port ( i_port1 : in std_logic := '0'; i_port2 : out std_logic :='1' ); end entity FIFO;
library ieee; use ieee.std_logic_1164.all; entity inverter is port ( i: in std_logic_vector(1 downto 0); o: out std_logic_vector(1 downto 0)); end inverter; architecture inverter_beh of inverter is begin o <= not i; end architecture;
------------------------------------------------------------------------------ -- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino) -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright notice, this -- list of conditions and the following disclaimer in the documentation and/or other -- materials provided with the distribution. -- -- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. ----------------------------------------------------------------------------- -- Entity: d2prc_edac -- File: d2prc_edac.vhd -- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino) -- Contacts: pascal.trotta@polito.it www.testgroup.polito.it -- Description: dprc secded mode (see the DPR IP-core user manual for operations details). -- Last revision: 14/08/2015 ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library grlib; use grlib.amba.all; use grlib.devices.all; use grlib.DMA2AHB_Package.all; library testgrouppolito; use testgrouppolito.dprc_pkg.all; library techmap; use techmap.gencomp.all; entity d2prc_edac is generic ( technology : integer := virtex4; -- Target technology fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth port ( rstn : in std_ulogic; -- Asynchronous Reset input (active low) clkm : in std_ulogic; -- Clock input clk100 : in std_ulogic; -- 100 MHz Clock input dmai : out DMA_In_Type; -- dma signals input dmao : in DMA_Out_Type; -- dma signals output icapi : out icap_in_type; -- icap input signals icapo : in icap_out_type; -- icap output signals apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset) apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition); end d2prc_edac; architecture d2prc_edac_rtl of d2prc_edac is type icap_state is (IDLE, START, READ_LENGTH, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY, ABORT_DED); signal pstate, nstate : icap_state; type ahb_state is (IDLE_AHB, START_AHB, GRANTED, WAIT_WRITE_END, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR, SECDED_ERROR); signal present_state, next_state : ahb_state; -- fifo types type ififo_type is record wen : std_ulogic; waddress : std_logic_vector(fifo_depth downto 0); waddress_gray : std_logic_vector(fifo_depth downto 0); idata : std_logic_vector(31 downto 0); full : std_ulogic; end record; type ofifo_type is record ren : std_ulogic; raddress : std_logic_vector(fifo_depth downto 0); raddress_gray : std_logic_vector(fifo_depth downto 0); odata : std_logic_vector(31 downto 0); empty : std_ulogic; end record; -- cdc control signals for async_dprc type cdc_async is record start : std_ulogic; stop : std_ulogic; icap_errn : std_ulogic; icap_end : std_ulogic; secded_err : std_ulogic; end record; signal fifo_in, regfifo_in : ififo_type; signal fifo_out, regfifo_out : ofifo_type; signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0); signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async; type regs_ahb is record c_grant : std_logic_vector(19 downto 0); c_ready : std_logic_vector(19 downto 0); c_latency : std_logic_vector(2 downto 0); rm_reset : std_logic_vector(31 downto 0); address : std_logic_vector(31 downto 0); rst_persist : std_ulogic; end record; type regs_icap is record c_bitstream : std_logic_vector(19 downto 0); c_latency : std_logic_vector(2 downto 0); end record; signal reg, regin : regs_ahb; signal regicap, reginicap :regs_icap; signal rstact : std_ulogic; type encoded_data_buffer_in is record renable : std_logic; renable_d : std_logic; raddress : std_logic_vector(2 downto 0); raddress_d : std_logic_vector(2 downto 0); idata : std_logic_vector(31 downto 0); wenable : std_logic; waddress : std_logic_vector(2 downto 0); words_cnt : std_logic_vector(19 downto 0); end record; signal data_buf, rdata_buf : encoded_data_buffer_in; signal data_buf_odata : std_logic_vector(31 downto 0); signal secded5, r_secded5 : std_logic_vector(31 downto 0); type decoding_type is record encoded : std_logic_vector(38 downto 0); parity : std_logic_vector(6 downto 0); end record; signal dec_sig, rdec_sig : decoding_type; signal sec_cnt, rsec_cnt, rsec_cnt_ahb : std_logic_vector(19 downto 0); begin -- fixed signals dmai.Data <= (others => '0'); dmai.Beat <= HINCR; dmai.Size <= HSIZE32; dmai.Store <= '0'; --Only read transfer requests dmai.Reset <= not(rstn); dmai.Address <= reg.address; rm_reset <= reg.rm_reset; fifo_in.idata <= dmao.Data; ------------------------------- -- ahb bus clock domain ------------------------------- ahbcomb: process(raddr_sync, regfifo_in, fifo_in, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao, rsec_cnt_ahb) variable vfifo_in : ififo_type; variable vcdc_ahb : cdc_async; variable regv : regs_ahb; variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0); begin apbcontrol.timer_clear <= '0'; apbcontrol.status_clr <= '0'; dmai.Request <= '0'; dmai.Burst <= '0'; dmai.Lock <= '0'; apbcontrol.status_value(23 downto 4) <= rsec_cnt_ahb; apbcontrol.status_value(31 downto 24) <= (others=>'0'); apbcontrol.status_value(3 downto 0) <= (others=>'0'); apbcontrol.status_en <= '0'; apbcontrol.control_clr <= '0'; apbcontrol.timer_en <= '0'; rstact <= '0'; regv := reg; vcdc_ahb := rcdc_ahb; vcdc_ahb.start := '0'; vcdc_ahb.stop := '0'; -- initialize fifo signals vfifo_in.waddress := regfifo_in.waddress; vfifo_in.full := '0'; fifo_in.wen <= '0'; -- fifo full generation gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded); if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then vfifo_in.full := '1'; elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then vfifo_in.full := '1'; end if; case present_state is when IDLE_AHB => if (apbregi.control(19 downto 0)/=X"00000") then next_state <= START_AHB; apbcontrol.timer_clear <= '1'; -- clear timer register apbcontrol.status_clr <= '1'; -- clear status register regv.c_grant := apbregi.control(19 downto 0); regv.c_ready := apbregi.control(19 downto 0); regv.address := apbregi.address; vcdc_ahb.start := '1'; -- start icap write controller else next_state <= IDLE_AHB; end if; when START_AHB => if (dmao.Grant and dmao.Ready)='1' then next_state <= GRANTED; else next_state <= START_AHB; end if; dmai.Request <= '1'; -- Request data dmai.Burst <= '1'; -- Burst transfer dmai.Lock <= '1'; -- Locked transfer vcdc_ahb.start := '1'; -- start icap write controller fifo_in.wen <= dmao.Ready; when GRANTED => if (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed next_state <= WAIT_WRITE_END; elsif (vfifo_in.full='1') then next_state<=FIFO_FULL; else next_state <= GRANTED; dmai.Request <= '1'; -- Request data dmai.Burst <= '1'; -- Burst transfer dmai.Lock <= '1'; -- Locked transfer end if; fifo_in.wen <= dmao.Ready; when FIFO_FULL => if ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0')) then next_state <= GRANTED; else next_state <= FIFO_FULL; end if; fifo_in.wen <= dmao.Ready; when WAIT_WRITE_END => if (cdc_ahb.icap_end='1') then next_state <= IDLE_AHB; regv.rst_persist := '0'; apbcontrol.status_value(3 downto 0) <= "1111"; apbcontrol.status_en <= '1'; -- Write Status Register apbcontrol.control_clr <= '1'; -- Clear Control Register vfifo_in.waddress := (others=>'0'); else next_state <= WAIT_WRITE_END; end if; fifo_in.wen <= dmao.Ready; when BUS_CNTL_ERROR => next_state <= IDLE_AHB; regv.rst_persist := '1'; apbcontrol.status_value(3 downto 0) <= "0100"; apbcontrol.status_en <= '1'; -- Write Status Register apbcontrol.control_clr <= '1'; -- Clear Control Register vfifo_in.waddress := (others=>'0'); vcdc_ahb.stop := '1'; when ICAP_ERROR => next_state <= IDLE_AHB; regv.rst_persist := '1'; apbcontrol.status_value(3 downto 0) <= "1000"; apbcontrol.status_en <= '1'; -- Write Status Register apbcontrol.control_clr <= '1'; -- Clear Control Register vfifo_in.waddress := (others=>'0'); when SECDED_ERROR => next_state <= IDLE_AHB; regv.rst_persist := '1'; apbcontrol.status_value(3 downto 0) <= "0010"; apbcontrol.status_en <= '1'; -- Write Status Register apbcontrol.control_clr <= '1'; -- Clear Control Register vfifo_in.waddress := (others=>'0'); end case; if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then next_state <= ICAP_ERROR; end if; if (present_state/=IDLE_AHB) and (cdc_ahb.secded_err='1') then next_state <= SECDED_ERROR; end if; if (present_state/=IDLE_AHB) then apbcontrol.timer_en <= '1'; -- Enable timer rstact <= '1'; if dmao.Ready='1' then regv.c_ready:=regv.c_ready-1; end if; if dmao.Grant='1' then regv.c_grant:=regv.c_grant-1; regv.address:=regv.address+4; end if; end if; if (dmao.Fault or dmao.Retry)='1' then next_state <= BUS_CNTL_ERROR; vcdc_ahb.stop := '1'; end if; -- write fifo if fifo_in.wen = '1' then vfifo_in.waddress := vfifo_in.waddress +1; end if; gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray); -- latched fifo write address fifo_in.waddress <= vfifo_in.waddress; fifo_in.waddress_gray <= vfifo_in.waddress_gray; -- update fifo full fifo_in.full <= vfifo_in.full; -- reconfigurable modules synchrounous reset generation (active high) for i in 0 to 31 loop regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist)); end loop; -- registers assignment cdc_ahb.start <= vcdc_ahb.start; cdc_ahb.stop <= vcdc_ahb.stop; regin <= regv; end process; ahbreg: process(clkm,rstn) begin if rstn='0' then regfifo_in.waddress <= (others =>'0'); regfifo_in.waddress_gray <= (others =>'0'); rcdc_ahb.start <= '0'; rcdc_ahb.stop <= '0'; present_state <= IDLE_AHB; reg.rm_reset <= (others=>'0'); reg.c_grant <= (others=>'0'); reg.c_ready <= (others=>'0'); reg.c_latency <= (others=>'0'); reg.address <= (others=>'0'); reg.rst_persist <= '0'; elsif rising_edge(clkm) then regfifo_in <= fifo_in; rcdc_ahb <= cdc_ahb; present_state <= next_state; reg <= regin; end if; end process; ------------------------------- -- synchronization registers ------------------------------- -- input d is already registered in the source clock domain syn_gen0: for i in 0 to fifo_depth generate -- fifo addresses syncreg_inst0: syncreg generic map (tech => technology, stages => 2) port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i)); syncreg_inst1: syncreg generic map (tech => technology, stages => 2) port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i)); end generate; -- CDC control signals syncreg_inst2: syncreg generic map (tech => technology, stages => 2) port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn); syncreg_inst3: syncreg generic map (tech => technology, stages => 2) port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end); syncreg_inst4: syncreg generic map (tech => technology, stages => 2) port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start); syncreg_inst5: syncreg generic map (tech => technology, stages => 2) port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop); syncreg_inst6: syncreg generic map (tech => technology, stages => 2) port map(clk => clkm, d => rcdc_icap.secded_err, q => cdc_ahb.secded_err); syn_gen1: for i in 0 to 19 generate syncreg_inst1: syncreg generic map (tech => technology, stages => 2) port map(clk => clkm, d => rsec_cnt(i), q => rsec_cnt_ahb(i)); end generate; ------------------------------- -- icap clock domain ------------------------------- icapcomb: process(waddr_sync, regfifo_out, fifo_out, cdc_icap, pstate, regicap, icapo, rdata_buf, data_buf_odata, rdec_sig, r_secded5, rsec_cnt) variable vfifo_out : ofifo_type; variable vcdc_icap : cdc_async; variable vregicap : regs_icap; variable vdata_buf : encoded_data_buffer_in; variable vdec_sig : decoding_type; variable checkbits : std_logic_vector(31 downto 0); variable v_secded5 : std_logic_vector(31 downto 0); variable status : std_logic_vector(1 downto 0); variable vsec_cnt : std_logic_vector(19 downto 0); variable decoded_data : std_logic_vector(31 downto 0); begin icapi.cen <= '1'; icapi.wen <= '1'; vcdc_icap.icap_end := '0'; vcdc_icap.icap_errn := '1'; vcdc_icap.secded_err := '0'; vregicap := regicap; -- initialize buffer signals vdata_buf.renable := rdata_buf.renable; vdata_buf.renable_d := vdata_buf.renable; vdata_buf.wenable := '0'; vdata_buf.idata := fifo_out.odata; vdata_buf.raddress := rdata_buf.raddress; vdata_buf.raddress_d := vdata_buf.raddress; vdata_buf.waddress := rdata_buf.waddress; vdata_buf.words_cnt := rdata_buf.words_cnt; vdec_sig := rdec_sig; v_secded5 := r_secded5; vsec_cnt := rsec_cnt; -- initialize fifo signals vfifo_out.raddress := regfifo_out.raddress; vfifo_out.empty := '0'; vfifo_out.ren := '0'; -- fifo empty generation gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray); if (vfifo_out.raddress_gray=waddr_sync) then vfifo_out.empty := '1'; end if; case pstate is when IDLE => if (cdc_icap.start='1') then nstate <= START; else nstate <= IDLE; end if; vdata_buf.words_cnt := (others => '0'); when START => if (fifo_out.empty='0') then vfifo_out.ren := '1'; nstate <= READ_LENGTH; else nstate <= START; end if; icapi.wen <= '0'; vsec_cnt := (others=>'0'); -- reset SEC counter when READ_LENGTH => nstate <= WRITE_ICAP; -- Extract bitstream length removing out checkbits (i.e, bitstream length is represented on 20 bits, its value will be checked later) vregicap.c_bitstream := fifo_out.odata(25 downto 17)&fifo_out.odata(15 downto 9)&fifo_out.odata(7 downto 5)&fifo_out.odata(3); if (fifo_out.empty='0') then vfifo_out.ren := '1'; end if; icapi.wen <= '0'; when WRITE_ICAP => if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status nstate <= WRITE_ICAP_VERIFY; elsif (vregicap.c_bitstream=0) then nstate <= ICAP_ERROR_LATENCY; elsif (fifo_out.empty='0') then nstate <= WRITE_ICAP; vfifo_out.ren := '1'; else nstate <= WRITE_ICAP; end if; icapi.wen <= '0'; if vdata_buf.words_cnt/=x"00000" then -- do not send first word to ICAP (i.e., bitstream words count) icapi.cen <= not(rdata_buf.renable_d); end if; when WRITE_ICAP_VERIFY => if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors nstate <= ABORT; vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain elsif (vregicap.c_bitstream=0) then nstate <= ICAP_ERROR_LATENCY; elsif (fifo_out.empty='0') then nstate <= WRITE_ICAP_VERIFY; vfifo_out.ren := '1'; else nstate <= WRITE_ICAP_VERIFY; end if; icapi.wen <= '0'; if vdata_buf.words_cnt/=x"00000" then icapi.cen <= not(rdata_buf.renable_d); end if; when END_CONFIG => nstate <= IDLE; vfifo_out.raddress := (others=>'0'); vcdc_icap.icap_end := '1'; when ABORT => if (vregicap.c_latency=4) then nstate <= IDLE; vregicap.c_latency := (others=>'0'); else nstate <= ABORT; vregicap.c_latency := vregicap.c_latency+1; end if; icapi.cen <= '0'; -- continue abort sequence vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain vfifo_out.raddress := (others=>'0'); when ABORT_DED => if (vregicap.c_latency=4) then nstate <= IDLE; vregicap.c_latency := (others=>'0'); else nstate <= ABORT_DED; vregicap.c_latency := vregicap.c_latency+1; end if; icapi.cen <= '0'; -- continue abort sequence vcdc_icap.secded_err := '1'; -- uncorrectable error vfifo_out.raddress := (others=>'0'); vdata_buf.raddress := (others=>'0'); vdata_buf.waddress := (others=>'0'); vdata_buf.renable := '0'; when ICAP_ERROR_LATENCY => if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors nstate <= ABORT; vregicap.c_latency := (others=>'0'); vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain elsif (vregicap.c_latency=7) then -- to ensure that the last SECDED has been also verified nstate <= END_CONFIG; vregicap.c_latency := (others=>'0'); vcdc_icap.icap_end := '1'; else nstate <= ICAP_ERROR_LATENCY; vregicap.c_latency := vregicap.c_latency+1; end if; icapi.wen <= '0'; icapi.cen <= not(rdata_buf.renable_d); end case; if (cdc_icap.stop='1') then nstate <= ABORT; vregicap.c_latency := (others=>'0'); vfifo_out.ren := '1'; end if; -- read fifo if vfifo_out.ren = '1' then vfifo_out.raddress := vfifo_out.raddress +1; end if; if regfifo_out.ren = '1' then vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data end if; -- latched fifo read address fifo_out.raddress <= vfifo_out.raddress; fifo_out.raddress_gray <= vfifo_out.raddress_gray; -- update fifo empty fifo_out.empty <= vfifo_out.empty; cdc_icap.icap_errn <= vcdc_icap.icap_errn; cdc_icap.icap_end <= vcdc_icap.icap_end; cdc_icap.secded_err <= vcdc_icap.secded_err; reginicap <= vregicap; fifo_out.ren <= vfifo_out.ren; -- read data from FIFO and write into 4-elements RAM (the 5th element of each SECDED group is stored in a register) if (regfifo_out.ren = '1') then if (rdata_buf.waddress/="100") then vdata_buf.wenable := '1'; vdata_buf.waddress := vdata_buf.waddress + '1'; else vdata_buf.waddress := (others=>'0'); v_secded5 := fifo_out.odata; vdata_buf.renable := '1'; -- start decoding at the next cycle end if; end if; -- decoding and error correction/detection if rdata_buf.raddress="100" then vdata_buf.renable := '0'; vdata_buf.raddress := (others=>'0'); end if; if vdata_buf.renable = '1' then vdata_buf.raddress := vdata_buf.raddress + '1'; end if; if rdata_buf.renable = '1' then vdec_sig.encoded := r_secded5(to_integer(unsigned(rdata_buf.raddress_d))*8+6 downto to_integer(unsigned(rdata_buf.raddress_d))*8)&data_buf_odata; end if; parity_gen(vdec_sig.encoded,vdec_sig.parity); syndrome_gen_check(rdec_sig.encoded, rdec_sig.parity, decoded_data, status); icapi.idata <= decoded_data; if rdata_buf.renable_d='1' then if ((status="10") or ((status="01") and (vdata_buf.words_cnt=x"00000"))) then -- abort is double error or if single error on bitstream size word nstate <= ABORT_DED; elsif status="01" then vsec_cnt := rsec_cnt + '1'; end if; end if; if rdata_buf.renable_d = '1' then vdata_buf.words_cnt := vdata_buf.words_cnt + '1'; -- counts words sent to the ICAP (debug) end if; dec_sig <= vdec_sig; -- update buffer signals data_buf <= vdata_buf; secded5 <= v_secded5; sec_cnt <= vsec_cnt; end process; icapreg: process(clk100,rstn) begin if rstn='0' then regfifo_out.raddress <= (others =>'0'); regfifo_out.raddress_gray <= (others =>'0'); regfifo_out.ren <= '0'; regicap.c_bitstream <= (others =>'0'); regicap.c_latency <= (others =>'0'); rcdc_icap.start <= '0'; rcdc_icap.stop <= '0'; rcdc_icap.secded_err <= '0'; rdata_buf.raddress <= (others =>'0'); rdata_buf.raddress_d <= (others =>'0'); rdata_buf.waddress <= (others =>'0'); rdata_buf.renable <= '0'; rdata_buf.renable_d <= '0'; rdata_buf.idata <= (others =>'0'); rdata_buf.wenable <= '0'; rdata_buf.words_cnt <= (others =>'0'); rdec_sig.encoded <= (others=>'0'); rdec_sig.parity <= (others=>'0'); r_secded5 <= (others=>'0'); rsec_cnt <= (others=>'0'); elsif rising_edge(clk100) then regfifo_out <= fifo_out; pstate <= nstate; regicap <= reginicap; rcdc_icap <= cdc_icap; rdata_buf <= data_buf; rdec_sig <= dec_sig; r_secded5 <= secded5; rsec_cnt <= sec_cnt; end if; end process; ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata); ram1 : syncram_2p generic map ( tech => technology, abits => 2, dbits => 32, sepclk => 0) port map (clk100, data_buf.renable, rdata_buf.raddress(1 downto 0), data_buf_odata, clk100, data_buf.wenable, rdata_buf.waddress(1 downto 0), data_buf.idata); end d2prc_edac_rtl;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Fri Jan 13 17:31:20 2017 -- Host : KLight-PC running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.vhdl -- Design : bg_rp -- Purpose : Stub declaration of top-level module interface -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bg_rp is Port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 7 downto 0 ); dina : in STD_LOGIC_VECTOR ( 11 downto 0 ); douta : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); end bg_rp; architecture stub of bg_rp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[7:0],dina[11:0],douta[11:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4"; begin end;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Fri Jan 13 17:31:20 2017 -- Host : KLight-PC running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.vhdl -- Design : bg_rp -- Purpose : Stub declaration of top-level module interface -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bg_rp is Port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 7 downto 0 ); dina : in STD_LOGIC_VECTOR ( 11 downto 0 ); douta : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); end bg_rp; architecture stub of bg_rp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[7:0],dina[11:0],douta[11:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4"; begin end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity BusRouter is PORT( SW: IN std_logic_vector(9 downto 0); KEY: IN std_logic_vector(3 downto 0); LEDR: OUT std_logic_vector(9 downto 0) := (others => '0'); LEDG: OUT std_logic_vector(7 downto 0) := (others => '0'); CLOCK_24: IN std_logic_vector(1 downto 0); CLOCK_27: IN std_logic_vector(1 downto 0); CLOCK_50: IN std_logic; -- video VGA_R: OUT std_logic_vector(3 downto 0); VGA_G: OUT std_logic_vector(3 downto 0); VGA_B: OUT std_logic_vector(3 downto 0); VGA_VS: OUT std_logic := '0'; VGA_HS: OUT std_logic := '0'; -- SRAM SRAM_ADDR: OUT std_logic_vector(17 downto 0); SRAM_DQ: INOUT std_logic_vector(15 downto 0); SRAM_CE_N: OUT std_logic; SRAM_OE_N: OUT std_logic; SRAM_WE_N: OUT std_logic; SRAM_LB_N: OUT std_logic; SRAM_UB_N: OUT std_logic; -- SDRAM DRAM_CS_N: OUT std_logic; DRAM_WE_N: OUT std_logic; DRAM_CAS_N: OUT std_logic; DRAM_RAS_N: OUT std_logic; DRAM_ADDR: OUT std_logic_vector(11 downto 0); DRAM_BA_0: OUT std_logic; DRAM_BA_1: OUT std_logic; DRAM_CKE: OUT std_logic; DRAM_CLK: OUT std_logic; DRAM_DQ: INOUT std_logic_vector(15 downto 0); DRAM_LDQM: OUT std_logic; DRAM_UDQM: OUT std_logic; -- Flash memory FL_ADDR: OUT std_logic_vector(21 downto 0); FL_DQ: INOUT std_logic_vector(7 downto 0); FL_OE_N: OUT std_logic := '1'; FL_RST_N: OUT std_logic := '1'; FL_WE_N: OUT std_logic := '1'; -- PS2 PS2_CLK: INOUT std_logic; PS2_DAT: INOUT std_logic; -- SD card SD_MISO: IN std_logic; SD_MOSI: OUT std_logic; SD_SCLK: OUT std_logic; SD_CS: OUT std_logic; -- UART UART_RXD: IN std_logic; UART_TXD: OUT std_logic; -- audio codec I2C_SCLK: INOUT std_logic; I2C_SDAT: INOUT std_logic; AUD_ADCDAT: IN std_logic; AUD_ADCLRCK: OUT std_logic; AUD_BCLK: OUT std_logic; AUD_XCK: OUT std_logic; AUD_DACDAT: OUT std_logic; AUD_DACLRCK: OUT std_logic; -- seven segment displays HEX0: OUT std_logic_vector(6 downto 0); HEX1: OUT std_logic_vector(6 downto 0); HEX2: OUT std_logic_vector(6 downto 0); HEX3: OUT std_logic_vector(6 downto 0) ); end BusRouter; architecture behavioral of BusRouter is signal clk_cpu: std_logic; signal clk_sdram: std_logic; signal sys_reset: std_logic := '1'; -- 68k bus: system control signal bus_reset: std_logic := '1'; signal bus_clk: std_logic; -- CPU clock signal bus_halt: std_logic := '1'; signal bus_error: std_logic := '1'; -- 68k bus: data signal bus_data: std_logic_vector(15 downto 0) := (others => 'Z'); signal bus_addr: std_logic_vector(23 downto 0) := (others => '0'); -- 68k bus: bus control signal bus_as: std_logic := '1'; signal bus_rw: std_logic := '1'; -- read = 1, write = 0 signal bus_uds: std_logic := '1'; -- upper and lower byte strobes signal bus_lds: std_logic := '1'; signal bus_dtack: std_logic := '1'; -- data acknowledge, driven by peripheral -- 68k bus: bus arbitration signal bus_br: std_logic := '1'; -- assert to request bus signal bus_bg: std_logic := '1'; -- asserted when bus is free signal bus_bgack: std_logic := '1'; -- assert to acknowledge bus request -- 68k bus: interrupt control signal bus_irq: std_logic_vector(2 downto 0) := (others => '1'); -- 68k bus: processor status signal bus_fc: std_logic_vector(3 downto 0); -- 5Hz blink clock generator signal blink_clk: std_logic; -- chip selects for various HW (low active) signal cs_rom: std_logic := '1'; signal cs_ram: std_logic := '1'; signal cs_video: std_logic := '1'; begin -- VDP u_VideoController: entity work.VideoController(behavioral) port map( reset => sys_reset, In_Clk_24 => CLOCK_24(0), Out_R => VGA_R, Out_G => VGA_G, Out_B => VGA_B, Out_HSync => VGA_HS, Out_VSync => VGA_VS, SRAM_Addr => SRAM_ADDR, SRAM_Data => SRAM_DQ, SRAM_CE => SRAM_CE_N, SRAM_OE => SRAM_OE_N, SRAM_WE => SRAM_WE_N, SRAM_LB => SRAM_LB_N, SRAM_UB => SRAM_UB_N, -- bus interface bus_clk => bus_clk, bus_data => bus_data, bus_address => bus_addr(18 downto 0), bus_rw => bus_rw, bus_as => bus_as, bus_dtack => bus_dtack, bus_uds => bus_uds, bus_lds => bus_lds, bus_cs => cs_video ); -- SDRAM controller u_sdram: entity work.BusSDRAM(behavioral) port map( reset => sys_reset, reset_n => bus_reset, sdram_clk => clk_sdram, bus_cs => cs_ram, bus_clk => clk_cpu, bus_address => bus_addr (22 downto 0), bus_data => bus_data, bus_rw => bus_rw, bus_as => bus_as, bus_dtack => bus_dtack, bus_uds => bus_uds, bus_lds => bus_lds, DRAM_CS_N => DRAM_CS_N, DRAM_WE_N => DRAM_WE_N, DRAM_CAS_N => DRAM_CAS_N, DRAM_RAS_N => DRAM_RAS_N, DRAM_ADDR => DRAM_ADDR, DRAM_BA_0 => DRAM_BA_0, DRAM_BA_1 => DRAM_BA_1, DRAM_CKE => DRAM_CKE, DRAM_CLK => DRAM_CLK, DRAM_DQ => DRAM_DQ, DRAM_LDQM => DRAM_LDQM, DRAM_UDQM => DRAM_UDQM ); -- bus PLL u_buspll: entity work.BusPLL(SYN) port map( areset => sys_reset, inclk0 => CLOCK_50, c0 => clk_cpu, c1 => clk_sdram ); -- debug monitor u_monitor: entity work.BusMonitor(behavioral) port map( clk_cpu => clk_cpu, blink_clk => blink_clk, sys_reset => sys_reset, bus_reset => bus_reset, bus_clk => bus_clk, bus_halt => bus_halt, bus_error => bus_error, bus_data => bus_data, bus_addr => bus_addr, bus_as => bus_as, bus_rw => bus_rw, bus_uds => bus_uds, bus_lds => bus_lds, bus_dtack => bus_dtack, bus_br => bus_br, bus_bg => bus_bg, bus_bgack => bus_bgack, bus_irq => bus_irq, HEX0 => HEX0, HEX1 => HEX1, HEX2 => HEX2, HEX3 => HEX3, SW => SW, KEY => KEY, LEDR => LEDR, LEDG => LEDG ); -- Address decoder: tied to the FALLING edge of bus_clk process (bus_clk, sys_reset, bus_as) begin -- if reset, make sure everything is deselected if sys_reset='1' then -- decode address elsif falling_edge(bus_clk) then -- is the address on the bus valid? if bus_as='0' then -- decode high nybble case bus_addr(23 downto 20) is when x"0" => cs_rom <= '0'; when x"1" => cs_ram <= '0'; when x"2" => cs_ram <= '0'; when x"3" => cs_ram <= '0'; when x"4" => cs_ram <= '0'; when x"5" => cs_ram <= '0'; when x"6" => cs_ram <= '0'; when x"7" => cs_ram <= '0'; when x"8" => cs_ram <= '0'; when x"9" => -- video controller cs_video <= '0'; when x"A" => when x"B" => when x"C" => when x"D" => when x"E" => when x"F" => end case; else -- address invalid cs_rom <= '1'; cs_ram <= '1'; cs_video <= '1'; end if; end if; end process; -- LED blink clock generator process (clk_cpu, sys_reset) variable cnt: integer := 0; begin if sys_reset='1' then cnt := 0; elsif rising_edge(clk_cpu) then if cnt = 741337 then blink_clk <= NOT blink_clk; cnt := 0; else cnt := cnt + 1; end if; end if; end process; -- reset logic bus_reset <= NOT sys_reset; end behavioral;
-------------------------------------------------------------------------------- -- Title : ModelSim library for Riviera-PRO -- Project : -------------------------------------------------------------------------------- -- File : modelsim_lib.vhd -- Author : M. Henze -- Email : -- Organization: MEN Mikro Elektronik Nuremberg GmbH -- Created : -------------------------------------------------------------------------------- -- Simulator : Riviera-PRO -- Synthesis : -------------------------------------------------------------------------------- -- Description : -- CAUTION - this file shall not be used for new designs. It is only kept -- for compliance with old designs. -- For new designs use VHDL2008 syntax instead. -- -------------------------------------------------------------------------------- -- Hierarchy : -------------------------------------------------------------------------------- -- Copyright (C) 2016, MEN Mikro Elektronik Nuremberg GmbH -- -- All rights reserved. Reproduction in whole or part is -- prohibited without the written permission of the -- copyright owner. -------------------------------------------------------------------------------- LIBRARY aldec; USE aldec.signal_agent_pkg.ALL; USE aldec.aldec_tools.ALL; ---------------------------------------- -- CAUTION! Don't use for new designs! -- Use VHDL2008 instead! ---------------------------------------- PACKAGE util IS TYPE force_type IS (default, deposit, drive, freeze); type del_mode is (MTI_INERTIAL, MTI_TRANSPORT); PROCEDURE init_signal_spy( source : IN string; destination : IN string; verbose : IN integer; control : IN integer); procedure init_signal_spy( source : in string; dest : in string ); PROCEDURE signal_force( destination : IN string; value : IN string; rel_time : IN time; forcetype : IN force_type; cancel_period : IN time; verbose : IN integer); PROCEDURE signal_release( destination : IN string; verbose : IN integer); procedure init_signal_driver( src_obj : in string; dest_obj : in string; delay : in time; delay_type : in del_mode; verbose : in integer ); END; PACKAGE BODY util IS PROCEDURE init_signal_spy( source : IN string; destination : IN string; verbose : IN integer; control : IN integer) IS BEGIN signal_agent(source, destination ,verbose); END PROCEDURE init_signal_spy; procedure init_signal_spy( source : in string; dest : in string ) is begin signal_agent(source,dest,0); end procedure init_signal_spy; PROCEDURE signal_force( destination : IN string; value : IN string; rel_time : IN time; forcetype : IN force_type; cancel_period : IN time; verbose : IN integer) IS BEGIN ------------------------------------------------ -- in RivieraPRO2014 the force command changed ------------------------------------------------ --force(force_type'image(forcetype), destination, value); force_signal(force_type'image(forcetype), destination, value); END PROCEDURE signal_force; PROCEDURE signal_release( destination : IN string; verbose : IN integer) IS BEGIN ------------------------------------------------ -- in RivieraPRO2014 the force command changed ------------------------------------------------ --noforce ( destination ); noforce_signal ( destination ); END PROCEDURE signal_release; procedure init_signal_driver( src_obj : in string; dest_obj : in string; delay : in time; delay_type : in del_mode; verbose : in integer ) is begin signal_agent(src_obj, dest_obj, 0); end procedure init_signal_driver; END;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.AbstractMmPkg.all; entity testbench is end entity testbench; architecture TB of testbench is signal AWADDR : std_logic_vector(6 downto 0); signal AWPROT : std_logic_vector(2 downto 0); signal AWVALID : std_logic; signal AWREADY : std_logic; signal WDATA : std_logic_vector(31 downto 0); signal WSTRB : std_logic_vector(3 downto 0); signal WVALID : std_logic; signal WREADY : std_logic; signal BRESP : std_logic_vector(1 downto 0); signal BVALID : std_logic; signal BREADY : std_logic; signal ARADDR : std_logic_vector(6 downto 0); signal ARPROT : std_logic_vector(2 downto 0); signal ARVALID : std_logic; signal ARREADY : std_logic; signal RDATA : std_logic_vector(31 downto 0); signal RRESP : std_logic_vector(1 downto 0); signal RVALID : std_logic; signal RREADY : std_logic; signal ACLK : std_logic; signal ARESETn : std_logic; signal rec : AbstractMmRecType( writedata(31 downto 0), readdata(31 downto 0), address(4 downto 0), byteen(3 downto 0) ); begin BFM: entity work.axi_master generic map ( DATAWIDTH => 32, ADDRWIDTH => AWADDR'length ) port map( -- AXI interface, AWADDR => AWADDR, AWPROT => AWPROT, AWVALID => AWVALID, AWREADY => AWREADY, WDATA => WDATA, WSTRB => WSTRB, WVALID => WVALID, WREADY => WREADY, BRESP => BRESP, BVALID => BVALID, BREADY => BREADY, ARADDR => ARADDR, ARPROT => ARPROT, ARVALID => ARVALID, ARREADY => ARREADY, RDATA => RDATA, RRESP => RRESP, RVALID => RVALID, RREADY => RREADY, ACLK => ACLK, ARESETn => ARESETn, -- AMR interface amr => rec ); end architecture TB;
-------------------------------------------------------------------------------- -- File Name: conversions.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- This package was originally written by SEVA Technologies, Inc. and donated -- to the FMF. -- www.seva.com -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file -- V1.1 R. Munden 98 NOV 28 Corrected some comments -- Corrected function b -- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values -- and combined into a single file -- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int -- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function -- int_to_slv -- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str -- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0 -- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in -- function int_to_slv) from > to >= -- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -------------------------------------------------------------------------------- -- CONVERSION FUNCTION SELECTION TABLES -------------------------------------------------------------------------------- -- -- FROM TO: std_logic_vector std_logic natural time string -- -----------------|---------------|---------|---------|---------|----------- -- std_logic_vector | N/A | N/A | to_nat | combine | see below -- std_logic | N/A | N/A | to_nat | combine | see below -- natural | to_slv | to_sl | N/A | to_time | see below -- integer | to_slv | N/A | N/A | N/A | N/A -- time | N/A | N/A | to_nat | N/A | to_time_str -- hex string | h | N/A | h | combine | N/A -- decimal string | d | N/A | d | combine | N/A -- octal string | o | N/A | o | combine | N/A -- binary string | b | N/A | b | combine | N/A -- -----------------|---------------|---------|---------|---------|----------- -- -- FROM TO: hex string decimal string octal string binary string -- -----------------|------------|-------------|------------|---------------- -- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str -- std_logic | N/A | N/A | N/A | to_bin_str -- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str -- -----------------|------------|-------------|------------|---------------- -- -- FROM TO: integer -- -----------------|---------------| -- std_logic_vector | to_int | -------------------------------------------------------------------------------- PACKAGE conversion IS ---------------------------------------------------------------------------- -- the conversions in this package are not intended to be synthesizable. -- -- others functions available -- fill creates a variable length string of the fill character -- -- -- -- input parameters of type natural or integer can be in the form: -- normal -> 8, 99, 4_237 -- base#value# -> 2#0101#, 16#fa4C#, 8#6_734# -- with exponents(x10) -> 8e4, 16#2e#E4 -- -- input parameters of type string can be in the form: -- "99", "4_237", "0101", "1010_1010" -- -- for bit/bit_vector <-> std_logic/std_logic_vector conversions use -- package std_logic_1164 -- to_bit(std_logic) -- to_bitvector(std_logic_vector) -- to_stdlogic(bit) -- to_stdlogicvector(bit_vector) -- -- for "synthesizable" signed/unsigned/std_logic_vector/integer -- conversions use -- package std_logic_arith -- conv_integer(signed/unsigned) -- conv_unsigned(integer/signed,size) -- conv_signed(integer/unsigned,size) -- conv_std_logic_vector(integer/signed/unsigned,size) -- -- for "synthesizable" std_logic_vector -> integer conversions use -- package std_logic_unsigned/std_logic_signed -- <these packages are mutually exclusive> -- conv_integer(std_logic_vector) -- <except for this conversion, these packages are unnecessary) -- to minimize compile problems write: -- use std_logic_unsigned.conv_integer; -- use std_logic_signed.conv_integer; -- -- std_logic_vector, signed and unsigned types are "closely related" -- no type conversion functions are needed, use type casting or qualified -- expressions -- -- type1(object of type2) <type casting> -- type1'(expression of type2) <qualified expression> -- -- most conversions have 4 parmeters: -- x : value to be converted -- rtn_len : size of the return value -- justify : justify value 'left' or 'right', default is right -- basespec : print the base of the value - 'yes'/'no', default is yes -- -- Typical ways to call these functions: -- simple, all defaults used -- to_bin_str(x) -- x will be converted to a string of minimum size with a -- base specification appended for clarity -- if x is 10101 then return is b"10101" -- -- to control size of return string -- to_hex_str(x, -- 6) -- length of string returned will be 6 characters -- value will be right justified in the field -- if x is 10101 then return is ....h"15" -- where '.' represents a blank -- if 'rtn_len' parm defaults or is set to 0 then -- return string will always be minimum size -- -- to left justify and suppress base specification -- to_int_str(x, -- 6, -- justify => left, -- basespec => yes) -- length of return string will be 6 characters -- the base specification will be suppressed -- if x is 10101 then return is 21.... -- where '.' represents a blank -- -- other usage notes -- -- if rtn_len less than or equal to x'length then ignore -- rtn_len and return string of x'length -- the 'justify' parm is effectively ignored in this case -- -- if rtn_len greater than x'length then return string -- of rtn_len with blanks based on 'justify' parm -- -- these routines do not handle negative numbers ---------------------------------------------------------------------------- type justify_side is (left, right); type b_spec is (no , yes); -- std_logic_vector to binary string function to_bin_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- std_logic to binary string function to_bin_str(x : std_logic; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- natural to binary string function to_bin_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- see note above regarding possible formats for x -- std_logic_vector to hex string function to_hex_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- natural to hex string function to_hex_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- see note above regarding possible formats for x -- std_logic_vector to octal string function to_oct_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- natural to octal string function to_oct_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- see note above regarding possible formats for x -- natural to integer string function to_int_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- see note above regarding possible formats for x -- std_logic_vector to integer string function to_int_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string; -- time to string function to_time_str (x : time) return string; -- add characters to a string function fill (fill_char : character := '*'; rtn_len : integer := 1) return string; -- usage: -- fill -- returns * -- fill(' ',10) -- returns .......... when '.' represents a blank -- fill(lf) or fill(ht) -- returns line feed character or tab character respectively -- std_logic_vector to natural function to_nat (x : std_logic_vector) return natural; -- std_logic to natural function to_nat (x : std_logic) return natural; -- time to natural function to_nat (x : time) return natural; -- hex string to std_logic_vector function h (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than x'length*4, result will be truncated on the left -- if x is other than characters 0 to 9 or a,A to f,F -- or x,X,z,Z,u,U,-,w,W, result will be 0 -- decimal string to std_logic_vector function d (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than x'length*4, result will be truncated on the left -- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W, -- result will be 0 -- octal string to std_logic_vector function o (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than x'length*4, result will be truncated on the left -- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W, -- result will be 0 -- binary string to std_logic_vector function b (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than x'length*4, result will be truncated on the left -- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W, -- result will be 0 -- hex string to natural function h (x : string) return natural; -- if x is other than characters 0 to 9 or a,A to f,F, result will be 0 -- decimal string to natural function d (x : string) return natural; -- if x is other than characters 0 to 9, result will be 0 -- octal string to natural function o (x : string) return natural; -- if x is other than characters 0 to 7, result will be 0 -- binary string to natural function b (x : string) return natural; -- if x is other than characters 0 to 1, result will be 0 -- natural to std_logic_vector function to_slv (x : natural; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than sizeof(x), result will be truncated on the left -- see note above regarding possible formats for x -- integer to std_logic_vector function int_to_slv (x : integer; rtn_len : positive range 1 to 32 := 32) return std_logic_vector; -- if rtn_len is < than sizeof(x), result will be truncated on the left -- see note above regarding possible formats for x -- natural to std_logic function to_sl (x : natural) return std_logic; -- natural to time function to_time (x : natural) return time; -- see note above regarding possible formats for x -- std_logic_vector to integer function to_int (x : std_logic_vector) return integer; END conversion; -- -------------------------------------------------------------------------------- -- PACKAGE BODY conversion IS -- private declarations for this package type basetype is (binary, octal, decimal, hex); function max(x,y: integer) return integer is begin if x > y then return x; else return y; end if; end max; function min(x,y: integer) return integer is begin if x < y then return x; else return y; end if; end min; -- consider function sizeof for string/slv/???, return natural -- function size(len: natural) return natural is -- begin -- if len=0 then -- return 31; -- else return len; -- end if; -- end size; function nextmultof (x : positive; size : positive) return positive is begin case x mod size is when 0 => return size * x/size; when others => return size * (x/size + 1); end case; end nextmultof; function rtn_base (base : basetype) return character is begin case base is when binary => return 'b'; when octal => return 'o'; when decimal => return 'd'; when hex => return 'h'; end case; end rtn_base; function format (r : string; base : basetype; rtn_len : natural ; justify : justify_side; basespec : b_spec) return string is variable int_rtn_len : integer; begin if basespec=yes then int_rtn_len := rtn_len - 3; else int_rtn_len := rtn_len; end if; if int_rtn_len <= r'length then case basespec is when no => return r ; when yes => return rtn_base(base) & '"' & r & '"'; end case; else case justify is when left => case basespec is when no => return r & fill(' ',int_rtn_len - r'length); when yes => return rtn_base(base) & '"' & r & '"' & fill(' ',int_rtn_len - r'length); end case; when right => case basespec is when no => return fill(' ',int_rtn_len - r'length) & r ; when yes => return fill(' ',int_rtn_len - r'length) & rtn_base(base) & '"' & r & '"'; end case; end case; end if; end format; -- convert numeric string of any base to natural function cnvt_base (x : string; inbase : natural range 2 to 16) return natural is -- assumes x is an unsigned number string of base 'inbase' -- values larger than natural'high are not supported variable r,t : natural := 0; variable place : positive := 1; begin for i in x'reverse_range loop case x(i) is when '0' => t := 0; when '1' => t := 1; when '2' => t := 2; when '3' => t := 3; when '4' => t := 4; when '5' => t := 5; when '6' => t := 6; when '7' => t := 7; when '8' => t := 8; when '9' => t := 9; when 'a'|'A' => t := 10; when 'b'|'B' => t := 11; when 'c'|'C' => t := 12; when 'd'|'D' => t := 13; when 'e'|'E' => t := 14; when 'f'|'F' => t := 15; when '_' => t := 0; -- ignore these characters place := place / inbase; when others => assert false report lf & "CNVT_BASE found input value larger than base: " & lf & "Input value: " & x(i) & " Base: " & to_int_str(inbase) & lf & "converting input to integer 0" severity warning; return 0; end case; if t / inbase > 1 then -- invalid value for base assert false report lf & "CNVT_BASE found input value larger than base: " & lf & "Input value: " & x(i) & " Base: " & to_int_str(inbase) & lf & "converting input to integer 0" severity warning; return 0; else r := r + (t * place); place := place * inbase; end if; end loop; return r; end cnvt_base; function extend (x : std_logic; len : positive) return std_logic_vector is variable v : std_logic_vector(1 to len) := (others => x); begin return v; end extend; -- implementation of public declarations function to_bin_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable int : std_logic_vector(1 to x'length):=x; variable r : string(1 to x'length):=(others=>'$'); begin for i in int'range loop r(i to i) := to_bin_str(int(i),basespec=>no); end loop; return format (r,binary,rtn_len,justify,basespec); end to_bin_str; function to_bin_str(x : std_logic; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable r : string(1 to 1); begin case x is when '0' => r(1) := '0'; when '1' => r(1) := '1'; when 'U' => r(1) := 'U'; when 'X' => r(1) := 'X'; when 'Z' => r(1) := 'Z'; when 'W' => r(1) := 'W'; when 'H' => r(1) := 'H'; when 'L' => r(1) := 'L'; when '-' => r(1) := '-'; end case; return format (r,binary,rtn_len,justify,basespec); end to_bin_str; function to_bin_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable int : natural := x; variable ptr : positive range 2 to 32 := 32; variable r : string(2 to 32):=(others=>'$'); begin if int = 0 then return format ("0",binary,rtn_len,justify,basespec); end if; while int > 0 loop case int rem 2 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when others => assert false report lf & "TO_BIN_STR, shouldn't happen" severity failure; return "$"; null; end case; int := int / 2; ptr := ptr - 1; end loop; return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec); end to_bin_str; function to_hex_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is -- will return x'length/4 variable nxt : positive := nextmultof(x'length,4); variable int : std_logic_vector(1 to nxt):= (others => '0'); variable ptr : positive range 1 to (nxt/4)+1 := 1; variable r : string(1 to nxt/4):=(others=>'$'); subtype slv4 is std_logic_vector(1 to 4); variable slv4_val : slv4; begin int(nxt-x'length+1 to nxt) := x; if nxt-x'length > 0 and x(x'left) /= '1' then int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length); end if; for i in int'range loop next when i rem 4 /= 1; slv4_val := int(i to i+3); case slv4_val is when "0000" => r(ptr) := '0'; when "0001" => r(ptr) := '1'; when "0010" => r(ptr) := '2'; when "0011" => r(ptr) := '3'; when "0100" => r(ptr) := '4'; when "0101" => r(ptr) := '5'; when "0110" => r(ptr) := '6'; when "0111" => r(ptr) := '7'; when "1000" => r(ptr) := '8'; when "1001" => r(ptr) := '9'; when "1010" => r(ptr) := 'A'; when "1011" => r(ptr) := 'B'; when "1100" => r(ptr) := 'C'; when "1101" => r(ptr) := 'D'; when "1110" => r(ptr) := 'E'; when "1111" => r(ptr) := 'F'; when "ZZZZ" => r(ptr) := 'Z'; when "WWWW" => r(ptr) := 'W'; when "LLLL" => r(ptr) := 'L'; when "HHHH" => r(ptr) := 'H'; when "UUUU" => r(ptr) := 'U'; when "XXXX" => r(ptr) := 'X'; when "----" => r(ptr) := '-'; when others => assert false report lf & "TO_HEX_STR found illegal value: " & to_bin_str(int(i to i+3)) & lf & "converting input to '-'" severity warning; r(ptr) := '-'; end case; ptr := ptr + 1; end loop; return format (r,hex,rtn_len,justify,basespec); end to_hex_str; function to_hex_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable int : natural := x; variable ptr : positive range 1 to 20 := 20; variable r : string(1 to 20):=(others=>'$'); begin if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if; while int > 0 loop case int rem 16 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when 2 => r(ptr) := '2'; when 3 => r(ptr) := '3'; when 4 => r(ptr) := '4'; when 5 => r(ptr) := '5'; when 6 => r(ptr) := '6'; when 7 => r(ptr) := '7'; when 8 => r(ptr) := '8'; when 9 => r(ptr) := '9'; when 10 => r(ptr) := 'A'; when 11 => r(ptr) := 'B'; when 12 => r(ptr) := 'C'; when 13 => r(ptr) := 'D'; when 14 => r(ptr) := 'E'; when 15 => r(ptr) := 'F'; when others => assert false report lf & "TO_HEX_STR, shouldn't happen" severity failure; return "$"; end case; int := int / 16; ptr := ptr - 1; end loop; return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec); end to_hex_str; function to_oct_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is -- will return x'length/3 variable nxt : positive := nextmultof(x'length,3); variable int : std_logic_vector(1 to nxt):= (others => '0'); variable ptr : positive range 1 to (nxt/3)+1 := 1; variable r : string(1 to nxt/3):=(others=>'$'); subtype slv3 is std_logic_vector(1 to 3); begin int(nxt-x'length+1 to nxt) := x; if nxt-x'length > 0 and x(x'left) /= '1' then int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length); end if; for i in int'range loop next when i rem 3 /= 1; case slv3'(int(i to i+2)) is when "000" => r(ptr) := '0'; when "001" => r(ptr) := '1'; when "010" => r(ptr) := '2'; when "011" => r(ptr) := '3'; when "100" => r(ptr) := '4'; when "101" => r(ptr) := '5'; when "110" => r(ptr) := '6'; when "111" => r(ptr) := '7'; when "ZZZ" => r(ptr) := 'Z'; when "WWW" => r(ptr) := 'W'; when "LLL" => r(ptr) := 'L'; when "HHH" => r(ptr) := 'H'; when "UUU" => r(ptr) := 'U'; when "XXX" => r(ptr) := 'X'; when "---" => r(ptr) := '-'; when others => assert false report lf & "TO_OCT_STR found illegal value: " & to_bin_str(int(i to i+2)) & lf & "converting input to '-'" severity warning; r(ptr) := '-'; end case; ptr := ptr + 1; end loop; return format (r,octal,rtn_len,justify,basespec); end to_oct_str; function to_oct_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable int : natural := x; variable ptr : positive range 1 to 20 := 20; variable r : string(1 to 20):=(others=>'$'); begin if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if; while int > 0 loop case int rem 8 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when 2 => r(ptr) := '2'; when 3 => r(ptr) := '3'; when 4 => r(ptr) := '4'; when 5 => r(ptr) := '5'; when 6 => r(ptr) := '6'; when 7 => r(ptr) := '7'; when others => assert false report lf & "TO_OCT_STR, shouldn't happen" severity failure; return "$"; end case; int := int / 8; ptr := ptr - 1; end loop; return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec); end to_oct_str; function to_int_str(x : natural; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is variable int : natural := x; variable ptr : positive range 1 to 32 := 32; variable r : string(1 to 32):=(others=>'$'); begin if x=0 then return format ("0",decimal,rtn_len,justify,basespec); else while int > 0 loop case int rem 10 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when 2 => r(ptr) := '2'; when 3 => r(ptr) := '3'; when 4 => r(ptr) := '4'; when 5 => r(ptr) := '5'; when 6 => r(ptr) := '6'; when 7 => r(ptr) := '7'; when 8 => r(ptr) := '8'; when 9 => r(ptr) := '9'; when others => assert false report lf & "TO_INT_STR, shouldn't happen" severity failure; return "$"; end case; int := int / 10; ptr := ptr - 1; end loop; return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec); end if; end to_int_str; function to_int_str(x : std_logic_vector; rtn_len : natural := 0; justify : justify_side := right; basespec : b_spec := yes) return string is begin return to_int_str(to_nat(x),rtn_len,justify,basespec); end to_int_str; function to_time_str (x : time) return string is begin return to_int_str(to_nat(x),basespec=>no) & " ns"; end to_time_str; function fill (fill_char : character := '*'; rtn_len : integer := 1) return string is variable r : string(1 to max(rtn_len,1)) := (others => fill_char); variable len : integer; begin if rtn_len < 2 then -- always returns at least 1 fill char len := 1; else len := rtn_len; end if; return r(1 to len); end fill; function to_nat(x : std_logic_vector) return natural is -- assumes x is an unsigned number, lsb on right, -- more than 31 bits are truncated on left variable t : std_logic_vector(1 to x'length) := x; variable int : std_logic_vector(1 to 31) := (others => '0'); variable r : natural := 0; variable place : positive := 1; begin if x'length < 32 then int(max(32-x'length,1) to 31) := t(1 to x'length); else -- x'length >= 32 int(1 to 31) := t(x'length-30 to x'length); end if; for i in int'reverse_range loop case int(i) is when '1' | 'H' => r := r + place; when '0' | 'L' => null; when others => assert false report lf & "TO_NAT found illegal value: " & to_bin_str(int(i)) & lf & "converting input to integer 0" severity warning; return 0; end case; exit when i=1; place := place * 2; end loop; return r; end to_nat; function to_nat (x : std_logic) return natural is begin case x is when '0' => return 0 ; when '1' => return 1 ; when others => assert false report lf & "TO_NAT found illegal value: " & to_bin_str(x) & lf & "converting input to integer 0" severity warning; return 0; end case; end to_nat; function to_nat (x : time) return natural is begin return x / 1 ns; end to_nat; function h(x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than x'length*4, result will be truncated on the left -- if x is other than characters 0 to 9 or a,A to f,F or -- x,X,z,Z,u,U,-,w,W, -- those result bits will be set to 0 variable int : string(1 to x'length) := x; variable size: positive := max(x'length*4,rtn_len); variable ptr : integer range -3 to size := size; variable r : std_logic_vector(1 to size) := (others=>'0'); begin for i in int'reverse_range loop case int(i) is when '0' => r(ptr-3 to ptr) := "0000"; when '1' => r(ptr-3 to ptr) := "0001"; when '2' => r(ptr-3 to ptr) := "0010"; when '3' => r(ptr-3 to ptr) := "0011"; when '4' => r(ptr-3 to ptr) := "0100"; when '5' => r(ptr-3 to ptr) := "0101"; when '6' => r(ptr-3 to ptr) := "0110"; when '7' => r(ptr-3 to ptr) := "0111"; when '8' => r(ptr-3 to ptr) := "1000"; when '9' => r(ptr-3 to ptr) := "1001"; when 'a'|'A' => r(ptr-3 to ptr) := "1010"; when 'b'|'B' => r(ptr-3 to ptr) := "1011"; when 'c'|'C' => r(ptr-3 to ptr) := "1100"; when 'd'|'D' => r(ptr-3 to ptr) := "1101"; when 'e'|'E' => r(ptr-3 to ptr) := "1110"; when 'f'|'F' => r(ptr-3 to ptr) := "1111"; when 'U' => r(ptr-3 to ptr) := "UUUU"; when 'X' => r(ptr-3 to ptr) := "XXXX"; when 'Z' => r(ptr-3 to ptr) := "ZZZZ"; when 'W' => r(ptr-3 to ptr) := "WWWW"; when 'H' => r(ptr-3 to ptr) := "HHHH"; when 'L' => r(ptr-3 to ptr) := "LLLL"; when '-' => r(ptr-3 to ptr) := "----"; when '_' => ptr := ptr + 4; when others => assert false report lf & "O conversion found illegal input character: " & int(i) & lf & "converting character to '----'" severity warning; r(ptr-3 to ptr) := "----"; end case; ptr := ptr - 4; end loop; return r(size-rtn_len+1 to size); end h; function d (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than binary length of x, result will be truncated on -- the left -- if x is other than characters 0 to 9, result will be 0 begin return to_slv(cnvt_base(x,10),rtn_len); end d; function o (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than x'length*3, result will be truncated on the left -- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W, -- those result bits will be set to 0 variable int : string(1 to x'length) := x; variable size: positive := max(x'length*3,rtn_len); variable ptr : integer range -2 to size := size; variable r : std_logic_vector(1 to size) := (others=>'0'); begin for i in int'reverse_range loop case int(i) is when '0' => r(ptr-2 to ptr) := "000"; when '1' => r(ptr-2 to ptr) := "001"; when '2' => r(ptr-2 to ptr) := "010"; when '3' => r(ptr-2 to ptr) := "011"; when '4' => r(ptr-2 to ptr) := "100"; when '5' => r(ptr-2 to ptr) := "101"; when '6' => r(ptr-2 to ptr) := "110"; when '7' => r(ptr-2 to ptr) := "111"; when 'U' => r(ptr-2 to ptr) := "UUU"; when 'X' => r(ptr-2 to ptr) := "XXX"; when 'Z' => r(ptr-2 to ptr) := "ZZZ"; when 'W' => r(ptr-2 to ptr) := "WWW"; when 'H' => r(ptr-2 to ptr) := "HHH"; when 'L' => r(ptr-2 to ptr) := "LLL"; when '-' => r(ptr-2 to ptr) := "---"; when '_' => ptr := ptr + 3; when others => assert false report lf & "O conversion found illegal input character: " & int(i) & lf & "converting character to '---'" severity warning; r(ptr-2 to ptr) := "---"; end case; ptr := ptr - 3; end loop; return r(size-rtn_len+1 to size); end o; function b (x : string; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than x'length, result will be truncated on the left -- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W, -- those result bits will be set to 0 variable int : string(1 to x'length) := x; variable size: positive := max(x'length,rtn_len); variable ptr : integer range 0 to size+1 := size; -- csa variable r : std_logic_vector(1 to size) := (others=>'0'); begin for i in int'reverse_range loop case int(i) is when '0' => r(ptr) := '0'; when '1' => r(ptr) := '1'; when 'U' => r(ptr) := 'U'; when 'X' => r(ptr) := 'X'; when 'Z' => r(ptr) := 'Z'; when 'W' => r(ptr) := 'W'; when 'H' => r(ptr) := 'H'; when 'L' => r(ptr) := 'L'; when '-' => r(ptr) := '-'; when '_' => ptr := ptr + 1; when others => assert false report lf & "B conversion found illegal input character: " & int(i) & lf & "converting character to '-'" severity warning; r(ptr) := '-'; end case; ptr := ptr - 1; end loop; return r(size-rtn_len+1 to size); end b; function h (x : string) return natural is -- only following characters are allowed, otherwise result will be 0 -- 0 to 9 -- a,A to f,F -- blanks, underscore begin return cnvt_base(x,16); end h; function d (x : string) return natural is -- only following characters are allowed, otherwise result will be 0 -- 0 to 9 -- blanks, underscore begin return cnvt_base(x,10); end d; function o (x : string) return natural is -- only following characters are allowed, otherwise result will be 0 -- 0 to 7 -- blanks, underscore begin return cnvt_base(x,8); end o; function b (x : string) return natural is -- only following characters are allowed, otherwise result will be 0 -- 0 to 1 -- blanks, underscore begin return cnvt_base(x,2); end b; function to_slv(x : natural; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than sizeof(x), result will be truncated on the left variable int : natural := x; variable ptr : positive := 32; variable r : std_logic_vector(1 to 32) := (others=>'0'); begin while int > 0 loop case int rem 2 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when others => assert false report lf & "TO_SLV, shouldn't happen" severity failure; return "0"; end case; int := int / 2; ptr := ptr - 1; end loop; return r(33-rtn_len to 32); end to_slv; function to_sl(x : natural) return std_logic is variable r : std_logic := '0'; begin case x is when 0 => null; when 1 => r := '1'; when others => assert false report lf & "TO_SL found illegal input character: " & to_int_str(x) & lf & "converting character to '-'" severity warning; return '-'; end case; return r; end to_sl; function int_to_slv(x : integer; rtn_len : positive range 1 to 32 := 32) return std_logic_vector is -- if rtn_len is < than sizeof(x), result will be truncated on the left variable int : integer := x; variable ptr : positive := 32; variable r : std_logic_vector(1 to 32) := (others=>'0'); begin if int >= 0 or int = 0 then while int > 0 loop case int rem 2 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when others => assert false report lf & " shouldn't happen" severity failure; return "0"; end case; int := int / 2; ptr := ptr - 1; end loop; return r(33-rtn_len to 32); else int := 2**(rtn_len - 1) + int; while int > 0 loop case int rem 2 is when 0 => r(ptr) := '0'; when 1 => r(ptr) := '1'; when others => assert false report lf & " shouldn't happen" severity failure; return "0"; end case; int := int / 2; ptr := ptr - 1; end loop; r(33-rtn_len) := '1'; return r(33-rtn_len to 32); end if; end int_to_slv; function to_time (x: natural) return time is begin return x * 1 ns; end to_time; function to_int(x : std_logic_vector) return integer is -- assumes x is an signed number -- more than 32 bits are truncated on left variable t : std_logic_vector(x'length downto 1) := x; variable int : std_logic_vector(32 downto 1) := (others => '0'); variable sign : std_logic := '0'; variable size : integer := 0; variable inv : boolean := false; variable r : integer := 0; variable place : positive := 1; begin if x'length < 33 then sign := t(x'length); for i in t'reverse_range loop if sign = '1' then if inv = true then t(i) := not(t(i)); elsif t(i) = '1' then inv := true; end if; end if; size := size +1; end loop; inv := false; for i in 1 to size - 1 loop case t(i) is when '1' | 'H' => r := r + place; when '0' | 'L' => null; when others => assert false report lf & " TO_INT found illegal value " severity warning; return 0; end case; place := place * 2; end loop; if sign = '1' THEN return (- r); else return r; end if; else -- x'length >= 33 int := t(32 downto 1); sign := t(32); for i in 1 to 31 loop if sign = '1' then if inv = true then int(i) := not(int(i)); elsif int(i) = '1' then inv := true; end if; end if; end loop; inv := false; for i in 1 to 31 loop case int(i) is when '1' | 'H' => r := r + place; when '0' | 'L' => null; when others => assert false report lf & " TO_INT found illegal value " severity warning; return 0; end case; place := place * 2; end loop; if sign = '1' THEN return (- r); else return r; end if; end if; end to_int; END conversion;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s01b03x00p07n01i00278ent IS END c03s01b03x00p07n01i00278ent; ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS type twos_complement_integer is range -32768 to 32767; type J is range twos_complement_integer'low to twos_complement_integer'high units -- Success_here A; B = 10 A; C = 10 B; D = 10 C; end units; BEGIN TESTING: PROCESS variable k : J := 31000 A; BEGIN k := 5 A; assert NOT(k=5 A) report "***PASSED TEST: c03s01b03x00p07n01i00278" severity NOTE; assert (k=5 A) report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions." severity ERROR; wait; END PROCESS TESTING; END c03s01b03x00p07n01i00278arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s01b03x00p07n01i00278ent IS END c03s01b03x00p07n01i00278ent; ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS type twos_complement_integer is range -32768 to 32767; type J is range twos_complement_integer'low to twos_complement_integer'high units -- Success_here A; B = 10 A; C = 10 B; D = 10 C; end units; BEGIN TESTING: PROCESS variable k : J := 31000 A; BEGIN k := 5 A; assert NOT(k=5 A) report "***PASSED TEST: c03s01b03x00p07n01i00278" severity NOTE; assert (k=5 A) report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions." severity ERROR; wait; END PROCESS TESTING; END c03s01b03x00p07n01i00278arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s01b03x00p07n01i00278ent IS END c03s01b03x00p07n01i00278ent; ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS type twos_complement_integer is range -32768 to 32767; type J is range twos_complement_integer'low to twos_complement_integer'high units -- Success_here A; B = 10 A; C = 10 B; D = 10 C; end units; BEGIN TESTING: PROCESS variable k : J := 31000 A; BEGIN k := 5 A; assert NOT(k=5 A) report "***PASSED TEST: c03s01b03x00p07n01i00278" severity NOTE; assert (k=5 A) report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions." severity ERROR; wait; END PROCESS TESTING; END c03s01b03x00p07n01i00278arch;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sgmii -- File: sgmii.vhd -- Author: Fredrik Ringhage - Aeroflex Gaisler -- Description: GMII to SGMII interface ------------------------------------------------------------------------------ -------------------------------------------------------------------------------- -- Description: This is the top level vhdl example design for the -- Ethernet 1000BASE-X PCS/PMA core. -- -- This design example instantiates IOB flip-flops -- and input/output buffers on the GMII. -- -- A Transmitter Elastic Buffer is instantiated on the Tx -- GMII path to perform clock compenstation between the -- core and the external MAC driving the Tx GMII. -- -- This design example can be synthesised. -- -- -- -- ---------------------------------------------------------------- -- | Example Design | -- | | -- | ---------------------------------------------- | -- | | Core Block (wrapper) | | -- | | | | -- | | -------------- -------------- | | -- | | | Core | | tranceiver | | | -- | | | | | | | | -- | --------- | | | | | | | -- | | | | | | | | | | -- | | Tx | | | | | | | | -- ---->|Elastic|----->| GMII |--------->| TXP |---------> -- | |Buffer | | | Tx | | TXN | | | -- | | | | | | | | | | -- | --------- | | | | | | | -- | GMII | | | | | | | -- | IOBs | | | | | | | -- | | | | | | | | -- | | | GMII | | RXP | | | -- <-------------------| Rx |<---------| RXN |<--------- -- | | | | | | | | -- | | -------------- -------------- | | -- | | | | -- | ---------------------------------------------- | -- | | -- ---------------------------------------------------------------- -- -------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library gaisler; use gaisler.misc.all; use gaisler.net.all; -------------------------------------------------------------------------------- -- The entity declaration for the example design -------------------------------------------------------------------------------- entity sgmii_kc705 is generic( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; autonegotiation : integer := 1 ); port( -- Tranceiver Interface sgmiii : in eth_sgmii_in_type; sgmiio : out eth_sgmii_out_type; -- GMII Interface (client MAC <=> PCS) gmiii : out eth_in_type; gmiio : in eth_out_type; -- Asynchronous reset for entire core. reset : in std_logic; -- APB Status bus apb_clk : in std_logic; apb_rstn : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type ); end sgmii_kc705; architecture top_level of sgmii_kc705 is ------------------------------------------------------------------------------ -- Component Declaration for the Core Block (core wrapper). ------------------------------------------------------------------------------ component sgmii_block port( -- Transceiver Interface ------------------------ drpaddr_in : in std_logic_vector(8 downto 0); drpclk_in : in std_logic; drpdi_in : in std_logic_vector(15 downto 0); drpdo_out : out std_logic_vector(15 downto 0); drpen_in : in std_logic; drprdy_out : out std_logic; drpwe_in : in std_logic; gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD. txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD. rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA. rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA. txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz) resetdone : out std_logic; -- The GT transceiver has completed its reset cycle mmcm_locked : in std_logic; -- Locked signal from MMCM userclk : in std_logic; -- 62.5MHz clock. userclk2 : in std_logic; -- 125MHz clock. independent_clock_bufg : in std_logic; pma_reset : in std_logic; -- transceiver PMA reset signal -- GMII Interface ----------------- sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_en : out std_logic; -- Clock enable for client MAC gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC. gmii_tx_en : in std_logic; -- Transmit control signal from client MAC. gmii_tx_er : in std_logic; -- Transmit control signal from client MAC. gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC. gmii_rx_dv : out std_logic; -- Received control signal to client MAC. gmii_rx_er : out std_logic; -- Received control signal to client MAC. gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII. -- Management: MDIO Interface ----------------------------- configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface. an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV) an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0 link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control -- Speed Control ---------------- speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed -- General IO's --------------- status_vector : out std_logic_vector(15 downto 0); -- Core status. reset : in std_logic; -- Asynchronous reset for entire core. signal_detect : in std_logic -- Input from PMD to indicate presence of optical input. ); end component; component MMCME2_ADV generic ( BANDWIDTH : string := "OPTIMIZED"; CLKFBOUT_MULT_F : real := 5.000; CLKFBOUT_PHASE : real := 0.000; CLKFBOUT_USE_FINE_PS : boolean := FALSE; CLKIN1_PERIOD : real := 0.000; CLKIN2_PERIOD : real := 0.000; CLKOUT0_DIVIDE_F : real := 1.000; CLKOUT0_DUTY_CYCLE : real := 0.500; CLKOUT0_PHASE : real := 0.000; CLKOUT0_USE_FINE_PS : boolean := FALSE; CLKOUT1_DIVIDE : integer := 1; CLKOUT1_DUTY_CYCLE : real := 0.500; CLKOUT1_PHASE : real := 0.000; CLKOUT1_USE_FINE_PS : boolean := FALSE; CLKOUT2_DIVIDE : integer := 1; CLKOUT2_DUTY_CYCLE : real := 0.500; CLKOUT2_PHASE : real := 0.000; CLKOUT2_USE_FINE_PS : boolean := FALSE; CLKOUT3_DIVIDE : integer := 1; CLKOUT3_DUTY_CYCLE : real := 0.500; CLKOUT3_PHASE : real := 0.000; CLKOUT3_USE_FINE_PS : boolean := FALSE; CLKOUT4_CASCADE : boolean := FALSE; CLKOUT4_DIVIDE : integer := 1; CLKOUT4_DUTY_CYCLE : real := 0.500; CLKOUT4_PHASE : real := 0.000; CLKOUT4_USE_FINE_PS : boolean := FALSE; CLKOUT5_DIVIDE : integer := 1; CLKOUT5_DUTY_CYCLE : real := 0.500; CLKOUT5_PHASE : real := 0.000; CLKOUT5_USE_FINE_PS : boolean := FALSE; CLKOUT6_DIVIDE : integer := 1; CLKOUT6_DUTY_CYCLE : real := 0.500; CLKOUT6_PHASE : real := 0.000; CLKOUT6_USE_FINE_PS : boolean := FALSE; COMPENSATION : string := "ZHOLD"; DIVCLK_DIVIDE : integer := 1; REF_JITTER1 : real := 0.0; REF_JITTER2 : real := 0.0; SS_EN : string := "FALSE"; SS_MODE : string := "CENTER_HIGH"; SS_MOD_PERIOD : integer := 10000; STARTUP_WAIT : boolean := FALSE ); port ( CLKFBOUT : out std_ulogic := '0'; CLKFBOUTB : out std_ulogic := '0'; CLKFBSTOPPED : out std_ulogic := '0'; CLKINSTOPPED : out std_ulogic := '0'; CLKOUT0 : out std_ulogic := '0'; CLKOUT0B : out std_ulogic := '0'; CLKOUT1 : out std_ulogic := '0'; CLKOUT1B : out std_ulogic := '0'; CLKOUT2 : out std_ulogic := '0'; CLKOUT2B : out std_ulogic := '0'; CLKOUT3 : out std_ulogic := '0'; CLKOUT3B : out std_ulogic := '0'; CLKOUT4 : out std_ulogic := '0'; CLKOUT5 : out std_ulogic := '0'; CLKOUT6 : out std_ulogic := '0'; DO : out std_logic_vector (15 downto 0); DRDY : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; PSDONE : out std_ulogic := '0'; CLKFBIN : in std_ulogic; CLKIN1 : in std_ulogic; CLKIN2 : in std_ulogic; CLKINSEL : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; PSCLK : in std_ulogic; PSEN : in std_ulogic; PSINCDEC : in std_ulogic; PWRDWN : in std_ulogic; RST : in std_ulogic ); end component; ----- component IBUFDS_GTE2 ----- component IBUFDS_GTE2 generic ( CLKCM_CFG : boolean := TRUE; CLKRCV_TRST : boolean := TRUE; CLKSWING_CFG : bit_vector := "11" ); port ( O : out std_ulogic; ODIV2 : out std_ulogic; CEB : in std_ulogic; I : in std_ulogic; IB : in std_ulogic ); end component; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0), 1 => apb_iobar(paddr, pmask)); ------------------------------------------------------------------------------ -- internal signals used in this top level example design. ------------------------------------------------------------------------------ -- clock generation signals for tranceiver signal gtrefclk : std_logic; signal txoutclk : std_logic; signal resetdone : std_logic; signal mmcm_locked : std_logic; signal mmcm_reset : std_logic; signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1 : std_logic; signal userclk : std_logic; signal userclk2 : std_logic; -- PMA reset generation signals for tranceiver signal pma_reset_pipe : std_logic_vector(3 downto 0); signal pma_reset : std_logic; -- clock generation signals for SGMII clock signal sgmii_clk_r : std_logic; signal sgmii_clk_f : std_logic; signal sgmii_clk_en : std_logic; signal sgmii_clk : std_logic; signal sgmii_clk_int : std_logic; -- GMII signals signal gmii_txd : std_logic_vector(7 downto 0); signal gmii_tx_en : std_logic; signal gmii_tx_er : std_logic; signal gmii_rxd : std_logic_vector(7 downto 0); signal gmii_rx_dv : std_logic; signal gmii_rx_er : std_logic; signal gmii_isolate : std_logic; signal gmii_txd_int : std_logic_vector(7 downto 0); signal gmii_tx_en_int : std_logic; signal gmii_tx_er_int : std_logic; signal gmii_rxd_int : std_logic_vector(7 downto 0); signal gmii_rx_dv_int : std_logic; signal gmii_rx_er_int : std_logic; -- Extra registers to ease IOB placement signal status_vector_int : std_logic_vector(15 downto 0); signal status_vector_apb : std_logic_vector(15 downto 0); -- These attributes will stop timing errors being reported in back annotated -- SDF simulation. attribute ASYNC_REG : string; attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE"; -- Configuration register signal speed_is_10_100 : std_logic; signal speed_is_100 : std_logic; signal configuration_vector : std_logic_vector(4 downto 0); signal an_interrupt : std_logic; signal an_adv_config_vector : std_logic_vector(15 downto 0); signal an_restart_config : std_logic; signal link_timer_value : std_logic_vector(8 downto 0); signal status_vector : std_logic_vector(15 downto 0); signal synchronization_done : std_logic; signal linkup : std_logic; signal signal_detect : std_logic; attribute clock_signal : string; attribute clock_signal of sgmii_clk : signal is "yes"; attribute clock_signal of sgmii_clk_int : signal is "yes"; begin ----------------------------------------------------------------------------- -- Default for KC705 ----------------------------------------------------------------------------- -- Remove AN during simulation i.e. "00000" configuration_vector <= "10000" when (autonegotiation = 1) else "00000"; --an_adv_config_vector <= x"4001"; an_adv_config_vector <= "0000000000100001"; an_restart_config <= '0'; link_timer_value <= "000110010"; -- Core Status vector outputs synchronization_done <= status_vector_int(1); linkup <= status_vector_int(0); signal_detect <= '1'; apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.pirq <= (others => '0'); apbo.prdata(31 downto 16) <= (others => '0'); apbo.prdata(15 downto 0) <= status_vector_apb; gmiii.gtx_clk <= sgmii_clk; gmiii.tx_clk <= sgmii_clk; gmiii.rx_clk <= sgmii_clk; gmii_txd <= gmiio.txd; gmii_tx_en <= gmiio.tx_en; gmii_tx_er <= gmiio.tx_er; gmiii.rxd <= gmii_rxd; gmiii.rx_dv <= gmii_rx_dv; gmiii.rx_er <= gmii_rx_er; gmiii.edclsepahb <= '0'; gmiii.edcldisable <= '0'; gmiii.phyrstaddr <= (others => '0'); gmiii.edcladdr <= (others => '0'); gmiii.rmii_clk <= sgmii_clk; gmiii.rx_col <= '0'; gmiii.rx_crs <= '0'; sgmiio.mdio_o <= gmiio.mdio_o; sgmiio.mdio_oe <= gmiio.mdio_oe; gmiii.mdio_i <= sgmiii.mdio_i; sgmiio.mdc <= gmiio.mdc; gmiii.mdint <= sgmiii.mdint; sgmiio.reset <= apb_rstn; ----------------------------------------------------------------------------- -- Transceiver Clock Management ----------------------------------------------------------------------------- -- Clock circuitry for the GT Transceiver uses a differential input clock. -- gtrefclk is routed to the tranceiver. ibufds_gtrefclk : IBUFDS_GTE2 port map ( I => sgmiii.clkp, IB => sgmiii.clkn, CEB => '0', O => gtrefclk, ODIV2 => open ); -- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is -- routed to an MMCM module where it is used to create phase and frequency -- related 62.5MHz and 125MHz clock sources mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", -- STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 16.000, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 8.000, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_DIVIDE => 16, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT1_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 16.0, REF_JITTER1 => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKFBOUTB => open, CLKOUT0 => clkout0, CLKOUT0B => open, CLKOUT1 => clkout1, CLKOUT1B => open, CLKOUT2 => open, CLKOUT2B => open, CLKOUT3 => open, CLKOUT3B => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, -- Input clock control CLKFBIN => clkfbout, CLKIN1 => txoutclk, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => open, DRDY => open, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => mmcm_locked, CLKINSTOPPED => open, CLKFBSTOPPED => open, PWRDWN => '0', RST => mmcm_reset); mmcm_reset <= reset or (not resetdone); -- This 62.5MHz clock is placed onto global clock routing and is then used -- for tranceiver TXUSRCLK/RXUSRCLK. bufg_userclk: BUFG port map ( I => clkout1, O => userclk ); -- This 125MHz clock is placed onto global clock routing and is then used -- to clock all Ethernet core logic. bufg_userclk2: BUFG port map ( I => clkout0, O => userclk2 ); ----------------------------------------------------------------------------- -- Transceiver PMA reset circuitry ----------------------------------------------------------------------------- -- Create a reset pulse of a decent length process(reset, apb_clk) begin if (reset = '1') then pma_reset_pipe <= "1111"; elsif apb_clk'event and apb_clk = '1' then pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset; end if; end process; pma_reset <= pma_reset_pipe(3); ------------------------------------------------------------------------------ -- Instantiate the Core Block (core wrapper). ------------------------------------------------------------------------------ speed_is_10_100 <= not gmiio.gbit; speed_is_100 <= gmiio.speed; core_wrapper : sgmii_block port map ( drpaddr_in => "000000000", drpclk_in => '0', drpdi_in => "0000000000000000", drpdo_out => OPEN, drpen_in => '0', drprdy_out => OPEN, drpwe_in => '0', gtrefclk => gtrefclk, txp => sgmiio.txp, txn => sgmiio.txn, rxp => sgmiii.rxp, rxn => sgmiii.rxn, txoutclk => txoutclk, resetdone => resetdone, mmcm_locked => mmcm_locked, userclk => userclk, userclk2 => userclk2, independent_clock_bufg => apb_clk, pma_reset => pma_reset, sgmii_clk_r => sgmii_clk_r, sgmii_clk_f => sgmii_clk_f, sgmii_clk_en => sgmii_clk_en, gmii_txd => gmii_txd_int, gmii_tx_en => gmii_tx_en_int, gmii_tx_er => gmii_tx_er_int, gmii_rxd => gmii_rxd_int, gmii_rx_dv => gmii_rx_dv_int, gmii_rx_er => gmii_rx_er_int, gmii_isolate => gmii_isolate, configuration_vector => configuration_vector, an_interrupt => an_interrupt, an_adv_config_vector => an_adv_config_vector, an_restart_config => an_restart_config, link_timer_value => link_timer_value, speed_is_10_100 => speed_is_10_100, speed_is_100 => speed_is_100, status_vector => status_vector_int, reset => reset, signal_detect => signal_detect ); ----------------------------------------------------------------------------- -- GMII transmitter data logic ----------------------------------------------------------------------------- -- Drive input GMII signals through IOB input flip-flops (inferred). process (userclk2) begin if userclk2'event and userclk2 = '1' then gmii_txd_int <= gmii_txd; gmii_tx_en_int <= gmii_tx_en; gmii_tx_er_int <= gmii_tx_er; end if; end process; ----------------------------------------------------------------------------- -- SGMII clock logic ----------------------------------------------------------------------------- process (userclk2) begin if userclk2'event and userclk2 = '1' then sgmii_clk_int <= sgmii_clk_r; end if; end process; sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int; ----------------------------------------------------------------------------- -- GMII receiver data logic ----------------------------------------------------------------------------- -- Drive input GMII signals through IOB output flip-flops (inferred). process (userclk2) begin if userclk2'event and userclk2 = '1' then gmii_rxd <= gmii_rxd_int; gmii_rx_dv <= gmii_rx_dv_int; gmii_rx_er <= gmii_rx_er_int; end if; end process; ----------------------------------------------------------------------------- -- Extra registers to ease IOB placement ----------------------------------------------------------------------------- process (userclk2) begin if userclk2'event and userclk2 = '1' then status_vector <= status_vector_int; end if; end process; ----------------------------------------------------------------------------- -- Extra registers to ease CDC placement ----------------------------------------------------------------------------- process (apb_clk) begin if apb_clk'event and apb_clk = '1' then status_vector_apb <= status_vector_int; end if; end process; end top_level;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sgmii -- File: sgmii.vhd -- Author: Fredrik Ringhage - Aeroflex Gaisler -- Description: GMII to SGMII interface ------------------------------------------------------------------------------ -------------------------------------------------------------------------------- -- Description: This is the top level vhdl example design for the -- Ethernet 1000BASE-X PCS/PMA core. -- -- This design example instantiates IOB flip-flops -- and input/output buffers on the GMII. -- -- A Transmitter Elastic Buffer is instantiated on the Tx -- GMII path to perform clock compenstation between the -- core and the external MAC driving the Tx GMII. -- -- This design example can be synthesised. -- -- -- -- ---------------------------------------------------------------- -- | Example Design | -- | | -- | ---------------------------------------------- | -- | | Core Block (wrapper) | | -- | | | | -- | | -------------- -------------- | | -- | | | Core | | tranceiver | | | -- | | | | | | | | -- | --------- | | | | | | | -- | | | | | | | | | | -- | | Tx | | | | | | | | -- ---->|Elastic|----->| GMII |--------->| TXP |---------> -- | |Buffer | | | Tx | | TXN | | | -- | | | | | | | | | | -- | --------- | | | | | | | -- | GMII | | | | | | | -- | IOBs | | | | | | | -- | | | | | | | | -- | | | GMII | | RXP | | | -- <-------------------| Rx |<---------| RXN |<--------- -- | | | | | | | | -- | | -------------- -------------- | | -- | | | | -- | ---------------------------------------------- | -- | | -- ---------------------------------------------------------------- -- -------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library gaisler; use gaisler.misc.all; use gaisler.net.all; -------------------------------------------------------------------------------- -- The entity declaration for the example design -------------------------------------------------------------------------------- entity sgmii_kc705 is generic( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; autonegotiation : integer := 1 ); port( -- Tranceiver Interface sgmiii : in eth_sgmii_in_type; sgmiio : out eth_sgmii_out_type; -- GMII Interface (client MAC <=> PCS) gmiii : out eth_in_type; gmiio : in eth_out_type; -- Asynchronous reset for entire core. reset : in std_logic; -- APB Status bus apb_clk : in std_logic; apb_rstn : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type ); end sgmii_kc705; architecture top_level of sgmii_kc705 is ------------------------------------------------------------------------------ -- Component Declaration for the Core Block (core wrapper). ------------------------------------------------------------------------------ component sgmii_block port( -- Transceiver Interface ------------------------ drpaddr_in : in std_logic_vector(8 downto 0); drpclk_in : in std_logic; drpdi_in : in std_logic_vector(15 downto 0); drpdo_out : out std_logic_vector(15 downto 0); drpen_in : in std_logic; drprdy_out : out std_logic; drpwe_in : in std_logic; gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD. txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD. rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA. rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA. txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz) resetdone : out std_logic; -- The GT transceiver has completed its reset cycle mmcm_locked : in std_logic; -- Locked signal from MMCM userclk : in std_logic; -- 62.5MHz clock. userclk2 : in std_logic; -- 125MHz clock. independent_clock_bufg : in std_logic; pma_reset : in std_logic; -- transceiver PMA reset signal -- GMII Interface ----------------- sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_en : out std_logic; -- Clock enable for client MAC gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC. gmii_tx_en : in std_logic; -- Transmit control signal from client MAC. gmii_tx_er : in std_logic; -- Transmit control signal from client MAC. gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC. gmii_rx_dv : out std_logic; -- Received control signal to client MAC. gmii_rx_er : out std_logic; -- Received control signal to client MAC. gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII. -- Management: MDIO Interface ----------------------------- configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface. an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV) an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0 link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control -- Speed Control ---------------- speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed -- General IO's --------------- status_vector : out std_logic_vector(15 downto 0); -- Core status. reset : in std_logic; -- Asynchronous reset for entire core. signal_detect : in std_logic -- Input from PMD to indicate presence of optical input. ); end component; component MMCME2_ADV generic ( BANDWIDTH : string := "OPTIMIZED"; CLKFBOUT_MULT_F : real := 5.000; CLKFBOUT_PHASE : real := 0.000; CLKFBOUT_USE_FINE_PS : boolean := FALSE; CLKIN1_PERIOD : real := 0.000; CLKIN2_PERIOD : real := 0.000; CLKOUT0_DIVIDE_F : real := 1.000; CLKOUT0_DUTY_CYCLE : real := 0.500; CLKOUT0_PHASE : real := 0.000; CLKOUT0_USE_FINE_PS : boolean := FALSE; CLKOUT1_DIVIDE : integer := 1; CLKOUT1_DUTY_CYCLE : real := 0.500; CLKOUT1_PHASE : real := 0.000; CLKOUT1_USE_FINE_PS : boolean := FALSE; CLKOUT2_DIVIDE : integer := 1; CLKOUT2_DUTY_CYCLE : real := 0.500; CLKOUT2_PHASE : real := 0.000; CLKOUT2_USE_FINE_PS : boolean := FALSE; CLKOUT3_DIVIDE : integer := 1; CLKOUT3_DUTY_CYCLE : real := 0.500; CLKOUT3_PHASE : real := 0.000; CLKOUT3_USE_FINE_PS : boolean := FALSE; CLKOUT4_CASCADE : boolean := FALSE; CLKOUT4_DIVIDE : integer := 1; CLKOUT4_DUTY_CYCLE : real := 0.500; CLKOUT4_PHASE : real := 0.000; CLKOUT4_USE_FINE_PS : boolean := FALSE; CLKOUT5_DIVIDE : integer := 1; CLKOUT5_DUTY_CYCLE : real := 0.500; CLKOUT5_PHASE : real := 0.000; CLKOUT5_USE_FINE_PS : boolean := FALSE; CLKOUT6_DIVIDE : integer := 1; CLKOUT6_DUTY_CYCLE : real := 0.500; CLKOUT6_PHASE : real := 0.000; CLKOUT6_USE_FINE_PS : boolean := FALSE; COMPENSATION : string := "ZHOLD"; DIVCLK_DIVIDE : integer := 1; REF_JITTER1 : real := 0.0; REF_JITTER2 : real := 0.0; SS_EN : string := "FALSE"; SS_MODE : string := "CENTER_HIGH"; SS_MOD_PERIOD : integer := 10000; STARTUP_WAIT : boolean := FALSE ); port ( CLKFBOUT : out std_ulogic := '0'; CLKFBOUTB : out std_ulogic := '0'; CLKFBSTOPPED : out std_ulogic := '0'; CLKINSTOPPED : out std_ulogic := '0'; CLKOUT0 : out std_ulogic := '0'; CLKOUT0B : out std_ulogic := '0'; CLKOUT1 : out std_ulogic := '0'; CLKOUT1B : out std_ulogic := '0'; CLKOUT2 : out std_ulogic := '0'; CLKOUT2B : out std_ulogic := '0'; CLKOUT3 : out std_ulogic := '0'; CLKOUT3B : out std_ulogic := '0'; CLKOUT4 : out std_ulogic := '0'; CLKOUT5 : out std_ulogic := '0'; CLKOUT6 : out std_ulogic := '0'; DO : out std_logic_vector (15 downto 0); DRDY : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; PSDONE : out std_ulogic := '0'; CLKFBIN : in std_ulogic; CLKIN1 : in std_ulogic; CLKIN2 : in std_ulogic; CLKINSEL : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; PSCLK : in std_ulogic; PSEN : in std_ulogic; PSINCDEC : in std_ulogic; PWRDWN : in std_ulogic; RST : in std_ulogic ); end component; ----- component IBUFDS_GTE2 ----- component IBUFDS_GTE2 generic ( CLKCM_CFG : boolean := TRUE; CLKRCV_TRST : boolean := TRUE; CLKSWING_CFG : bit_vector := "11" ); port ( O : out std_ulogic; ODIV2 : out std_ulogic; CEB : in std_ulogic; I : in std_ulogic; IB : in std_ulogic ); end component; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0), 1 => apb_iobar(paddr, pmask)); ------------------------------------------------------------------------------ -- internal signals used in this top level example design. ------------------------------------------------------------------------------ -- clock generation signals for tranceiver signal gtrefclk : std_logic; signal txoutclk : std_logic; signal resetdone : std_logic; signal mmcm_locked : std_logic; signal mmcm_reset : std_logic; signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1 : std_logic; signal userclk : std_logic; signal userclk2 : std_logic; -- PMA reset generation signals for tranceiver signal pma_reset_pipe : std_logic_vector(3 downto 0); signal pma_reset : std_logic; -- clock generation signals for SGMII clock signal sgmii_clk_r : std_logic; signal sgmii_clk_f : std_logic; signal sgmii_clk_en : std_logic; signal sgmii_clk : std_logic; signal sgmii_clk_int : std_logic; -- GMII signals signal gmii_txd : std_logic_vector(7 downto 0); signal gmii_tx_en : std_logic; signal gmii_tx_er : std_logic; signal gmii_rxd : std_logic_vector(7 downto 0); signal gmii_rx_dv : std_logic; signal gmii_rx_er : std_logic; signal gmii_isolate : std_logic; signal gmii_txd_int : std_logic_vector(7 downto 0); signal gmii_tx_en_int : std_logic; signal gmii_tx_er_int : std_logic; signal gmii_rxd_int : std_logic_vector(7 downto 0); signal gmii_rx_dv_int : std_logic; signal gmii_rx_er_int : std_logic; -- Extra registers to ease IOB placement signal status_vector_int : std_logic_vector(15 downto 0); signal status_vector_apb : std_logic_vector(15 downto 0); -- These attributes will stop timing errors being reported in back annotated -- SDF simulation. attribute ASYNC_REG : string; attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE"; -- Configuration register signal speed_is_10_100 : std_logic; signal speed_is_100 : std_logic; signal configuration_vector : std_logic_vector(4 downto 0); signal an_interrupt : std_logic; signal an_adv_config_vector : std_logic_vector(15 downto 0); signal an_restart_config : std_logic; signal link_timer_value : std_logic_vector(8 downto 0); signal status_vector : std_logic_vector(15 downto 0); signal synchronization_done : std_logic; signal linkup : std_logic; signal signal_detect : std_logic; attribute clock_signal : string; attribute clock_signal of sgmii_clk : signal is "yes"; attribute clock_signal of sgmii_clk_int : signal is "yes"; begin ----------------------------------------------------------------------------- -- Default for KC705 ----------------------------------------------------------------------------- -- Remove AN during simulation i.e. "00000" configuration_vector <= "10000" when (autonegotiation = 1) else "00000"; --an_adv_config_vector <= x"4001"; an_adv_config_vector <= "0000000000100001"; an_restart_config <= '0'; link_timer_value <= "000110010"; -- Core Status vector outputs synchronization_done <= status_vector_int(1); linkup <= status_vector_int(0); signal_detect <= '1'; apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.pirq <= (others => '0'); apbo.prdata(31 downto 16) <= (others => '0'); apbo.prdata(15 downto 0) <= status_vector_apb; gmiii.gtx_clk <= sgmii_clk; gmiii.tx_clk <= sgmii_clk; gmiii.rx_clk <= sgmii_clk; gmii_txd <= gmiio.txd; gmii_tx_en <= gmiio.tx_en; gmii_tx_er <= gmiio.tx_er; gmiii.rxd <= gmii_rxd; gmiii.rx_dv <= gmii_rx_dv; gmiii.rx_er <= gmii_rx_er; gmiii.edclsepahb <= '0'; gmiii.edcldisable <= '0'; gmiii.phyrstaddr <= (others => '0'); gmiii.edcladdr <= (others => '0'); gmiii.rmii_clk <= sgmii_clk; gmiii.rx_col <= '0'; gmiii.rx_crs <= '0'; sgmiio.mdio_o <= gmiio.mdio_o; sgmiio.mdio_oe <= gmiio.mdio_oe; gmiii.mdio_i <= sgmiii.mdio_i; sgmiio.mdc <= gmiio.mdc; gmiii.mdint <= sgmiii.mdint; sgmiio.reset <= apb_rstn; ----------------------------------------------------------------------------- -- Transceiver Clock Management ----------------------------------------------------------------------------- -- Clock circuitry for the GT Transceiver uses a differential input clock. -- gtrefclk is routed to the tranceiver. ibufds_gtrefclk : IBUFDS_GTE2 port map ( I => sgmiii.clkp, IB => sgmiii.clkn, CEB => '0', O => gtrefclk, ODIV2 => open ); -- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is -- routed to an MMCM module where it is used to create phase and frequency -- related 62.5MHz and 125MHz clock sources mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", -- STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 16.000, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 8.000, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_DIVIDE => 16, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT1_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 16.0, REF_JITTER1 => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKFBOUTB => open, CLKOUT0 => clkout0, CLKOUT0B => open, CLKOUT1 => clkout1, CLKOUT1B => open, CLKOUT2 => open, CLKOUT2B => open, CLKOUT3 => open, CLKOUT3B => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, -- Input clock control CLKFBIN => clkfbout, CLKIN1 => txoutclk, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => open, DRDY => open, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => mmcm_locked, CLKINSTOPPED => open, CLKFBSTOPPED => open, PWRDWN => '0', RST => mmcm_reset); mmcm_reset <= reset or (not resetdone); -- This 62.5MHz clock is placed onto global clock routing and is then used -- for tranceiver TXUSRCLK/RXUSRCLK. bufg_userclk: BUFG port map ( I => clkout1, O => userclk ); -- This 125MHz clock is placed onto global clock routing and is then used -- to clock all Ethernet core logic. bufg_userclk2: BUFG port map ( I => clkout0, O => userclk2 ); ----------------------------------------------------------------------------- -- Transceiver PMA reset circuitry ----------------------------------------------------------------------------- -- Create a reset pulse of a decent length process(reset, apb_clk) begin if (reset = '1') then pma_reset_pipe <= "1111"; elsif apb_clk'event and apb_clk = '1' then pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset; end if; end process; pma_reset <= pma_reset_pipe(3); ------------------------------------------------------------------------------ -- Instantiate the Core Block (core wrapper). ------------------------------------------------------------------------------ speed_is_10_100 <= not gmiio.gbit; speed_is_100 <= gmiio.speed; core_wrapper : sgmii_block port map ( drpaddr_in => "000000000", drpclk_in => '0', drpdi_in => "0000000000000000", drpdo_out => OPEN, drpen_in => '0', drprdy_out => OPEN, drpwe_in => '0', gtrefclk => gtrefclk, txp => sgmiio.txp, txn => sgmiio.txn, rxp => sgmiii.rxp, rxn => sgmiii.rxn, txoutclk => txoutclk, resetdone => resetdone, mmcm_locked => mmcm_locked, userclk => userclk, userclk2 => userclk2, independent_clock_bufg => apb_clk, pma_reset => pma_reset, sgmii_clk_r => sgmii_clk_r, sgmii_clk_f => sgmii_clk_f, sgmii_clk_en => sgmii_clk_en, gmii_txd => gmii_txd_int, gmii_tx_en => gmii_tx_en_int, gmii_tx_er => gmii_tx_er_int, gmii_rxd => gmii_rxd_int, gmii_rx_dv => gmii_rx_dv_int, gmii_rx_er => gmii_rx_er_int, gmii_isolate => gmii_isolate, configuration_vector => configuration_vector, an_interrupt => an_interrupt, an_adv_config_vector => an_adv_config_vector, an_restart_config => an_restart_config, link_timer_value => link_timer_value, speed_is_10_100 => speed_is_10_100, speed_is_100 => speed_is_100, status_vector => status_vector_int, reset => reset, signal_detect => signal_detect ); ----------------------------------------------------------------------------- -- GMII transmitter data logic ----------------------------------------------------------------------------- -- Drive input GMII signals through IOB input flip-flops (inferred). process (userclk2) begin if userclk2'event and userclk2 = '1' then gmii_txd_int <= gmii_txd; gmii_tx_en_int <= gmii_tx_en; gmii_tx_er_int <= gmii_tx_er; end if; end process; ----------------------------------------------------------------------------- -- SGMII clock logic ----------------------------------------------------------------------------- process (userclk2) begin if userclk2'event and userclk2 = '1' then sgmii_clk_int <= sgmii_clk_r; end if; end process; sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int; ----------------------------------------------------------------------------- -- GMII receiver data logic ----------------------------------------------------------------------------- -- Drive input GMII signals through IOB output flip-flops (inferred). process (userclk2) begin if userclk2'event and userclk2 = '1' then gmii_rxd <= gmii_rxd_int; gmii_rx_dv <= gmii_rx_dv_int; gmii_rx_er <= gmii_rx_er_int; end if; end process; ----------------------------------------------------------------------------- -- Extra registers to ease IOB placement ----------------------------------------------------------------------------- process (userclk2) begin if userclk2'event and userclk2 = '1' then status_vector <= status_vector_int; end if; end process; ----------------------------------------------------------------------------- -- Extra registers to ease CDC placement ----------------------------------------------------------------------------- process (apb_clk) begin if apb_clk'event and apb_clk = '1' then status_vector_apb <= status_vector_int; end if; end process; end top_level;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2707.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s04b01x00p11n01i02707ent IS END c13s04b01x00p11n01i02707ent; ARCHITECTURE c13s04b01x00p11n01i02707arch OF c13s04b01x00p11n01i02707ent IS constant i : integer := 003; constant k : integer := 3; BEGIN TESTING: PROCESS BEGIN assert NOT( i=k ) report "***PASSED TEST: c13s04b01x00p11n01i02707" severity NOTE; assert ( i=k ) report "***FAILED TEST: c13s04b01x00p11n01i02707 - Leading zeros should be allowed for an integer literal." severity ERROR; wait; END PROCESS TESTING; END c13s04b01x00p11n01i02707arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2707.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s04b01x00p11n01i02707ent IS END c13s04b01x00p11n01i02707ent; ARCHITECTURE c13s04b01x00p11n01i02707arch OF c13s04b01x00p11n01i02707ent IS constant i : integer := 003; constant k : integer := 3; BEGIN TESTING: PROCESS BEGIN assert NOT( i=k ) report "***PASSED TEST: c13s04b01x00p11n01i02707" severity NOTE; assert ( i=k ) report "***FAILED TEST: c13s04b01x00p11n01i02707 - Leading zeros should be allowed for an integer literal." severity ERROR; wait; END PROCESS TESTING; END c13s04b01x00p11n01i02707arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2707.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s04b01x00p11n01i02707ent IS END c13s04b01x00p11n01i02707ent; ARCHITECTURE c13s04b01x00p11n01i02707arch OF c13s04b01x00p11n01i02707ent IS constant i : integer := 003; constant k : integer := 3; BEGIN TESTING: PROCESS BEGIN assert NOT( i=k ) report "***PASSED TEST: c13s04b01x00p11n01i02707" severity NOTE; assert ( i=k ) report "***FAILED TEST: c13s04b01x00p11n01i02707 - Leading zeros should be allowed for an integer literal." severity ERROR; wait; END PROCESS TESTING; END c13s04b01x00p11n01i02707arch;
library ieee; use ieee.std_logic_1164.all; entity sub_rng1 is port ( clk : in std_logic; a : in natural range 0 to 7; b : out natural range 0 to 7 ); end sub_rng1; architecture rtl of sub_rng1 is begin process(clk) begin if rising_edge(clk) then b <= a; end if; end process; end rtl; library ieee; use ieee.std_logic_1164.all; entity repro_rng1 is port ( clk : in std_logic; a : in natural range 0 to 7; b : out natural range 0 to 7 ); end repro_rng1; architecture rtl of repro_rng1 is begin i_sub_rng1 : entity work.sub_rng1 port map ( clk => clk, a => a, b => b ); end rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:42:23 12/19/2013 -- Design Name: -- Module Name: virtual_top_level - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity virtual_top_level is port( clk, reset : in std_logic ; pb, sw : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0); sseg_anode : out std_logic_vector(7 downto 0); sseg_common_cathode : out std_logic_vector(7 downto 0) ); end virtual_top_level; architecture Behavioral of virtual_top_level is constant DIVIDER1HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(100_000_000, 32)); constant DIVIDER5HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(20_000_000, 32)); constant DIVIDER10HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(10_000_000, 32)); constant DIVIDER100HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1_000_000, 32)); signal divider_output1hz,divider_output5hz ,divider_output10hz ,divider_output100hz : std_logic_vector(31 downto 0); signal onehz_signal, fivehz_signal, tenhz_signal, onehundredhz_signal : std_logic ; signal update_count_output: std_logic; signal counter_output : std_logic_vector(7 downto 0); signal counter_enable, counter_reset : std_logic ; signal sel: std_logic_vector(1 downto 0); begin process(clk, reset) begin if reset='1' then divider_output1hz <= DIVIDER1HZ ; divider_output5hz <= DIVIDER5HZ ; divider_output10hz <= DIVIDER10HZ; divider_output100hz <= DIVIDER100HZ; elsif clk'event and clk = '1' then if divider_output1hz = 0 then divider_output1hz <= DIVIDER1HZ ; else divider_output1hz <= divider_output1hz - 1 ; end if ; if divider_output5hz = 0 then divider_output5hz <= DIVIDER5HZ ; else divider_output5hz <= divider_output5hz - 1 ; end if ; if divider_output10hz = 0 then divider_output10hz <= DIVIDER10HZ ; else divider_output10hz <= divider_output10hz - 1 ; end if ; if divider_output100hz = 0 then divider_output100hz <= DIVIDER100HZ ; else divider_output100hz <= divider_output100hz - 1 ; end if ; end if ; end process ; onehz_signal <= '1' when divider_output1hz = 0 else '0' ; fivehz_signal <= '1' when divider_output5hz = 0 else '0' ; tenhz_signal <= '1' when divider_output10hz = 0 else '0' ; onehundredhz_signal <= '1' when divider_output100hz = 0 else '0' ; --mux the count out enable input different frequncy values with sw(7 downto 6) select update_count_output <= onehz_signal when "00", fivehz_signal when "01", tenhz_signal when "10", onehundredhz_signal when "11"; counter_enable <= sw(0); counter_reset <= pb(1); process(clk, reset) begin if reset = '1' then counter_output <= (others => '0'); elsif clk'event and clk = '1' then if counter_reset = '1' then counter_output <= (others => '0'); elsif counter_enable = '1' and update_count_output = '1' then --100 hz updateupdate_count_output counter_output <= counter_output + 1; end if ; end if ; end process ; led(7 downto 0) <= counter_output; sseg_common_cathode <= (others => '0'); sseg_anode(7) <= '0' ; -- dot point with counter_output(3 downto 0) select --"gfedcba" segments sseg_anode(6 downto 0)<= "0111111" when "0000",--0 "0000110" when "0001",--1 "1011011" when "0010",--2 "1001111" when "0011",--3 "1100110" when "0100",--4 "1101101" when "0101",--5 "1111101" when "0110",--6 "0000111" when "0111",--7 "1111111" when "1000",--8 "1101111" when "1001",--9 "1110111" when "1010", --a "1111100" when "1011", --b "0111001" when "1100", --c "1011110" when "1101", --d "1111001" when "1110", --e "1110001" when others; --f end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:42:23 12/19/2013 -- Design Name: -- Module Name: virtual_top_level - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity virtual_top_level is port( clk, reset : in std_logic ; pb, sw : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0); sseg_anode : out std_logic_vector(7 downto 0); sseg_common_cathode : out std_logic_vector(7 downto 0) ); end virtual_top_level; architecture Behavioral of virtual_top_level is constant DIVIDER1HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(100_000_000, 32)); constant DIVIDER5HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(20_000_000, 32)); constant DIVIDER10HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(10_000_000, 32)); constant DIVIDER100HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1_000_000, 32)); signal divider_output1hz,divider_output5hz ,divider_output10hz ,divider_output100hz : std_logic_vector(31 downto 0); signal onehz_signal, fivehz_signal, tenhz_signal, onehundredhz_signal : std_logic ; signal update_count_output: std_logic; signal counter_output : std_logic_vector(7 downto 0); signal counter_enable, counter_reset : std_logic ; signal sel: std_logic_vector(1 downto 0); begin process(clk, reset) begin if reset='1' then divider_output1hz <= DIVIDER1HZ ; divider_output5hz <= DIVIDER5HZ ; divider_output10hz <= DIVIDER10HZ; divider_output100hz <= DIVIDER100HZ; elsif clk'event and clk = '1' then if divider_output1hz = 0 then divider_output1hz <= DIVIDER1HZ ; else divider_output1hz <= divider_output1hz - 1 ; end if ; if divider_output5hz = 0 then divider_output5hz <= DIVIDER5HZ ; else divider_output5hz <= divider_output5hz - 1 ; end if ; if divider_output10hz = 0 then divider_output10hz <= DIVIDER10HZ ; else divider_output10hz <= divider_output10hz - 1 ; end if ; if divider_output100hz = 0 then divider_output100hz <= DIVIDER100HZ ; else divider_output100hz <= divider_output100hz - 1 ; end if ; end if ; end process ; onehz_signal <= '1' when divider_output1hz = 0 else '0' ; fivehz_signal <= '1' when divider_output5hz = 0 else '0' ; tenhz_signal <= '1' when divider_output10hz = 0 else '0' ; onehundredhz_signal <= '1' when divider_output100hz = 0 else '0' ; --mux the count out enable input different frequncy values with sw(7 downto 6) select update_count_output <= onehz_signal when "00", fivehz_signal when "01", tenhz_signal when "10", onehundredhz_signal when "11"; counter_enable <= sw(0); counter_reset <= pb(1); process(clk, reset) begin if reset = '1' then counter_output <= (others => '0'); elsif clk'event and clk = '1' then if counter_reset = '1' then counter_output <= (others => '0'); elsif counter_enable = '1' and update_count_output = '1' then --100 hz updateupdate_count_output counter_output <= counter_output + 1; end if ; end if ; end process ; led(7 downto 0) <= counter_output; sseg_common_cathode <= (others => '0'); sseg_anode(7) <= '0' ; -- dot point with counter_output(3 downto 0) select --"gfedcba" segments sseg_anode(6 downto 0)<= "0111111" when "0000",--0 "0000110" when "0001",--1 "1011011" when "0010",--2 "1001111" when "0011",--3 "1100110" when "0100",--4 "1101101" when "0101",--5 "1111101" when "0110",--6 "0000111" when "0111",--7 "1111111" when "1000",--8 "1101111" when "1001",--9 "1110111" when "1010", --a "1111100" when "1011", --b "0111001" when "1100", --c "1011110" when "1101", --d "1111001" when "1110", --e "1110001" when others; --f end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity issue2 is end issue2; architecture beh of issue2 is begin assert (unsigned'("1111") > unsigned'("0111")); assert (unsigned'("1111") >= unsigned'("0111")); assert (unsigned'("0111") < unsigned'("1111")); assert (unsigned'("0111") <= unsigned'("1111")); assert (signed'("0111") > signed'("1111")); assert (signed'("0111") >= signed'("1111")); assert (signed'("1111") < signed'("0111")); assert (signed'("1111") <= signed'("0111")); assert signed'("1111") = -1; end architecture beh;
------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014 -- Date : Thu Jul 24 13:45:40 2014 -- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_funcsim.vhdl -- Design : blk_mem_gen_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1blk_mem_gen_prim_wrapper is port ( doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; enb : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end blk_mem_gen_1blk_mem_gen_prim_wrapper; architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_prim_wrapper is signal \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "READ_FIRST", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2) => '1', ADDRARDADDR(1) => '1', ADDRARDADDR(0) => '1', ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 5) => addrb(9 downto 0), ADDRBWRADDR(4) => '1', ADDRBWRADDR(3) => '1', ADDRBWRADDR(2) => '1', ADDRBWRADDR(1) => '1', ADDRBWRADDR(0) => '1', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 0) => doutb(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3) => \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, DOPBDOP(2) => \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, DOPBDOP(1) => \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => wea(0), ENBWREN => enb, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => '1', WEA(2) => '1', WEA(1) => '1', WEA(0) => '1', WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1blk_mem_gen_prim_width is port ( doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; enb : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_gen_1blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.blk_mem_gen_1blk_mem_gen_prim_wrapper port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), enb => enb, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; enb : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_gen_1blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.blk_mem_gen_1blk_mem_gen_prim_width port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), enb => enb, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; enb : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_gen_1blk_mem_gen_top; architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_top is begin \valid.cstr\: entity work.blk_mem_gen_1blk_mem_gen_generic_cstr port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), enb => enb, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1blk_mem_gen_v8_2_synth is port ( doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; enb : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth"; end blk_mem_gen_1blk_mem_gen_v8_2_synth; architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_v8_2_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_1blk_mem_gen_top port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), enb => enb, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ); sleep : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2"; attribute C_FAMILY : string; attribute C_FAMILY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "./"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "NONE"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 9; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_1.mem"; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 8; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 8; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4096; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4096; attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 12; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITB_VAL : string; attribute C_INITB_VAL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST"; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 32; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 32; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1024; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 10; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "ALL"; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "1"; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 5.528025 mW"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "yes"; end \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\; architecture STRUCTURE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; douta(7) <= \<const0>\; douta(6) <= \<const0>\; douta(5) <= \<const0>\; douta(4) <= \<const0>\; douta(3) <= \<const0>\; douta(2) <= \<const0>\; douta(1) <= \<const0>\; douta(0) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(31) <= \<const0>\; s_axi_rdata(30) <= \<const0>\; s_axi_rdata(29) <= \<const0>\; s_axi_rdata(28) <= \<const0>\; s_axi_rdata(27) <= \<const0>\; s_axi_rdata(26) <= \<const0>\; s_axi_rdata(25) <= \<const0>\; s_axi_rdata(24) <= \<const0>\; s_axi_rdata(23) <= \<const0>\; s_axi_rdata(22) <= \<const0>\; s_axi_rdata(21) <= \<const0>\; s_axi_rdata(20) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.blk_mem_gen_1blk_mem_gen_v8_2_synth port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), enb => enb, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity blk_mem_gen_1 is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; enb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of blk_mem_gen_1 : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_gen_1 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of blk_mem_gen_1 : entity is "blk_mem_gen_v8_2,Vivado 2014.1"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of blk_mem_gen_1 : entity is "blk_mem_gen_1,blk_mem_gen_v8_2,{}"; attribute core_generation_info : string; attribute core_generation_info of blk_mem_gen_1 : entity is "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.528025 mW}"; end blk_mem_gen_1; architecture STRUCTURE of blk_mem_gen_1 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 1; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 5.528025 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 1; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "blk_mem_gen_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 0; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 32; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 32; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), addrb(9 downto 0) => addrb(9 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, dina(7 downto 0) => dina(7 downto 0), dinb(31) => '0', dinb(30) => '0', dinb(29) => '0', dinb(28) => '0', dinb(27) => '0', dinb(26) => '0', dinb(25) => '0', dinb(24) => '0', dinb(23) => '0', dinb(22) => '0', dinb(21) => '0', dinb(20) => '0', dinb(19) => '0', dinb(18) => '0', dinb(17) => '0', dinb(16) => '0', dinb(15) => '0', dinb(14) => '0', dinb(13) => '0', dinb(12) => '0', dinb(11) => '0', dinb(10) => '0', dinb(9) => '0', dinb(8) => '0', dinb(7) => '0', dinb(6) => '0', dinb(5) => '0', dinb(4) => '0', dinb(3) => '0', dinb(2) => '0', dinb(1) => '0', dinb(0) => '0', douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0), doutb(31 downto 0) => doutb(31 downto 0), eccpipece => '0', ena => '0', enb => enb, injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0), regcea => '0', regceb => '0', rsta => '0', rstb => '0', s_aclk => '0', s_aresetn => '0', s_axi_araddr(31) => '0', s_axi_araddr(30) => '0', s_axi_araddr(29) => '0', s_axi_araddr(28) => '0', s_axi_araddr(27) => '0', s_axi_araddr(26) => '0', s_axi_araddr(25) => '0', s_axi_araddr(24) => '0', s_axi_araddr(23) => '0', s_axi_araddr(22) => '0', s_axi_araddr(21) => '0', s_axi_araddr(20) => '0', s_axi_araddr(19) => '0', s_axi_araddr(18) => '0', s_axi_araddr(17) => '0', s_axi_araddr(16) => '0', s_axi_araddr(15) => '0', s_axi_araddr(14) => '0', s_axi_araddr(13) => '0', s_axi_araddr(12) => '0', s_axi_araddr(11) => '0', s_axi_araddr(10) => '0', s_axi_araddr(9) => '0', s_axi_araddr(8) => '0', s_axi_araddr(7) => '0', s_axi_araddr(6) => '0', s_axi_araddr(5) => '0', s_axi_araddr(4) => '0', s_axi_araddr(3) => '0', s_axi_araddr(2) => '0', s_axi_araddr(1) => '0', s_axi_araddr(0) => '0', s_axi_arburst(1) => '0', s_axi_arburst(0) => '0', s_axi_arid(3) => '0', s_axi_arid(2) => '0', s_axi_arid(1) => '0', s_axi_arid(0) => '0', s_axi_arlen(7) => '0', s_axi_arlen(6) => '0', s_axi_arlen(5) => '0', s_axi_arlen(4) => '0', s_axi_arlen(3) => '0', s_axi_arlen(2) => '0', s_axi_arlen(1) => '0', s_axi_arlen(0) => '0', s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2) => '0', s_axi_arsize(1) => '0', s_axi_arsize(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31) => '0', s_axi_awaddr(30) => '0', s_axi_awaddr(29) => '0', s_axi_awaddr(28) => '0', s_axi_awaddr(27) => '0', s_axi_awaddr(26) => '0', s_axi_awaddr(25) => '0', s_axi_awaddr(24) => '0', s_axi_awaddr(23) => '0', s_axi_awaddr(22) => '0', s_axi_awaddr(21) => '0', s_axi_awaddr(20) => '0', s_axi_awaddr(19) => '0', s_axi_awaddr(18) => '0', s_axi_awaddr(17) => '0', s_axi_awaddr(16) => '0', s_axi_awaddr(15) => '0', s_axi_awaddr(14) => '0', s_axi_awaddr(13) => '0', s_axi_awaddr(12) => '0', s_axi_awaddr(11) => '0', s_axi_awaddr(10) => '0', s_axi_awaddr(9) => '0', s_axi_awaddr(8) => '0', s_axi_awaddr(7) => '0', s_axi_awaddr(6) => '0', s_axi_awaddr(5) => '0', s_axi_awaddr(4) => '0', s_axi_awaddr(3) => '0', s_axi_awaddr(2) => '0', s_axi_awaddr(1) => '0', s_axi_awaddr(0) => '0', s_axi_awburst(1) => '0', s_axi_awburst(0) => '0', s_axi_awid(3) => '0', s_axi_awid(2) => '0', s_axi_awid(1) => '0', s_axi_awid(0) => '0', s_axi_awlen(7) => '0', s_axi_awlen(6) => '0', s_axi_awlen(5) => '0', s_axi_awlen(4) => '0', s_axi_awlen(3) => '0', s_axi_awlen(2) => '0', s_axi_awlen(1) => '0', s_axi_awlen(0) => '0', s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2) => '0', s_axi_awsize(1) => '0', s_axi_awsize(0) => '0', s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0), s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7) => '0', s_axi_wdata(6) => '0', s_axi_wdata(5) => '0', s_axi_wdata(4) => '0', s_axi_wdata(3) => '0', s_axi_wdata(2) => '0', s_axi_wdata(1) => '0', s_axi_wdata(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
------------------------------------------------------------------------------------------------- -- Company : CNES -- Author : Mickael Carl (CNES) -- Copyright : Copyright (c) CNES. -- Licensing : GNU GPLv3 ------------------------------------------------------------------------------------------------- -- Version : V1 -- Version history : -- V1 : 2015-04-08 : Mickael Carl (CNES): Creation ------------------------------------------------------------------------------------------------- -- File name : STD_00400_bad.vhd -- File Creation date : 2015-04-08 -- Project name : VHDL Handbook CNES Edition ------------------------------------------------------------------------------------------------- -- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor) ------------------------------------------------------------------------------------------------- -- Description : Handbook example: Label for process: bad example -- -- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at -- demonstrating good practices in VHDL and as such, its design is minimalistic. -- It is provided as is, without any warranty. -- This example is compliant with the Handbook version 1. -- ------------------------------------------------------------------------------------------------- -- Naming conventions: -- -- i_Port: Input entity port -- o_Port: Output entity port -- b_Port: Bidirectional entity port -- g_My_Generic: Generic entity port -- -- c_My_Constant: Constant definition -- t_My_Type: Custom type definition -- -- My_Signal_n: Active low signal -- v_My_Variable: Variable -- sm_My_Signal: FSM signal -- pkg_Param: Element Param coming from a package -- -- My_Signal_re: Rising edge detection of My_Signal -- My_Signal_fe: Falling edge detection of My_Signal -- My_Signal_rX: X times registered My_Signal signal -- -- P_Process_Name: Process -- ------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity STD_00400_bad is port ( i_Clock : in std_logic; -- Clock signal i_Reset_n : in std_logic; -- Reset signal i_D : in std_logic; -- D Flip-Flop input signal o_Q : out std_logic -- D Flip-Flop output signal ); end STD_00400_bad; architecture Behavioral of STD_00400_bad is signal Q : std_logic; -- D Flip-Flop output begin -- D FlipFlop process --CODE -- UNLABELLED PROCESS process(i_Clock, i_Reset_n) begin if (i_Reset_n = '0') then Q <= '0'; elsif (rising_edge(i_Clock)) then Q <= i_D; end if; end process; --CODE o_Q <= Q; end Behavioral;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 15 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0_15; USE axi_gpio_v2_0_15.axi_gpio; ENTITY zqynq_lab_1_design_axi_gpio_0_1 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END zqynq_lab_1_design_axi_gpio_0_1; ARCHITECTURE zqynq_lab_1_design_axi_gpio_0_1_arch OF zqynq_lab_1_design_axi_gpio_0_1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_0_1_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_gpio_0_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_gpio_0_1_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_0_1,axi_gpio,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_gpio_0_1_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_0_1,axi_gpio,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 8, C_GPIO2_WIDTH => 32, C_ALL_INPUTS => 0, C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 1, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), gpio_io_o => gpio_io_o, gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END zqynq_lab_1_design_axi_gpio_0_1_arch;
use work.c.all; package b is end package;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Mathematical Packages -- : (MATH_COMPLEX package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC VHDL Mathematical Packages Working Group -- : -- Purpose : This package defines a standard for designers to use in -- : describing VHDL models that make use of common COMPLEX -- : constants and common COMPLEX mathematical functions and -- : operators. -- : -- Limitation: The values generated by the functions in this package -- : may vary from platform to platform, and the precision -- : of results is only guaranteed to be the minimum required -- : by IEEE Std 1076-2008. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use WORK.MATH_REAL.all; package MATH_COMPLEX is constant CopyRightNotice : STRING := "Copyright 2008 IEEE. All rights reserved."; -- -- Type Definitions -- type COMPLEX is record RE : REAL; -- Real part IM : REAL; -- Imaginary part end record; subtype POSITIVE_REAL is REAL range 0.0 to REAL'high; subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI; type COMPLEX_POLAR is record MAG : POSITIVE_REAL; -- Magnitude ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal end record; -- -- Constant Definitions -- constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0); constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0); constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0); -- -- Overloaded equality and inequality operators for COMPLEX_POLAR -- (equality and inequality operators for COMPLEX are predefined) -- function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is equal to R and returns FALSE otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE -- regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "="(L,R) is either TRUE or FALSE -- Notes: -- None function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is not equal to R and returns FALSE -- otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns -- FALSE regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "/="(L,R) is either TRUE or FALSE -- Notes: -- None -- -- Function Declarations -- function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX; -- Purpose: -- Returns COMPLEX number X + iY -- Special values: -- None -- Domain: -- X in REAL -- Y in REAL -- Error conditions: -- None -- Range: -- CMPLX(X,Y) is mathematically unbounded -- Notes: -- None function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE; -- Purpose: -- Returns principal value of angle X; X in radians -- Special values: -- None -- Domain: -- X in REAL -- Error conditions: -- None -- Range: -- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI -- Notes: -- None function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR; -- Purpose: -- Returns principal value COMPLEX_POLAR of Z -- Special values: -- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0) -- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM), -- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX; -- Purpose: -- Returns COMPLEX value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- POLAR_TO_COMPLEX(Z) is mathematically unbounded -- Notes: -- None function "ABS"(Z : in COMPLEX) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(Z) is mathematically unbounded -- Notes: -- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- ABS(Z) >= 0.0 -- Notes: -- ABS(Z) = Z.MAG function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0 -- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0 -- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = ARCTAN(Z.IM, Z.RE) function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = Z.ARG function "-" (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns unary minus of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- Returns -x -jy for Z= x + jy function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of unary minus of Z -- Special values: -- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if -- Z.ARG /= 0.0 function CONJ (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns complex conjugate of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- CONJ(Z) is mathematically unbounded -- Notes: -- Returns x -jy for Z= x + jy function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of complex conjugate of Z -- Special values: -- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI function SQRT(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(MATH_CZERO) = MATH_CZERO -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- SQRT(Z) is mathematically unbounded -- Notes: -- None function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function EXP(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns exponential of Z -- Special values: -- EXP(MATH_CZERO) = MATH_CBASE_1 -- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI -- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and -- ABS(Z.IM) = MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- EXP(Z) is mathematically unbounded -- Notes: -- None function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of exponential of Z -- Special values: -- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and -- Z.ARG = 0.0 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- ABS(Z.ARG) = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns natural logarithm of Z -- Special values: -- LOG(MATH_CBASE_1) = MATH_CZERO -- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI) -- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2) -- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2) -- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG(Z) is mathematically unbounded -- Notes: -- None function LOG2(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 2 of Z -- Special values: -- LOG2(MATH_CBASE_1) = MATH_CZERO -- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG2(Z) is mathematically unbounded -- Notes: -- None function LOG10(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 10 of Z -- Special values: -- LOG10(MATH_CBASE_1) = MATH_CZERO -- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG10(Z) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of natural logarithm of Z -- Special values: -- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 2 of Z -- Special values: -- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 10 of Z -- Special values: -- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX; -- Purpose: -- Returns logarithm base BASE of Z -- Special values: -- LOG(MATH_CBASE_1, BASE) = MATH_CZERO -- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- LOG(Z,BASE) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base BASE of Z -- Special values: -- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SIN (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns sine of Z -- Special values: -- SIN(MATH_CZERO) = MATH_CZERO -- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of sine of Z -- Special values: -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COS (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns cosine of Z -- Special values: -- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0) -- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of cosine of Z -- Special values: -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = 0.0 -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SINH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic sine of Z -- Special values: -- SINH(MATH_CZERO) = MATH_CZERO -- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI -- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = MATH_PI_OVER_2 -- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- SIN(Z.IM)*SIN(Z.IM)) -- Notes: -- None function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic sine of Z -- Special values: -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COSH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic cosine of Z -- Special values: -- COSH(MATH_CZERO) = MATH_CBASE_1 -- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2 -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- COS(Z.IM)*COS(Z.IM)) -- Notes: -- None function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic cosine of Z -- Special values: -- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None -- -- Arithmetic Operators -- function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL and R /= 0.0 -- Error conditions: -- Error if R = 0.0 -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R /= 0.0 -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None end package MATH_COMPLEX;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Mathematical Packages -- : (MATH_COMPLEX package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC VHDL Mathematical Packages Working Group -- : -- Purpose : This package defines a standard for designers to use in -- : describing VHDL models that make use of common COMPLEX -- : constants and common COMPLEX mathematical functions and -- : operators. -- : -- Limitation: The values generated by the functions in this package -- : may vary from platform to platform, and the precision -- : of results is only guaranteed to be the minimum required -- : by IEEE Std 1076-2008. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use WORK.MATH_REAL.all; package MATH_COMPLEX is constant CopyRightNotice : STRING := "Copyright 2008 IEEE. All rights reserved."; -- -- Type Definitions -- type COMPLEX is record RE : REAL; -- Real part IM : REAL; -- Imaginary part end record; subtype POSITIVE_REAL is REAL range 0.0 to REAL'high; subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI; type COMPLEX_POLAR is record MAG : POSITIVE_REAL; -- Magnitude ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal end record; -- -- Constant Definitions -- constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0); constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0); constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0); -- -- Overloaded equality and inequality operators for COMPLEX_POLAR -- (equality and inequality operators for COMPLEX are predefined) -- function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is equal to R and returns FALSE otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE -- regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "="(L,R) is either TRUE or FALSE -- Notes: -- None function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is not equal to R and returns FALSE -- otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns -- FALSE regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "/="(L,R) is either TRUE or FALSE -- Notes: -- None -- -- Function Declarations -- function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX; -- Purpose: -- Returns COMPLEX number X + iY -- Special values: -- None -- Domain: -- X in REAL -- Y in REAL -- Error conditions: -- None -- Range: -- CMPLX(X,Y) is mathematically unbounded -- Notes: -- None function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE; -- Purpose: -- Returns principal value of angle X; X in radians -- Special values: -- None -- Domain: -- X in REAL -- Error conditions: -- None -- Range: -- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI -- Notes: -- None function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR; -- Purpose: -- Returns principal value COMPLEX_POLAR of Z -- Special values: -- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0) -- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM), -- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX; -- Purpose: -- Returns COMPLEX value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- POLAR_TO_COMPLEX(Z) is mathematically unbounded -- Notes: -- None function "ABS"(Z : in COMPLEX) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(Z) is mathematically unbounded -- Notes: -- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- ABS(Z) >= 0.0 -- Notes: -- ABS(Z) = Z.MAG function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0 -- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0 -- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = ARCTAN(Z.IM, Z.RE) function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = Z.ARG function "-" (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns unary minus of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- Returns -x -jy for Z= x + jy function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of unary minus of Z -- Special values: -- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if -- Z.ARG /= 0.0 function CONJ (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns complex conjugate of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- CONJ(Z) is mathematically unbounded -- Notes: -- Returns x -jy for Z= x + jy function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of complex conjugate of Z -- Special values: -- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI function SQRT(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(MATH_CZERO) = MATH_CZERO -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- SQRT(Z) is mathematically unbounded -- Notes: -- None function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function EXP(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns exponential of Z -- Special values: -- EXP(MATH_CZERO) = MATH_CBASE_1 -- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI -- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and -- ABS(Z.IM) = MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- EXP(Z) is mathematically unbounded -- Notes: -- None function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of exponential of Z -- Special values: -- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and -- Z.ARG = 0.0 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- ABS(Z.ARG) = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns natural logarithm of Z -- Special values: -- LOG(MATH_CBASE_1) = MATH_CZERO -- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI) -- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2) -- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2) -- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG(Z) is mathematically unbounded -- Notes: -- None function LOG2(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 2 of Z -- Special values: -- LOG2(MATH_CBASE_1) = MATH_CZERO -- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG2(Z) is mathematically unbounded -- Notes: -- None function LOG10(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 10 of Z -- Special values: -- LOG10(MATH_CBASE_1) = MATH_CZERO -- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG10(Z) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of natural logarithm of Z -- Special values: -- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 2 of Z -- Special values: -- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 10 of Z -- Special values: -- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX; -- Purpose: -- Returns logarithm base BASE of Z -- Special values: -- LOG(MATH_CBASE_1, BASE) = MATH_CZERO -- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- LOG(Z,BASE) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base BASE of Z -- Special values: -- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SIN (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns sine of Z -- Special values: -- SIN(MATH_CZERO) = MATH_CZERO -- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of sine of Z -- Special values: -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COS (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns cosine of Z -- Special values: -- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0) -- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of cosine of Z -- Special values: -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = 0.0 -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SINH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic sine of Z -- Special values: -- SINH(MATH_CZERO) = MATH_CZERO -- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI -- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = MATH_PI_OVER_2 -- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- SIN(Z.IM)*SIN(Z.IM)) -- Notes: -- None function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic sine of Z -- Special values: -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COSH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic cosine of Z -- Special values: -- COSH(MATH_CZERO) = MATH_CBASE_1 -- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2 -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- COS(Z.IM)*COS(Z.IM)) -- Notes: -- None function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic cosine of Z -- Special values: -- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None -- -- Arithmetic Operators -- function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL and R /= 0.0 -- Error conditions: -- Error if R = 0.0 -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R /= 0.0 -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None end package MATH_COMPLEX;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Mathematical Packages -- : (MATH_COMPLEX package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC VHDL Mathematical Packages Working Group -- : -- Purpose : This package defines a standard for designers to use in -- : describing VHDL models that make use of common COMPLEX -- : constants and common COMPLEX mathematical functions and -- : operators. -- : -- Limitation: The values generated by the functions in this package -- : may vary from platform to platform, and the precision -- : of results is only guaranteed to be the minimum required -- : by IEEE Std 1076-2008. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use WORK.MATH_REAL.all; package MATH_COMPLEX is constant CopyRightNotice : STRING := "Copyright 2008 IEEE. All rights reserved."; -- -- Type Definitions -- type COMPLEX is record RE : REAL; -- Real part IM : REAL; -- Imaginary part end record; subtype POSITIVE_REAL is REAL range 0.0 to REAL'high; subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI; type COMPLEX_POLAR is record MAG : POSITIVE_REAL; -- Magnitude ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal end record; -- -- Constant Definitions -- constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0); constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0); constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0); -- -- Overloaded equality and inequality operators for COMPLEX_POLAR -- (equality and inequality operators for COMPLEX are predefined) -- function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is equal to R and returns FALSE otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE -- regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "="(L,R) is either TRUE or FALSE -- Notes: -- None function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is not equal to R and returns FALSE -- otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns -- FALSE regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "/="(L,R) is either TRUE or FALSE -- Notes: -- None -- -- Function Declarations -- function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX; -- Purpose: -- Returns COMPLEX number X + iY -- Special values: -- None -- Domain: -- X in REAL -- Y in REAL -- Error conditions: -- None -- Range: -- CMPLX(X,Y) is mathematically unbounded -- Notes: -- None function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE; -- Purpose: -- Returns principal value of angle X; X in radians -- Special values: -- None -- Domain: -- X in REAL -- Error conditions: -- None -- Range: -- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI -- Notes: -- None function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR; -- Purpose: -- Returns principal value COMPLEX_POLAR of Z -- Special values: -- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0) -- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM), -- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX; -- Purpose: -- Returns COMPLEX value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- POLAR_TO_COMPLEX(Z) is mathematically unbounded -- Notes: -- None function "ABS"(Z : in COMPLEX) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(Z) is mathematically unbounded -- Notes: -- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- ABS(Z) >= 0.0 -- Notes: -- ABS(Z) = Z.MAG function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0 -- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0 -- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = ARCTAN(Z.IM, Z.RE) function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = Z.ARG function "-" (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns unary minus of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- Returns -x -jy for Z= x + jy function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of unary minus of Z -- Special values: -- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if -- Z.ARG /= 0.0 function CONJ (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns complex conjugate of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- CONJ(Z) is mathematically unbounded -- Notes: -- Returns x -jy for Z= x + jy function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of complex conjugate of Z -- Special values: -- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI function SQRT(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(MATH_CZERO) = MATH_CZERO -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- SQRT(Z) is mathematically unbounded -- Notes: -- None function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function EXP(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns exponential of Z -- Special values: -- EXP(MATH_CZERO) = MATH_CBASE_1 -- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI -- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and -- ABS(Z.IM) = MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- EXP(Z) is mathematically unbounded -- Notes: -- None function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of exponential of Z -- Special values: -- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and -- Z.ARG = 0.0 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- ABS(Z.ARG) = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns natural logarithm of Z -- Special values: -- LOG(MATH_CBASE_1) = MATH_CZERO -- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI) -- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2) -- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2) -- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG(Z) is mathematically unbounded -- Notes: -- None function LOG2(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 2 of Z -- Special values: -- LOG2(MATH_CBASE_1) = MATH_CZERO -- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG2(Z) is mathematically unbounded -- Notes: -- None function LOG10(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 10 of Z -- Special values: -- LOG10(MATH_CBASE_1) = MATH_CZERO -- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG10(Z) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of natural logarithm of Z -- Special values: -- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 2 of Z -- Special values: -- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 10 of Z -- Special values: -- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX; -- Purpose: -- Returns logarithm base BASE of Z -- Special values: -- LOG(MATH_CBASE_1, BASE) = MATH_CZERO -- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- LOG(Z,BASE) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base BASE of Z -- Special values: -- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SIN (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns sine of Z -- Special values: -- SIN(MATH_CZERO) = MATH_CZERO -- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of sine of Z -- Special values: -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COS (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns cosine of Z -- Special values: -- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0) -- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of cosine of Z -- Special values: -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = 0.0 -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SINH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic sine of Z -- Special values: -- SINH(MATH_CZERO) = MATH_CZERO -- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI -- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = MATH_PI_OVER_2 -- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- SIN(Z.IM)*SIN(Z.IM)) -- Notes: -- None function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic sine of Z -- Special values: -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COSH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic cosine of Z -- Special values: -- COSH(MATH_CZERO) = MATH_CBASE_1 -- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2 -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- COS(Z.IM)*COS(Z.IM)) -- Notes: -- None function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic cosine of Z -- Special values: -- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None -- -- Arithmetic Operators -- function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL and R /= 0.0 -- Error conditions: -- Error if R = 0.0 -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R /= 0.0 -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None end package MATH_COMPLEX;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Mathematical Packages -- : (MATH_COMPLEX package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC VHDL Mathematical Packages Working Group -- : -- Purpose : This package defines a standard for designers to use in -- : describing VHDL models that make use of common COMPLEX -- : constants and common COMPLEX mathematical functions and -- : operators. -- : -- Limitation: The values generated by the functions in this package -- : may vary from platform to platform, and the precision -- : of results is only guaranteed to be the minimum required -- : by IEEE Std 1076-2008. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use WORK.MATH_REAL.all; package MATH_COMPLEX is constant CopyRightNotice : STRING := "Copyright 2008 IEEE. All rights reserved."; -- -- Type Definitions -- type COMPLEX is record RE : REAL; -- Real part IM : REAL; -- Imaginary part end record; subtype POSITIVE_REAL is REAL range 0.0 to REAL'high; subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI; type COMPLEX_POLAR is record MAG : POSITIVE_REAL; -- Magnitude ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal end record; -- -- Constant Definitions -- constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0); constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0); constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0); -- -- Overloaded equality and inequality operators for COMPLEX_POLAR -- (equality and inequality operators for COMPLEX are predefined) -- function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is equal to R and returns FALSE otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE -- regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "="(L,R) is either TRUE or FALSE -- Notes: -- None function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN; -- Purpose: -- Returns TRUE if L is not equal to R and returns FALSE -- otherwise -- Special values: -- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns -- FALSE regardless of the value of X and Y. -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- "/="(L,R) is either TRUE or FALSE -- Notes: -- None -- -- Function Declarations -- function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX; -- Purpose: -- Returns COMPLEX number X + iY -- Special values: -- None -- Domain: -- X in REAL -- Y in REAL -- Error conditions: -- None -- Range: -- CMPLX(X,Y) is mathematically unbounded -- Notes: -- None function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE; -- Purpose: -- Returns principal value of angle X; X in radians -- Special values: -- None -- Domain: -- X in REAL -- Error conditions: -- None -- Range: -- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI -- Notes: -- None function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR; -- Purpose: -- Returns principal value COMPLEX_POLAR of Z -- Special values: -- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0) -- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM), -- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX; -- Purpose: -- Returns COMPLEX value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- POLAR_TO_COMPLEX(Z) is mathematically unbounded -- Notes: -- None function "ABS"(Z : in COMPLEX) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(Z) is mathematically unbounded -- Notes: -- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM) function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL; -- Purpose: -- Returns absolute value (magnitude) of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- ABS(Z) >= 0.0 -- Notes: -- ABS(Z) = Z.MAG function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0 -- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0 -- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = ARCTAN(Z.IM, Z.RE) function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE; -- Purpose: -- Returns argument (angle) in radians of the principal -- value of Z -- Special values: -- None -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- -MATH_PI < ARG(Z) <= MATH_PI -- Notes: -- ARG(Z) = Z.ARG function "-" (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns unary minus of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- Returns -x -jy for Z= x + jy function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of unary minus of Z -- Special values: -- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if -- Z.ARG /= 0.0 function CONJ (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns complex conjugate of Z -- Special values: -- None -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- CONJ(Z) is mathematically unbounded -- Notes: -- Returns x -jy for Z= x + jy function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of complex conjugate of Z -- Special values: -- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI function SQRT(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(MATH_CZERO) = MATH_CZERO -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- SQRT(Z) is mathematically unbounded -- Notes: -- None function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns square root of Z with positive real part -- or, if the real part is zero, the one with nonnegative -- imaginary part -- Special values: -- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function EXP(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns exponential of Z -- Special values: -- EXP(MATH_CZERO) = MATH_CBASE_1 -- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI -- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and -- ABS(Z.IM) = MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- EXP(Z) is mathematically unbounded -- Notes: -- None function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of exponential of Z -- Special values: -- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and -- Z.ARG = 0.0 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- ABS(Z.ARG) = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = MATH_PI_OVER_2 -- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if -- Z.MAG = MATH_PI_OVER_2 and -- Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns natural logarithm of Z -- Special values: -- LOG(MATH_CBASE_1) = MATH_CZERO -- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI) -- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2) -- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2) -- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG(Z) is mathematically unbounded -- Notes: -- None function LOG2(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 2 of Z -- Special values: -- LOG2(MATH_CBASE_1) = MATH_CZERO -- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG2(Z) is mathematically unbounded -- Notes: -- None function LOG10(Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns logarithm base 10 of Z -- Special values: -- LOG10(MATH_CBASE_1) = MATH_CZERO -- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Range: -- LOG10(Z) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of natural logarithm of Z -- Special values: -- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if -- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2 -- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 2 of Z -- Special values: -- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base 10 of Z -- Special values: -- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX; -- Purpose: -- Returns logarithm base BASE of Z -- Special values: -- LOG(MATH_CBASE_1, BASE) = MATH_CZERO -- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0) -- Domain: -- Z in COMPLEX and ABS(Z) /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if ABS(Z) = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- LOG(Z,BASE) is mathematically unbounded -- Notes: -- None function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of logarithm base BASE of Z -- Special values: -- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and -- Z.ARG = 0.0 -- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Z.MAG /= 0.0 -- BASE > 0.0 -- BASE /= 1.0 -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Error if Z.MAG = 0.0 -- Error if BASE <= 0.0 -- Error if BASE = 1.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SIN (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns sine of Z -- Special values: -- SIN(MATH_CZERO) = MATH_CZERO -- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of sine of Z -- Special values: -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = 0.0 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COS (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns cosine of Z -- Special values: -- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0) -- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0) -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) + -- SINH(Z.IM)*SINH(Z.IM)) -- Notes: -- None function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of cosine of Z -- Special values: -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = 0.0 -- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2 -- and Z.ARG = MATH_PI -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function SINH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic sine of Z -- Special values: -- SINH(MATH_CZERO) = MATH_CZERO -- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI -- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = MATH_PI_OVER_2 -- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and -- Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- SIN(Z.IM)*SIN(Z.IM)) -- Notes: -- None function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic sine of Z -- Special values: -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function COSH (Z : in COMPLEX) return COMPLEX; -- Purpose: -- Returns hyperbolic cosine of Z -- Special values: -- COSH(MATH_CZERO) = MATH_CBASE_1 -- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2 -- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX -- Error conditions: -- None -- Range: -- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) + -- COS(Z.IM)*COS(Z.IM)) -- Notes: -- None function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns principal value of hyperbolic cosine of Z -- Special values: -- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and -- Z.ARG = 0.0 -- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and -- Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 -- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = -- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 -- Domain: -- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI -- Error conditions: -- Error if Z.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None -- -- Arithmetic Operators -- function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "+"(Z) is mathematically unbounded -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic addition of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "-"(Z) is mathematically unbounded -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic subtraction of L minus R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL -- Error conditions: -- None -- Range: -- "*"(Z) is mathematically unbounded -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- Error conditions: -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic multiplication of L and R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in REAL -- Error conditions: -- Error if L.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX and R /= MATH_CZERO -- Error conditions: -- Error if R = MATH_CZERO -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX; R : in REAL) return COMPLEX; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX -- R in REAL and R /= 0.0 -- Error conditions: -- Error if R = 0.0 -- Range: -- "/"(Z) is mathematically unbounded -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if L.ARG = -MATH_PI -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in REAL -- R in COMPLEX_POLAR and R.ARG /= -MATH_PI -- R.MAG > 0.0 -- Error conditions: -- Error if R.MAG <= 0.0 -- Error if R.ARG = -MATH_PI -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR; -- Purpose: -- Returns arithmetic division of L by R -- Special values: -- None -- Domain: -- L in COMPLEX_POLAR and L.ARG /= -MATH_PI -- R /= 0.0 -- Error conditions: -- Error if L.ARG = -MATH_PI -- Error if R = 0.0 -- Range: -- result.MAG >= 0.0 -- -MATH_PI < result.ARG <= MATH_PI -- Notes: -- None end package MATH_COMPLEX;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL_ONE.VHD *** --*** *** --*** Function: Single Block Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del_one ; ARCHITECTURE rtl OF fp_del_one IS signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); BEGIN pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff(width DOWNTO 1) <= aa; END IF; END IF; END PROCESS; cc <= delff(width DOWNTO 1); END rtl;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Register7 is Port ( rst_n : in STD_LOGIC; clk : in STD_LOGIC; enable : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 6 DOWNTO 0 ); dout : out STD_LOGIC_VECTOR ( 6 DOWNTO 0 ) ); end Register7; architecture Behavioral of Register7 is signal data : STD_LOGIC_VECTOR ( 6 DOWNTO 0 ); --7 bit register begin PROCESS BEGIN wait until clk'event AND clk = '1'; IF rst_n = '1' then data <= (others => '0'); elsif enable = '1' then data <= din; else data <= data; END IF; END PROCESS; dout <= data; end Behavioral;
package pack1 is type ma_t is array(1 downto 0) of bit_vector(1 downto 0); end pack1; use work.pack1.all; entity arraysub is generic(par1: bit_vector(3 downto 0)); end entity; architecture test of arraysub is signal s1, s2: ma_t; begin s1(1)<=par1(1 downto 0); s1(0)<=par1(3 downto 2); s2(1 downto 1) <= ( 1 => par1(3 downto 2) ); s2(0 downto 0) <= ( 0 => par1(1 downto 0) ); process is begin wait for 1 ns; assert s1 = ( "11", "11" ); assert s2 = ( "11", "11" ); wait; end process; end architecture; entity issue72 is end entity; architecture topi of issue72 is begin subi: entity work.arraysub generic map(par1=>"1111"); end architecture;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- architecture rtl of mul is begin mul : entity work.mul_inferred(rtl) generic map ( src1_bits => src1_bits, src2_bits => src2_bits ) port map ( unsgnd => unsgnd, src1 => src1, src2 => src2, result => result ); end;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block HebB+GugH4RJ9V1neJSyHrNTL9+RNhL1Sqheay4lsmNU+npLou6zm+Jemy7mzutun/vsUMF6TI32 3mTSenXHXQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block lIIfi4YdGCqyGowIA7Q/i2U1hL+tRoXGTwZKXY+9zGkxePWlWQMVP4UeGDy0F5o8z74Hkg9JW7ZD ooSMzIzhc3mTdEKRzCLp948n7ycgrtiwuGsKgRM0b5Y5QHihZcI4h8L52DVNXAH8566bjUyeo3pT oxnhmGlpU4AAx8ebgkE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block AEqzVUuNlyj29NwmwMc9ylB6/KVV9mNKlyHVy33DS+C6yMPZMjsBl5fF4uiahLWKw//GcyvGFZIz l3X9dpo1JI8CDQEi5Ji5rJbW0AmUyCbt1ATL1C7Eq9qoJ2GkaOwRXIVJp3Kr0X/DY/0m8tPdsF7i hRZ1o4sy6od8rtw7REd3sxL34OuAUo2VYHS0vnguWlbhzyrOanBuOOdlgWjgW4thfTlG+oDoRsWK kwo5WF8Y239ek56Pfv+GzSMyovJxLAOpkD0YruxbqwILExNaiO7UXGqYy0xZiLR3NedFTwaxPwYa mZgKMyhv6inqRc7cmwlM1hzX0CMNG03ae+jtqw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ZM0gIzl3Lf2XlyN041bRAEfV+j6OBCshLjBnB9T8UHK+MmzO/d7ZRNLRnsmenaspXz1O2ypIPkMx e5hVYF1Z69kjnqVccBL/tebv9nd/3Hn31RqvCdaVP9VleEErwMaWXxe3LnVYg6vmaT9aB01WrOhL cNTtYPU4CuA8qODY1nA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block azosIWxfe42jBLIVDwVuRnh2YSWA7XLkC9Zrc4/uTZRF7XhOlZxeJKUl/2+rkS6vJ4XyOmQx0hiq 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-- ------------------------------------------------------------- -- -- Generated Configuration for __COMMON__ -- -- Generated -- by: wig -- on: Mon Apr 10 13:26:55 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: bitsplice-c.vhd,v 1.1 2006/04/10 15:42:10 wig Exp $ -- $Date: 2006/04/10 15:42:10 $ -- $Log: bitsplice-c.vhd,v $ -- Revision 1.1 2006/04/10 15:42:10 wig -- Updated testcase (__TOP__) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.44 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e -- configuration inst_a_e_rtl_conf of inst_a_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_aa : ent_aa // __I_NO_CONFIG_VERILOG // use configuration work.ent_aa_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ab : ent_ab // __I_NO_CONFIG_VERILOG // use configuration work.ent_ab_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ac : ent_ac // __I_NO_CONFIG_VERILOG // use configuration work.ent_ac_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ad : ent_ad // __I_NO_CONFIG_VERILOG // use configuration work.ent_ad_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ae : ent_ae // __I_NO_CONFIG_VERILOG // use configuration work.ent_ae_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_a_e_rtl_conf; -- -- End of Generated Configuration inst_a_e_rtl_conf -- -- -- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e -- configuration inst_b_e_rtl_conf of inst_b_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_ba : ent_ba // __I_NO_CONFIG_VERILOG // use configuration work.ent_ba_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_bb : ent_bb // __I_NO_CONFIG_VERILOG // use configuration work.ent_bb_RTL_CONF; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_b_e_rtl_conf; -- -- End of Generated Configuration inst_b_e_rtl_conf -- -- -- Start of Generated Configuration inst_e_e_rtl_conf / inst_e_e -- configuration inst_e_e_rtl_conf of inst_e_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_ea : inst_ea_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ea_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_eb : inst_eb_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eb_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ec : inst_ec_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ec_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ed : inst_ed_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ed_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ee : inst_ee_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ee_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ef : inst_ef_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ef_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_eg : inst_eg_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eg_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_e_e_rtl_conf; -- -- End of Generated Configuration inst_e_e_rtl_conf -- -- -- Start of Generated Configuration inst_ea_e_rtl_conf / inst_ea_e -- configuration inst_ea_e_rtl_conf of inst_ea_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_eaa : inst_eaa_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eaa_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_eab : inst_eab_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eab_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_eac : inst_eac_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eac_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ead : inst_ead_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ead_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_ea_e_rtl_conf; -- -- End of Generated Configuration inst_ea_e_rtl_conf -- -- -- Start of Generated Configuration inst_eb_e_rtl_conf / inst_eb_e -- configuration inst_eb_e_rtl_conf of inst_eb_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_eba : inst_eba_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eba_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ebb : inst_ebb_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ebb_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ebc : inst_ebc_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ebc_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_eb_e_rtl_conf; -- -- End of Generated Configuration inst_eb_e_rtl_conf -- -- -- Start of Generated Configuration inst_ec_e_rtl_conf / inst_ec_e -- configuration inst_ec_e_rtl_conf of inst_ec_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_eca : inst_eca_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eca_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ecb : inst_ecb_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ecb_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_ecc : inst_ecc_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_ecc_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_ec_e_rtl_conf; -- -- End of Generated Configuration inst_ec_e_rtl_conf -- -- -- Start of Generated Configuration inst_ed_e_rtl_conf / inst_ed_e -- configuration inst_ed_e_rtl_conf of inst_ed_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_eda : inst_eda_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_eda_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_edb : inst_edb_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_edb_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_ed_e_rtl_conf; -- -- End of Generated Configuration inst_ed_e_rtl_conf -- -- -- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e -- configuration inst_t_e_rtl_conf of inst_t_e is for rtl -- Generated Configuration // __I_NO_CONFIG_VERILOG //for inst_a : inst_a_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_a_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_b : inst_b_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_b_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_c : inst_c_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_c_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_d : inst_d_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_d_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; // __I_NO_CONFIG_VERILOG //for inst_e : inst_e_e // __I_NO_CONFIG_VERILOG // use configuration work.inst_e_e_rtl_conf; // __I_NO_CONFIG_VERILOG //end for; end for; end inst_t_e_rtl_conf; -- -- End of Generated Configuration inst_t_e_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
library verilog; use verilog.vl_types.all; entity mss_clockgen is generic( CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0) ); port( SYSCLK : in vl_logic; F2MRESETN : in vl_logic; MSSRESETN : in vl_logic; ESRAM0_SOFTRESET: in vl_logic; ESRAM1_SOFTRESET: in vl_logic; ENVM_SOFTRESET : in vl_logic; EMC_SOFTRESET : in vl_logic; ACE_SOFTRESET : in vl_logic; FPGA_SOFTRESET : in vl_logic; USERRESETACTIVE : in vl_logic; PADRESETENABLE : in vl_logic; M3_HCLK : out vl_logic; PER0_PCLK : out vl_logic; PER1_PCLK : out vl_logic; ACE_PCLK : out vl_logic; ACE_HCLK : out vl_logic; M3_HRESETN : out vl_logic; FIC_HRESETN : out vl_logic; ESRAM0_HRESETN : out vl_logic; ESRAM1_HRESETN : out vl_logic; ENVM_HRESETN : out vl_logic; EMC_HRESETN : out vl_logic; ACE_PRESETN : out vl_logic; PER0_PRESETN : out vl_logic; PER1_PRESETN : out vl_logic; CORERESETN : out vl_logic; PER0_DIV : out vl_logic_vector(1 downto 0); PER1_DIV : out vl_logic_vector(1 downto 0); ACEPCLK_DIV : out vl_logic_vector(1 downto 0) ); attribute CLKDIVISORS_mti_vect_attrib : integer; attribute CLKDIVISORS_mti_vect_attrib of CLKDIVISORS : constant is 0; end mss_clockgen;
library verilog; use verilog.vl_types.all; entity mss_clockgen is generic( CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0) ); port( SYSCLK : in vl_logic; F2MRESETN : in vl_logic; MSSRESETN : in vl_logic; ESRAM0_SOFTRESET: in vl_logic; ESRAM1_SOFTRESET: in vl_logic; ENVM_SOFTRESET : in vl_logic; EMC_SOFTRESET : in vl_logic; ACE_SOFTRESET : in vl_logic; FPGA_SOFTRESET : in vl_logic; USERRESETACTIVE : in vl_logic; PADRESETENABLE : in vl_logic; M3_HCLK : out vl_logic; PER0_PCLK : out vl_logic; PER1_PCLK : out vl_logic; ACE_PCLK : out vl_logic; ACE_HCLK : out vl_logic; M3_HRESETN : out vl_logic; FIC_HRESETN : out vl_logic; ESRAM0_HRESETN : out vl_logic; ESRAM1_HRESETN : out vl_logic; ENVM_HRESETN : out vl_logic; EMC_HRESETN : out vl_logic; ACE_PRESETN : out vl_logic; PER0_PRESETN : out vl_logic; PER1_PRESETN : out vl_logic; CORERESETN : out vl_logic; PER0_DIV : out vl_logic_vector(1 downto 0); PER1_DIV : out vl_logic_vector(1 downto 0); ACEPCLK_DIV : out vl_logic_vector(1 downto 0) ); attribute CLKDIVISORS_mti_vect_attrib : integer; attribute CLKDIVISORS_mti_vect_attrib of CLKDIVISORS : constant is 0; end mss_clockgen;
library verilog; use verilog.vl_types.all; entity mss_clockgen is generic( CLKDIVISORS : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0) ); port( SYSCLK : in vl_logic; F2MRESETN : in vl_logic; MSSRESETN : in vl_logic; ESRAM0_SOFTRESET: in vl_logic; ESRAM1_SOFTRESET: in vl_logic; ENVM_SOFTRESET : in vl_logic; EMC_SOFTRESET : in vl_logic; ACE_SOFTRESET : in vl_logic; FPGA_SOFTRESET : in vl_logic; USERRESETACTIVE : in vl_logic; PADRESETENABLE : in vl_logic; M3_HCLK : out vl_logic; PER0_PCLK : out vl_logic; PER1_PCLK : out vl_logic; ACE_PCLK : out vl_logic; ACE_HCLK : out vl_logic; M3_HRESETN : out vl_logic; FIC_HRESETN : out vl_logic; ESRAM0_HRESETN : out vl_logic; ESRAM1_HRESETN : out vl_logic; ENVM_HRESETN : out vl_logic; EMC_HRESETN : out vl_logic; ACE_PRESETN : out vl_logic; PER0_PRESETN : out vl_logic; PER1_PRESETN : out vl_logic; CORERESETN : out vl_logic; PER0_DIV : out vl_logic_vector(1 downto 0); PER1_DIV : out vl_logic_vector(1 downto 0); ACEPCLK_DIV : out vl_logic_vector(1 downto 0) ); attribute CLKDIVISORS_mti_vect_attrib : integer; attribute CLKDIVISORS_mti_vect_attrib of CLKDIVISORS : constant is 0; end mss_clockgen;
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 08.01.2013 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CTRL_TELEGRAM_CHECK is Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit BYTE_NUM : in std_logic_vector (7 downto 0); --Eingangsvariable, Bytenummer, 8bit NEXT_TELEGRAM : in std_logic; --Eingangsvariable, naechstes Telegramm TELEGRAM_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegrammlaenge, 8bit TELEGRAM_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegrammtyp, 4bit TELEGRAM_CMPLT : out std_logic; --Ausgangsvariable, Telegramm komplett -- DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen CLK : in std_logic; --Taktvariable CLK_IO : in std_logic; --Tanktvariable, --Ein- und Ausgangsregister IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich RESET : in std_logic); --1: Initialzustand annehmen -- DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl -- DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl -- DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl -- DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl end CTRL_TELEGRAM_CHECK; architecture Behavioral of CTRL_TELEGRAM_CHECK is type TYPE_STATE is (ST_TC_00, --Zustaende TELEGRAM_CHECK ST_TC_01, ST_TC_02, ST_TC_03, ST_TC_04, ST_TC_05, ST_TC_06, ST_TC_07, ST_TC_08, ST_TC_09, ST_TC_10, ST_TC_11, ST_TC_12, ST_TC_13); signal SV : TYPE_STATE; --Zustandsvariable signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master signal TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELEGRAM_LE_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELEGRAM_LEr_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister signal BYTE_NUM_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister signal NEXT_TELEGRAM_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister Signal FIRST_4_BITS : std_logic_vector (3 downto 0); -- Zwischenspeicher der ersten 4 bit von BYTE_IN_S --signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand, Anzeige, in 8 Bit, binär --signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand, Anzeige, in 8 Bit, binär signal not_CLK : std_logic; --negierte Taktvariable signal not_CLK_IO: std_logic; --negierte Taktvariable --Ein- und Ausgangsregister begin NOT_CLK_PROC: process (CLK) --negieren Taktvariable begin not_CLK <= not CLK; end process; NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible --Ein- und Ausgangsregister begin not_CLK_IO <= not CLK_IO; end process; IREG_PROC: process (not_CLK_IO) --Eingangsregister begin if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister then BYTE_IN_S <= BYTE_IN; BYTE_NUM_S <= BYTE_NUM; NEXT_TELEGRAM_S <= NEXT_TELEGRAM; end if; end process; SREG_M_PROC: process (RESET, n_SV, CLK) --Master begin if (RESET ='1') then SV_M <= ST_TC_00; else if (CLK'event and CLK = '1') then if (IN_NEXT_STATE = '1') then SV_M <= n_SV; TELE_COUNT_M <= n_TELE_COUNT; TELEGRAM_LE_M <= n_TELEGRAM_LE; TELEGRAM_LEr_M <= n_TELEGRAM_LEr; else SV_M <= SV_M; TELE_COUNT_M <= TELE_COUNT_M; TELEGRAM_LE_M <= TELEGRAM_LE_M; TELEGRAM_LEr_M <= TELEGRAM_LEr_M; end if; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave begin if (RESET = '1') then SV <= ST_TC_00; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; TELE_COUNT <= TELE_COUNT_M; TELEGRAM_LE <= TELEGRAM_LE_M; TELEGRAM_LEr <= TELEGRAM_LEr_M; end if; end if; end process; TELEGRAM_CHECK_PROC:process (BYTE_IN_S, BYTE_NUM_S, NEXT_TELEGRAM_S, SV, TELE_COUNT, FIRST_4_BITS, TELEGRAM_LE, TELEGRAM_LEr) --Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen begin case SV is when ST_TC_00 => if (NEXT_TELEGRAM_S = '1') then -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_01; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end if; when ST_TC_01 => if (BYTE_NUM_S = x"01") -- Eins then -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_02; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_01; -- bleibt im aktuellen Zustand end if; when ST_TC_02 => if (FIRST_4_BITS = "0001") -- SD1 then -- TC02 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_03; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_04; -- Zustandsuebergang end if; when ST_TC_03 => if (BYTE_NUM_S = x"06") -- 6 Byte Laenge then -- TC04 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC03 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_03; -- bleibt im aktuellen Zustand end if; when ST_TC_04 => if (FIRST_4_BITS = "1010") -- SD3 then -- TC05 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_05; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; -- bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_06; -- Zustandsuebergang end if; when ST_TC_05 => if (BYTE_NUM_S = x"07") -- 7 Byte Laenge then -- TC07 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC06 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_05; -- bleibt im aktuellen Zustand end if; when ST_TC_06 => if (FIRST_4_BITS = "1101") -- SD4 then -- TC08 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_07; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_08; -- Zustandsuebergang end if; when ST_TC_07 => if (BYTE_NUM_S = x"03") -- 3 Byte Laenge then -- TC10 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC09 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_07; -- Zustandsuebergang end if; when ST_TC_08 => if (FIRST_4_BITS = "1110") -- SC then -- TC11 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "1000"; -- 8 fur SC TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_09; -- Zustandsuebergang end if; when ST_TC_09 => if (FIRST_4_BITS = "0110") -- SD2 then -- TC12 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- evtl. n_TELE_COUNT hier n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_10; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; -- Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_00; -- Zustandsuebergang end if; when ST_TC_10 => if (BYTE_NUM_S = x"02") -- 2. Byte then -- TC14 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= BYTE_IN_S; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_11; -- Zustandsuebergang else -- TC13 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_10; -- bleibt im aktuellen Zustand end if; when ST_TC_11 => if (BYTE_NUM_S = x"03") -- 3. Byte then -- TC16 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= BYTE_IN_S; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_12; -- Zustandsuebergang else -- TC15 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= BYTE_IN_S; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_11; -- bleibt im aktuellen Zustand end if; when ST_TC_12 => if (TELEGRAM_LE = TELEGRAM_LEr) -- Vergleich ob Laenge uebereinstimmt then -- TC17 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_13; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end if; when ST_TC_13 => if (BYTE_NUM_S = TELEGRAM_LE) -- Wenn ermittelte Laenge eintritt then -- TC19 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC18 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_13; -- bleibt im aktuellen Zustand end if; when others => -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end case; end process; BYTE_IN_8_TO_4_PROC: process (BYTE_IN_S) -- Umwandlung von BYTE_IN zu FIRST_4_BITS begin FIRST_4_BITS(0) <= BYTE_IN_S(0); FIRST_4_BITS(1) <= BYTE_IN_S(1); FIRST_4_BITS(2) <= BYTE_IN_S(2); FIRST_4_BITS(3) <= BYTE_IN_S(3); end process; --STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, TELE_COUNT) -- Zustandsanzeige -- begin -- STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit -- STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8); --anktuellen Zustand anzeigen -- DISPL1_SV(0) <= STATE_SV(0); --Bit0 -- DISPL1_SV(1) <= STATE_SV(1); --Bit1 -- DISPL1_SV(2) <= STATE_SV(2); --Bit2 -- DISPL1_SV(3) <= STATE_SV(3); --Bit3 -- DISPL2_SV(0) <= STATE_SV(4); --usw. -- DISPL2_SV(1) <= STATE_SV(5); -- DISPL2_SV(2) <= STATE_SV(6); -- DISPL2_SV(3) <= STATE_SV(7); -- if (DISPL_COUNT ='0') --Original -- then --Folgezustand anzeigen -- DISPL1_n_SV(0) <= STATE_n_SV(0); -- DISPL1_n_SV(1) <= STATE_n_SV(1); -- DISPL1_n_SV(2) <= STATE_n_SV(2); -- DISPL1_n_SV(3) <= STATE_n_SV(3); -- DISPL2_n_SV(0) <= STATE_n_SV(4); -- DISPL2_n_SV(1) <= STATE_n_SV(5); -- DISPL2_n_SV(2) <= STATE_n_SV(6); -- DISPL2_n_SV(3) <= STATE_n_SV(7); -- else --Telegrammzaehler anzeigen -- DISPL1_n_SV(0) <= TELE_COUNT(0); -- DISPL1_n_SV(1) <= TELE_COUNT(1); -- DISPL1_n_SV(2) <= TELE_COUNT(2); -- DISPL1_n_SV(3) <= TELE_COUNT(3); -- DISPL2_n_SV(0) <= TELE_COUNT(4); -- DISPL2_n_SV(1) <= TELE_COUNT(5); -- DISPL2_n_SV(2) <= TELE_COUNT(6); -- DISPL2_n_SV(3) <= TELE_COUNT(7); -- end if; -- end process; end Behavioral;
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 08.01.2013 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CTRL_TELEGRAM_CHECK is Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit BYTE_NUM : in std_logic_vector (7 downto 0); --Eingangsvariable, Bytenummer, 8bit NEXT_TELEGRAM : in std_logic; --Eingangsvariable, naechstes Telegramm TELEGRAM_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegrammlaenge, 8bit TELEGRAM_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegrammtyp, 4bit TELEGRAM_CMPLT : out std_logic; --Ausgangsvariable, Telegramm komplett -- DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen CLK : in std_logic; --Taktvariable CLK_IO : in std_logic; --Tanktvariable, --Ein- und Ausgangsregister IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich RESET : in std_logic); --1: Initialzustand annehmen -- DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl -- DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl -- DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl -- DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl end CTRL_TELEGRAM_CHECK; architecture Behavioral of CTRL_TELEGRAM_CHECK is type TYPE_STATE is (ST_TC_00, --Zustaende TELEGRAM_CHECK ST_TC_01, ST_TC_02, ST_TC_03, ST_TC_04, ST_TC_05, ST_TC_06, ST_TC_07, ST_TC_08, ST_TC_09, ST_TC_10, ST_TC_11, ST_TC_12, ST_TC_13); signal SV : TYPE_STATE; --Zustandsvariable signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master signal TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELEGRAM_LE_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit signal n_TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert signal TELEGRAM_LEr_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister signal BYTE_NUM_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister signal NEXT_TELEGRAM_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister Signal FIRST_4_BITS : std_logic_vector (3 downto 0); -- Zwischenspeicher der ersten 4 bit von BYTE_IN_S --signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand, Anzeige, in 8 Bit, binär --signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand, Anzeige, in 8 Bit, binär signal not_CLK : std_logic; --negierte Taktvariable signal not_CLK_IO: std_logic; --negierte Taktvariable --Ein- und Ausgangsregister begin NOT_CLK_PROC: process (CLK) --negieren Taktvariable begin not_CLK <= not CLK; end process; NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible --Ein- und Ausgangsregister begin not_CLK_IO <= not CLK_IO; end process; IREG_PROC: process (not_CLK_IO) --Eingangsregister begin if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister then BYTE_IN_S <= BYTE_IN; BYTE_NUM_S <= BYTE_NUM; NEXT_TELEGRAM_S <= NEXT_TELEGRAM; end if; end process; SREG_M_PROC: process (RESET, n_SV, CLK) --Master begin if (RESET ='1') then SV_M <= ST_TC_00; else if (CLK'event and CLK = '1') then if (IN_NEXT_STATE = '1') then SV_M <= n_SV; TELE_COUNT_M <= n_TELE_COUNT; TELEGRAM_LE_M <= n_TELEGRAM_LE; TELEGRAM_LEr_M <= n_TELEGRAM_LEr; else SV_M <= SV_M; TELE_COUNT_M <= TELE_COUNT_M; TELEGRAM_LE_M <= TELEGRAM_LE_M; TELEGRAM_LEr_M <= TELEGRAM_LEr_M; end if; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave begin if (RESET = '1') then SV <= ST_TC_00; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; TELE_COUNT <= TELE_COUNT_M; TELEGRAM_LE <= TELEGRAM_LE_M; TELEGRAM_LEr <= TELEGRAM_LEr_M; end if; end if; end process; TELEGRAM_CHECK_PROC:process (BYTE_IN_S, BYTE_NUM_S, NEXT_TELEGRAM_S, SV, TELE_COUNT, FIRST_4_BITS, TELEGRAM_LE, TELEGRAM_LEr) --Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen begin case SV is when ST_TC_00 => if (NEXT_TELEGRAM_S = '1') then -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_01; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end if; when ST_TC_01 => if (BYTE_NUM_S = x"01") -- Eins then -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_02; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_01; -- bleibt im aktuellen Zustand end if; when ST_TC_02 => if (FIRST_4_BITS = "0001") -- SD1 then -- TC02 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_03; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_04; -- Zustandsuebergang end if; when ST_TC_03 => if (BYTE_NUM_S = x"06") -- 6 Byte Laenge then -- TC04 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC03 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0001"; -- Eins fur SD1 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_03; -- bleibt im aktuellen Zustand end if; when ST_TC_04 => if (FIRST_4_BITS = "1010") -- SD3 then -- TC05 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_05; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; -- bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_06; -- Zustandsuebergang end if; when ST_TC_05 => if (BYTE_NUM_S = x"07") -- 7 Byte Laenge then -- TC07 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC06 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- 3 fuer SD3 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_05; -- bleibt im aktuellen Zustand end if; when ST_TC_06 => if (FIRST_4_BITS = "1101") -- SD4 then -- TC08 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_07; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_08; -- Zustandsuebergang end if; when ST_TC_07 => if (BYTE_NUM_S = x"03") -- 3 Byte Laenge then -- TC10 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC09 n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0100"; -- 4 fur SD4) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_07; -- Zustandsuebergang end if; when ST_TC_08 => if (FIRST_4_BITS = "1110") -- SC then -- TC11 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "1000"; -- 8 fur SC TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC01 n_TELE_COUNT <= TELE_COUNT; --bleibt gleich TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_09; -- Zustandsuebergang end if; when ST_TC_09 => if (FIRST_4_BITS = "0110") -- SD2 then -- TC12 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; -- evtl. n_TELE_COUNT hier n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_10; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; -- Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_00; -- Zustandsuebergang end if; when ST_TC_10 => if (BYTE_NUM_S = x"02") -- 2. Byte then -- TC14 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= BYTE_IN_S; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_11; -- Zustandsuebergang else -- TC13 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_10; -- bleibt im aktuellen Zustand end if; when ST_TC_11 => if (BYTE_NUM_S = x"03") -- 3. Byte then -- TC16 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= BYTE_IN_S; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_12; -- Zustandsuebergang else -- TC15 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= BYTE_IN_S; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_11; -- bleibt im aktuellen Zustand end if; when ST_TC_12 => if (TELEGRAM_LE = TELEGRAM_LEr) -- Vergleich ob Laenge uebereinstimmt then -- TC17 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_13; -- Zustandsuebergang else -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end if; when ST_TC_13 => if (BYTE_NUM_S = TELEGRAM_LE) -- Wenn ermittelte Laenge eintritt then -- TC19 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '1'; -- komplett n_SV <= ST_TC_00; -- Zustandsuebergang else -- TC18 n_TELE_COUNT <= TELE_COUNT+1; --erhoehen TELEGRAM_LENGTH <= TELE_COUNT; n_TELEGRAM_LE <= TELEGRAM_LE; n_TELEGRAM_LEr <= TELEGRAM_LEr; TELEGRAM_TYPE <= "0010"; -- 2 fur SD2 TELEGRAM_CMPLT <= '0'; n_SV <= ST_TC_13; -- bleibt im aktuellen Zustand end if; when others => -- TC00 n_TELE_COUNT <= x"00"; --Null (hex) TELEGRAM_LENGTH <= x"00"; -- Null (hex) n_TELEGRAM_LE <= x"00"; n_TELEGRAM_LEr <= x"00"; TELEGRAM_TYPE <= "0000"; -- Null (bin) TELEGRAM_CMPLT <= '0'; -- Null (bin) n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand end case; end process; BYTE_IN_8_TO_4_PROC: process (BYTE_IN_S) -- Umwandlung von BYTE_IN zu FIRST_4_BITS begin FIRST_4_BITS(0) <= BYTE_IN_S(0); FIRST_4_BITS(1) <= BYTE_IN_S(1); FIRST_4_BITS(2) <= BYTE_IN_S(2); FIRST_4_BITS(3) <= BYTE_IN_S(3); end process; --STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, TELE_COUNT) -- Zustandsanzeige -- begin -- STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit -- STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8); --anktuellen Zustand anzeigen -- DISPL1_SV(0) <= STATE_SV(0); --Bit0 -- DISPL1_SV(1) <= STATE_SV(1); --Bit1 -- DISPL1_SV(2) <= STATE_SV(2); --Bit2 -- DISPL1_SV(3) <= STATE_SV(3); --Bit3 -- DISPL2_SV(0) <= STATE_SV(4); --usw. -- DISPL2_SV(1) <= STATE_SV(5); -- DISPL2_SV(2) <= STATE_SV(6); -- DISPL2_SV(3) <= STATE_SV(7); -- if (DISPL_COUNT ='0') --Original -- then --Folgezustand anzeigen -- DISPL1_n_SV(0) <= STATE_n_SV(0); -- DISPL1_n_SV(1) <= STATE_n_SV(1); -- DISPL1_n_SV(2) <= STATE_n_SV(2); -- DISPL1_n_SV(3) <= STATE_n_SV(3); -- DISPL2_n_SV(0) <= STATE_n_SV(4); -- DISPL2_n_SV(1) <= STATE_n_SV(5); -- DISPL2_n_SV(2) <= STATE_n_SV(6); -- DISPL2_n_SV(3) <= STATE_n_SV(7); -- else --Telegrammzaehler anzeigen -- DISPL1_n_SV(0) <= TELE_COUNT(0); -- DISPL1_n_SV(1) <= TELE_COUNT(1); -- DISPL1_n_SV(2) <= TELE_COUNT(2); -- DISPL1_n_SV(3) <= TELE_COUNT(3); -- DISPL2_n_SV(0) <= TELE_COUNT(4); -- DISPL2_n_SV(1) <= TELE_COUNT(5); -- DISPL2_n_SV(2) <= TELE_COUNT(6); -- DISPL2_n_SV(3) <= TELE_COUNT(7); -- end if; -- end process; end Behavioral;
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <support@bitvis.no>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.types_pkg.all; use work.adaptations_pkg.all; package string_methods_pkg is -- Need a low level "alert" in the form of a simple assertion (as string handling may also fail) procedure bitvis_assert( val : boolean; severeness : severity_level; msg : string; scope : string ); function justify( val : string; justified : side; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string; -- DEPRECATED. -- Function will be removed in future versions of UVVM-Util function justify( val : string; width : natural := 0; justified : side := RIGHT; format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio ) return string; function pos_of_leftmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_rightmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_leftmost_non_zero( vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_rightmost_non_whitespace( vector : string; result_if_not_found : natural := 1 ) return natural; function valid_length( -- of string excluding trailing NULs vector : string ) return natural; function get_string_between_delimiters( val : string; delim_left : character; delim_right: character; start_from : SIDE; -- search from left or right (Only RIGHT implemented so far) occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence ) return string; function get_procedure_name_from_instance_name( val : string ) return string; function get_process_name_from_instance_name( val : string ) return string; function get_entity_name_from_instance_name( val : string ) return string; function return_string_if_true( val : string; return_val : boolean ) return string; function return_string1_if_true_otherwise_string2( val1 : string; val2 : string; return_val : boolean ) return string; function to_upper( val : string ) return string; function fill_string( val : character; width : natural ) return string; function pad_string( val : string; char : character; width : natural; side : side := LEFT ) return string; function replace_backslash_n_with_lf( source : string ) return string; function remove_initial_chars( source : string; num : natural ) return string; function wrap_lines( constant text_string : string; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc... constant line_width : natural ) return string; procedure wrap_lines( variable text_lines : inout line; constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix) constant alignment_pos2 : natural; constant line_width : natural ); procedure prefix_lines( variable text_lines : inout line; constant prefix : string := C_LOG_PREFIX ); function replace( val : string; target_char : character; exchange_char : character ) return string; procedure replace( variable text_line : inout line; target_char : character; exchange_char : character ); --======================================================== -- Handle missing overloads from 'standard_additions' --======================================================== function to_string( val : boolean; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string; function to_string( val : integer; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string; -- This function has been deprecated and will be removed in the next major release -- DEPRECATED function to_string( val : boolean; width : natural; justified : side := right; format: t_format_string := AS_IS ) return string; -- This function has been deprecated and will be removed in the next major release -- DEPRECATED function to_string( val : integer; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string; function to_string( val : std_logic_vector; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : unsigned; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : signed; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : t_byte_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; --======================================================== -- Handle types defined at lower levels --======================================================== function to_string( val : t_alert_level; width : natural; justified : side := right ) return string; function to_string( val : t_msg_id; width : natural; justified : side := right ) return string; function to_string( val : t_attention; width : natural; justified : side := right ) return string; procedure to_string( val : t_alert_attention_counters; order : t_order := FINAL ); function ascii_to_char( ascii_pos : integer range 0 to 255; ascii_allow : t_ascii_allow := ALLOW_ALL ) return character; function char_to_ascii( char : character ) return integer; -- return string with only valid ascii characters function to_string( val : string ) return string; function add_msg_delimiter( msg : string ) return string; end package string_methods_pkg; package body string_methods_pkg is -- Need a low level "alert" in the form of a simple assertion (as string handling may also fail) procedure bitvis_assert( val : boolean; severeness : severity_level; msg : string; scope : string ) is begin assert val report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > " & scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF severity severeness; end; function to_upper( val : string ) return string is variable v_result : string (val'range) := val; variable char : character; begin for i in val'range loop -- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit) if ( v_result(i) >= 'a' and v_result(i) <= 'z') then v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') ); end if; end loop; return v_result; end to_upper; function fill_string( val : character; width : natural ) return string is variable v_result : string (1 to maximum(1, width)); begin if (width = 0) then return ""; else for i in 1 to width loop v_result(i) := val; end loop; end if; return v_result; end fill_string; function pad_string( val : string; char : character; width : natural; side : side := LEFT ) return string is variable v_result : string (1 to maximum(1, width)); begin if (width = 0) then return ""; elsif (width <= val'length) then return val(1 to width); else v_result := (others => char); if side = LEFT then v_result(1 to val'length) := val; else v_result(v_result'length-val'length+1 to v_result'length) := val; end if; end if; return v_result; end pad_string; -- This procedure has been deprecated, and will be removed in the near future. function justify( val : string; width : natural := 0; justified : side := RIGHT; format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio ) return string is constant val_length : natural := val'length; variable result : string(1 to width) := (others => ' '); begin -- return val if width is too small if val_length >= width then if (format = TRUNCATE) then return val(1 to width); else return val; end if; end if; if justified = left then result(1 to val_length) := val; elsif justified = right then result(width - val_length + 1 to width) := val; end if; return result; end function; function justify( val : string; justified : side; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string is variable v_val_length : natural := val'length; variable v_formatted_val : string (1 to val'length); variable v_num_leading_space : natural := 1; variable v_result : string(1 to width) := (others => ' '); begin -- Remove leading space if format_spaces is SKIP_LEADING_SPACE if format_spaces = SKIP_LEADING_SPACE then -- Find how many leading spaces there are while( (val(v_num_leading_space) = ' ') and (v_num_leading_space < v_val_length)) loop v_num_leading_space := v_num_leading_space + 1; end loop; -- Remove leading space if any v_formatted_val := remove_initial_chars(val,v_num_leading_space); v_val_length := v_formatted_val'length; else v_formatted_val := val; end if; -- Truncate and return if the string is wider that allowed if v_val_length >= width then if (truncate = ALLOW_TRUNCATE) then return v_formatted_val(1 to width); else return v_formatted_val; end if; end if; -- Justify if string is within the width specifications if justified = left then v_result(1 to v_val_length) := v_formatted_val; elsif justified = right then v_result(width - v_val_length + 1 to width) := v_formatted_val; end if; return v_result; end function; function pos_of_leftmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()"); bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()"); for i in a_vector'left to a_vector'right loop if (a_vector(i) = target) then return i; end if; end loop; return result_if_not_found; end; function pos_of_rightmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()"); bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()"); for i in a_vector'right downto a_vector'left loop if (a_vector(i) = target) then return i; end if; end loop; return result_if_not_found; end; function pos_of_leftmost_non_zero( vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()"); for i in a_vector'left to a_vector'right loop if (a_vector(i) /= '0' and a_vector(i) /= ' ') then return i; end if; end loop; return result_if_not_found; end; function pos_of_rightmost_non_whitespace( vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()"); for i in a_vector'right downto a_vector'left loop if a_vector(i) /= ' ' then return i; end if; end loop; return result_if_not_found; end; function valid_length( -- of string excluding trailing NULs vector : string ) return natural is begin return pos_of_leftmost(NUL, vector, vector'length); end; function string_contains_char( val : string; char : character ) return boolean is alias a_val : string(1 to val'length) is val; begin if (val'length = 0) then return false; else for i in val'left to val'right loop if (val(i) = char) then return true; end if; end loop; -- falls through only if not found return false; end if; end; -- get_*_name -- Note: for sub-programs the following is given: library:package:procedure:object -- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object -- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg' -- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name) function get_string_between_delimiters( val : string; delim_left : character; delim_right: character; start_from : SIDE; -- search from left or right (Only RIGHT implemented so far) occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence ) return string is variable v_left : natural := 0; variable v_right : natural := 0; variable v_start : natural := val'length; variable v_occurrence : natural := 0; alias a_val : string(1 to val'length) is val; begin bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()"); bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()"); loop -- RIGHT v_left := 0; -- default v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0); if v_right > 0 then -- i.e. found L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter if (a_val(i) = delim_left) then v_left := i; v_start := i; -- Previous end delimeter could also be a start delimeter for next section v_occurrence := v_occurrence + 1; exit L1; end if; end loop; -- searching backwards end if; if v_right = 0 or v_left = 0 then return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between) end if; if v_occurrence = occurrence then -- Match if (v_right - v_left) < 2 then return ""; -- no chars in between delimeters else return a_val(v_left+1 to v_right-1); end if; end if; if v_start < 3 then return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between) end if; end loop; -- Will continue until match or not found end; -- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance' -- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance' -- - Process name: Search for 2nd last param in path name -- - Entity name: Search for 3nd last param in path name --':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned, -- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg' -- - Procedure name: Search for 2nd last param in path name and remove all inside [] function get_procedure_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()"); write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT)); if (string_contains_char(val, '@')) then write(v_msg_line, string'("Must be called with <sub-program object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()"); return v_line.all; end; function get_process_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()"); write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT)); if (string_contains_char(val, '[')) then write(v_msg_line, string'("Must be called with <process-local object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()"); return v_line.all; end; function get_entity_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()"); if string_contains_char(val, '@') then -- for path with instantiations write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT)); else -- for path with only a single entity write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT)); end if; if (string_contains_char(val, '[')) then write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()"); return v_line.all; end; function adjust_leading_0( val : string; format : t_format_zeros := SKIP_LEADING_0 ) return string is alias a_val : string(1 to val'length) is val; constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1); begin if val'length <= 1 then return val; end if; if format = SKIP_LEADING_0 then return a_val(leftmost_non_zero to val'length); else return a_val; end if; end function; function return_string_if_true( val : string; return_val : boolean ) return string is begin if return_val then return val; else return ""; end if; end function; function return_string1_if_true_otherwise_string2( val1 : string; val2 : string; return_val : boolean ) return string is begin if return_val then return val1; else return val2; end if; end function; function replace_backslash_n_with_lf( source : string ) return string is variable v_source_idx : natural := 0; variable v_dest_idx : natural := 0; variable v_dest : string(1 to source'length); begin if source'length = 0 then return ""; else if C_USE_BACKSLASH_N_AS_LF then loop v_source_idx := v_source_idx + 1; v_dest_idx := v_dest_idx + 1; if (v_source_idx < source'length) then if (source(v_source_idx to v_source_idx +1) /= "\n") then v_dest(v_dest_idx) := source(v_source_idx); else v_dest(v_dest_idx) := LF; v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed if (v_source_idx = source'length) then exit; end if; end if; else -- Final character in string v_dest(v_dest_idx) := source(v_source_idx); exit; end if; end loop; else v_dest := source; v_dest_idx := source'length; end if; return v_dest(1 to v_dest_idx); end if; end; function remove_initial_chars( source : string; num : natural ) return string is begin if source'length <= num then return ""; else return source(1 + num to source'right); end if; end; function wrap_lines( constant text_string : string; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2 constant line_width : natural ) return string is variable v_text_lines : line; variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions variable v_result_width : natural; begin write(v_text_lines, text_string); wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width); v_result_width := v_text_lines'length; bitvis_assert(v_result_width <= v_result'length, FAILURE, " String is too long after wrapping. Increase v_result string size.", "wrap_lines()"); v_result(1 to v_result_width) := v_text_lines.all; deallocate(v_text_lines); return v_result(1 to v_result_width); end; procedure wrap_lines( variable text_lines : inout line; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2 constant line_width : natural ) is variable v_string : string(1 to text_lines'length) := text_lines.all; variable v_string_width : natural := text_lines'length; variable v_line_no : natural := 0; variable v_last_string_wrap : natural := 0; variable v_min_string_wrap : natural; variable v_max_string_wrap : natural; begin deallocate(text_lines); -- empty the line prior to filling it up again l_line: loop -- For every tekstline found in text_lines v_line_no := v_line_no + 1; -- Find position to wrap in v_string if (v_line_no = 1) then v_min_string_wrap := 1; -- Minimum 1 character of input line v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width); write(text_lines, fill_string(' ', alignment_pos1 - 1)); else v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width); write(text_lines, fill_string(' ', alignment_pos2 - 1)); end if; -- 1. First handle any potential explicit line feed in the current maximum text line -- Search forward for potential LF for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop if (character(v_string(i)) = LF) then write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part v_last_string_wrap := i; next l_line; -- next line end if; end loop; -- 2. Then check if remaining text fits into a single text line if (v_string_width <= v_max_string_wrap) then -- No (more) wrapping required write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width)); exit; -- No more lines end if; -- 3. Search for blanks from char after max msg width and downwards (in the left direction) for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop if (character(v_string(i)) = ' ') then write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF v_last_string_wrap := i; if (i = v_string_width ) then exit l_line; end if; -- Skip any potential extra blanks in the string for j in (i+1) to v_string_width loop if (v_string(j) = ' ') then v_last_string_wrap := j; if (j = v_string_width ) then exit l_line; end if; else write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string exit; end if; end loop; next l_line; -- next line end if; end loop; -- 4. At this point no LF or blank is found in the searched section of the string. -- Hence just break the string - and continue. write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination v_last_string_wrap := v_max_string_wrap; end loop; end; procedure prefix_lines( variable text_lines : inout line; constant prefix : string := C_LOG_PREFIX ) is variable v_string : string(1 to text_lines'length) := text_lines.all; variable v_string_width : natural := text_lines'length; constant prefix_width : natural := prefix'length; variable v_last_string_wrap : natural := 0; variable i : natural := 0; -- for indexing v_string begin deallocate(text_lines); -- empty the line prior to filling it up again l_line : loop -- 1. Write prefix write(text_lines, prefix); -- 2. Write rest of text line (or rest of input line if no LF) l_char: loop i := i + 1; if (i < v_string_width) then if (character(v_string(i)) = LF) then write(text_lines, v_string((v_last_string_wrap + 1) to i)); v_last_string_wrap := i; exit l_char; end if; else -- 3. Reached end of string. Hence just write the rest. write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width)); -- But ensure new line with prefix if ending with LF if (v_string(i) = LF) then write(text_lines, prefix); end if; exit l_char; end if; end loop; if (i = v_string_width) then exit; end if; end loop; end; function replace( val : string; target_char : character; exchange_char : character ) return string is variable result : string(1 to val'length) := val; begin for i in val'range loop if val(i) = target_char then result(i) := exchange_char; end if; end loop; return result; end; procedure replace( variable text_line : inout line; target_char : character; exchange_char : character ) is variable v_string : string(1 to text_line'length) := text_line.all; variable v_string_width : natural := text_line'length; variable i : natural := 0; -- for indexing v_string begin if v_string_width > 0 then deallocate(text_line); -- empty the line prior to filling it up again -- 1. Loop through string and replace characters l_char: loop i := i + 1; if (i < v_string_width) then if (character(v_string(i)) = target_char) then v_string(i) := exchange_char; end if; else -- 2. Reached end of string. Hence just write the new string. write(text_line, v_string); exit l_char; end if; end loop; end if; end; --======================================================== -- Handle missing overloads from 'standard_additions' + advanced overloads --======================================================== function to_string( val : boolean; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string is begin return justify(to_string(val), justified, width, format_spaces, truncate); end; function to_string( val : integer; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string is begin return justify(to_string(val), justified, width, format_spaces, truncate); end; -- This function has been deprecated and will be removed in the next major release function to_string( val : boolean; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string is begin return justify(to_string(val), width, justified, format); end; -- This function has been deprecated and will be removed in the next major release function to_string( val : integer; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string is begin return justify(to_string(val), width, justified, format); end; function to_string( val : std_logic_vector; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; alias a_val : std_logic_vector(val'length - 1 downto 0) is val; variable v_result : string(1 to 10 + 2 * val'length); -- variable v_width : natural; variable v_use_end_char : boolean := false; begin if val'length = 0 then -- Value length is zero, -- return empty string. return ""; end if; if radix = BIN then if prefix = INCL_RADIX then write(v_line, string'("b""")); v_use_end_char := true; end if; write(v_line, adjust_leading_0(to_string(val), format)); elsif radix = HEX then if prefix = INCL_RADIX then write(v_line, string'("x""")); v_use_end_char := true; end if; write(v_line, adjust_leading_0(to_hstring(val), format)); elsif radix = DEC then if prefix = INCL_RADIX then write(v_line, string'("d""")); v_use_end_char := true; end if; -- Assuming that val is not signed if (val'length > 31) then write(v_line, to_hstring(val) & " (too wide to be converted to integer)" ); else write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format)); end if; elsif radix = HEX_BIN_IF_INVALID then if prefix = INCL_RADIX then write(v_line, string'("x""")); end if; if is_x(val) then write(v_line, adjust_leading_0(to_hstring(val), format)); if prefix = INCL_RADIX then write(v_line, string'("""")); -- terminate hex value end if; write(v_line, string'(" (b""")); write(v_line, adjust_leading_0(to_string(val), format)); write(v_line, string'("""")); write(v_line, string'(")")); else write(v_line, adjust_leading_0(to_hstring(val), format)); if prefix = INCL_RADIX then write(v_line, string'("""")); end if; end if; end if; if v_use_end_char then write(v_line, string'("""")); end if; v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end; function to_string( val : unsigned; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is begin return to_string(std_logic_vector(val), radix, format, prefix); end; function to_string( val : signed; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 10 + 2 * val'length); -- variable v_width : natural; variable v_use_end_char : boolean := false; begin -- Support negative numbers by _not_ using the slv overload when converting to decimal if radix = DEC then if val'length = 0 then -- Value length is zero, -- return empty string. return ""; end if; if prefix = INCL_RADIX then write(v_line, string'("d""")); v_use_end_char := true; end if; if (val'length > 32) then write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" ); else write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format)); end if; if v_use_end_char then write(v_line, string'("""")); end if; v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); else -- No decimal convertion: May be treated as slv, so use the slv overload return to_string(std_logic_vector(val), radix, format, prefix); end if; end; function to_string( val : t_byte_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 2 + -- parentheses 2*(val'length - 1) + -- commas 26 * val'length); -- 26 is max length of returned value from slv to_string() variable v_width : natural; begin if val'length = 0 then -- Value length is zero, -- return empty string. return ""; elsif val'length = 1 then -- Value length is 1 -- Return the single value it contains return to_string(val(val'low), radix, format, prefix); else -- Value length more than 1 -- Comma-separate all array members and return write(v_line, string'("(")); for i in val'range loop write(v_line, to_string(val(i), radix, format, prefix)); if i < val'right and val'ascending then write(v_line, string'(", ")); elsif i > val'right and not val'ascending then write(v_line, string'(", ")); end if; end loop; write(v_line, string'(")")); v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end if; end; --======================================================== -- Handle types defined at lower levels --======================================================== function to_string( val : t_alert_level; width : natural; justified : side := right ) return string is constant inner_string : string := t_alert_level'image(val); begin return to_upper(justify(inner_string, justified, width)); end function; function to_string( val : t_msg_id; width : natural; justified : side := right ) return string is constant inner_string : string := t_msg_id'image(val); begin return to_upper(justify(inner_string, justified, width)); end function; function to_string( val : t_attention; width : natural; justified : side := right ) return string is begin return to_upper(justify(t_attention'image(val), justified, width)); end; -- function to_string( -- dummy : t_void -- ) return string is -- begin -- return "VOID"; -- end function; procedure to_string( val : t_alert_attention_counters; order : t_order := FINAL ) is variable v_line : line; variable v_line_copy : line; variable v_status_failed : boolean := true; variable v_mismatch : boolean := false; variable v_header : string(1 to 42); constant prefix : string := C_LOG_PREFIX & " "; begin if order = INTERMEDIATE then v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***"; else -- order=FINAL v_header := "*** FINAL SUMMARY OF ALL ALERTS *** "; end if; write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & v_header & LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & " REGARDED EXPECTED IGNORED Comment?" & LF); for i in NOTE to t_alert_level'right loop write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity for j in t_attention'left to t_attention'right loop write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " "); end loop; if (val(i)(REGARD) = val(i)(EXPECT)) then write(v_line, " ok " & LF); else write(v_line, " *** " & to_string(i,0) & " *** " & LF); if (i > MANUAL_CHECK) then if (val(i)(REGARD) < val(i)(EXPECT)) then v_mismatch := true; else v_status_failed := false; end if; end if; end if; end loop; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF); -- Print a conclusion when called from the FINAL part of the test sequencer -- but not when called from in the middle of the test sequence (order=INTERMEDIATE) if order = FINAL then if not v_status_failed then write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF); elsif v_mismatch then write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF); else write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF); end if; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF); end if; wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length); prefix_lines(v_line, prefix); -- Write the info string to the target file write (v_line_copy, v_line.all & lf); -- copy line writeline(OUTPUT, v_line); writeline(LOG_FILE, v_line_copy); end; -- Convert from ASCII to character -- Inputs: -- ascii_pos (integer) : ASCII number input -- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters: -- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos -- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable function ascii_to_char( ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII ascii_allow : t_ascii_allow := ALLOW_ALL ) return character is variable v_printable : boolean := true; begin if ascii_pos < 32 or -- NUL, SOH, STX etc (ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159 v_printable := false; end if; if ascii_allow = ALLOW_ALL or (ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then return character'val(ascii_pos); else return ' '; -- Must return something when invisible control signals end if; end; -- Convert from character to ASCII integer function char_to_ascii( char : character ) return integer is begin return character'pos(char); end; -- return string with only valid ascii characters function to_string( val : string ) return string is variable v_new_string : string(1 to val'length); variable v_char_idx : natural := 0; variable v_ascii_pos : natural; begin for i in val'range loop v_ascii_pos := character'pos(val(i)); if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed. (v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159 -- illegal char null; else -- legal char v_char_idx := v_char_idx + 1; v_new_string(v_char_idx) := val(i); end if; end loop; if v_char_idx = 0 then return ""; else return v_new_string(1 to v_char_idx); end if; end; function add_msg_delimiter( msg : string ) return string is begin if msg'length /= 0 then if valid_length(msg) /= 1 then if msg(1) = C_MSG_DELIMITER then return msg; else return C_MSG_DELIMITER & msg & C_MSG_DELIMITER; end if; end if; end if; return ""; end; end package body string_methods_pkg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p05n02i01139ent IS END c06s05b00x00p05n02i01139ent; ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS BEGIN TESTING: PROCESS type ENUM1 is (M1, M2, M3, M4, M5); type ABASE is array (ENUM1 range <>) of BOOLEAN; subtype A1 is ABASE(ENUM1 range M1 to M5); function F(i : integer) return ENUM1 is begin return M2; end F; function G(j : integer) return ENUM1 is begin return M4; end G; variable ii : integer; variable jj : integer; variable V1 : A1 ; -- := (others=>TRUE); variable V4 : A1 ; -- := (others=>TRUE); variable V2, V3: ENUM1; BEGIN V1(M1 to M3) := V1(F(ii) to G(jj)); assert NOT(V1(M1 to M3)=(false,false,false)) report "***PASSED TEST: c06s05b00x00p05n02i01139" severity NOTE; assert (V1(M1 to M3)=(false,false,false)) report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p05n02i01139arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p05n02i01139ent IS END c06s05b00x00p05n02i01139ent; ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS BEGIN TESTING: PROCESS type ENUM1 is (M1, M2, M3, M4, M5); type ABASE is array (ENUM1 range <>) of BOOLEAN; subtype A1 is ABASE(ENUM1 range M1 to M5); function F(i : integer) return ENUM1 is begin return M2; end F; function G(j : integer) return ENUM1 is begin return M4; end G; variable ii : integer; variable jj : integer; variable V1 : A1 ; -- := (others=>TRUE); variable V4 : A1 ; -- := (others=>TRUE); variable V2, V3: ENUM1; BEGIN V1(M1 to M3) := V1(F(ii) to G(jj)); assert NOT(V1(M1 to M3)=(false,false,false)) report "***PASSED TEST: c06s05b00x00p05n02i01139" severity NOTE; assert (V1(M1 to M3)=(false,false,false)) report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p05n02i01139arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s05b00x00p05n02i01139ent IS END c06s05b00x00p05n02i01139ent; ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS BEGIN TESTING: PROCESS type ENUM1 is (M1, M2, M3, M4, M5); type ABASE is array (ENUM1 range <>) of BOOLEAN; subtype A1 is ABASE(ENUM1 range M1 to M5); function F(i : integer) return ENUM1 is begin return M2; end F; function G(j : integer) return ENUM1 is begin return M4; end G; variable ii : integer; variable jj : integer; variable V1 : A1 ; -- := (others=>TRUE); variable V4 : A1 ; -- := (others=>TRUE); variable V2, V3: ENUM1; BEGIN V1(M1 to M3) := V1(F(ii) to G(jj)); assert NOT(V1(M1 to M3)=(false,false,false)) report "***PASSED TEST: c06s05b00x00p05n02i01139" severity NOTE; assert (V1(M1 to M3)=(false,false,false)) report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." severity ERROR; wait; END PROCESS TESTING; END c06s05b00x00p05n02i01139arch;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:48:40 11/19/2013 -- Design Name: -- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/Tester_tb.vhd -- Project Name: Mips32_948282_19.11.2013 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Tester -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Tester_tb IS END Tester_tb; ARCHITECTURE behavior OF Tester_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Tester PORT( A : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Outputs signal A : std_logic_vector(15 downto 0); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Tester PORT MAP ( A => A ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; -- insert stimulus here wait; end process; END;
---------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov --! @brief Internal SRAM implementation with the byte access. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library commonlib; use commonlib.types_common.all; library techmap; use techmap.gencomp.all; use techmap.types_mem.all; --! AMBA system bus specific library. library ambalib; --! AXI4 configuration constants. use ambalib.types_amba4.all; entity srambytes_tech is generic ( memtech : integer := 0; abits : integer := 16; init_file : string := "" ); port ( clk : in std_logic; raddr : in global_addr_array_type; rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0); waddr : in global_addr_array_type; we : in std_logic; wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0) ); end; architecture rtl of srambytes_tech is --! reduced name of configuration constant: constant dw : integer := CFG_NASTI_ADDR_OFFSET; type local_addr_type is array (0 to CFG_NASTI_DATA_BYTES-1) of std_logic_vector(abits-dw-1 downto 0); signal address : local_addr_type; signal wr_ena : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); --! @brief Declaration of the one-byte SRAM element. --! @details This component is used for the FPGA implementation. component sram8_inferred is generic ( abits : integer := 12; byte_idx : integer := 0 ); port ( clk : in std_ulogic; address : in std_logic_vector(abits-1 downto 0); rdata : out std_logic_vector(7 downto 0); we : in std_logic; wdata : in std_logic_vector(7 downto 0) ); end component; --! @brief Declaration of the one-byte SRAM element with init function. --! @details This component is used for the RTL simulation. component sram8_inferred_init is generic ( abits : integer := 12; byte_idx : integer := 0; init_file : string ); port ( clk : in std_ulogic; address : in std_logic_vector(abits-1 downto 0); rdata : out std_logic_vector(7 downto 0); we : in std_logic; wdata : in std_logic_vector(7 downto 0) ); end component; begin --! Instantiate component for RTL simulation rtlsim0 : if memtech = inferred generate rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate wr_ena(n) <= we and wstrb(n); address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1' else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw); x0 : sram8_inferred_init generic map ( abits => abits-dw, byte_idx => n, init_file => init_file ) port map ( clk, address => address(n), rdata => rdata(8*(n+1)-1 downto 8*n), we => wr_ena(n), wdata => wdata(8*(n+1)-1 downto 8*n) ); end generate; -- cycle end generate; -- tech=inferred --! Instantiate component for FPGA (checked with Xilinx) fpgasim0 : if memtech /= inferred and is_fpga(memtech) /= 0 generate rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate wr_ena(n) <= we and wstrb(n); address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1' else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw); x0 : sram8_inferred generic map ( abits => abits-dw, byte_idx => n ) port map ( clk, address => address(n), rdata => rdata(8*(n+1)-1 downto 8*n), we => wr_ena(n), wdata => wdata(8*(n+1)-1 downto 8*n) ); end generate; -- cycle end generate; -- tech=inferred end;
---------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov --! @brief Internal SRAM implementation with the byte access. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library commonlib; use commonlib.types_common.all; library techmap; use techmap.gencomp.all; use techmap.types_mem.all; --! AMBA system bus specific library. library ambalib; --! AXI4 configuration constants. use ambalib.types_amba4.all; entity srambytes_tech is generic ( memtech : integer := 0; abits : integer := 16; init_file : string := "" ); port ( clk : in std_logic; raddr : in global_addr_array_type; rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0); waddr : in global_addr_array_type; we : in std_logic; wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0) ); end; architecture rtl of srambytes_tech is --! reduced name of configuration constant: constant dw : integer := CFG_NASTI_ADDR_OFFSET; type local_addr_type is array (0 to CFG_NASTI_DATA_BYTES-1) of std_logic_vector(abits-dw-1 downto 0); signal address : local_addr_type; signal wr_ena : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0); --! @brief Declaration of the one-byte SRAM element. --! @details This component is used for the FPGA implementation. component sram8_inferred is generic ( abits : integer := 12; byte_idx : integer := 0 ); port ( clk : in std_ulogic; address : in std_logic_vector(abits-1 downto 0); rdata : out std_logic_vector(7 downto 0); we : in std_logic; wdata : in std_logic_vector(7 downto 0) ); end component; --! @brief Declaration of the one-byte SRAM element with init function. --! @details This component is used for the RTL simulation. component sram8_inferred_init is generic ( abits : integer := 12; byte_idx : integer := 0; init_file : string ); port ( clk : in std_ulogic; address : in std_logic_vector(abits-1 downto 0); rdata : out std_logic_vector(7 downto 0); we : in std_logic; wdata : in std_logic_vector(7 downto 0) ); end component; begin --! Instantiate component for RTL simulation rtlsim0 : if memtech = inferred generate rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate wr_ena(n) <= we and wstrb(n); address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1' else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw); x0 : sram8_inferred_init generic map ( abits => abits-dw, byte_idx => n, init_file => init_file ) port map ( clk, address => address(n), rdata => rdata(8*(n+1)-1 downto 8*n), we => wr_ena(n), wdata => wdata(8*(n+1)-1 downto 8*n) ); end generate; -- cycle end generate; -- tech=inferred --! Instantiate component for FPGA (checked with Xilinx) fpgasim0 : if memtech /= inferred and is_fpga(memtech) /= 0 generate rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate wr_ena(n) <= we and wstrb(n); address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1' else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw); x0 : sram8_inferred generic map ( abits => abits-dw, byte_idx => n ) port map ( clk, address => address(n), rdata => rdata(8*(n+1)-1 downto 8*n), we => wr_ena(n), wdata => wdata(8*(n+1)-1 downto 8*n) ); end generate; -- cycle end generate; -- tech=inferred end;