content stringlengths 1 1.04M ⌀ |
|---|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: ram_dp_sr_sw.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the term... |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Fileo: pciwbsequ.vhd |
--| ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
switches : in STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0);
JOY_PUSH : in STD_LOGIC
)... |
component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library altera_mf;
use altera_mf.all;
entity fifo_com_tx is
generic
(
DEPTH : POSITIVE;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port
(
aclr : in std_logic;
... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - bett... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_15.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- ... |
-- manchester decoder test bench
--
-- test coverage includes all possible input manchester combinations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity manchester_dec_tb is
end manchester_dec_tb;
architecture behav of manchester_dec_tb is
component manchester_dec
po... |
------------------------------------------------------------------------------
-- @license MIT
-- @brief Histogram for Huffman encoding.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_72 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_72;
architecture BEHAVIO... |
----- Libraries ------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Counter is
port(
SW : in std_logic_vector(17 downto 16);
KEY0, KEY3 : in std_logic;
LEDR : out std_logic_vector(0 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end Counter;
... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
package pack0 is
constant foo : integer := 42;
constant v : bit_vector := "1010101";
constant q : bit_vector(3 downto 0) := X"F";
constant z : integer := 2;
end package;
-------------------------------------------------------------------------------
use work.pack0.all;
package pack1 is
function b... |
-- Design unit: DSP
-- Structural implementation
-- Included components: distortion_component, reverb
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
entity dsp is
port(
clk: in std_logic;
reset_n: in std_logic;
enable: in st... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits_vlg_check_tst is
port(
HEX0 : in vl_logic_vector(6 downto 0);
HEX1 : in vl_logic_vector(6 downto 0);
LEDR : in vl_logic_vector(4 downto 0);
sampler_rx : in vl_logi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_tx.vhd
-------------------------------------------------------------------------------
library IEEE;
use I... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx_dpa is
generic(
enable_soft_cdr_mode: string := "OFF";
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enabl... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:20:45 10/21/2015
-- Design Name:
-- Module Name: alu_decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B_Core is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;... |
library IEEE;
use IEEE.std_logic_1164.all;
entity FIR is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(3... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_ll64.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por ... |
-------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge, test controller entity declaration
--
-- Description:
-- Normal operation testcase
--
-- Author(s):
-- Guy Eschemann, guy@airhdl.com
--
-------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port
(srl_usn : out unsigned (8-1 downto 0);
sll_usn : out unsigned (8-1 downto 0);
srl_sgn : out signed (8-1 downto 0);
sll_sgn : out signed (8-1 downto 0));
end issue;
architecture beh of ... |
----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: test_cpu_top
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are... |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are... |
-------------------------------------------------------------------------------
--! @file dpRam-e.vhd
--
--! @brief Dual Port Ram Entity
--
--! @details This is the DPRAM entity
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in s... |
entity call3 is
end;
use work.pkg.all;
architecture behav of call3 is
procedure p (a : rec) is
begin
report natural'image (a.s'left);
report natural'image (a.s'right);
assert a.s'left = 1;
assert a.s'right = 4;
end;
begin
process
variable v : rec_4dyn;
begin
p (v);
wait;
end pro... |
entity call3 is
end;
use work.pkg.all;
architecture behav of call3 is
procedure p (a : rec) is
begin
report natural'image (a.s'left);
report natural'image (a.s'right);
assert a.s'left = 1;
assert a.s'right = 4;
end;
begin
process
variable v : rec_4dyn;
begin
p (v);
wait;
end pro... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
en... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART Transmitter ---------------------------------------------------------
entity uart_tx is
generic (
fullbit : integer );
port (
clk : in ... |
-------------------------------------------------------------------------------
-- Title : Helper Functions
-- Project :
-------------------------------------------------------------------------------
-- File : Helpers_Pkg.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-... |
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
en... |
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
en... |
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
en... |
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
en... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
architecture rtl of InputSwitchingMatrix is
signal CfgValue : std_logic_vector(InputWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => InputWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i =... |
architecture rtl of InputSwitchingMatrix is
signal CfgValue : std_logic_vector(InputWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => InputWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i =... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitt... |
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitt... |
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitt... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Latch is
port( clk : in std_logic;
d : in std_logic;
q : out std_logic);
end Latch;
architecture Behavioral of Latch is
begin
process (clk)
begin
if(clk='1') then
q <= d;
end if;
end process;
end Behavioral; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
PORT MAP (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
PORT MAP (
PORT_1 => w_port... |
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