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-- ========== Copyright Header Begin =============================================
-- AmgPacman File: ram_dp_sr_sw.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: albertomg994@gmail.com
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity ram_dp_sr_sw is
generic (
DATA_WIDTH :integer := 3;
ADDR_WIDTH :integer := 6
);
port (
-- Señales comunes:
rst : in std_logic; -- Reset
clk : in std_logic; -- Clock Input
-- Puerto 0 (solo escritura)
address_0 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. escritura (port 0)
data_0 : in std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato escribir (port 0)
wr_0 : in std_logic; -- Write Enable (port 0)
-- Puerto 1 (solo lectura)
address_1 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. lectura (port 1)
data_1 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato leído (port 1)
-- Puerto 2 (solo lectura)
address_2 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. lectura (port 2)
data_2 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato leído (port 2)
-- NOTA: metemos la direccion y da el dato en el siguiente ciclo(?)
-- Senales de depuracion:
bt_ld: in std_logic;
addr_db: out std_logic_vector(5 downto 0);
data_db: out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of ram_dp_sr_sw is
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_1_out : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_2_out : std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); -- ORIGINAL
signal mem : RAM (0 to RAM_DEPTH-1); -- original
--Senales debug
signal cntr_db: std_logic_vector( 5 downto 0);
begin
-- Conexion de senales de depuracion
----------------------------------------------------------
addr_db <= cntr_db;
data_db <= mem(conv_integer(cntr_db));
-- Puerto_0: solo escritura
-------------------------------------------------------
MEM_WRITE_0: process (rst,clk) begin
if rst = '1' then
mem(0) <= "100";
mem(7) <= "010";
mem(63) <= "001";
elsif rising_edge(clk) then
if wr_0 = '1' then
mem(conv_integer(address_0)) <= data_0;
end if;
end if;
end process;
-- Puerto_1: solo lectura
-------------------------------------------------------
data_1 <= data_1_out;
MEM_READ_1: process (rst,clk) begin
if rising_edge(clk) then
data_1_out <= mem(conv_integer(address_1));
end if;
end process;
-- Puerto_2: solo lectura
-------------------------------------------------------
data_2 <= data_2_out;
MEM_READ_2: process (rst,clk) begin
if rising_edge(clk) then
data_2_out <= mem(conv_integer(address_2));
end if;
end process;
-- Contador de depuración
---------------------------------------------------------------
p_cntr_db: process(clk, rst, bt_ld)
begin
if rst = '1' then
cntr_db <= (others => '0');
elsif rising_edge(clk) then
if bt_ld = '1' then
cntr_db <= std_logic_vector(unsigned(cntr_db) + 1);
else
cntr_db <= cntr_db;
end if;
end if;
end process p_cntr_db;
-----------------------------------------------------------------
end architecture;
|
--+-------------------------------------------------------------------------------------------------+
--| |
--| Fileo: pciwbsequ.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: FSM controling pci to whisbone transactions. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pciwbsequ is
generic (
BARS : string := "1BARMEM";
WBSIZE : integer := 16;
WBENDIAN : string := "BIG"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- pci
cmd_i : in std_logic_vector(3 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
frame_i : in std_logic;
irdy_i : in std_logic;
devsel_o : out std_logic;
trdy_o : out std_logic;
stop_o : out std_logic;
targ_oe : out std_logic;
-- control
adrcfg_i : in std_logic;
adrmem_i : in std_logic;
pciadrLD_o : out std_logic;
pcidOE_o : out std_logic;
parOE_o : out std_logic;
wbdatLD_o : out std_logic;
wrcfg_o : out std_logic;
rdcfg_o : out std_logic;
-- whisbone
wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_rty_i : in std_logic;
wb_err_i : in std_logic
);
end pciwbsequ;
architecture rtl of pciwbsequ is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, BACKOFF, TURN_ARL, TURN_ARE );
signal pst_pci : PciFSM;
signal nxt_pci : PciFSM;
signal bbusy : std_logic;
signal idle : std_logic;
signal sdata1 : std_logic;
signal sdata2 : std_logic;
signal sdata1NX : std_logic;
signal sdata2NX : std_logic;
signal turnarlNX : std_logic;
signal turnarl : std_logic;
signal devselNX_n : std_logic;
signal trdyNX_n : std_logic;
signal stopNx_n : std_logic;
signal devsel : std_logic;
signal trdy : std_logic;
signal stop : std_logic;
signal adrpci : std_logic;
signal acking : std_logic;
signal retrying : std_logic;
signal rdcfg : std_logic;
signal targOE : std_logic;
signal pcidOE : std_logic;
signal pcidOE_s : std_logic;
begin
--+-------------------------------------------------------------------------+
--| PCI-Whisbone Sequencer |
--+-------------------------------------------------------------------------+
--+-------------------------------------------------------------+
--| FSM PCI-Whisbone |
--+-------------------------------------------------------------+
PCIFSM_CLOCKED: process( rst_i, clk_i, nxt_pci )
begin
if( rst_i = '1' ) then
pst_pci <= PCIIDLE;
elsif( rising_edge(clk_i) ) then
pst_pci <= nxt_pci;
end if;
end process PCIFSM_CLOCKED;
PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking, retrying )
begin
devselNX_n <= '1';
trdyNX_n <= '1';
stopNX_n <= '1';
case pst_pci is
when PCIIDLE =>
if ( frame_i = '0' ) then
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end if;
when B_BUSY =>
if ( adrpci = '0' ) then
nxt_pci <= TURN_ARE;
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA1 =>
if (acking = '1') then
if (frame_i = '0') then
stopNX_n <= '0';
end if;
nxt_pci <= S_DATA2;
devselNX_n <= '0';
trdyNX_n <= '0';
elsif (retrying = '1') then
nxt_pci <= BACKOFF;
devselNX_n <= '0';
stopNX_n <= '0';
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA2 =>
nxt_pci <= TURN_ARL;
when BACKOFF =>
if ( frame_i = '1' and irdy_i = '0' ) then
nxt_pci <= TURN_ARL;
else
nxt_pci <= BACKOFF;
devselNX_n <= '0';
stopNX_n <= '0';
end if;
when TURN_ARL =>
if (frame_i = '0') then
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end if;
when TURN_ARE =>
if (frame_i = '0') then
nxt_pci <= TURN_ARE;
else
nxt_pci <= PCIIDLE;
end if;
end case;
end process PCIFSM_COMB;
--+-------------------------------------------------------------+
--| FSM control signals |
--+-------------------------------------------------------------+
adrpci <= adrmem_i or adrcfg_i;
acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0')
else '0';
retrying <= '1' when ( wb_rty_i = '1' ) else '0';
--+-------------------------------------------------------------+
--| FSM derived Control signals |
--+-------------------------------------------------------------+
idle <= '1' when ( pst_pci = PCIIDLE ) else '0';
bbusy <= '1' when ( pst_pci = B_BUSY ) else '0';
sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0';
sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0';
--turnar <= '1' when ( pst_pci = TURN_AR ) else '0';
turnarl <= '1' when ( pst_pci = TURN_ARL ) else '0';
sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0';
sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0';
--turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0';
turnarlNX <= '1' when ( nxt_pci = TURN_ARL ) else '0';
--+-------------------------------------------------------------+
--| PCI Data Output Enable |
--+-------------------------------------------------------------+
PCIDOE_P: process( rst_i, clk_i, cmd_i(0), sdata1NX, turnarlNX )
begin
if ( rst_i = '1' ) then
pcidOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' and cmd_i(0) = '0' ) then
pcidOE <= '1';
elsif ( turnarlNX = '1' ) then
pcidOE <= '0';
end if;
end if;
end process PCIDOE_P;
pcidOE_o <= pcidOE;
--+-------------------------------------------------------------+
--| PAR Output Enable |
--| PCI Read data phase |
--| PAR is valid 1 cicle after data is valid |
--+-------------------------------------------------------------+
uu1: entity work.syncl port map ( clk => clk_i, rst => rst_i, d => pcidOE, q => pcidOE_s );
parOE_o <= pcidOE_s;
--+-------------------------------------------------------------+
--| Target s/t/s signals OE control |
--+-------------------------------------------------------------+
TARGOE_P: process( rst_i, clk_i, sdata1NX, turnarl )
begin
if ( rst_i = '1' ) then
targOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' ) then
targOE <= '1';
elsif ( turnarl = '1' ) then
targOE <= '0';
end if;
end if;
end process TARGOE_P;
--+-------------------------------------------------------------------------+
--| WHISBONE outs |
--+-------------------------------------------------------------------------+
cyc_p: process(rst_i, clk_i, adrmem_i, bbusy, acking, retrying, frame_i)
begin
if ( rst_i = '1' ) then
wb_cyc_o <= '0';
elsif ( rising_edge(clk_i) ) then
if (adrmem_i = '1' and bbusy = '1' ) then
wb_cyc_o <= '1';
elsif ((acking = '1' or retrying = '1') and frame_i = '1') then
wb_cyc_o <= '0';
end if;
end if;
end process cyc_p;
wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';
wb_we_o <= cmd_i(0);
--+-----------------------------------------+
--| wb_sel_o generation depending on WBSIZE |
--| and WBENDIAN "generics" configuration |
--+-----------------------------------------+
sel32: if (WBSIZE = 32) generate
wb_sel_o(3) <= not cbe_i(3);
wb_sel_o(2) <= not cbe_i(2);
wb_sel_o(1) <= not cbe_i(1);
wb_sel_o(0) <= not cbe_i(0);
end generate;
sel16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));
wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));
end generate;
sel16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
wb_sel_o(1) <= (not cbe_i(1)) or (not cbe_i(3));
wb_sel_o(0) <= (not cbe_i(0)) or (not cbe_i(2));
end generate;
sel8: if (WBSIZE = 8) generate
wb_sel_o(0) <= not (cbe_i(0) and cbe_i(1) and cbe_i(2) and cbe_i(3));
end generate;
--+-------------------------------------------------------------------------+
--| Syncronized PCI outs |
--+-------------------------------------------------------------------------+
PCISIG: process( rst_i, clk_i, devselNX_n, trdyNX_n, stopNX_n)
begin
if( rst_i = '1' ) then
devsel <= '1';
trdy <= '1';
stop <= '1';
elsif( rising_edge(clk_i) ) then
devsel <= devselNX_n;
trdy <= trdyNX_n;
stop <= stopNX_n;
end if;
end process PCISIG;
targ_oe <= targOE;
devsel_o <= devsel;
trdy_o <= trdy;
stop_o <= stop;
--+-------------------------------------------------------------------------+
--| Other outs |
--+-------------------------------------------------------------------------+
-- rd/wr Configuration Space Registers
wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';
rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';
rdcfg_o <= rdcfg;
-- LoaD enable signals
--pciadrLD_o <= '1' when(frame_i = '0' and idle = '1') else '0';
-- added turnarl to support Fast Back to Back
pciadrLD_o <= '1' when(frame_i = '0' and (idle = '1' or turnarl = '1')) else '0';
wbdatLD_o <= wb_ack_i;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
switches : in STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0);
JOY_PUSH : in STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal data_shiftreg : std_logic_vector(9 downto 0) := (others => '1');
signal busy_shiftreg : std_logic_vector(9 downto 0) := (others => '0');
signal counter : std_logic_vector(12 downto 0) := (others => '0');
signal data_byte : std_logic_vector(7 downto 0) := (others => '1');
--signal data_buf : std_logic_vector(7 downto 0) := (others => '0');
signal send : std_logic := '0';
signal sig_old : std_logic := '0';
begin
data_out <= data_shiftreg(0);
--debug_out <= shiftreg(0);
leds <= switches;
send <= not JOY_PUSH;
data_byte <= switches;
process(clk)
begin
if rising_edge(clk) then
if busy_shiftreg(0) = '0' then
sig_old <= send;
if sig_old='0' and send='1' then
-- least significant bit is 0 indicating that the line is free
-- now set the whole shiftregister to 1, indicating that the line is busy
busy_shiftreg <= (others => '1');
data_shiftreg <= '1' & data_byte & '0';
counter <= (others => '0');
end if;
else
if counter=3332 then
data_shiftreg <= '1' & data_shiftreg(9 downto 1);
busy_shiftreg <= '0' & busy_shiftreg(9 downto 1);
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter
end if; -- rising_edge
end if;
end process;
end Behavioral;
|
component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
keycode_export : out std_logic_vector(7 downto 0); -- export
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
sdram_out_clk_clk : out std_logic; -- clk
usb_out_clk_clk : out std_logic -- clk
);
end component usb_system;
u0 : component usb_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library altera_mf;
use altera_mf.all;
entity fifo_com_tx is
generic
(
DEPTH : POSITIVE;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port
(
aclr : in std_logic;
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdclk : in std_logic;
rdreq : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic;
rdusedw : out std_logic_vector (integer(ceil(log2(real(DEPTH))*(real(IN_SIZE)/real(OUT_SIZE))))-1 downto 0);
wrfull : out std_logic;
wrusedw : out std_logic_vector (integer(ceil(log2(real(DEPTH))))-1 downto 0)
);
END fifo_com_tx;
architecture syn of fifo_com_tx is
signal sub_wire0 : std_logic;
signal sub_wire1 : std_logic_vector (OUT_SIZE-1 downto 0);
signal sub_wire2 : std_logic;
signal sub_wire3 : std_logic_vector (integer(ceil(log2(real(DEPTH))))-1 downto 0);
signal sub_wire4 : std_logic_vector (integer(ceil(log2(real(DEPTH))*(real(IN_SIZE)/real(OUT_SIZE))))-1 downto 0);
component dcfifo
generic (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
port (
rdclk : in std_logic;
wrfull : out std_logic;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
wrusedw : out std_logic_vector (integer(ceil(log2(real(depth))))-1 downto 0);
aclr : in std_logic;
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdreq : in std_logic;
rdusedw : out std_logic_vector (integer(ceil(log2(real(depth))))-1 downto 0)
);
end component;
component dcfifo_mixed_widths
generic (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
port (
rdclk : in std_logic;
wrfull : out std_logic;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
wrusedw : out std_logic_vector (integer(ceil(log2(real(depth))))-1 downto 0);
aclr : in std_logic;
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdreq : in std_logic;
rdusedw : out std_logic_vector (integer(ceil(log2(real(DEPTH))*(real(IN_SIZE)/real(OUT_SIZE))))-1 downto 0)
);
end component;
begin
wrfull <= sub_wire0;
q <= sub_wire1;
rdempty <= sub_wire2;
wrusedw <= sub_wire3;
rdusedw <= sub_wire4;
FIFO_GEN_SAME_WIDTH : if (IN_SIZE = OUT_SIZE) generate
dcfifo_component : dcfifo
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => IN_SIZE,
lpm_widthu => integer(ceil(log2(real(DEPTH)))),
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
port map (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2,
wrusedw => sub_wire3,
rdusedw => sub_wire4
);
end generate;
FIFO_GEN_MIXED_WIDTH : if (IN_SIZE /= OUT_SIZE) generate
dcfifo_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => IN_SIZE,
lpm_widthu => integer(ceil(log2(real(DEPTH)))),
lpm_widthu_r => integer(ceil(log2(real(DEPTH))*(real(IN_SIZE)/real(OUT_SIZE)))),
lpm_width_r => OUT_SIZE,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
port map (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data(7 downto 0) & data(15 downto 8), -- inverse bytes
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2,
wrusedw => sub_wire3,
rdusedw => sub_wire4
);
end generate;
end syn;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(7 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(11 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(19 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter;
-- use the register value to fill the variable
frequency <= Freq_hi & Freq_lo;
-- use the register value to fill the variable
pulsewidth <= Pw_hi & Pw_lo;
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency);
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= pulsewidth) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specific values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel <= Att_dec(3 downto 0);
else
Dec_rel <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_15.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_15
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_15
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_15 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_vld : OUT std_logic
);
END TWDLROM_3_15;
ARCHITECTURE rtl OF TWDLROM_3_15 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_15_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_15_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_15_re_tmp <= twdlIn_re;
twdl_3_15_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_15_re <= std_logic_vector(twdl_3_15_re_tmp);
twdl_3_15_im <= std_logic_vector(twdl_3_15_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_15_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_15_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1705.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01705ent IS
END c09s02b00x00p07n01i01705ent;
ARCHITECTURE c09s02b00x00p07n01i01705arch OF c09s02b00x00p07n01i01705ent IS
signal S1 : Bit;
signal S2 : Bit;
BEGIN
TESTING: PROCESS( S1 )
BEGIN
S1 <= '1' after 10 ns;
END PROCESS TESTING;
TESTING1: PROCESS
BEGIN
S2 <= '1' after 10 ns;
wait on S2;
assert NOT(S1=S2)
report "***PASSED TEST: c09s02b00x00p07n01i01705"
severity NOTE;
assert (S1=S2)
report "***FAILED TEST: c09s02b00x00p07n01i01705 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
severity ERROR;
wait;
END PROCESS TESTING1;
END c09s02b00x00p07n01i01705arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1705.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01705ent IS
END c09s02b00x00p07n01i01705ent;
ARCHITECTURE c09s02b00x00p07n01i01705arch OF c09s02b00x00p07n01i01705ent IS
signal S1 : Bit;
signal S2 : Bit;
BEGIN
TESTING: PROCESS( S1 )
BEGIN
S1 <= '1' after 10 ns;
END PROCESS TESTING;
TESTING1: PROCESS
BEGIN
S2 <= '1' after 10 ns;
wait on S2;
assert NOT(S1=S2)
report "***PASSED TEST: c09s02b00x00p07n01i01705"
severity NOTE;
assert (S1=S2)
report "***FAILED TEST: c09s02b00x00p07n01i01705 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
severity ERROR;
wait;
END PROCESS TESTING1;
END c09s02b00x00p07n01i01705arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1705.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01705ent IS
END c09s02b00x00p07n01i01705ent;
ARCHITECTURE c09s02b00x00p07n01i01705arch OF c09s02b00x00p07n01i01705ent IS
signal S1 : Bit;
signal S2 : Bit;
BEGIN
TESTING: PROCESS( S1 )
BEGIN
S1 <= '1' after 10 ns;
END PROCESS TESTING;
TESTING1: PROCESS
BEGIN
S2 <= '1' after 10 ns;
wait on S2;
assert NOT(S1=S2)
report "***PASSED TEST: c09s02b00x00p07n01i01705"
severity NOTE;
assert (S1=S2)
report "***FAILED TEST: c09s02b00x00p07n01i01705 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
severity ERROR;
wait;
END PROCESS TESTING1;
END c09s02b00x00p07n01i01705arch;
|
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`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_PapilioDuo.vhd
-- /___/ /\ Timestamp : 19/04/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_PapilioDuo
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_PapilioDuo is
port (clk_32M00 : in std_logic;
ps2_kbd_clk : in std_logic;
ps2_kbd_data : in std_logic;
ps2_mse_clk : inout std_logic;
ps2_mse_data : inout std_logic;
ERST : in std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audioL : out std_logic;
audioR : out std_logic;
SRAM_nOE : out std_logic;
SRAM_nWE : out std_logic;
SRAM_nCS : out std_logic;
SRAM_A : out std_logic_vector (20 downto 0);
SRAM_D : inout std_logic_vector (7 downto 0);
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO
avr_RxD : in std_logic;
avr_TxD : out std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
DIP : in std_logic_vector (3 downto 0);
JOYSTICK1 : in std_logic_vector (7 downto 0);
JOYSTICK2 : in std_logic_vector (7 downto 0)
);
end AtomFpga_PapilioDuo;
architecture behavioral of AtomFpga_PapilioDuo is
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal phi2 : std_logic;
signal RAM_A : std_logic_vector(18 downto 0);
signal RAM_Din : std_logic_vector(7 downto 0);
signal RAM_Dout : std_logic_vector(7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 128KB (32x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"020000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
--------------------------------------------------------
-- Atom Fpga Core
--------------------------------------------------------
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => false,
CImplAtoMMC2 => true,
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
CImplRamRomNone => false,
CImplRamRomPhill => true,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clk_vga => clock_25,
clk_main => clock_32,
clk_avr => clock_32,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_kbd_clk,
ps2_data => ps2_kbd_data,
ps2_mouse_clk => ps2_mse_clk,
ps2_mouse_data => ps2_mse_data,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red(3 downto 1),
green => green(3 downto 1),
blue => blue(3 downto 1),
vsync => vsync,
hsync => hsync,
phi2 => phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
LED1 => LED1,
LED2 => LED2,
charSet => DIP(0),
Joystick1 => JOYSTICK1,
Joystick2 => JOYSTICK2
);
red(0) <= '0';
green(0) <= '0';
blue(0) <= '0';
--------------------------------------------------------
-- Clock Generation
--------------------------------------------------------
inst_dcm4 : entity work.dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clock_32,
CLKFX_OUT => clock_25
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= not ERST and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Papilio Duo Misc
--------------------------------------------------------
ARDUINO_RESET <= SW1;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_length => user_length
)
port map(
clock => clock_32,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => SRAM_nOE,
SRAM_nWE => SRAM_nWE,
SRAM_nCS => SRAM_nCS,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
MemProcess : process (clock_32)
begin
if rising_edge(clock_32) then
RAM_A <= ExternA;
RAM_nCS <= not ExternCE;
RAM_nOE <= not ((not ExternWE) and ExternCE and phi2);
RAM_nWE <= not (ExternWE and ExternCE and phi2);
RAM_Din <= ExternDin;
end if;
end process;
ExternDout <= RAM_Dout;
end behavioral;
|
-- manchester decoder test bench
--
-- test coverage includes all possible input manchester combinations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity manchester_dec_tb is
end manchester_dec_tb;
architecture behav of manchester_dec_tb is
component manchester_dec
port
(
clk : in std_logic;
inclk : in std_logic;
outclk : out std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic;
err : out std_logic
);
end component;
signal clk : std_logic := '0';
signal inclk : std_logic := '0';
signal outclk : std_logic;
signal rst : std_logic := '1';
signal d : std_logic := '0';
signal q : std_logic;
signal err : std_logic;
begin
dut : manchester_dec
port map (clk, inclk, outclk, rst, d, q, err);
clk <= not clk after 50 ns;
rst <= '0' after 200 ns;
process
variable l : line;
file vector_file : text is in "manchester_dec_test.txt";
begin
wait until rst <= '0';
while not endfile(vector_file) loop
readline(vector_file, l);
wait until rising_edge(clk);
inclk <= '1';
case l(1) is
when '0' =>
d <= '0';
when '1' =>
d <= '1';
when others =>
assert false
report "illegal character";
exit;
end case;
wait until rising_edge(clk);
inclk <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
inclk <= '1';
case l(3) is
when '0' =>
d <= '0';
when '1' =>
d <= '1';
when others =>
assert false
report "illegal character";
exit;
end case;
wait until rising_edge(clk);
inclk <= '0';
wait until rising_edge(clk);
-- output check
case l(5) is
when '0' =>
if q = '1' then
assert false
report "Behavioral error, q=1, exp q=0!";
exit;
end if;
when '1' =>
if q = '0' then
assert false
report "Behavioral error, q=0, exp q=1!";
exit;
end if;
when others =>
assert false
report "illegal character";
exit;
end case;
-- error check
case l(7) is
when '0' =>
if err = '1' then
assert false
report "Behavioral error, err=1, exp err=0!";
exit;
end if;
when '1' =>
if err = '0' then
assert false
report "Behavioral error, err=0, exp err=1!";
exit;
end if;
when others =>
assert false
report "illegal character";
exit;
end case;
if outclk = '0' then
assert false
report "output clock not active!";
exit;
end if;
wait until rising_edge(clk);
if outclk = '1' then
assert false
report "output clock active too long!";
exit;
end if;
end loop;
end process;
end behav;
|
------------------------------------------------------------------------------
-- @license MIT
-- @brief Histogram for Huffman encoding.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.global.all;
entity histogram is
port(
i_clk : in std_logic;
in_rst : in std_logic;
i_stage : in t_stage;
i_pipe_en : in std_logic;
i_sym : in t_sym;
o_hist : out t_freq_array(0 to 15)
);
end entity histogram;
architecture arch_histogram_v1 of histogram is
signal hist : t_freq_array(0 to 15);
begin
process(i_clk, in_rst)
begin
if in_rst = '0' then
hist <= (others => (others => '0'));
elsif rising_edge(i_clk) then
if i_pipe_en = '1' then
if i_stage /= 16 then
hist(conv_integer(i_sym)) <= hist(conv_integer(i_sym)) + 1;
else
hist <= (others => (others => '0'));
end if;
end if;
end if;
end process;
o_hist <= hist;
end architecture arch_histogram_v1;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity test_bench is
end entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process is
begin
d0 <= '1'; d1 <= '1'; d2 <= '1'; d3 <= '1';
en <= '0'; clk <= '0';
wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
d0 <= '0'; d1 <= '0'; d2 <= '0'; d3 <= '0'; wait for 20 ns;
en <= '0'; wait for 20 ns;
-- . . .
wait;
end process stimulus;
end architecture test_reg4;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity test_bench is
end entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process is
begin
d0 <= '1'; d1 <= '1'; d2 <= '1'; d3 <= '1';
en <= '0'; clk <= '0';
wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
d0 <= '0'; d1 <= '0'; d2 <= '0'; d3 <= '0'; wait for 20 ns;
en <= '0'; wait for 20 ns;
-- . . .
wait;
end process stimulus;
end architecture test_reg4;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity test_bench is
end entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process is
begin
d0 <= '1'; d1 <= '1'; d2 <= '1'; d3 <= '1';
en <= '0'; clk <= '0';
wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
d0 <= '0'; d1 <= '0'; d2 <= '0'; d3 <= '0'; wait for 20 ns;
en <= '0'; wait for 20 ns;
-- . . .
wait;
end process stimulus;
end architecture test_reg4;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_72 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_72;
architecture BEHAVIORAL of dcm_32_72 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 72.00 = 32.000 * 9/4
CLKFX_MULTIPLY => 9,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
----- Libraries ------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Counter is
port(
SW : in std_logic_vector(17 downto 16);
KEY0, KEY3 : in std_logic;
LEDR : out std_logic_vector(0 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end Counter;
----- Architecture -----
architecture multi_counter of Counter is
-- declare signals, components here...
signal clk, reset, cout : std_logic;
signal mode : unsigned(1 downto 0) := (others => '0');
signal count : unsigned(3 downto 0) := (others => '0');
begin
-- architecture body...
process(reset, clk)
begin
if(reset = '0') then
elsif (rising_edge(clk)) then
case (mode) is
when "00" =>
-- count from 0-9
if count < X"9" then
count <= count + "1";
cout <= "00";
else
count <= "0000";
cout <= "01";
end if;
when "01" =>
-- count from 0-5
if count < X"5" then
count <= count + "1";
cout <= "00";
else
count <= "0000";
cout <= "01";
end if;
when others =>
-- count from 0-2
if count<2 then
count <= count + "1";
cout <= "00";
else
count <= "00";
cout <= "01";
end if;
end case;
end if;
end process;
end multi_counter; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.all;
use work.debug.all;
use work.config.all;
use work.ml605.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_tdqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_logic;
signal egtx_clk : std_logic;
signal gmiiclk_p : std_logic := '1';
signal gmiiclk_n : std_logic := '0';
-- Output signals for LEDs
signal led : std_logic_vector(6 downto 0);
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal clk_33 : std_ulogic := '0';
signal brdyn : std_ulogic;
component ddr3_model is
port (
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector(1 downto 0);
ba : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(12 downto 0);
dq : inout std_logic_vector(15 downto 0);
dqs : inout std_logic_vector(1 downto 0);
dqs_n : inout std_logic_vector(1 downto 0);
tdqs_n : out std_logic_vector(1 downto 0);
odt : in std_logic
);
end component ddr3_model;
---------------------pcie----------------------------------------------
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
---------------------pcie end---------------------------------------------
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
gmiiclk_p <= not gmiiclk_p after 4 ns;
gmiiclk_n <= not gmiiclk_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rst <= '1', '0' after 200 us;
rstn1 <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL)
port map (
reset => rst,
errorn => error,
clk_ref_p => clk200p,
clk_ref_n => clk200n,
-- PROM
address => address(24 downto 1),
data => data(15 downto 0),
romsn => romsn,
oen => oen,
writen => writen,
-- DDR3
ddr3_dq => ddr3_dq,
ddr3_dm => ddr3_dm,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
gmiiclk_p => gmiiclk_p,
gmiiclk_n => gmiiclk_n,
egtx_clk => egtx_clk,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
emdint => emdint,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- Output signals for LEDs
iic_scl_main => iic_scl_main,
iic_sda_main => iic_sda_main,
dvi_iic_scl => iic_scl_dvi,
dvi_iic_sda => iic_sda_dvi,
tft_lcd_data => tft_lcd_data,
tft_lcd_clk_p => tft_lcd_clk_p,
tft_lcd_clk_n => tft_lcd_clk_n,
tft_lcd_hsync => tft_lcd_hsync,
tft_lcd_vsync => tft_lcd_vsync,
tft_lcd_de => tft_lcd_de,
tft_lcd_reset_b => tft_lcd_reset_b,
clk_33 => clk_33,
sysace_mpa => sysace_mpa,
sysace_mpce => sysace_mpce,
sysace_mpirq => sysace_mpirq,
sysace_mpoe => sysace_mpoe,
sysace_mpwe => sysace_mpwe,
sysace_d => sysace_d,
pci_exp_txp=> cor_pci_exp_txp,
pci_exp_txn=> cor_pci_exp_txn,
pci_exp_rxp=> cor_pci_exp_rxp,
pci_exp_rxn=> cor_pci_exp_rxn,
sys_clk_p=> ep_sys_clk_p,
sys_clk_n=> ep_sys_clk_n,
sys_reset_n=> cor_sys_reset_n,
led => led
);
gen_mem: for i in 0 to 3 generate
u1: ddr3_model port map
(
rst_n => ddr3_reset_n,
ck => ddr3_ck_p(0),
ck_n => ddr3_ck_n(0),
cke => ddr3_cke(0),
cs_n => ddr3_cs_n(0),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm((2*(i+1)-1) downto (i*2)),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq((16*i+15) downto (16*i)),
dqs => ddr3_dqs_p((2*(i+1)-1) downto (i*2)),
dqs_n => ddr3_dqs_n((2*(i+1)-1) downto (i*2)),
tdqs_n => ddr3_tdqs_n((2*(i+1)-1) downto (i*2)),
odt => ddr3_odt(0));
end generate gen_mem;
-- prom0 : sram
-- generic map (index => 6, abits => 24, fname => promfile)
-- port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
address(0) <= '0';
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 7)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, egtx_clk);
end generate;
-- spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
-- end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
package pack0 is
constant foo : integer := 42;
constant v : bit_vector := "1010101";
constant q : bit_vector(3 downto 0) := X"F";
constant z : integer := 2;
end package;
-------------------------------------------------------------------------------
use work.pack0.all;
package pack1 is
function bar return integer;
end package;
package body pack1 is
function bar return integer is
begin
return 5;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack1.all;
use work.pack0.all;
package pack2 is
function foo return integer;
function get_v return bit_vector;
function get_v0 return bit;
end package;
package body pack2 is
constant x : bit_vector(1 downto 0) := q(1 downto 0);
constant gv : bit_vector(6 downto 0) := get_v;
function foo return integer is
begin
return bar + 2;
end function;
function get_v return bit_vector is
begin
return v;
end function;
function get_v0 return bit is
begin
return v(0);
end function;
end package body;
-------------------------------------------------------------------------------
entity link2 is
end entity;
use work.pack2.all;
architecture test of link2 is
begin
process is
variable v : bit_vector(6 downto 0);
begin
assert foo = 7;
assert get_v = "1010101"; -- Will be constant folded
v := get_v;
wait for 1 ns;
assert v = get_v;
assert get_v0 = '1';
wait;
end process;
end architecture;
|
-- Design unit: DSP
-- Structural implementation
-- Included components: distortion_component, reverb
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
entity dsp is
port(
clk: in std_logic;
reset_n: in std_logic;
enable: in std_logic_vector(4 downto 0); --select signals
incoming_data_left: in std_logic_vector(15 downto 0); --left channel audio
incoming_valid_left: in std_logic; ----left channel audio in (valid signal)
incoming_data_right: in std_logic_vector(15 downto 0); -- right channel audio
incoming_valid_right: in std_logic; -- right channel audio in (valid signal)
outgoing_data_left: out std_logic_vector(15 downto 0); --left channel audio out
outgoing_valid_left: out std_logic; --left channel audio out (valid signal)
outgoing_data_right: out std_logic_vector(15 downto 0); --right channel audio out
outgoing_valid_right: out std_logic; --right channel audio out (valid signal)
clipping_write : in std_logic;
clipping_read : in std_logic;
clipping_readdata: out std_logic_vector(15 downto 0);
clipping_value: in std_logic_vector(15 downto 0);
reverb_sink_valid: out std_logic; -- Valid signal for sdram input. Used for reverb
reverb_sink_data: out std_logic_vector(15 downto 0); -- sdram input. Used for reverb.
reverb_source_valid: in std_logic; --Valid signal for sdram output. Used for reverb.
reverb_source_data: in std_logic_vector(15 downto 0); --output from sdram. Used for reverb
reverb_delayed_valid: in std_logic; --Valid signal for delayed audio from sdram. Used for reverb
reverb_delayed_data: in std_logic_vector(15 downto 0); --delayed audio from sdram. Used for reverb
--loopBuffer_in_valid : out std_logic;
--loopBuffer_in : out std_logic_vector(15 downto 0);
loopBuffer_out_valid : in std_logic;
loopBuffer_out : in std_logic_vector(15 downto 0);
tuner_readdata: out std_logic_vector(31 downto 0) --guitar tuner data
);
end entity dsp;
architecture arch of dsp is
signal dist_completed: std_logic_vector(1 downto 0);
signal dist_en : std_logic;
signal reverb_en : std_logic;
signal tuner_en : std_logic;
signal out_valid: std_logic;
signal distortion, reverb, outgoing, placeholder,current, prev, audio_loop :std_logic_vector(15 downto 0);
signal mult_result : std_logic_vector(17 downto 0);
constant multiplier : std_logic_vector(1 downto 0) := "11";
signal decayed_signal : std_logic_vector(15 downto 0);
signal reverb_int : std_logic_vector(15 downto 0);
component distort is
port(
clk : in std_logic;
reset : in std_logic;
dist_en : in std_logic; -- 1-bit distortion enable signal
ready : in std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 downto 0); -- 16-bit data stream input
clipping_write : in std_logic;
clipping_read : in std_logic;
clipping_value: in std_logic_vector(15 downto 0); -- 16-bit input clipping threshold
clipping_readdata: out std_logic_vector(15 downto 0);
data_out: out std_logic_vector(15 downto 0) -- 16-bit data stream output (either clipped or not)
);
end component;
component reverb_component is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
reverb_en : in STD_LOGIC;
ready : in std_logic; --
done : out std_logic; --
data_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component MUX5X1 is
port(
clk: in std_logic;
distortion: in std_logic_vector(15 downto 0);
reverb: in std_logic_vector(15 downto 0);
AUDIO_IN: in std_logic_vector(15 downto 0);
audio_loop : in std_logic_vector(15 downto 0);
OUTPUT: out std_logic_vector(15 downto 0);
SEL: in std_logic_vector(4 downto 0)
);
end component;
component tuner is
port(
clk: in std_logic;
reset: in std_logic;
tuner_en: in std_logic;
tuner_in: in std_logic;
tuner_data: in std_logic_vector(15 downto 0);
tuner_data_available: in std_logic;
tuner_out: out std_logic_vector(31 downto 0)
);
end component;
begin
out_valid <= dist_completed(0) or (reverb_source_valid and reverb_delayed_valid) or loopBuffer_out_valid;
--Reverb start
mult_result <= std_logic_vector(signed(multiplier)*signed(reverb_delayed_data)); -- 18 bits
decayed_signal <= mult_result(15 downto 0);
reverb_int <= std_logic_vector(signed(reverb_source_data) + signed(decayed_signal(15) & decayed_signal(15 downto 2)));
reverb <= reverb_int;
reverb_sink_data <= std_logic_vector(signed(reverb_int) + signed(incoming_data_left));
reverb_sink_valid <= incoming_valid_left;
--Reverb end
--Loop Back Start
audio_loop <= loopBuffer_out; --std_logic_vector(signed(loopBuffer_out)+signed(incoming_data_left));
--Loop Back End
--Output signals
outgoing_data_left <= outgoing;
outgoing_valid_left <= out_valid;
outgoing_valid_right <= incoming_valid_right;
outgoing_data_right <= incoming_data_right;
MUX: MUX5X1 port map ( clk => clk,
distortion => distortion,
reverb => reverb,
AUDIO_IN => incoming_data_left(15 downto 0),
audio_loop => audio_loop,
OUTPUT => outgoing,
SEL => enable(4 downto 0));
d1:distort port map ( clk =>clk,reset=>reset_n,
dist_en => enable(0),
ready => incoming_valid_left,
done => dist_completed(0),
data_in => incoming_data_left(15 downto 0),
clipping_write => clipping_write,
clipping_read => clipping_read,
clipping_value => clipping_value,
clipping_readdata => clipping_readdata,
data_out => distortion(15 downto 0));
t0:tuner port map(
clk => clk,
reset => reset_n,
tuner_en => enable(2),
tuner_in => outgoing(15),
tuner_data => outgoing,
tuner_data_available => out_valid,
tuner_out => tuner_readdata);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits_vlg_check_tst is
port(
HEX0 : in vl_logic_vector(6 downto 0);
HEX1 : in vl_logic_vector(6 downto 0);
LEDR : in vl_logic_vector(4 downto 0);
sampler_rx : in vl_logic
);
end MeioSomador4Bits_vlg_check_tst;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02399ent IS
END c07s03b02x00p08n01i02399ent;
ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v23 : rec;
BEGIN
v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***PASSED TEST: c07s03b02x00p08n01i02399"
severity NOTE;
assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02399arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02399ent IS
END c07s03b02x00p08n01i02399ent;
ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v23 : rec;
BEGIN
v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***PASSED TEST: c07s03b02x00p08n01i02399"
severity NOTE;
assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02399arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02399ent IS
END c07s03b02x00p08n01i02399ent;
ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v23 : rec;
BEGIN
v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***PASSED TEST: c07s03b02x00p08n01i02399"
severity NOTE;
assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02399arch;
|
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_tx.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dma_tx is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Señales procedentes del bus del uP.
Databus : in STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales procedentes de la FSM del Controlador de Bus.
Start_TX : in STD_LOGIC;
Ready_TX : out STD_LOGIC;
End_TX : out STD_LOGIC;
-- Bus de datos y señales de handshake orientadas al transmisor del
-- RS232.
DataOut : out STD_LOGIC_VECTOR(7 downto 0);
Valid_DO : out STD_LOGIC;
Ack_DO : in STD_LOGIC);
end dma_tx;
architecture Behavioral of dma_tx is
-- Definición de los posibles estados de la FSM del Transmisor:
type Transmitter_ST is (idle, CPY_REG0, CPY_REG1, SND_REG0, SND_REG1);
signal TX_now, TX_next : Transmitter_ST;
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros de copia de los datos a envíar.
signal REG0, REG1 : std_logic_vector(7 downto 0);
-- Señal de enable de cada uno de los registros anteriores.
signal R0_enable, R1_enable : std_logic;
-- Tabla de direcciones:
-- El valor contenido en cada uno de los registros anteriores será recibido
-- desde su respectiva dirección de memoria.
constant R0_address : std_logic_vector(7 downto 0) := X"04";
constant R1_address : std_logic_vector(7 downto 0) := X"05";
begin
-- El Transmisor nunca modificará un valor de memoria. Únicamente lee los
-- datos necesarios de ella.
WriteEnable <= '0';
-- Proceso secuencial de la máquina de estados del Transmisor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle',
-- y los registros se inicializan a 0.
process(Clk, Reset)
begin
if (Reset = '0') then
TX_now <= idle;
REG0 <= X"00";
REG1 <= X"00";
elsif Clk'event and Clk = '1' then
TX_now <= TX_next;
if R0_enable = '1' then
REG0 <= Databus;
end if;
if R1_enable = '1' then
REG1 <= Databus;
end if;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(TX_now, Start_TX, REG0, REG1, Ack_DO)
begin
-- Valores preasignados por defecto.
Address <= X"00";
ChipSelect <= '0';
OutputEnable <= '0';
Ready_TX <= '0';
End_TX <= '0';
DataOut <= X"00";
Valid_DO <= '1';
R0_enable <= '0';
R1_enable <= '0';
case TX_now is
when idle =>
Ready_TX <= '1';
-- Si el Controlador de Bus da permiso para iniciar una nueva
-- transmisión...
if Start_TX = '1' then
TX_next <= CPY_REG0;
else
TX_next <= idle;
end if;
when CPY_REG0 =>
Address <= R0_address;
ChipSelect <= '1';
OutputEnable <= '1';
R0_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R0 habrá
-- almacenado su dato, y se debe pedir a la memoria el siguiente
-- valor.
TX_next <= CPY_REG1;
when CPY_REG1 =>
Address <= R1_address;
ChipSelect <= '1';
OutputEnable <= '1';
R1_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R1 habrá
-- almacenado su dato, terminando así el uso de los buses del uP,
-- pudiendo devolver su control e iniciando la tranferencia con el
-- RS232.
End_TX <= '1';
TX_next <= SND_REG0;
when SND_REG0 =>
DataOut <= REG0;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= SND_REG1;
else
TX_next <= SND_REG0;
end if;
when SND_REG1 =>
DataOut <= REG1;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= idle;
else
TX_next <= SND_REG1;
end if;
end case;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2890.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n03i02890ent IS
END c02s01b01x00p05n03i02890ent;
ARCHITECTURE c02s01b01x00p05n03i02890arch OF c02s01b01x00p05n03i02890ent IS
function F1 ( A,B : integer) return integer;
function F1 ( A,B : integer ) return integer is
begin
A := 2 ; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
B := B * A; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
return 3;
end F1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n03i02890 - Cannot assign a value to a 'constant'."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n03i02890arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2890.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n03i02890ent IS
END c02s01b01x00p05n03i02890ent;
ARCHITECTURE c02s01b01x00p05n03i02890arch OF c02s01b01x00p05n03i02890ent IS
function F1 ( A,B : integer) return integer;
function F1 ( A,B : integer ) return integer is
begin
A := 2 ; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
B := B * A; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
return 3;
end F1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n03i02890 - Cannot assign a value to a 'constant'."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n03i02890arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2890.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n03i02890ent IS
END c02s01b01x00p05n03i02890ent;
ARCHITECTURE c02s01b01x00p05n03i02890arch OF c02s01b01x00p05n03i02890ent IS
function F1 ( A,B : integer) return integer;
function F1 ( A,B : integer ) return integer is
begin
A := 2 ; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
B := B * A; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
return 3;
end F1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n03i02890 - Cannot assign a value to a 'constant'."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n03i02890arch;
|
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx_dpa is
generic(
enable_soft_cdr_mode: string := "OFF";
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enable_dpa_initial_phase_selection: string := "OFF";
dpa_initial_phase_value: integer := 0;
INITIAL_PHASE_SELECT: vl_notype;
PHASE_NUM : integer := 8
);
port(
rx_in : in vl_logic;
rx_fastclk : in vl_logic;
rx_enable : in vl_logic;
rx_dpa_reset : in vl_logic;
rx_dpa_hold : in vl_logic;
rx_out : out vl_logic;
rx_dpa_clk : out vl_logic;
rx_dpa_loaden : out vl_logic;
rx_dpa_locked : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1;
attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1;
attribute mti_svvh_generic_type of INITIAL_PHASE_SELECT : constant is 3;
attribute mti_svvh_generic_type of PHASE_NUM : constant is 1;
end stratixiii_lvds_rx_dpa;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_08a is
end entity inline_08a;
architecture test of inline_08a is
-- code from book
terminal bias_node : electrical;
--
subnature accurate_electrical is electrical
tolerance "accurate_voltage" across "accurate_current" through;
--
terminal n1, n2 : accurate_electrical;
--
quantity n1_n2_voltage across n1_n2_current through n1 to n2;
--
quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
quantity internal_current : current tolerance n1_n2_current'tolerance;
--
terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
quantity bus_currents through bus_a_end to bus_b_end;
-- end code from book
begin
-- code from book
bias_node'reference == 0.5;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_08a is
end entity inline_08a;
architecture test of inline_08a is
-- code from book
terminal bias_node : electrical;
--
subnature accurate_electrical is electrical
tolerance "accurate_voltage" across "accurate_current" through;
--
terminal n1, n2 : accurate_electrical;
--
quantity n1_n2_voltage across n1_n2_current through n1 to n2;
--
quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
quantity internal_current : current tolerance n1_n2_current'tolerance;
--
terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
quantity bus_currents through bus_a_end to bus_b_end;
-- end code from book
begin
-- code from book
bias_node'reference == 0.5;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_08a is
end entity inline_08a;
architecture test of inline_08a is
-- code from book
terminal bias_node : electrical;
--
subnature accurate_electrical is electrical
tolerance "accurate_voltage" across "accurate_current" through;
--
terminal n1, n2 : accurate_electrical;
--
quantity n1_n2_voltage across n1_n2_current through n1 to n2;
--
quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
quantity internal_current : current tolerance n1_n2_current'tolerance;
--
terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
quantity bus_currents through bus_a_end to bus_b_end;
-- end code from book
begin
-- code from book
bias_node'reference == 0.5;
-- end code from book
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
M_AXIS_TVALID <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => M_AXIS_TREADY,
out_data => M_AXIS_TDATA
);
M_AXIS_TKEEP <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and M_AXIS_TREADY = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end process;
end; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:20:45 10/21/2015
-- Design Name:
-- Module Name: alu_decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu_decode is
Port ( exe : in STD_LOGIC;
OP_EN : in STD_LOGIC;
clk : in STD_LOGIC;
clk_fast: in std_logic;
rst : in STD_LOGIC;
OP_Code : in STD_LOGIC_VECTOR(3 downto 0);
WE : out STD_LOGIC;
A_EN : out STD_LOGIC;
STAT_EN : out STD_LOGIC;
HLT : out STD_LOGIC;
JMP : out STD_LOGIC;
Arith_S : out STD_LOGIC;
Stat_S : out STD_LOGIC;
LOD_S : out STD_LOGIC;
STR : out STD_LOGIC);
end alu_decode;
architecture Behavioral of alu_decode is
signal stored_OP_Code : STD_LOGIC_VECTOR(3 downto 0);
signal i_WE : std_logic;
begin
process(clk)
--ADD A RESET THAT SETS OPCODE TO NOP
begin
if clk' event and clk = '1' then
--Write op_code into temp storage
if OP_EN = '1' then
stored_OP_Code <= OP_Code;
end if;
end if;
end process;
--process(clk)
--begin
-- --Execute instruction
--
-- if rst = '1' then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- elsif exe = '1' then
-- --HLT
-- if stored_OP_Code = "0000" then
-- i_WE <= '1';
-- HLT <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --LOD
-- elsif stored_OP_Code = "0001" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- LOD_S <= '1';
--
-- --STR
-- elsif stored_OP_Code = "0010" then
--
--
-- --if i_WE = '1' then
-- -- i_WE <= '0';
-- --else
-- -- i_WE <= '1';
-- --end if;
--
-- i_WE <= '0';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --ADD
-- elsif stored_OP_Code = "0011" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '1';
-- JMP <= '0';
-- Arith_S <= '0';
-- Stat_S <= '0';
-- LOD_S <= '0';
--
-- --NOP
-- elsif stored_OP_Code = "0100" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --NND
-- elsif stored_OP_Code = "0101" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- Arith_S <= '1';
-- Stat_S <= '0';
-- LOD_S <= '0';
--
-- --CXA
-- elsif stored_OP_Code = "0111" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- Stat_S <= '1';
-- LOD_S <= '0';
--
-- --JMP
-- elsif stored_OP_Code = "0110" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '1';
--
-- --Unknown - halt the CPU
-- else
-- i_WE <= '1';
-- HLT <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
-- end if;
--
--
--
-- else
-- HLT <= '0';
-- i_WE <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
-- end if;
--
--end process;
-- Decoder Combinational Logic --
-- Active Low WE
WE <= '0' when ( stored_OP_code = "0010" and exe = '1' and clk = '1') else '1';
STR <= '1' when (stored_OP_code = "0010" and exe = '1') else '0';
-- HLT
HLT <= '1' when( stored_OP_code = "0000" and exe = '1') else '0';
-- A_EN
A_EN <= '1' when( (stored_OP_code = "0001" or stored_OP_code = "0011" or stored_OP_code = "0101" or stored_OP_code = "0111") and exe = '1' ) else '0';
-- STAT_EN
STAT_EN <= '1' when( stored_OP_code = "0011" and exe = '1') else '0';
-- JMP
JMP <= '1' when( stored_OP_code = "0110" and exe = '1') else '0';
-- Arith_S
Arith_S <= '1' when( stored_OP_code = "0101" and exe = '1') else '0';
-- Stat_S
Stat_S <= '1' when( stored_OP_code = "0111" and exe = '1') else '0';
-- LOD_S
LOD_S <= '1' when( stored_OP_code = "0001" and exe = '1') else '0';
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2652.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02652ent IS
END c13s03b01x00p02n01i02652ent;
ARCHITECTURE c13s03b01x00p02n01i02652arch OF c13s03b01x00p02n01i02652ent IS
BEGIN
TESTING: PROCESS
variable -k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02652 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02652arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2652.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02652ent IS
END c13s03b01x00p02n01i02652ent;
ARCHITECTURE c13s03b01x00p02n01i02652arch OF c13s03b01x00p02n01i02652ent IS
BEGIN
TESTING: PROCESS
variable -k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02652 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02652arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2652.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02652ent IS
END c13s03b01x00p02n01i02652ent;
ARCHITECTURE c13s03b01x00p02n01i02652arch OF c13s03b01x00p02n01i02652ent IS
BEGIN
TESTING: PROCESS
variable -k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02652 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02652arch;
|
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B_Core is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B_Core;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11001000",
"00100000", "00000010", "00000000", "10001001",
"00100000", "00000011", "00000000", "11001101",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "11101111",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00000000", "00000000", "00001000", "00100101",
"00100000", "00000110", "00000000", "11001000",
"00100000", "11000111", "00000000", "00000001",
"00100000", "00000101", "00000000", "11001101",
"00010000", "10100111", "00000000", "00001011",
"10000000", "11000011", "00000000", "00000000",
"10000000", "11100100", "00000000", "00000000",
"00000000", "10000011", "00010000", "00101010",
"00010000", "01000000", "00000000", "00000100",
"00100000", "00100001", "00000000", "00000001",
"10100000", "11000100", "00000000", "00000000",
"10100000", "11100011", "00000000", "00000000",
"00000000", "11100000", "00110000", "00100000",
"00100000", "11100111", "00000000", "00000001",
"00010000", "00000000", "00000000", "11110110",
"00010000", "00000001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11110000",
"00100000", "00000011", "00000000", "11001101",
"00100000", "00000001", "00000000", "11001000",
"10000000", "00100010", "00000000", "00000000",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00010000", "01100001", "00000000", "11111100",
"00010000", "00000000", "00000000", "11111100",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B_Core
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B_Core Use Configuration Work.Mips8B_Core_struct_conf;
End For;
End For;
End Configuration general_test;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity FIR is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end FIR;
architecture syn of FIR is
component FIR_ast
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_ready : out STD_LOGIC;
ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC;
ast_source_eop : out STD_LOGIC;
ast_source_channel : out STD_LOGIC_VECTOR(1 - 1 downto 0);
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
begin
FIR_ast_inst : FIR_ast
port map (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => open,
ast_source_ready => '1',
ast_source_valid => ast_source_valid,
ast_sink_sop => '0',
ast_sink_eop => '0',
ast_sink_error => ast_sink_error,
ast_source_sop => open,
ast_source_eop => open,
ast_source_channel => open,
ast_source_error => ast_source_error
);
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end entity syncram2;
architecture syncrama2 of syncram2 is
type ram_type is array (0 to (2**n)-1) of std_logic_vector(15 downto 0);
signal ram : ram_type;
signal stackAdress : std_logic_vector(9 downto 0);
begin
process(clk,datain,rst) is
begin
if rst = '1' then
stackAdress <= "1111111111";
end if;
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
--end if;
elsif weStack = '1' then
if stackPushPop = '0' then--push
ram(to_integer(unsigned(stackAdress))) <= datain;
stackAdress <= std_logic_vector(unsigned(stackAdress)-1);
else -- pop
stackAdress <= std_logic_vector(unsigned(stackAdress)+1);
ram(to_integer(unsigned(stackAdress))) <= datain;
end if;
end if;
end if;
end process;
dataout <= ram(to_integer(unsigned(stackAdress))) when weStack = '1' and stackPushPop = '1' else
ram(to_integer(unsigned(address)));
dataout0 <= ram(0);
dataout1 <= ram(1);
end architecture syncrama2; |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
|
library ieee;
use ieee.std_logic_ll64.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena := '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := '0';
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= count;
end process;
end; |
-------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge, test controller entity declaration
--
-- Description:
-- Normal operation testcase
--
-- Author(s):
-- Guy Eschemann, guy@airhdl.com
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
use osvvm.ScoreboardPkg_slv.all;
library osvvm_axi4;
use osvvm_axi4.Axi4OptionsPkg.all;
architecture operation of tb_spi2axi_testctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant SPI_PACKET_LENGTH_BYTES : natural := 11;
-------------------------------------------------------------------------------
-- Aliases
-------------------------------------------------------------------------------
alias TxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
alias RxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
begin
------------------------------------------------------------
-- ControlProc
-- Set up AlertLog and wait for end of test
------------------------------------------------------------
ControlProc : process
procedure spi_process(tx_bytes : integer_vector; rx_bytes : out integer_vector) is
variable num_bytes : integer;
variable valid : boolean;
variable rx_byte : std_logic_vector(7 downto 0);
variable bytes_to_send : integer;
begin
-- Push TX bytes to SPI VC
PushBurst(TxBurstFifo, tx_bytes, 8);
SendBurst(SpiRec, tx_bytes'length);
-- Fetch RX bytes from SPI VC
GetBurst(SpiRec, num_bytes);
AlertIfNot(num_bytes = tx_bytes'length, "unexpected number of received bytes");
for i in 0 to num_bytes - 1 loop
PopWord(RxBurstFifo, valid, rx_byte, bytes_to_send);
AlertIfNot(valid, "invalid receive data");
Log("RX byte: " & to_string(rx_byte), DEBUG);
rx_bytes(i) := to_integer(unsigned(rx_byte));
end loop;
end procedure;
-- Write an AXI4 register over SPI
procedure spi_write(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 0; -- write
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(unsigned(data(i * 8 + 7 downto i * 8)));
tx_byte_idx := tx_byte_idx + 1;
end loop;
tx_bytes(tx_byte_idx) := 0; -- a dummy byte to allow writing the data word
tx_byte_idx := tx_byte_idx + 1;
tx_bytes(tx_byte_idx) := 0; -- AXI4 write response
tx_byte_idx := tx_byte_idx + 1;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
-- Read an AXI4 register over SPI
procedure spi_read(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 1; -- read
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 0 to 5 loop
tx_bytes(tx_byte_idx) := 0; -- don't care
tx_byte_idx := tx_byte_idx + 1;
end loop;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
data(31 downto 24) := std_logic_vector(to_unsigned(rx_bytes(6), 8));
data(23 downto 16) := std_logic_vector(to_unsigned(rx_bytes(7), 8));
data(15 downto 8) := std_logic_vector(to_unsigned(rx_bytes(8), 8));
data(7 downto 0) := std_logic_vector(to_unsigned(rx_bytes(9), 8));
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
variable addr : unsigned(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable mem_reg : std_logic_vector(31 downto 0);
variable status : std_logic_vector(7 downto 0);
alias s_axi_awvalid_mask is << signal .tb_spi2axi.s_axi_awvalid_mask : std_logic >>;
alias s_axi_arvalid_mask is << signal .tb_spi2axi.s_axi_arvalid_mask : std_logic >>;
begin
-- Initialization of test
SetAlertLogName("tb_spi2axi_operation");
SetLogEnable(INFO, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(FindAlertLogID("Axi4LiteMemory"), INFO, FALSE, TRUE);
-- Wait for testbench initialization
wait for 0 ns;
-- Wait for Design Reset
wait until nReset = '1';
ClearAlerts;
SetCPHA(SpiRec, SPI_CPHA);
SetCPOL(SpiRec, SPI_CPOL);
wait for 1 us;
Log("Testing normal SPI write");
addr := x"76543210";
wdata := x"12345678";
spi_write(addr, wdata, status);
AffirmIfEqual(status(2), '0', "timeout");
AffirmIfEqual(status(1 downto 0), "00", "write response");
Read(Axi4MemRec, std_logic_vector(addr), mem_reg);
AffirmIfEqual(mem_reg, wdata, "memory data word");
Log("Testing SPI write with SLVERR response");
addr := x"76543210";
wdata := x"12345678";
SetAxi4Options(Axi4MemRec, BRESP, 2); -- SLVERR
spi_write(addr, wdata, status);
AffirmIfEqual(status(2), '0', "Timeout");
AffirmIfEqual(status(1 downto 0), "10", "Write response");
SetAxi4Options(Axi4MemRec, BRESP, 0);
Log("Testing SPI write timeout");
s_axi_awvalid_mask <= force '0';
addr := x"76543210";
wdata := x"12345678";
spi_write(addr, wdata, status);
AffirmIfEqual('1', status(2), "timeout");
s_axi_awvalid_mask <= release;
Log("Testing normal SPI read");
addr := x"12345678";
wdata := x"12345678";
Write(Axi4MemRec, std_logic_vector(addr), wdata);
spi_read(addr, rdata, status);
AffirmIfEqual(rdata, wdata, "read data");
AffirmIfEqual('0', status(2), "timeout");
AffirmIfEqual("00", status(1 downto 0), "read response");
Log("Testing SPI read with DECERR response");
addr := x"12345678";
wdata := x"12345678";
SetAxi4Options(Axi4MemRec, RRESP, 3); -- DECERR
spi_read(addr, rdata, status);
AffirmIfEqual(rdata, wdata, "read data");
AffirmIfEqual('0', status(2), "timeout");
AffirmIfEqual("11", status(1 downto 0), "read response");
SetAxi4Options(Axi4MemRec, RRESP, 0);
Log("Testing SPI read timeout");
s_axi_arvalid_mask <= force '0';
spi_read(addr, rdata, status);
AffirmIfEqual('1', status(2), "timeout");
s_axi_arvalid_mask <= release;
wait for 1 us;
EndOfTestReports;
std.env.stop;
wait;
end process ControlProc;
end architecture operation;
configuration tb_spi2axi_operation of tb_spi2axi is
for TestHarness
for testctrl_inst : tb_spi2axi_testctrl
use entity work.tb_spi2axi_testctrl(operation);
end for;
end for;
end tb_spi2axi_operation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2929.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02929ent IS
END c02s02b00x00p04n01i02929ent;
ARCHITECTURE c02s02b00x00p04n01i02929arch OF c02s02b00x00p04n01i02929ent IS
function Q return BIT;
function Q return BIT is
for all : COMP_NAME use entity (open) architecture(open);
end for; -- Failure_here
-- ERROR : configuration specification not allowed in subprogram declarations
begin
return '0';
end Q;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02929 - Configuration declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02929arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2929.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02929ent IS
END c02s02b00x00p04n01i02929ent;
ARCHITECTURE c02s02b00x00p04n01i02929arch OF c02s02b00x00p04n01i02929ent IS
function Q return BIT;
function Q return BIT is
for all : COMP_NAME use entity (open) architecture(open);
end for; -- Failure_here
-- ERROR : configuration specification not allowed in subprogram declarations
begin
return '0';
end Q;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02929 - Configuration declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02929arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2929.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02929ent IS
END c02s02b00x00p04n01i02929ent;
ARCHITECTURE c02s02b00x00p04n01i02929arch OF c02s02b00x00p04n01i02929ent IS
function Q return BIT;
function Q return BIT is
for all : COMP_NAME use entity (open) architecture(open);
end for; -- Failure_here
-- ERROR : configuration specification not allowed in subprogram declarations
begin
return '0';
end Q;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02929 - Configuration declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02929arch;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(8-1 downto 0);
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNVTJPHWYT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_0: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(8-1 downto 0);
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNVTJPHWYT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_0: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(8-1 downto 0);
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNVTJPHWYT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_0: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(8-1 downto 0);
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNVTJPHWYT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_0: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port
(srl_usn : out unsigned (8-1 downto 0);
sll_usn : out unsigned (8-1 downto 0);
srl_sgn : out signed (8-1 downto 0);
sll_sgn : out signed (8-1 downto 0));
end issue;
architecture beh of issue is
begin
srl_usn <= unsigned'(b"0000_0000") srl 1; -- work
sll_usn <= unsigned'(b"0000_0000") sll 1; -- fail
srl_sgn <= signed'(b"0000_0000") srl 1; -- fail
sll_sgn <= signed'(b"0000_0000") sll 1; -- fail
end architecture beh;
|
----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: test_cpu_top
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library std;
use std.textio.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_textio.all;
use std.standard.all;
entity test_cpu_top_tb is
end test_cpu_top_tb;
architecture behavioral of test_cpu_top_tb is
component cpu_top
port(
clk : in std_logic;
resetb : in std_logic;
-- Interface with boot ROM
cpu_rom_addr : out unsigned(31 downto 0);
cpu_rom_data : in std_logic_vector(31 downto 0);
-- Interface with board
boot_done : out std_logic
);
end component cpu_top;
subtype word_t is std_logic_vector(31 downto 0);
type ram_t is array(0 to 1023) of word_t;
signal rom : ram_t;
signal clk, resetb, boot_done : std_logic;
signal cpu_rom_addr : unsigned(31 downto 0);
signal cpu_rom_data : std_logic_vector(31 downto 0);
-- Simulation control
shared variable END_SIMULATION : boolean := false;
-- https://electronics.stackexchange.com/questions/180446/how-to-load-std-logic-vector-array-from-text-file-at-start-of-simulation
-- Read a *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : word_t;
variable Result : ram_t := (others => (others => '0'));
variable i : integer;
begin
for i in 0 to 1023 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
read(CurrentLine, TempWord);
Result(i) := TempWord;
end loop;
return Result;
end function;
-- Test procedures
procedure reset (
signal resetb : out std_logic
) is
begin
wait until rising_edge(clk);
resetb <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
resetb <= '1';
end procedure reset;
procedure test_1(
signal resetb : out std_logic;
signal rom : inout ram_t
) is
begin
rom <= ocram_ReadMemFile("test/simulation/code/00-SW.bin");
reset(resetb);
write(output, lf & "(TT)==============================================" & lf);
write(output, "(TT) Test 1 SW Expected Behaviour:" & lf);
write(output, "(TT) 1. All instructions are SD x0, off(x0)" & lf);
write(output, "(TT) 2. Offset start from 0x100 to 0x120" & lf);
write(output, "(TT) 3. RAM data in range should be cleared" & lf);
write(output, "(TT) 4. Waveforms must be read" & lf);
write(output, "(TT) ==============================================" & lf);
for i in 0 to 127 loop
wait until rising_edge(clk);
end loop;
end procedure test_1;
procedure test_2(
signal resetb : out std_logic;
signal rom : inout ram_t
) is
begin
rom <= ocram_ReadMemFile("test/simulation/code/01-add.bin");
-- rom <= ocram_ReadMemFile("01-add.bin");
reset(resetb);
write(output, lf & "(TT) ==============================================" & lf);
write(output, "(TT) Test 2 Add Expected Behaviour:" & lf);
write(output, "(TT) 1. 1+1 is performed" & lf);
write(output, "(TT) 2. 2 is stored in 0x100" & lf);
write(output, "(TT) 3. Waveforms must be read" & lf);
write(output, "(TT) ==============================================" & lf);
for i in 0 to 127 loop
wait until rising_edge(clk);
end loop;
end procedure test_2;
procedure test_3(
signal resetb : out std_logic;
signal rom : inout ram_t
) is
begin
rom <= ocram_ReadMemFile("test/simulation/code/02-accum.bin");
-- rom <= ocram_ReadMemFile("01-add.bin");
reset(resetb);
write(output, lf & "(TT) ==============================================" & lf);
write(output, "(TT) Test 2 Add Expected Behaviour:" & lf);
write(output, "(TT) 1. 1+1 is performed" & lf);
write(output, "(TT) 2. 2 is stored in 0x100" & lf);
write(output, "(TT) 3. Waveforms must be read" & lf);
write(output, "(TT) ==============================================" & lf);
for i in 0 to 127 loop
wait until rising_edge(clk);
end loop;
end procedure test_3;
begin
-- Reads ROM
cpu_rom_data <= rom(to_integer(signed(cpu_rom_addr(11 downto 2))));
UUT : cpu_top
port map (clk, resetb, cpu_rom_addr, cpu_rom_data, boot_done);
clk_generation : process
begin
if (not END_SIMULATION) then
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
else
wait;
end if;
end process clk_generation;
stimulus : process
begin
-- test_1(resetb, rom);
-- test_2(resetb, rom);
test_3(resetb, rom);
-- End Simulation
END_SIMULATION := true;
wait;
-- assert false report "Simulation Ended" severity failure;
end process stimulus;
end architecture behavioral;
|
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
-------------------------------------------------------------------------------
--! @file dpRam-e.vhd
--
--! @brief Dual Port Ram Entity
--
--! @details This is the DPRAM entity
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRam is
generic (
--! Data width [bit]
gWordWidth : natural := 32;
--! Number of words
gNumberOfWords : natural := 1024;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port A
oReaddata_A : out std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Write enable of port B
iWriteEnable_B : in std_logic;
--! Byteenable of port B
iByteenable_B : in std_logic_vector(gWordWidth/8-1 downto 0);
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port B
iWritedata_B : in std_logic_vector(gWordWidth-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRam;
|
entity call3 is
end;
use work.pkg.all;
architecture behav of call3 is
procedure p (a : rec) is
begin
report natural'image (a.s'left);
report natural'image (a.s'right);
assert a.s'left = 1;
assert a.s'right = 4;
end;
begin
process
variable v : rec_4dyn;
begin
p (v);
wait;
end process;
end behav;
|
entity call3 is
end;
use work.pkg.all;
architecture behav of call3 is
procedure p (a : rec) is
begin
report natural'image (a.s'left);
report natural'image (a.s'right);
assert a.s'left = 1;
assert a.s'right = 4;
end;
begin
process
variable v : rec_4dyn;
begin
p (v);
wait;
end process;
end behav;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:40:43 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for DLX,
-- consisting of clock generator, memory and bus_monitor
--
use std.textio.all,
work.dlx_types.all, work.mem_types.all;
architecture bench of dlx_test is
component clock_gen
port (phi1, phi2 : out bit;
reset : out bit);
end component;
component memory
port (phi1, phi2 : in bit;
a : in dlx_address;
d : inout dlx_word_bus bus;
width : in mem_width;
write_enable : in bit;
burst : in bit := '0';
mem_enable : in bit;
ready : out bit);
end component;
component dlx
port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
reset : in bit; -- synchronous reset input
a : out dlx_address; -- address bus output
d : inout dlx_word_bus bus; -- bidirectional data bus
halt : out bit; -- halt indicator
width : out mem_width; -- byte/haldword/word indicator
write_enable : out bit; -- selects read or write cycle
mem_enable : out bit; -- starts memory cycle
ifetch : out bit; -- indicates instruction fetch
ready : in bit); -- status from memory system
end component;
component dlx_bus_monitor
port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
reset : in bit; -- synchronous reset
a : in dlx_address; -- address bus
d : in dlx_word; -- data bus
halt : in bit; -- halt indicator
width : in mem_width; -- byte/haldword/word indicator
write_enable : in bit; -- selects read or write cycle
burst : in bit := '0'; -- indicates more to come in burst
mem_enable : in bit; -- starts memory cycle
ifetch : in bit; -- indicates instruction fetch
ready : in bit); -- status from memory system
end component;
signal phi1, phi2, reset : bit;
signal a : dlx_address;
signal d : dlx_word_bus bus;
signal halt : bit;
signal width : mem_width;
signal write_enable, mem_enable, ifetch, ready : bit;
begin
cg : clock_gen
port map (phi1, phi2, reset);
mem : memory
port map (phi1, phi2, a, d, width, write_enable, open, mem_enable, ready);
proc : dlx
port map (phi1, phi2, reset, a, d,
halt, width, write_enable, mem_enable, ifetch, ready);
bus_monitor : dlx_bus_monitor
port map (phi1, phi2, reset, a, d,
halt, width, write_enable, open, mem_enable, ifetch, ready);
end bench;
|
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8+BAy+C1dIE=
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART Transmitter ---------------------------------------------------------
entity uart_tx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
busy : out std_logic;
--
txd : out std_logic );
end uart_tx;
-----------------------------------------------------------------------------
-- Implemenattion -----------------------------------------------------------
architecture rtl of uart_tx is
constant halfbit : integer := fullbit / 2;
-- Signals
signal bitcount : integer range 0 to 10;
signal count : integer range 0 to fullbit;
signal shiftreg : std_logic_vector(7 downto 0);
begin
proc: process(clk, reset)
begin
if reset='1' then
count <= 0;
bitcount <= 0;
busy <= '0';
txd <= '1';
elsif clk'event and clk='1' then
if count/=0 then
count <= count - 1;
else
if bitcount=0 then
busy <= '0';
if wr='1' then -- START BIT
shiftreg <= din;
busy <= '1';
txd <= '0';
bitcount <= bitcount + 1;
count <= fullbit;
end if;
elsif bitcount=9 then -- STOP BIT
txd <= '1';
bitcount <= 0;
count <= fullbit;
else -- DATA BIT
shiftreg(6 downto 0) <= shiftreg(7 downto 1);
txd <= shiftreg(0);
bitcount <= bitcount + 1;
count <= fullbit;
end if;
end if;
end if;
end process;
end rtl; |
-------------------------------------------------------------------------------
-- Title : Helper Functions
-- Project :
-------------------------------------------------------------------------------
-- File : Helpers_Pkg.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-29
-- Last update: 2016-07-29
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Helper Functions for VHDL
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-29 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Helpers_Pkg is
-----------------------------------------------------------------------------
-- helper functions
-----------------------------------------------------------------------------
-- converts a boolean signal to a std_logic signal
function bool2sl(L : boolean) return std_logic;
-- does bit-reversal on an SLV (only downto indexing!)
function reverseBits(L : std_logic_vector) return std_logic_vector;
end package Helpers_Pkg;
package body Helpers_Pkg is
-----------------------------------------------------------------------------
-- helper functions
-----------------------------------------------------------------------------
function bool2sl(L : boolean) return std_logic is
begin
if L then
return('1');
else
return('0');
end if;
end function bool2sl;
function reverseBits(L : std_logic_vector) return std_logic_vector is
constant maxidx : integer := L'left;
variable result : std_logic_vector(L'range) := (others => '0');
begin
for i in L'range loop
result(i) := L(maxidx-i);
end loop; -- i
return result;
end function reverseBits;
end package body Helpers_Pkg;
|
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
end behav;
|
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
end behav;
|
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
end behav;
|
entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
end behav;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
--use work.protected_types_pkg.all;
use work.vhdl_version_layer_pkg.all;
use work.license_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_DEFAULT_MSG_ID_PANEL;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
);
-- Overloaded version with additional arguments
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_bitvis_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_bitvis_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME, ID_NEVER);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME, ID_NEVER);
end if;
--show_license(VOID);
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
-- show_bitvis_utility_library_info(VOID);
-- end if;
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO then
-- show_bitvis_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_alert_file_name_is_set then
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
else
warning("alert file name already set - or set too late");
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_log_file_name_is_set then
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
else
warning("log file name already set - or set too late");
end if;
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all & lf);
writeline(file_handle, v_line);
end procedure tee;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel -- compatible with old code
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), C_LOG_MSG_ID_WIDTH, LEFT, TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
else
v_log_scope := justify(scope, C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, global_show_log_id) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, global_show_log_scope) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, replace_backslash_n_with_lf(v_msg.all));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_info_final);
end if;
end;
-- Logging for multi line text
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
tee(OUTPUT, text_block); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, text_block);
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
tee(OUTPUT, v_header_line); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_header_line);
-- Print header using log function
log(msg_id, msg_header, scope, msg_id_panel);
-- Print header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
tee(OUTPUT, v_log_body); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_log_body);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
log(ID_LOG_MSG_CTRL, "enable_log_msg() ignored for " & to_string(msg_id) & ". (Not allowed)" & msg, scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
when others =>
msg_id_panel(msg_id) := ENABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_msg, replace_backslash_n_with_lf(msg));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_string(alert_level) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_string(alert_level) & "s by " & to_string(number) & ". " & msg, scope);
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(order);
pot_initialise_util(VOID); -- Only executed the first time called
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
pot_initialise_util(VOID); -- Only executed the first time called
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", C_LOG_MSG_ID_WIDTH, LEFT) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if (i /= ID_NEVER) then -- report all but ID_NEVER
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_string(shared_msg_id_panel(i)) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_string(alert_level) & ", " & to_string(attention) & "). " & msg);
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
return shared_alert_attention(alert_level);
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_string(alert_level) & " set to " & to_string(value) &
", which is lower than the current " & to_string(alert_level) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
return shared_stop_limit(alert_level);
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", 100) then
deprecated_subprogram_list(i) := justify(caller_name, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, name & " => OK, for boolean true. " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Boolean was false. " & msg, scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for boolean " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & msg, scope, msg_id_panel);
end if;
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "' (exp: x'" & v_exp_str & "'). " & msg,
scope, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. " & value_type & " Was x'" & v_value_str & "'. Expected x'" & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & value & "'. " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK." & value_string & " stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & msg, scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, name & " => Unknown stable_req_from." & msg, scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, name & " => Unknown timeout_from." & msg, scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, name & " => OK. Condition occurred immediately." & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(pulse_duration) & ". " & msg, scope);
target <= '1'; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= '0';
else
target <= transport '0' after pulse_duration;
end if;
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= '1';
wait for 0 ns;
end if;
target <= '0';
end;
-- gen_pulse(slv)
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= pulse_value;
wait for 0 ns;
end if;
target(target'range) <= (others => '0');
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
if not clock_ena then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
end package body methods_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
--use work.protected_types_pkg.all;
use work.vhdl_version_layer_pkg.all;
use work.license_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_DEFAULT_MSG_ID_PANEL;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
);
-- Overloaded version with additional arguments
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_bitvis_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_bitvis_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME, ID_NEVER);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME, ID_NEVER);
end if;
--show_license(VOID);
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
-- show_bitvis_utility_library_info(VOID);
-- end if;
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO then
-- show_bitvis_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_alert_file_name_is_set then
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
else
warning("alert file name already set - or set too late");
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_log_file_name_is_set then
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
else
warning("log file name already set - or set too late");
end if;
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all & lf);
writeline(file_handle, v_line);
end procedure tee;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel -- compatible with old code
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), C_LOG_MSG_ID_WIDTH, LEFT, TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
else
v_log_scope := justify(scope, C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, global_show_log_id) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, global_show_log_scope) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, replace_backslash_n_with_lf(v_msg.all));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_info_final);
end if;
end;
-- Logging for multi line text
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
tee(OUTPUT, text_block); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, text_block);
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
tee(OUTPUT, v_header_line); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_header_line);
-- Print header using log function
log(msg_id, msg_header, scope, msg_id_panel);
-- Print header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
tee(OUTPUT, v_log_body); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_log_body);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
log(ID_LOG_MSG_CTRL, "enable_log_msg() ignored for " & to_string(msg_id) & ". (Not allowed)" & msg, scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
when others =>
msg_id_panel(msg_id) := ENABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_msg, replace_backslash_n_with_lf(msg));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_string(alert_level) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_string(alert_level) & "s by " & to_string(number) & ". " & msg, scope);
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(order);
pot_initialise_util(VOID); -- Only executed the first time called
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
pot_initialise_util(VOID); -- Only executed the first time called
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", C_LOG_MSG_ID_WIDTH, LEFT) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if (i /= ID_NEVER) then -- report all but ID_NEVER
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_string(shared_msg_id_panel(i)) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_string(alert_level) & ", " & to_string(attention) & "). " & msg);
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
return shared_alert_attention(alert_level);
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_string(alert_level) & " set to " & to_string(value) &
", which is lower than the current " & to_string(alert_level) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
return shared_stop_limit(alert_level);
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", 100) then
deprecated_subprogram_list(i) := justify(caller_name, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, name & " => OK, for boolean true. " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Boolean was false. " & msg, scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for boolean " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & msg, scope, msg_id_panel);
end if;
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "' (exp: x'" & v_exp_str & "'). " & msg,
scope, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. " & value_type & " Was x'" & v_value_str & "'. Expected x'" & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & value & "'. " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK." & value_string & " stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & msg, scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, name & " => Unknown stable_req_from." & msg, scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, name & " => Unknown timeout_from." & msg, scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, name & " => OK. Condition occurred immediately." & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(pulse_duration) & ". " & msg, scope);
target <= '1'; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= '0';
else
target <= transport '0' after pulse_duration;
end if;
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= '1';
wait for 0 ns;
end if;
target <= '0';
end;
-- gen_pulse(slv)
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= pulse_value;
wait for 0 ns;
end if;
target(target'range) <= (others => '0');
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
if not clock_ena then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
end package body methods_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
--use work.protected_types_pkg.all;
use work.vhdl_version_layer_pkg.all;
use work.license_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_DEFAULT_MSG_ID_PANEL;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
);
-- Overloaded version with additional arguments
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_bitvis_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_bitvis_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME, ID_NEVER);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME, ID_NEVER);
end if;
--show_license(VOID);
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
-- show_bitvis_utility_library_info(VOID);
-- end if;
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO then
-- show_bitvis_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_alert_file_name_is_set then
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
else
warning("alert file name already set - or set too late");
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_log_file_name_is_set then
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
else
warning("log file name already set - or set too late");
end if;
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all & lf);
writeline(file_handle, v_line);
end procedure tee;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel -- compatible with old code
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), C_LOG_MSG_ID_WIDTH, LEFT, TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
else
v_log_scope := justify(scope, C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, global_show_log_id) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, global_show_log_scope) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, replace_backslash_n_with_lf(v_msg.all));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_info_final);
end if;
end;
-- Logging for multi line text
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
tee(OUTPUT, text_block); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, text_block);
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
tee(OUTPUT, v_header_line); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_header_line);
-- Print header using log function
log(msg_id, msg_header, scope, msg_id_panel);
-- Print header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
tee(OUTPUT, v_log_body); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_log_body);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
log(ID_LOG_MSG_CTRL, "enable_log_msg() ignored for " & to_string(msg_id) & ". (Not allowed)" & msg, scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
when others =>
msg_id_panel(msg_id) := ENABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_msg, replace_backslash_n_with_lf(msg));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_string(alert_level) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_string(alert_level) & "s by " & to_string(number) & ". " & msg, scope);
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(order);
pot_initialise_util(VOID); -- Only executed the first time called
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
pot_initialise_util(VOID); -- Only executed the first time called
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", C_LOG_MSG_ID_WIDTH, LEFT) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if (i /= ID_NEVER) then -- report all but ID_NEVER
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_string(shared_msg_id_panel(i)) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_string(alert_level) & ", " & to_string(attention) & "). " & msg);
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
return shared_alert_attention(alert_level);
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_string(alert_level) & " set to " & to_string(value) &
", which is lower than the current " & to_string(alert_level) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
return shared_stop_limit(alert_level);
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", 100) then
deprecated_subprogram_list(i) := justify(caller_name, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, name & " => OK, for boolean true. " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Boolean was false. " & msg, scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for boolean " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & msg, scope, msg_id_panel);
end if;
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "' (exp: x'" & v_exp_str & "'). " & msg,
scope, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. " & value_type & " Was x'" & v_value_str & "'. Expected x'" & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & value & "'. " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK." & value_string & " stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & msg, scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, name & " => Unknown stable_req_from." & msg, scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, name & " => Unknown timeout_from." & msg, scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, name & " => OK. Condition occurred immediately." & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(pulse_duration) & ". " & msg, scope);
target <= '1'; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= '0';
else
target <= transport '0' after pulse_duration;
end if;
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= '1';
wait for 0 ns;
end if;
target <= '0';
end;
-- gen_pulse(slv)
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= pulse_value;
wait for 0 ns;
end if;
target(target'range) <= (others => '0');
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
if not clock_ena then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
end package body methods_pkg;
|
architecture rtl of InputSwitchingMatrix is
signal CfgValue : std_logic_vector(InputWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => InputWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
-- InputWidth = 10
-- Input_i
-- /--------------------------\
--
-- 9 8 7 6 5 4 3 2 1 0
-- | | | | | | | | | |
-- v v v v v v v v v v
-- | | | | | | | | | |
-- X--X--X--X--X--X--X--+--+--+---> 3 \
-- | | | | | | | | | | |
-- +--X--X--X--X--X--X--X--+--+---> 2 |
-- | | | | | | | | | | | Output_o
-- +--+--X--X--X--X--X--X--X--+---> 1 | OutputWidth = 4
-- | | | | | | | | | | |
-- +--+--+--X--X--X--X--X--X--X---> 0 /
InputSwitching: process (Input_i,CfgValue)
type UsedArr_t is array (OutputWidth-1 downto 0) of std_logic_vector(InputWidth downto 0);
type DoneArr_t is array (OutputWidth downto 0) of std_logic_vector(InputWidth-1 downto 0);
type FullArr_t is array (OutputWidth-1 downto 0) of std_logic_vector(InputWidth-1 downto 0);
variable Enable : std_logic;
variable Used : UsedArr_t;
variable Done : DoneArr_t;
variable OutputPre : FullArr_t;
begin -- process InputSwitching
Used := (others => (others => '0'));
Done := (others => (others => '0'));
for OutputNr in OutputWidth-1 downto 0 loop
for InputNr in InputWidth-1 downto 0 loop
Enable := CfgValue(InputNr) and (not Done(OutputNr+1)(InputNr)) and (not Used(OutputNr)(InputNr+1));
OutputPre(OutputNr)(InputNr) := Enable and Input_i(InputNr);
Used (OutputNr)(InputNr) := Enable or Used(OutputNr)(InputNr+1);
Done (OutputNr)(InputNr) := Enable or Done(OutputNr+1)(InputNr);
if InputNr = OutputNr then
Used(OutputNr)(InputNr) := '1';
end if;
end loop; -- InputNr
Output_o(OutputNr) <= or_reduce(OutputPre(OutputNr));
end loop; -- OutputNr
end process InputSwitching;
CheckConfig: process (CfgValue)
variable NumOutputs : integer;
begin -- process CheckConfig
NumOutputs := 0;
for i in InputWidth-1 downto 0 loop
if CfgValue(i) = '1' then
NumOutputs := NumOutputs + 1;
end if;
end loop;
-- check if we have too many 1s
-- assert NumOutputs <= OutputWidth
-- report "FATAL: InputSwitchingMatrix with InputWidth = " & integer'image(InputWidth) & " and OutputWidth = " & integer'image(OutputWidth) & " has too many outputs configured (" & integer'image(NumOutputs) & ")"
-- severity failure;
end process CheckConfig;
end rtl; -- of InputSwitchingMatrix
|
architecture rtl of InputSwitchingMatrix is
signal CfgValue : std_logic_vector(InputWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => InputWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
-- InputWidth = 10
-- Input_i
-- /--------------------------\
--
-- 9 8 7 6 5 4 3 2 1 0
-- | | | | | | | | | |
-- v v v v v v v v v v
-- | | | | | | | | | |
-- X--X--X--X--X--X--X--+--+--+---> 3 \
-- | | | | | | | | | | |
-- +--X--X--X--X--X--X--X--+--+---> 2 |
-- | | | | | | | | | | | Output_o
-- +--+--X--X--X--X--X--X--X--+---> 1 | OutputWidth = 4
-- | | | | | | | | | | |
-- +--+--+--X--X--X--X--X--X--X---> 0 /
InputSwitching: process (Input_i,CfgValue)
type UsedArr_t is array (OutputWidth-1 downto 0) of std_logic_vector(InputWidth downto 0);
type DoneArr_t is array (OutputWidth downto 0) of std_logic_vector(InputWidth-1 downto 0);
type FullArr_t is array (OutputWidth-1 downto 0) of std_logic_vector(InputWidth-1 downto 0);
variable Enable : std_logic;
variable Used : UsedArr_t;
variable Done : DoneArr_t;
variable OutputPre : FullArr_t;
begin -- process InputSwitching
Used := (others => (others => '0'));
Done := (others => (others => '0'));
for OutputNr in OutputWidth-1 downto 0 loop
for InputNr in InputWidth-1 downto 0 loop
Enable := CfgValue(InputNr) and (not Done(OutputNr+1)(InputNr)) and (not Used(OutputNr)(InputNr+1));
OutputPre(OutputNr)(InputNr) := Enable and Input_i(InputNr);
Used (OutputNr)(InputNr) := Enable or Used(OutputNr)(InputNr+1);
Done (OutputNr)(InputNr) := Enable or Done(OutputNr+1)(InputNr);
if InputNr = OutputNr then
Used(OutputNr)(InputNr) := '1';
end if;
end loop; -- InputNr
Output_o(OutputNr) <= or_reduce(OutputPre(OutputNr));
end loop; -- OutputNr
end process InputSwitching;
CheckConfig: process (CfgValue)
variable NumOutputs : integer;
begin -- process CheckConfig
NumOutputs := 0;
for i in InputWidth-1 downto 0 loop
if CfgValue(i) = '1' then
NumOutputs := NumOutputs + 1;
end if;
end loop;
-- check if we have too many 1s
-- assert NumOutputs <= OutputWidth
-- report "FATAL: InputSwitchingMatrix with InputWidth = " & integer'image(InputWidth) & " and OutputWidth = " & integer'image(OutputWidth) & " has too many outputs configured (" & integer'image(NumOutputs) & ")"
-- severity failure;
end process CheckConfig;
end rtl; -- of InputSwitchingMatrix
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper;
architecture europa of tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper is
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk;
--synthesis read_comments_as_HDL on
-- component sld_virtual_jtag_basic is
--GENERIC (
-- sld_auto_instance_index : STRING;
-- sld_instance_index : NATURAL;
-- sld_ir_width : NATURAL;
-- sld_mfg_id : NATURAL;
-- sld_sim_action : STRING;
-- sld_sim_n_scan : NATURAL;
-- sld_sim_total_length : NATURAL;
-- sld_type_id : NATURAL;
-- sld_version : NATURAL
-- );
-- PORT (
-- signal virtual_state_udr : OUT STD_LOGIC;
-- signal ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdi : OUT STD_LOGIC;
-- signal virtual_state_sdr : OUT STD_LOGIC;
-- signal jtag_state_rti : OUT STD_LOGIC;
-- signal tck : OUT STD_LOGIC;
-- signal virtual_state_cdr : OUT STD_LOGIC;
-- signal virtual_state_uir : OUT STD_LOGIC;
-- signal ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal tdo : IN STD_LOGIC
-- );
-- end component sld_virtual_jtag_basic;
--synthesis read_comments_as_HDL off
signal internal_jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal internal_jrst_n : STD_LOGIC;
signal internal_st_ready_test_idle : STD_LOGIC;
signal internal_take_action_break_a : STD_LOGIC;
signal internal_take_action_break_b : STD_LOGIC;
signal internal_take_action_break_c : STD_LOGIC;
signal internal_take_action_ocimem_a : STD_LOGIC;
signal internal_take_action_ocimem_b : STD_LOGIC;
signal internal_take_action_tracectrl : STD_LOGIC;
signal internal_take_action_tracemem_a : STD_LOGIC;
signal internal_take_action_tracemem_b : STD_LOGIC;
signal internal_take_no_action_break_a : STD_LOGIC;
signal internal_take_no_action_break_b : STD_LOGIC;
signal internal_take_no_action_break_c : STD_LOGIC;
signal internal_take_no_action_ocimem_a : STD_LOGIC;
signal internal_take_no_action_tracemem_a : STD_LOGIC;
signal sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vji_cdr : STD_LOGIC;
signal vji_ir_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_ir_out : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal vji_rti : STD_LOGIC;
signal vji_sdr : STD_LOGIC;
signal vji_tck : STD_LOGIC;
signal vji_tdi : STD_LOGIC;
signal vji_tdo : STD_LOGIC;
signal vji_udr : STD_LOGIC;
signal vji_uir : STD_LOGIC;
begin
--Change the sld_virtual_jtag_basic's defparams to
--switch between a regular Nios II or an internally embedded Nios II.
--For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
--For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
--the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck, which is an e_instance
the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck : tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck
port map(
ir_out => vji_ir_out,
jrst_n => internal_jrst_n,
sr => sr,
st_ready_test_idle => internal_st_ready_test_idle,
tdo => vji_tdo,
MonDReg => MonDReg,
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
ir_in => vji_ir_in,
jtag_state_rti => vji_rti,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tck => vji_tck,
tdi => vji_tdi,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1,
vs_cdr => vji_cdr,
vs_sdr => vji_sdr,
vs_uir => vji_uir
);
--the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk, which is an e_instance
the_tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk : tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk
port map(
jdo => internal_jdo,
take_action_break_a => internal_take_action_break_a,
take_action_break_b => internal_take_action_break_b,
take_action_break_c => internal_take_action_break_c,
take_action_ocimem_a => internal_take_action_ocimem_a,
take_action_ocimem_b => internal_take_action_ocimem_b,
take_action_tracectrl => internal_take_action_tracectrl,
take_action_tracemem_a => internal_take_action_tracemem_a,
take_action_tracemem_b => internal_take_action_tracemem_b,
take_no_action_break_a => internal_take_no_action_break_a,
take_no_action_break_b => internal_take_no_action_break_b,
take_no_action_break_c => internal_take_no_action_break_c,
take_no_action_ocimem_a => internal_take_no_action_ocimem_a,
take_no_action_tracemem_a => internal_take_no_action_tracemem_a,
clk => clk,
ir_in => vji_ir_in,
sr => sr,
vs_udr => vji_udr,
vs_uir => vji_uir
);
--vhdl renameroo for output signals
jdo <= internal_jdo;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n;
--vhdl renameroo for output signals
st_ready_test_idle <= internal_st_ready_test_idle;
--vhdl renameroo for output signals
take_action_break_a <= internal_take_action_break_a;
--vhdl renameroo for output signals
take_action_break_b <= internal_take_action_break_b;
--vhdl renameroo for output signals
take_action_break_c <= internal_take_action_break_c;
--vhdl renameroo for output signals
take_action_ocimem_a <= internal_take_action_ocimem_a;
--vhdl renameroo for output signals
take_action_ocimem_b <= internal_take_action_ocimem_b;
--vhdl renameroo for output signals
take_action_tracectrl <= internal_take_action_tracectrl;
--vhdl renameroo for output signals
take_action_tracemem_a <= internal_take_action_tracemem_a;
--vhdl renameroo for output signals
take_action_tracemem_b <= internal_take_action_tracemem_b;
--vhdl renameroo for output signals
take_no_action_break_a <= internal_take_no_action_break_a;
--vhdl renameroo for output signals
take_no_action_break_b <= internal_take_no_action_break_b;
--vhdl renameroo for output signals
take_no_action_break_c <= internal_take_no_action_break_c;
--vhdl renameroo for output signals
take_no_action_ocimem_a <= internal_take_no_action_ocimem_a;
--vhdl renameroo for output signals
take_no_action_tracemem_a <= internal_take_no_action_tracemem_a;
--synthesis translate_off
vji_tck <= std_logic'('0');
vji_tdi <= std_logic'('0');
vji_sdr <= std_logic'('0');
vji_cdr <= std_logic'('0');
vji_rti <= std_logic'('0');
vji_uir <= std_logic'('0');
vji_udr <= std_logic'('0');
vji_ir_in <= std_logic_vector'("00");
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- tracking_camera_system_nios2_qsys_0_jtag_debug_module_phy : sld_virtual_jtag_basic
-- generic map(
-- sld_auto_instance_index => "YES",
-- sld_instance_index => 0,
-- sld_ir_width => 2,
-- sld_mfg_id => 70,
-- sld_sim_action => "",
-- sld_sim_n_scan => 0,
-- sld_sim_total_length => 0,
-- sld_type_id => 34,
-- sld_version => 3
-- )
-- port map(
-- ir_in => vji_ir_in,
-- ir_out => vji_ir_out,
-- jtag_state_rti => vji_rti,
-- tck => vji_tck,
-- tdi => vji_tdi,
-- tdo => vji_tdo,
-- virtual_state_cdr => vji_cdr,
-- virtual_state_sdr => vji_sdr,
-- virtual_state_udr => vji_udr,
-- virtual_state_uir => vji_uir
-- );
--
--synthesis read_comments_as_HDL off
end europa;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
-- 2012-03-21 V0.10 zelenkaj Fixed 32 bit FIFO to support openMAC endian
-- 2012-04-17 V0.11 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
-- 2012-03-21 V0.10 zelenkaj Fixed 32 bit FIFO to support openMAC endian
-- 2012-04-17 V0.11 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
-- 2012-03-21 V0.10 zelenkaj Fixed 32 bit FIFO to support openMAC endian
-- 2012-04-17 V0.11 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Latch is
port( clk : in std_logic;
d : in std_logic;
q : out std_logic);
end Latch;
architecture Behavioral of Latch is
begin
process (clk)
begin
if(clk='1') then
q <= d;
end if;
end process;
end Behavioral; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ml506_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 23;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 100000000;
CLK_MUL : positive := 20;
CLK_DIV : positive := 11;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
leds : out std_logic_vector(0 to 7)
);
end ml506_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of ml506_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "HIGH",
DFS_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
CLKFB => '0',
CLKIN => clkx,
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= (not rstx) & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail;
end rtl;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
PORT MAP (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
PORT MAP (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
PORT MAP (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
PORT MAP (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
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