content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2681.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02681ent IS
--ERROR: underline cannot lead a real literal
constant a:real:=_1234.5678; -- failure_here
END c13s04b01x00p02n01i02681ent;
ARCHITECTURE c13s04b01x00p02n01i02681arch OF c13s04b01x00p02n01i02681ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02681 - Decimal literal can only begin with an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02681arch;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_buf package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Technology constants definition.
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' Buffers components.
package types_buf is
--! @brief Clock signals multiplexer.
--! @param[in] tech Technology selector.
--! @param[out] O Output clock signal.
--! @param[in] I1 Input clock signal 1.
--! @param[in] I2 Input clock signal 2.
--! @param[in] S Input signals switcher:
--! 0 = I1; 1 = I2.
component bufgmux_tech is
generic (
tech : integer := 0;
rf_frontend_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic);
end component;
--! @brief Input PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered signal.
--! @param[in] i Input unbuffered signal.
component ibuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input clocking PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered clock signal.
--! @param[in] i Input unbuffered clock signal.
component ibufg_tech is generic (tech : integer := 0);
port (
O : out std_ulogic;
I : in std_ulogic
);
end component;
--! @brief Output PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal directly connected to the ASIC output pin.
--! @param[in] i Input signal.
component obuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input/Output PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal
--! @param[inout] io Bi-directional signal.
--! @param[in] i Input signal
--! @param[in] t Controlling signal: 0 = in; 1=out
--!
--! Example:
--! @code
--! entity foo is port (
--! io_gpio : inout std_logic
--! )
--! end foo;
--! architecture rtl of foo is
--! signal ob_gpio_direction : std_logic;
--! signal ob_gpio_opins : std_logic;
--! signal ib_gpio_ipins : std_logic;
--! ...
--! begin
--! ob_gpio_direction <= '1';
--!
--! iob : iobuf_tech generic map(kintex7)
--! port map (ib_gpio_ipins, io_gpio, ob_gpio_opins, ob_gpio_direction);
--!
--! reg : process(clk, nrst) begin
--! if rising_edge(clk) then
--! reg1 <= ib_gpio_ipins;
--! ob_gpio_opins <= reg2;
--! end;
--! end process;
--! end;
--! @endcode
component iobuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
--! @brief Gigabit buffer with differential inputs.
--! @param[in] gclk_p Differential clock input.
--! @param[in] gclk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
--! @brief Input buffer with differential inputs.
--! @param[in] clk_p Differential clock input.
--! @param[in] clk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component idsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
o_clk : out std_logic
);
end component;
end;
|
-- NEED RESULT: ARCH00540: Attributes for multi-dimensional arrays passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00540
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (12)
-- 14.1 (14)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00540)
-- ENT00540_Test_Bench(ARCH00540_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
-- 18-JAN-1988 - remove function calls as prefixes of predefined attributes
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00540 of E00000 is
begin
P :
process
type tt_arr2 is array (lowb to highb, false to true) of st_arr1;
variable a : st_arr2 ;
function f return st_arr2 is
variable x : st_arr2 ;
begin
return x ;
end f ;
subtype a_range_1 is integer range a'range ;
subtype a_range_2 is boolean range a'range(2) ;
-- subtype f_range_1 is integer range f'range ;
-- subtype f_range_2 is boolean range f'range(2) ;
subtype s_range_1 is integer range st_arr2'range ;
subtype s_range_2 is boolean range st_arr2'range(2) ;
subtype t_range_1 is integer range tt_arr2'range ;
subtype t_range_2 is boolean range tt_arr2'range(2) ;
subtype a_reverse_range_1 is integer range a'reverse_range ;
subtype a_reverse_range_2 is boolean range a'reverse_range(2) ;
-- subtype f_reverse_range_1 is integer range f'reverse_range ;
-- subtype f_reverse_range_2 is boolean range f'reverse_range(2) ;
subtype s_reverse_range_1 is integer range st_arr2'reverse_range ;
subtype s_reverse_range_2 is boolean range st_arr2'reverse_range(2) ;
subtype t_reverse_range_1 is integer range tt_arr2'reverse_range ;
subtype t_reverse_range_2 is boolean range tt_arr2'reverse_range(2) ;
begin
test_report ( "ARCH00540" ,
"Attributes for multi-dimensional arrays" ,
-- these test 14.1 (12)
(a'left(2) = false) and
(a'right(2) = true) and
(a'low(2) = false) and
(a'high(2) = true) and
(a_range_2'left = false) and
(a_reverse_range_2'left = true) and
(a'length(2) = 2) and
-- (f'left(2) = false) and
-- (f'right(2) = true) and
-- (f'low(2) = false) and
-- (f'high(2) = true) and
-- (f_range_2'left = false) and
-- (f_reverse_range_2'left = true) and
-- (f'length(2) = 2) and
(tt_arr2'left(2) = false) and
(tt_arr2'right(2) = true) and
(tt_arr2'low(2) = false) and
(tt_arr2'high(2) = true) and
(t_range_2'left = false) and
(t_reverse_range_2'left = true) and
(tt_arr2'length(2) = 2) and
(st_arr2'left(2) = false) and
(st_arr2'right(2) = true) and
(st_arr2'low(2) = false) and
(st_arr2'high(2) = true) and
(s_range_2'left = false) and
(s_reverse_range_2'left = true) and
(st_arr2'length(2) = 2) and
-- these test 14.1 (14)
(a_range_1'left = lowb) and
(a_reverse_range_1'left = highb) and
(a'length = highb-lowb+1) and
-- (f_range_1'left = lowb) and
-- (f_reverse_range_1'left = highb) and
-- (f'length = highb-lowb+1) and
(t_range_1'left = lowb) and
(t_reverse_range_1'left = highb) and
(tt_arr2'length = highb-lowb+1) and
(s_range_1'left = lowb) and
(s_reverse_range_1'left = highb) and
(st_arr2'length = highb-lowb+1)
) ;
wait ;
end process P ;
end ARCH00540 ;
--
entity ENT00540_Test_Bench is
end ENT00540_Test_Bench ;
architecture ARCH00540_Test_Bench of ENT00540_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00540 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00540_Test_Bench ;
--
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_413 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end cmp_413;
architecture augh of cmp_413 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_413 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end cmp_413;
architecture augh of cmp_413 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- 1 Khz clock source
--
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - 1 Mhz input, signal must be one cycle high each micro-second.
-- ena_1khz - 1 Khz output. Signal is one cycle '1' each 1 millisecond.
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_1khz is
port (
clk : in std_logic;
ena_1mhz : in std_logic;
ena_1khz : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_1khz is
constant reset_count : integer := 1025 - 1000;
signal cnt : unsigned(10 downto 0) := (others => '0');
signal ena_out : std_logic := '0';
begin
ena_1khz <= ena_out;
process(clk)
begin
if rising_edge(clk) then
ena_out <= '0';
if ena_1mhz = '1' then
ena_out <= cnt(cnt'high);
if cnt(cnt'high) = '1' then
cnt <= to_unsigned(reset_count, cnt'length);
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
end architecture;
|
package pack is
type op_t is (IDLE, DO_A, DO_B, CLASH);
type op_vec_t is array (natural range <>) of op_t;
function resolved (s : op_vec_t) return op_t;
subtype r_op_t is resolved op_t;
end package;
package body pack is
function resolved (s : op_vec_t) return op_t is
variable result : op_t := IDLE;
begin
for i in s'range loop
if result = IDLE then
result := s(i);
elsif s(i) /= IDLE then
result := CLASH;
exit;
end if;
end loop;
report "result=" & op_t'image(result);
return result;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( s : inout r_op_t;
done : out boolean );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert s = idle;
wait on s;
assert now = 1 ns;
assert s = do_a;
wait on s;
assert now = 2 ns;
assert s = do_b;
done <= true;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity driver10 is
end entity;
architecture test of driver10 is
signal t : r_op_t := IDLE;
signal done : boolean := false;
begin
uut: entity work.sub port map (t, done);
p2: process is
begin
assert t = IDLE;
wait for 1 ns;
t <= DO_A;
wait for 1 ns;
t <= DO_B;
wait;
end process;
p3: process is
begin
wait for 1 hr;
assert done = true;
wait;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
ddr0: ddrram
generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:43 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_stub.vhdl
-- Design : RAT_ControlUnit_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_ControlUnit_0_0 is
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC
);
end RAT_ControlUnit_0_0;
architecture stub of RAT_ControlUnit_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,C,Z,INT,RST,OPCODE_HI_5[4:0],OPCODE_LO_2[1:0],PC_LD,PC_INC,PC_RESET,PC_OE,PC_MUX_SEL[1:0],SP_LD,SP_MUX_SEL[1:0],SP_RESET,RF_WR,RF_WR_SEL[1:0],RF_OE,REG_IMMED_SEL,ALU_SEL[3:0],ALU_OPY_SEL,SCR_WR,SCR_OE,SCR_ADDR_SEL[1:0],C_FLAG_SEL,C_FLAG_LD,C_FLAG_SET,C_FLAG_CLR,SHAD_C_LD,Z_FLAG_SEL,Z_FLAG_LD,Z_FLAG_SET,Z_FLAG_CLR,SHAD_Z_LD,I_FLAG_SET,I_FLAG_CLR,IO_OE";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ControlUnit,Vivado 2016.4";
begin
end;
|
-- NEED RESULT: ARCH00386.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00386
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00386(ARCH00386)
-- ENT00386_Test_Bench(ARCH00386_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386 is
end ENT00386 ;
--
--
architecture ARCH00386 of ENT00386 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1(highb,false) after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1(highb,false) after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns ;
--
end ARCH00386 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386_Test_Bench is
end ENT00386_Test_Bench ;
--
--
architecture ARCH00386_Test_Bench of ENT00386_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00386 ( ARCH00386 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00386_Test_Bench ;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_nov;
architecture behaviour of ex5_nov is
constant s1: std_logic_vector(3 downto 0) := "1110";
constant s2: std_logic_vector(3 downto 0) := "1101";
constant s3: std_logic_vector(3 downto 0) := "1010";
constant s4: std_logic_vector(3 downto 0) := "1001";
constant s5: std_logic_vector(3 downto 0) := "1111";
constant s6: std_logic_vector(3 downto 0) := "1011";
constant s7: std_logic_vector(3 downto 0) := "1100";
constant s8: std_logic_vector(3 downto 0) := "1000";
constant s0: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_ControlUnit_0_0 IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END RAT_ControlUnit_0_0;
ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ControlUnit IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END COMPONENT ControlUnit;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST";
BEGIN
U0 : ControlUnit
PORT MAP (
CLK => CLK,
C => C,
Z => Z,
INT => INT,
RST => RST,
OPCODE_HI_5 => OPCODE_HI_5,
OPCODE_LO_2 => OPCODE_LO_2,
PC_LD => PC_LD,
PC_INC => PC_INC,
PC_RESET => PC_RESET,
PC_OE => PC_OE,
PC_MUX_SEL => PC_MUX_SEL,
SP_LD => SP_LD,
SP_MUX_SEL => SP_MUX_SEL,
SP_RESET => SP_RESET,
RF_WR => RF_WR,
RF_WR_SEL => RF_WR_SEL,
RF_OE => RF_OE,
REG_IMMED_SEL => REG_IMMED_SEL,
ALU_SEL => ALU_SEL,
ALU_OPY_SEL => ALU_OPY_SEL,
SCR_WR => SCR_WR,
SCR_OE => SCR_OE,
SCR_ADDR_SEL => SCR_ADDR_SEL,
C_FLAG_SEL => C_FLAG_SEL,
C_FLAG_LD => C_FLAG_LD,
C_FLAG_SET => C_FLAG_SET,
C_FLAG_CLR => C_FLAG_CLR,
SHAD_C_LD => SHAD_C_LD,
Z_FLAG_SEL => Z_FLAG_SEL,
Z_FLAG_LD => Z_FLAG_LD,
Z_FLAG_SET => Z_FLAG_SET,
Z_FLAG_CLR => Z_FLAG_CLR,
SHAD_Z_LD => SHAD_Z_LD,
I_FLAG_SET => I_FLAG_SET,
I_FLAG_CLR => I_FLAG_CLR,
IO_OE => IO_OE
);
END RAT_ControlUnit_0_0_arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_KCU105 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 300.0 MHz
);
port (
ClockIn_300MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_300MHz : out STD_LOGIC;
Clock_300MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_Stable_300MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC
);
end entity;
-- MMCM - Clock Wizard Report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 300.000 0.000 50.0 81.568 77.836
-- CLK_OUT1 200.000 0.000 50.0 88.351 77.836
-- CLK_OUT2 100.000 0.000 50.0 101.278 77.836
--
architecture rtl of clknet_ClockNetwork_KCU105 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 300 MHz
-- slowest output clock: 100 Mhz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (300 MHz / 100 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 100 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0) := (others => '0');
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_300MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_300MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_300MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock : entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset NOR MMCM_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= NOT MMCM_Locked_d AND MMCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
Locked <= MMCM_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_300MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 300 MHz BUFG
BUFG_Clock_300MHz : BUFG
port map (
I => MMCM_Clock_300MHz,
O => MMCM_Clock_300MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCME3_ADV
generic map (
STARTUP_WAIT => "FALSE",
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 4.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => "FALSE",
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 4.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => "FALSE",
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => "FALSE",
CLKOUT2_DIVIDE => 12,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => "FALSE",
CLKOUT3_DIVIDE => 120,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => "FALSE"
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_300MHz,
CLKIN2 => ClockIn_300MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_300MHz_BUFG,
CLKFBSTOPPED => open,
CDDCREQ => '0',
CDDCDONE => open,
CLKOUT0 => MMCM_Clock_300MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_200MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_100MHz,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
Control_Clock_300MHz <= Control_Clock_BUFR;
Clock_300MHz <= MMCM_Clock_300MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncLocked300MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_300MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_300MHz -- synchronized data
);
syncLocked200MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked100MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
end architecture;
|
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup.
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0210 : Fixed wait and halt
-- 0211 : Fixed Refresh addition and IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
-- 0237 : Changed 8080 I/O address output, added IntE output
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
NMICycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet : in std_logic := '0';
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80;
architecture rtl of T80 is
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0);
DIRSet : in std_logic;
DIR : in std_logic_vector(127 downto 0)
);
end component;
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal WZ : std_logic_vector(15 downto 0); -- MEMPTR register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_RXDD : std_logic;
signal I_INRC : std_logic;
signal SetWZ : std_logic_vector(1 downto 0);
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
signal DOR : std_logic_vector(127 downto 0);
begin
REG <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0'
else IntE_FF2 & IntE_FF1 & IStatus & DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) &
std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC;
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetWZ => SetWZ,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
WZ => WZ,
XY_State=> XY_State,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
variable n : std_logic_vector(7 downto 0);
variable ioq : std_logic_vector(8 downto 0);
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
WZ <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
I_RXDD <= '0';
elsif rising_edge(CLK_n) then
if DIRSet = '1' then
ACC <= DIR( 7 downto 0);
F <= DIR(15 downto 8);
Ap <= DIR(23 downto 16);
Fp <= DIR(31 downto 24);
I <= DIR(39 downto 32);
R <= unsigned(DIR(47 downto 40));
SP <= unsigned(DIR(63 downto 48));
PC <= unsigned(DIR(79 downto 64));
A <= DIR(79 downto 64);
IStatus <= DIR(209 downto 208);
elsif ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= WZ;
PC <= unsigned(WZ);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= WZ;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
WZ <= (ACC & DI_Reg) + "1";
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
if SetWZ = "01" then
WZ <= RegBusC + "1";
end if;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when aDE =>
A <= RegBusC;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(WZ) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
if SetWZ = "10" then
WZ(7 downto 0) <= WZ(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
if SetWZ = "11" then
WZ <= std_logic_vector(ID16);
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0)));
F(Flag_N) <= DI_Reg(7);
F(Flag_C) <= ioq(8);
F(Flag_H) <= ioq(8);
ioq := (ioq and ('0'&x"07")) xor ('0'&BusA);
F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7));
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
WZ <= std_logic_vector(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
WZ <= (others =>'0');
WZ(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
WZ <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if MCycle = "011" and TState = 4 and No_BTR = '0' then
if I_BT = '1' or I_BC = '1' then
WZ <= std_logic_vector(PC)-"1";
end if;
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
WZ(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
WZ(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= I(7);
if I = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= I(5);
F(Flag_H) <= '0';
F(Flag_X) <= I(3);
F(Flag_N) <= '0';
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= R(7);
if R = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= R(5);
F(Flag_H) <= '0';
F(Flag_X) <= R(3);
F(Flag_N) <= '0';
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
F(Flag_X) <= DI_Reg(3);
F(Flag_Y) <= DI_Reg(5);
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 and Auto_Wait_t1 = '0' then
-- Keep D0 from M3 for RLD/RRD (Sorgelig)
I_RXDD <= I_RLD or I_RRD;
if I_RXDD='0' then
DO <= BusB;
end if;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if TState = 1 and I_BC = '1' then
n := ALU_Q - ("0000000" & F_Out(Flag_H));
F(Flag_X) <= n(3);
F(Flag_Y) <= n(1);
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0),
DOR => DOR,
DIRSet => DIRSet,
DIR => DIR(207 downto 80));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
if IR = x"71" and out0 = '1' then
BusB <= "11111111";
else
BusB <= "00000000";
end if;
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif rising_edge(CLK_n) then
if DIRSet = '0' and CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
NMICycle_n <= not NMICycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
BusReq_s <= '0';
NMI_s <= '0';
elsif rising_edge(CLK_n) then
if DIRSet = '1' then
IntE_FF2 <= DIR(211);
IntE_FF1 <= DIR(210);
else
if NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
Auto_Wait_t2 <= Auto_Wait_t1;
if T_Res = '1' then
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
else
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMI_s <= '0';
NMICycle <= '1';
IntE_FF1 <= '0';
elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end if;
end process;
Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0';
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Pqf8KmjiZjA3/UTy+NyHpdMBjML6/KIdvXNIJMBDDKBpBC7xH+8YSi7Y3gwraeGZZ77o4MEadCqM
UrqtKBBfhg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RsvgpIqrQGiEQZz25zMPZjjrGoMvB8yA8A8EvX5oXKRgG54wYDtGFw8nFmJxxsky6CAHSpC1ub8m
Qu7UYthFqAAVQZUsew9JTo3/WakdgLlzduzicc1aHCcpoUXto2ViQooopQHCd8n5zyEzP3P5fl0c
L5G0YvEsUBQ4+m9wDK0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZTWalPraERU87LmLzhZUrgKZ1YsYaIG4pU0wUaEozR/UVStu9gN3jW5Wby6yUDIKo/DwA4QGh3P4
y0IRupqQZ9w95EsulWS8pRPPW/k511Aiu0IZnmFvypVxOuj1ZxTJTtmJm8qr+oBah2UlCktHWLkV
CbbZXJmyilfHQAnfdfE3u/G/Ou5z5EqjuYzE1PJMdbQegRz5ZBNjyFbFkmWxk3EiBBu14GwTR8k/
5N2c/tlZohGWcHUsJNd8kL+7c+jf4BwCJWQkxdzQZilzbFgQyqeqfWPUUie8FybIvSfhs18+LVIT
d6OfmBs5OdVzI093BznTT9RBkIjR1gjl8RpQng==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4CphWvXaoruS6d/x4VaoNkdD8qCEAPMqVfVFtETheUdfg1834a6KAdlQZG9MJHPTTrX3Munzq/du
a4ueD8NbOz0PlOibJ2UUebRbKhr6EJxUSZNxsmh9QljzyyK370ScI9GrRirJQ7rjDEsJNdeJ4aBh
U4s3Y1jtqaXjDx6WzvY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VbOIFZUVKhMut4H9ta9M5SD0KXwqGNia6sZnZH15ysmE4pA0JI9lbHOpiTS9z5rsZdCz8X0lSMx6
vatBer/iY6YOZcyJzqyGh59tCJJhaLftR4ohdqo0zDa6SLtk2Kw51/CXXxjTL05fIckUugciQ1Eg
w2CchLBjofMTDmqyNgdMuGfsYcZx27KavXdSg1rlrTXN7G0NNmIWZWRx9JaDvKnclrsram8N7yO1
y9JD3/qNnb5FB+MYnnpXQSz97fozk7v7t7u7xwVG0p5D9a+SoRJK4kRxqxcUFc6xfDrU49GJ8S7q
cUVjOCaORxDEGsYDcGdPDI60IwkZmpzmWVw04Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6256)
`protect data_block
XSEm3N+vbM518iSIHsOCebwS6wn4EAFzS3UIMFwhjrQdY081A9iY3xpk+kNgaNL7XvTMMDV5HvKS
gp0fcjhpkEJ6Y0F4q5q6jfZWYDg59TfMK2/rKHMdjhu+1azn52abmiPY0eB8ONHiIevd5H+OQiXa
ik7QxS1uOVYiT5PkiXkm05w2Sf5Il/2LwXtc+sstqYKE0YijR7H+e9qRs3+UR7h6tM90QR88bbq+
bXODV5eRNHfyRWOKWjYyoUODjGr5Z3otEZ5fPvWoHEcwmADjVzu9ZiWZq9Iliiwsnig1yuFcZEwe
2qIdXplvnFQ8s+Dy46sFAXOOUTCsoxPSIkr8iqRIITJeHCo/t9js3QBRKz4QIBQ3rKecDQp+H0UY
qY0S08ysAyofjlCzF2W4q7R9oBNOGyqMXFaPzP/3un2l3r8Lagmp9AP8ybaUVWG+Mq+ntFOq0hU0
fcEe7pc2epF0Q4J+yK0a9+UgnDmmtc/XOgfjeSlVmOKb8YrOYBioQM/v7lA8J7HGDuG5P2F2GYb6
HZrO9vmwgfx7yyj+1iAYQXwnokJaEJz3YC5AxXedZNfmP3eyQrj5P8/DO52aOuZAHXINEBA9g2CX
ZQBkZfIPOyyhRA89gAfS3LZJOSx113Vesdd6TS7XMaTEo/VsKT9cggIVMsl7D8D4waE7ZA9sP0cg
gE9k2LQaTPVgarsaSLO01xZ44d8hPPCMmQfjuC4B2qNjl1AfTxH0vssLYnp8EoGS3kysC0LJuboo
jQZyUvHK3HSYpbOgfKfUq+hCmDFyolbyUjK0EHdACR9EPSnSYjdbkZiVu/nmcDO5bCLqS0FG3Qh0
+oBqANlYYpwcfNZxA3YAtRa6k75bTMmitF0HxFNKkf1Ai4+80ZlZYWsMe801SP0EXq9Y9L4HV1mR
5JilM2dZRwBgcGiDm+Ztb4Yb8gPgslcAt8YsiKVbUcXTS8fCKl70m7kvJ2RXpkmVBGZrCSpZis9U
6gSBf2v6ooQH2b5RPA0HwrS0UYbzQ8pHP0S+noIhxX9Jq7yTb/bKbTXft9O6ko4nwmYaEcQX34Sp
v+zRswgccmq+bDFVIfT0bsB/Xgq5Yaqdf6ITmlAvnWbmzRnP1ZRUIxiup0KDhltY4YpiD9XVIF4x
2dLcwgJ8GBqnpW7YacbrA3baWKIEehm5VIjj0CNI5+H5FhIGfaaWUEqsQpd4+eQ5S8d33PsO2ecv
XP9duByJR/7GlcNT2MWQ8ki2V5YE1F1Zt8CgV7CkLqDdI+Q3f+o+KXEl7NHQKyv+e9DuK6CEzevU
t7Z0y2sKibxYIa8JjCvaRmVu8MxxmXMqVu/YG9Dfk5XnC4/NiWAapu3AJD/3L4um7Tc9B4cFd2gi
pICEoz1OXyDzxFsyZTZOlvU7fVSlpqLmPIL1OaDz7j7h/troweKSj238tRdwWnn4PNVPACR2xOxu
PD4tAqer6nnlbtUkDJNgf/lm5hleUvGXTVsdG1qAmkfuS+hNAqYqUU/D1tCjlKQM1X4g1koZS/mD
ziJ9vKZwRaaPpmsxfLlUSIwm1QKFcLW8LcWG63QYEOqLazRDQ+zmjUdZy3pqSBCVzqzOTD+FJ1o5
Z+reAg11axoWA3UWkL6sNW2JtC9r8pn5QII9vQGUTw3MADE7ZWk5zN9fXGOvlIqF5bU3/f1+qZme
6Y2fthofn+OYwKDgQ1Y+ouBeAHVwEZXz5LbSLaDPFoPgoBVKtkdXVToiedsjloaBkbDF+G8SI1ZX
MPXXAbH30CLLCCk9nqtrPeZZrX+XhD3KUQKcGySyd+ABQUZSJfheIAR8hvkyGtWeMyAoUJKok4Eo
DQWHJ90Q5F13mM4ZpPfu/gU8h4mTCsmyFJwaIuIBgI/dvVspVFXlQWq2MUQvIb9PTzSDG8AAhxy+
nIL7jjcQied0ht3rohMWtXITBodkaXKZ+HC3TUrxwhbbaykTNX4+dd+4p4slhJ72OctPypKEkue9
PZ6CFVCOFM7uOGVha51ckvVmkk6SxxCMsqdezGBgYAJawX4ts5M+AP9KC3GR5ZVLXJg0jWSZjdqs
c0Bz8gEgruiWTtBxMiebWAE2Gd1x4o9sAVMnhN9JXjYIsJu7mA7wBeKlWmAbHb0WjPBPSGCcHMIx
y9115DhymxQSqTMgHe1PYHY+IuOLlSEqRTQWJIh0VooHh9SepQ4LyD6npBAqXuDzulqLAq0gvvBs
VzwTju12o7zVsrTVdTyk+9AIQi/I23DzwHmP79xXDnfMNDSyb6LAIwr4vfFUMKMBw8SmTYx5lCGC
+E0PNOxgoCr7YgPwZ5KvqIi4AEaTMtBIILdPkFWe5MrRyse9ZmYX75Eho7MCkZpejbui+eJT+b9G
eHsJVzyVATfHXDEvOqSyGyfks9T2mgjzstpbkh7AYIIEH/j99JvS2n67/5zldHLDReJPSCo7KC6G
GxL+Gj5FRwytrcZnUDtzZdxYNR6QxwaPG4b1HVQ9ZOrBLpfSvSCVeF9W9G/V/wYwv9TGHbD/oK0a
g05gHl32jACXUah/utr3MAlO1iCTQ7CazSvQwAIs+m0/6Hk5s9jn7+Rc3f6nJrWCrUYMvr9RpKiO
MkEkblPivzAznpbAyWtlw4VcEipyYibcy8vZnrv86wGbNxbGMzVBAheCdeGgnYxr7FuQedIZhxBp
40DMKoOC/bgN0kAZfSH1YwfJ7z+iCLkpWuYGfB9xejCcepvbWfT7QAUXm1YOeFfvTVPx3yVia4bE
7Z0vH1RBxMYqtm+U4dd4Xxj6jEoSnbs5XlNL8uMRuOY1kJzBKmSO+864nrg87gHPYkCH+WrPrdTG
6f6Hym2nF3hg+CCC3i+zCo+milgaauYIguqKtBO1vEmv1LhE0UwPPxh6NYza4DiqVmZS8Tpc66wO
6aRLfs1X8VYl2lOgm5ctsl7GWCnIZtmlWKlcxRxdXxvGszGAAH9MlVhen22bBHcyOMx24Tsm2P6t
KPg5YobPws8aVh2OSEdhBL/QsgIBTa0lPd8WfGdJ9AIgil7xip+wCEJDM82E9PRnLm5sJwPI8Dhf
6q7eS092p1WUZBlfVQRX9M6I7giz2CV57tB1am7vE78u9yaND+3tN65Odpv7kUFVQjXF4i1VaTC1
0Nxhyg9/JmGNwMxqFUQs7v6uG0HsMsRtHl0zgFso/5JLgqD2pXrRr0SRfpnHa1B07ezv4bUaOfsD
9pbfWfSh9jComVkmbYERwiAOFX8L2CG9MAJYFG78qO1v6U9+GdsgvkvwahNfZx4fRyKyKojjCKay
GMCmiqFVZa9qlikJco933jlZH2aRkb67aM2L7WWexTdtXwaVRBZ/DmDwtomsM5cIp6Ww17yjLUyW
+E2N8/0t9oKLdmpbjTMI5Qg5bWxxPnWECdz5u3032/sSpFoROPVRiyrGo2lfyBIVdAOasDFtkNFA
ow/WiJKAK/Up6920VYIKgk2An2MZBKXuE5a7un9RkIC35nQZ82Xt61+SCmoa8PyhdlY7p80H2mkD
dOMraDIex2fRDFhbjRu/cHjDH4pWhmUEbZzXnd4FzxQMn7Mi3x4Rorwzx6Gt2Cy4T+IxX//CmHDf
BiKcEvqNUudfDm4B/7Pp5Gd2Vf4GJ2KpvdIYR+AQxmqYRKI/aEf1m4XK7J6gpKUWTF0+DlsDePsE
D5TUlIv1sXSvBZWO6DBgBkV6D3oOcXSOm4Z3F+9+1vRoztKdgt1PBS+XE2svBuopTsEzQhlErcFV
6xkSJ3ryBHCOIx2zwnGD+jxnqVdoW/7y7QFXiYSa6iPfrDgLP4L3G7pW+khKeeVkYauR58eAu5Wr
uAMud8o+vYPUNAVueacsy7kGyvP3rXQGjO7W1cEMoH6QP4XRRgrJ2OFkmO11jd8tRECz2Xoi3xuV
d/lTFfqHSldiXRfsZmTwETCnELYXBD10HdLoCLI+FpWRlwzNcIIao4IRv/YwjIllp7NCEq4OfejZ
w7pxJWM64rS2LD2STfMbV3FQftBw26xz7DhRBbxjviP9hvBhoZMb9oc77pW/59jtr1nOEExp1fal
KjRFOW2822ICKcZXvdrR8T9gTOQQeNBqqGu9r6VsssZ0Vq7oPARZc9SbihXB9mfozXVov+EZn+f8
w8ZBpPkEPi3qBNA17l67vTDV9kopLX2bmcRw9bLgvyhR+lWMxFFklMQ9satpkPAVNp6JYakDmYh4
kZ5T0Fqwdjtb1j64KzCuUMypzTsXbBo/WFQOkVmitAyP+/CW1FanneUfb70j6dODM0RyFBwnlOBD
fTOg8qnXcDpRoSjoBtb8NS5VXPesIBWI5smK5TCVVqrsLWMaPfiaSrz2VLrDvfF7/+cKrfhbL3Xe
CbJTMI2g44CEr3ira+yAcuVW11L4rumdWzR025ccCO5gUiFKcQdRafgisJjH9Rmdb3PlsXVVyJet
Afp3rKgv77WaZ+r21Lxyio3P+oFNz7L/oS7VWoe2EhqgrGkiODR6axLJiasCj+vVeQtA8dPpNPNH
jaOyIlozR7lWlbMoDpUIki8mIxHveKhiPkWLDoTFsykaCYRu5pLd2bxJIVFwORfX96nH4lUQgR3e
UmtpjkxV/fsNOyPInkcbjzJYdDkOvaOBUtxx0qu/z+fdWDfY/FwOe55V54BFm1YK4CWgYAezibr+
JW8FlB2CbgYJlrE9GEYwXfSqjPbd14uC23UPQ2QFtqJVyTnQ0J3SPuD4hUe+lsX6zzFzvKKowgRn
ntsKsqtjS5OJf8bAN6felMnyvn6V8bUX1JIHS2jimCaogEBfD1pCb3SLLMP5hLpgGClF4Q/fZAK3
FbAm3YlCtqjuiN0NKNQthMYMu2bpESgswQBOec0Ji6fLo8XD1604E9uaeb+gVwmWjpEy6MaQfzh7
w4Es90DuvbgaxF8PmQmx2jy2vtSnXfS+NDJnxYul5A3a6b4K617yKkRuTn3Krp3lsK6PlXbunxTm
6CCozVanh5CL/QycL7a0QdsdXyT9q1vjA0P0QL8kIGnt629W8zvHM6g238jL0Yc+f8QFar85nhap
Ki0g/V6n3SV2vf82XyeVcg7wQ6Z9rk5/EMGp61fFSaCcRoalP/k6aXB5IXIgtMmo9ulnl99Iia6Z
7DsDMVEoRek5Xivlevral1c6UoieyJQwwVYxzmuWxXuzEEfp0lfxT2lf5wfR4pBVy2/wuDcqdLsh
Yv/KGHumSirFBJW0UCh6w19bfK2Qj1q2hSOfF2mXe9PJomHQzoB1wRlONyiC/eRwasBP1t71ZcHp
621Due/51iknTJd65EuYPk4saVkAIwZ469svRuuT7b/0a02gDdAZDC3CvT0/7ITr8q7/QbJhNnyp
zXx3USLOvVwtL92LYv3SKkd7lBWLoLWPjtJkBeS9rjhHN9PjGpWCFv+qeJR8QMRMWtM0qPQYs+0x
/V1lB1fFKsuAk8Xel7qCshUR66ul/sc70J9/mVdVwK3vL85zeqcORE6bQ2TxxRu5/oRSAFKCt56J
R42QgJ4/hUKja22/7FFO0jQv9E1PbfCsOYljrneOYf3HBUD9MDBDX+WLZamDvbQjike8bgLCNhfp
9kntA4wKBia7ePtQ1gceggETbQlqR4zq99Ks3xWJbF1CS+SxEb4wYcPwXS+Wl8JEFCa7u7gv3nZE
RqicGgmkkJ2g9sOVzXhH/CDRwY8k03uzDOaMF+MhB4wTimcvBUWooob99Zh9i1vN2GwpvRdDRIWU
o8kk67KWec4rHbJMDdyFzIf+Mf0aMQqLveJZGVHgEfc8tpGVtkeQuGDvGrWvBCx/EgBHm4Q5wp3K
jydXy/Tr9xTq88/Ng8HxvnjONd2aRrgPlgu29oZn+igN+y53E67LqzXLs6XbiHWgn0mucKewL+ej
qfghM1g3tRuG/IEzVdhUhJ6lyIrfRmutfdI0VfXZ9uOY+1EVyMt7DzAPXgGzLWihvLgCaAjiJh01
15uZ/SC3r5NQGQSQy72+nmY2q33uDpUeR7MidGLJYhGIsffWcbKeH+VI0jaynxzxBP3BdskV+LzC
+GSgGvAu1VlvJVExbB/kBrCR32AZO99ElC2WhwuTvMjrJRgh+6OX4wjoQJIDlw2nIGGcqDbHRmDE
uI9CB7Radg1QX6uDWLxRboxtfdHVAIWdPRqcAQTuLUxUQrwWfQEblqdJrH4CV+fZQt3cO0ayX4RS
HxlYbwkusXh8Kk4hYtUDRkWS5Q4Ck5inEB98Mo/X4j1FENogOT7stAJaHyH9RTnE1rKXHgA8cuhI
jMKUsEVMaCkJ7g+SwrVehCKY3cnu3TOOUATGXDI49EyFtEyMu/RAzyggIB71o2IrLNuavsbjbM1f
sDO5ibYKxIl1j0vSXQYClY4o1sCq2R7mR2VYiwi6OGzGBuTWHzAZtRaEM8Bd9Nil6ZQ6Jq6Vo1Dp
LYTi4opG4ci6sQhyeoETN8wrJsZ9IZ8WzJ5iZv8ljE5XsY917JqkLhRsrQK/gHLptTe8rBc/jffT
sfybkYJVY8Wd95gY6Q9I3euKWWBF7MryjflQss/58wDyq5/BxBp7Z9pZmNdXu4zKPNpnFScTzl5Y
zbRfNzhPjh4Sl1LoOmChtuKBqKkQJPGScDWRQp6lCgUSw3oq5EnuehzRsNyelGB5OM67zynBrCNH
TEtektucMe1yxLB2gSIYTLSVy8HNqNY0xdFvhu5/C4d7fht3SurzaHeujfokNX3teVquR1e1r4Ep
yUN8f11eaefwT9A5xx++Mix4/QyNNf/U92c1KMibb2A7y2b34TMLMt6B/wiPqM4VilPGywUsd8ud
LiRVt0aYyAgkKO59a5fiUUkMBB2WapGRpDkvn9QjywdzSwopVPIuhUOB03RtspBrZZTUx00CNM6+
y5gyK8IJHNX26goWPPuKHConwko50bwTNqwg+2AHuE63ivz9DKxXahmwQAkldhsOHa9nE78uLXWu
ndEyjgKsBhJuhAxpVHds0sEBZ48mefExDQcHSy/juoyxsLSUykgQFLUIhLyhc2/HmToIHPEz3owN
RSm+6OEeWDmdE4zYulr9jRF4dw60LxnN5BBsVC2+9HialjvsKMDTSe6NP+vpG05GZREGgnXJvE+1
R8bp373YZBPYoxM7Br0JJ6q/B9XZ2UDPoMKpQ2EoIHwwF/dwzC7WZCAElf/ELNW6BgW+g9CS/9Ln
qhk0bd51uXFZkv+wnp0CjiUR58fimMBzp7Je/CzfbTvLZrzsHSbF/HBrPKM9bSh4lkX1IC6iNR3v
vTCo7gPOSd24yuol2aPtOO9FiFWeSHTjZGXfvfPImTjI+TjPxsdQ6L/J9R7hs+2M75xBhAs/t2lx
WVJhvbrzwsNFiiRzL/qU3liC6p3k8+JQ7FsNaz4A0q7qopitvSYIo0vH3OcVVh1wvmeiC2P6JmBT
IBukj2lKMxcSPKRcT1SRkQYVY0m/d9LVnuHS3WRa9k1qciJMOpKiechX/HWDMT+ZUnZ9xGM/qEQr
MMN+ju9wy0RgG32JFzjVMhrpoNXheErUoKz+rRIpioXNBfLIa2MTS4batMB9II7DQ4eMP6nIjR5E
V8ucTtVejWeZNYquWa3BR2C5CQNavhSzm3YlMvo+rF1I/TTMubf1/3Y41qxC5MqGEwOjZ2Is19Bb
BT12+laybaDpQFUgF2ecTZnrGT0Sq+2szWy5/abctDSbyIPrbCbF2AdS/IP8ZUI7At1shahmKxeR
6nhJSPBrYYguChNwNIMGD2+cf5NCNbBcNKyZFqFrYNtejasJV7YJiPWzEMY+9ZrvTjT23XcNft1C
YFsJz1XVy4wR6T8PCxteNSG2ACSx2o5vAvQ7t655RHT7TPt/VH2gRlOWV+j931SHRzWqehvFoP6h
51rN6QYFTGf3yDY9QGDTsmVFosUldt/rU9RIsCVBWduC6fo4zpXM7vPBaWr5eONwpbXOOqzwK1Vm
8s9UlM4JFuxaJvc4KJQSRUOg1xD3qUr6qs/C65Ap6zumuvy+T6Hor8ADw6hRb+pl5FTWjHbZxpHk
5wysJwQdvpKT7pi/F2wlkXGCt3AsHcikva4oVPmAPsB0uL0WNzqTGK1ThCRDU4JV+xwAf/UGu8RS
NSEsPnr4RfSGgvoBEbmkoCkrPE+uSNAbLFbt+OjWkDKMI2QpkqWLbiqTgfVnXpTuR3P8d253ozj1
gtYTJ+lYvZDiN/6ieF1krhmRjVdkW65yY6f23Fjbki+tJxt1JE53WkvNlLfoR8FckS369KhGfqtz
VaPG0P2jsIKSAWwqjxRxzgXOJnifvwdfrMxjlqkKTiWzCv9ANG4iKzXuTEiPzhkLEL9cDTDVRPUr
9JwVNKmoB7lIFgCH0hCU2W8KSPl42AAldBNCrlvUSzZrWf+gU98WqxoNDQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Pqf8KmjiZjA3/UTy+NyHpdMBjML6/KIdvXNIJMBDDKBpBC7xH+8YSi7Y3gwraeGZZ77o4MEadCqM
UrqtKBBfhg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RsvgpIqrQGiEQZz25zMPZjjrGoMvB8yA8A8EvX5oXKRgG54wYDtGFw8nFmJxxsky6CAHSpC1ub8m
Qu7UYthFqAAVQZUsew9JTo3/WakdgLlzduzicc1aHCcpoUXto2ViQooopQHCd8n5zyEzP3P5fl0c
L5G0YvEsUBQ4+m9wDK0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZTWalPraERU87LmLzhZUrgKZ1YsYaIG4pU0wUaEozR/UVStu9gN3jW5Wby6yUDIKo/DwA4QGh3P4
y0IRupqQZ9w95EsulWS8pRPPW/k511Aiu0IZnmFvypVxOuj1ZxTJTtmJm8qr+oBah2UlCktHWLkV
CbbZXJmyilfHQAnfdfE3u/G/Ou5z5EqjuYzE1PJMdbQegRz5ZBNjyFbFkmWxk3EiBBu14GwTR8k/
5N2c/tlZohGWcHUsJNd8kL+7c+jf4BwCJWQkxdzQZilzbFgQyqeqfWPUUie8FybIvSfhs18+LVIT
d6OfmBs5OdVzI093BznTT9RBkIjR1gjl8RpQng==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4CphWvXaoruS6d/x4VaoNkdD8qCEAPMqVfVFtETheUdfg1834a6KAdlQZG9MJHPTTrX3Munzq/du
a4ueD8NbOz0PlOibJ2UUebRbKhr6EJxUSZNxsmh9QljzyyK370ScI9GrRirJQ7rjDEsJNdeJ4aBh
U4s3Y1jtqaXjDx6WzvY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VbOIFZUVKhMut4H9ta9M5SD0KXwqGNia6sZnZH15ysmE4pA0JI9lbHOpiTS9z5rsZdCz8X0lSMx6
vatBer/iY6YOZcyJzqyGh59tCJJhaLftR4ohdqo0zDa6SLtk2Kw51/CXXxjTL05fIckUugciQ1Eg
w2CchLBjofMTDmqyNgdMuGfsYcZx27KavXdSg1rlrTXN7G0NNmIWZWRx9JaDvKnclrsram8N7yO1
y9JD3/qNnb5FB+MYnnpXQSz97fozk7v7t7u7xwVG0p5D9a+SoRJK4kRxqxcUFc6xfDrU49GJ8S7q
cUVjOCaORxDEGsYDcGdPDI60IwkZmpzmWVw04Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6256)
`protect data_block
XSEm3N+vbM518iSIHsOCebwS6wn4EAFzS3UIMFwhjrQdY081A9iY3xpk+kNgaNL7XvTMMDV5HvKS
gp0fcjhpkEJ6Y0F4q5q6jfZWYDg59TfMK2/rKHMdjhu+1azn52abmiPY0eB8ONHiIevd5H+OQiXa
ik7QxS1uOVYiT5PkiXkm05w2Sf5Il/2LwXtc+sstqYKE0YijR7H+e9qRs3+UR7h6tM90QR88bbq+
bXODV5eRNHfyRWOKWjYyoUODjGr5Z3otEZ5fPvWoHEcwmADjVzu9ZiWZq9Iliiwsnig1yuFcZEwe
2qIdXplvnFQ8s+Dy46sFAXOOUTCsoxPSIkr8iqRIITJeHCo/t9js3QBRKz4QIBQ3rKecDQp+H0UY
qY0S08ysAyofjlCzF2W4q7R9oBNOGyqMXFaPzP/3un2l3r8Lagmp9AP8ybaUVWG+Mq+ntFOq0hU0
fcEe7pc2epF0Q4J+yK0a9+UgnDmmtc/XOgfjeSlVmOKb8YrOYBioQM/v7lA8J7HGDuG5P2F2GYb6
HZrO9vmwgfx7yyj+1iAYQXwnokJaEJz3YC5AxXedZNfmP3eyQrj5P8/DO52aOuZAHXINEBA9g2CX
ZQBkZfIPOyyhRA89gAfS3LZJOSx113Vesdd6TS7XMaTEo/VsKT9cggIVMsl7D8D4waE7ZA9sP0cg
gE9k2LQaTPVgarsaSLO01xZ44d8hPPCMmQfjuC4B2qNjl1AfTxH0vssLYnp8EoGS3kysC0LJuboo
jQZyUvHK3HSYpbOgfKfUq+hCmDFyolbyUjK0EHdACR9EPSnSYjdbkZiVu/nmcDO5bCLqS0FG3Qh0
+oBqANlYYpwcfNZxA3YAtRa6k75bTMmitF0HxFNKkf1Ai4+80ZlZYWsMe801SP0EXq9Y9L4HV1mR
5JilM2dZRwBgcGiDm+Ztb4Yb8gPgslcAt8YsiKVbUcXTS8fCKl70m7kvJ2RXpkmVBGZrCSpZis9U
6gSBf2v6ooQH2b5RPA0HwrS0UYbzQ8pHP0S+noIhxX9Jq7yTb/bKbTXft9O6ko4nwmYaEcQX34Sp
v+zRswgccmq+bDFVIfT0bsB/Xgq5Yaqdf6ITmlAvnWbmzRnP1ZRUIxiup0KDhltY4YpiD9XVIF4x
2dLcwgJ8GBqnpW7YacbrA3baWKIEehm5VIjj0CNI5+H5FhIGfaaWUEqsQpd4+eQ5S8d33PsO2ecv
XP9duByJR/7GlcNT2MWQ8ki2V5YE1F1Zt8CgV7CkLqDdI+Q3f+o+KXEl7NHQKyv+e9DuK6CEzevU
t7Z0y2sKibxYIa8JjCvaRmVu8MxxmXMqVu/YG9Dfk5XnC4/NiWAapu3AJD/3L4um7Tc9B4cFd2gi
pICEoz1OXyDzxFsyZTZOlvU7fVSlpqLmPIL1OaDz7j7h/troweKSj238tRdwWnn4PNVPACR2xOxu
PD4tAqer6nnlbtUkDJNgf/lm5hleUvGXTVsdG1qAmkfuS+hNAqYqUU/D1tCjlKQM1X4g1koZS/mD
ziJ9vKZwRaaPpmsxfLlUSIwm1QKFcLW8LcWG63QYEOqLazRDQ+zmjUdZy3pqSBCVzqzOTD+FJ1o5
Z+reAg11axoWA3UWkL6sNW2JtC9r8pn5QII9vQGUTw3MADE7ZWk5zN9fXGOvlIqF5bU3/f1+qZme
6Y2fthofn+OYwKDgQ1Y+ouBeAHVwEZXz5LbSLaDPFoPgoBVKtkdXVToiedsjloaBkbDF+G8SI1ZX
MPXXAbH30CLLCCk9nqtrPeZZrX+XhD3KUQKcGySyd+ABQUZSJfheIAR8hvkyGtWeMyAoUJKok4Eo
DQWHJ90Q5F13mM4ZpPfu/gU8h4mTCsmyFJwaIuIBgI/dvVspVFXlQWq2MUQvIb9PTzSDG8AAhxy+
nIL7jjcQied0ht3rohMWtXITBodkaXKZ+HC3TUrxwhbbaykTNX4+dd+4p4slhJ72OctPypKEkue9
PZ6CFVCOFM7uOGVha51ckvVmkk6SxxCMsqdezGBgYAJawX4ts5M+AP9KC3GR5ZVLXJg0jWSZjdqs
c0Bz8gEgruiWTtBxMiebWAE2Gd1x4o9sAVMnhN9JXjYIsJu7mA7wBeKlWmAbHb0WjPBPSGCcHMIx
y9115DhymxQSqTMgHe1PYHY+IuOLlSEqRTQWJIh0VooHh9SepQ4LyD6npBAqXuDzulqLAq0gvvBs
VzwTju12o7zVsrTVdTyk+9AIQi/I23DzwHmP79xXDnfMNDSyb6LAIwr4vfFUMKMBw8SmTYx5lCGC
+E0PNOxgoCr7YgPwZ5KvqIi4AEaTMtBIILdPkFWe5MrRyse9ZmYX75Eho7MCkZpejbui+eJT+b9G
eHsJVzyVATfHXDEvOqSyGyfks9T2mgjzstpbkh7AYIIEH/j99JvS2n67/5zldHLDReJPSCo7KC6G
GxL+Gj5FRwytrcZnUDtzZdxYNR6QxwaPG4b1HVQ9ZOrBLpfSvSCVeF9W9G/V/wYwv9TGHbD/oK0a
g05gHl32jACXUah/utr3MAlO1iCTQ7CazSvQwAIs+m0/6Hk5s9jn7+Rc3f6nJrWCrUYMvr9RpKiO
MkEkblPivzAznpbAyWtlw4VcEipyYibcy8vZnrv86wGbNxbGMzVBAheCdeGgnYxr7FuQedIZhxBp
40DMKoOC/bgN0kAZfSH1YwfJ7z+iCLkpWuYGfB9xejCcepvbWfT7QAUXm1YOeFfvTVPx3yVia4bE
7Z0vH1RBxMYqtm+U4dd4Xxj6jEoSnbs5XlNL8uMRuOY1kJzBKmSO+864nrg87gHPYkCH+WrPrdTG
6f6Hym2nF3hg+CCC3i+zCo+milgaauYIguqKtBO1vEmv1LhE0UwPPxh6NYza4DiqVmZS8Tpc66wO
6aRLfs1X8VYl2lOgm5ctsl7GWCnIZtmlWKlcxRxdXxvGszGAAH9MlVhen22bBHcyOMx24Tsm2P6t
KPg5YobPws8aVh2OSEdhBL/QsgIBTa0lPd8WfGdJ9AIgil7xip+wCEJDM82E9PRnLm5sJwPI8Dhf
6q7eS092p1WUZBlfVQRX9M6I7giz2CV57tB1am7vE78u9yaND+3tN65Odpv7kUFVQjXF4i1VaTC1
0Nxhyg9/JmGNwMxqFUQs7v6uG0HsMsRtHl0zgFso/5JLgqD2pXrRr0SRfpnHa1B07ezv4bUaOfsD
9pbfWfSh9jComVkmbYERwiAOFX8L2CG9MAJYFG78qO1v6U9+GdsgvkvwahNfZx4fRyKyKojjCKay
GMCmiqFVZa9qlikJco933jlZH2aRkb67aM2L7WWexTdtXwaVRBZ/DmDwtomsM5cIp6Ww17yjLUyW
+E2N8/0t9oKLdmpbjTMI5Qg5bWxxPnWECdz5u3032/sSpFoROPVRiyrGo2lfyBIVdAOasDFtkNFA
ow/WiJKAK/Up6920VYIKgk2An2MZBKXuE5a7un9RkIC35nQZ82Xt61+SCmoa8PyhdlY7p80H2mkD
dOMraDIex2fRDFhbjRu/cHjDH4pWhmUEbZzXnd4FzxQMn7Mi3x4Rorwzx6Gt2Cy4T+IxX//CmHDf
BiKcEvqNUudfDm4B/7Pp5Gd2Vf4GJ2KpvdIYR+AQxmqYRKI/aEf1m4XK7J6gpKUWTF0+DlsDePsE
D5TUlIv1sXSvBZWO6DBgBkV6D3oOcXSOm4Z3F+9+1vRoztKdgt1PBS+XE2svBuopTsEzQhlErcFV
6xkSJ3ryBHCOIx2zwnGD+jxnqVdoW/7y7QFXiYSa6iPfrDgLP4L3G7pW+khKeeVkYauR58eAu5Wr
uAMud8o+vYPUNAVueacsy7kGyvP3rXQGjO7W1cEMoH6QP4XRRgrJ2OFkmO11jd8tRECz2Xoi3xuV
d/lTFfqHSldiXRfsZmTwETCnELYXBD10HdLoCLI+FpWRlwzNcIIao4IRv/YwjIllp7NCEq4OfejZ
w7pxJWM64rS2LD2STfMbV3FQftBw26xz7DhRBbxjviP9hvBhoZMb9oc77pW/59jtr1nOEExp1fal
KjRFOW2822ICKcZXvdrR8T9gTOQQeNBqqGu9r6VsssZ0Vq7oPARZc9SbihXB9mfozXVov+EZn+f8
w8ZBpPkEPi3qBNA17l67vTDV9kopLX2bmcRw9bLgvyhR+lWMxFFklMQ9satpkPAVNp6JYakDmYh4
kZ5T0Fqwdjtb1j64KzCuUMypzTsXbBo/WFQOkVmitAyP+/CW1FanneUfb70j6dODM0RyFBwnlOBD
fTOg8qnXcDpRoSjoBtb8NS5VXPesIBWI5smK5TCVVqrsLWMaPfiaSrz2VLrDvfF7/+cKrfhbL3Xe
CbJTMI2g44CEr3ira+yAcuVW11L4rumdWzR025ccCO5gUiFKcQdRafgisJjH9Rmdb3PlsXVVyJet
Afp3rKgv77WaZ+r21Lxyio3P+oFNz7L/oS7VWoe2EhqgrGkiODR6axLJiasCj+vVeQtA8dPpNPNH
jaOyIlozR7lWlbMoDpUIki8mIxHveKhiPkWLDoTFsykaCYRu5pLd2bxJIVFwORfX96nH4lUQgR3e
UmtpjkxV/fsNOyPInkcbjzJYdDkOvaOBUtxx0qu/z+fdWDfY/FwOe55V54BFm1YK4CWgYAezibr+
JW8FlB2CbgYJlrE9GEYwXfSqjPbd14uC23UPQ2QFtqJVyTnQ0J3SPuD4hUe+lsX6zzFzvKKowgRn
ntsKsqtjS5OJf8bAN6felMnyvn6V8bUX1JIHS2jimCaogEBfD1pCb3SLLMP5hLpgGClF4Q/fZAK3
FbAm3YlCtqjuiN0NKNQthMYMu2bpESgswQBOec0Ji6fLo8XD1604E9uaeb+gVwmWjpEy6MaQfzh7
w4Es90DuvbgaxF8PmQmx2jy2vtSnXfS+NDJnxYul5A3a6b4K617yKkRuTn3Krp3lsK6PlXbunxTm
6CCozVanh5CL/QycL7a0QdsdXyT9q1vjA0P0QL8kIGnt629W8zvHM6g238jL0Yc+f8QFar85nhap
Ki0g/V6n3SV2vf82XyeVcg7wQ6Z9rk5/EMGp61fFSaCcRoalP/k6aXB5IXIgtMmo9ulnl99Iia6Z
7DsDMVEoRek5Xivlevral1c6UoieyJQwwVYxzmuWxXuzEEfp0lfxT2lf5wfR4pBVy2/wuDcqdLsh
Yv/KGHumSirFBJW0UCh6w19bfK2Qj1q2hSOfF2mXe9PJomHQzoB1wRlONyiC/eRwasBP1t71ZcHp
621Due/51iknTJd65EuYPk4saVkAIwZ469svRuuT7b/0a02gDdAZDC3CvT0/7ITr8q7/QbJhNnyp
zXx3USLOvVwtL92LYv3SKkd7lBWLoLWPjtJkBeS9rjhHN9PjGpWCFv+qeJR8QMRMWtM0qPQYs+0x
/V1lB1fFKsuAk8Xel7qCshUR66ul/sc70J9/mVdVwK3vL85zeqcORE6bQ2TxxRu5/oRSAFKCt56J
R42QgJ4/hUKja22/7FFO0jQv9E1PbfCsOYljrneOYf3HBUD9MDBDX+WLZamDvbQjike8bgLCNhfp
9kntA4wKBia7ePtQ1gceggETbQlqR4zq99Ks3xWJbF1CS+SxEb4wYcPwXS+Wl8JEFCa7u7gv3nZE
RqicGgmkkJ2g9sOVzXhH/CDRwY8k03uzDOaMF+MhB4wTimcvBUWooob99Zh9i1vN2GwpvRdDRIWU
o8kk67KWec4rHbJMDdyFzIf+Mf0aMQqLveJZGVHgEfc8tpGVtkeQuGDvGrWvBCx/EgBHm4Q5wp3K
jydXy/Tr9xTq88/Ng8HxvnjONd2aRrgPlgu29oZn+igN+y53E67LqzXLs6XbiHWgn0mucKewL+ej
qfghM1g3tRuG/IEzVdhUhJ6lyIrfRmutfdI0VfXZ9uOY+1EVyMt7DzAPXgGzLWihvLgCaAjiJh01
15uZ/SC3r5NQGQSQy72+nmY2q33uDpUeR7MidGLJYhGIsffWcbKeH+VI0jaynxzxBP3BdskV+LzC
+GSgGvAu1VlvJVExbB/kBrCR32AZO99ElC2WhwuTvMjrJRgh+6OX4wjoQJIDlw2nIGGcqDbHRmDE
uI9CB7Radg1QX6uDWLxRboxtfdHVAIWdPRqcAQTuLUxUQrwWfQEblqdJrH4CV+fZQt3cO0ayX4RS
HxlYbwkusXh8Kk4hYtUDRkWS5Q4Ck5inEB98Mo/X4j1FENogOT7stAJaHyH9RTnE1rKXHgA8cuhI
jMKUsEVMaCkJ7g+SwrVehCKY3cnu3TOOUATGXDI49EyFtEyMu/RAzyggIB71o2IrLNuavsbjbM1f
sDO5ibYKxIl1j0vSXQYClY4o1sCq2R7mR2VYiwi6OGzGBuTWHzAZtRaEM8Bd9Nil6ZQ6Jq6Vo1Dp
LYTi4opG4ci6sQhyeoETN8wrJsZ9IZ8WzJ5iZv8ljE5XsY917JqkLhRsrQK/gHLptTe8rBc/jffT
sfybkYJVY8Wd95gY6Q9I3euKWWBF7MryjflQss/58wDyq5/BxBp7Z9pZmNdXu4zKPNpnFScTzl5Y
zbRfNzhPjh4Sl1LoOmChtuKBqKkQJPGScDWRQp6lCgUSw3oq5EnuehzRsNyelGB5OM67zynBrCNH
TEtektucMe1yxLB2gSIYTLSVy8HNqNY0xdFvhu5/C4d7fht3SurzaHeujfokNX3teVquR1e1r4Ep
yUN8f11eaefwT9A5xx++Mix4/QyNNf/U92c1KMibb2A7y2b34TMLMt6B/wiPqM4VilPGywUsd8ud
LiRVt0aYyAgkKO59a5fiUUkMBB2WapGRpDkvn9QjywdzSwopVPIuhUOB03RtspBrZZTUx00CNM6+
y5gyK8IJHNX26goWPPuKHConwko50bwTNqwg+2AHuE63ivz9DKxXahmwQAkldhsOHa9nE78uLXWu
ndEyjgKsBhJuhAxpVHds0sEBZ48mefExDQcHSy/juoyxsLSUykgQFLUIhLyhc2/HmToIHPEz3owN
RSm+6OEeWDmdE4zYulr9jRF4dw60LxnN5BBsVC2+9HialjvsKMDTSe6NP+vpG05GZREGgnXJvE+1
R8bp373YZBPYoxM7Br0JJ6q/B9XZ2UDPoMKpQ2EoIHwwF/dwzC7WZCAElf/ELNW6BgW+g9CS/9Ln
qhk0bd51uXFZkv+wnp0CjiUR58fimMBzp7Je/CzfbTvLZrzsHSbF/HBrPKM9bSh4lkX1IC6iNR3v
vTCo7gPOSd24yuol2aPtOO9FiFWeSHTjZGXfvfPImTjI+TjPxsdQ6L/J9R7hs+2M75xBhAs/t2lx
WVJhvbrzwsNFiiRzL/qU3liC6p3k8+JQ7FsNaz4A0q7qopitvSYIo0vH3OcVVh1wvmeiC2P6JmBT
IBukj2lKMxcSPKRcT1SRkQYVY0m/d9LVnuHS3WRa9k1qciJMOpKiechX/HWDMT+ZUnZ9xGM/qEQr
MMN+ju9wy0RgG32JFzjVMhrpoNXheErUoKz+rRIpioXNBfLIa2MTS4batMB9II7DQ4eMP6nIjR5E
V8ucTtVejWeZNYquWa3BR2C5CQNavhSzm3YlMvo+rF1I/TTMubf1/3Y41qxC5MqGEwOjZ2Is19Bb
BT12+laybaDpQFUgF2ecTZnrGT0Sq+2szWy5/abctDSbyIPrbCbF2AdS/IP8ZUI7At1shahmKxeR
6nhJSPBrYYguChNwNIMGD2+cf5NCNbBcNKyZFqFrYNtejasJV7YJiPWzEMY+9ZrvTjT23XcNft1C
YFsJz1XVy4wR6T8PCxteNSG2ACSx2o5vAvQ7t655RHT7TPt/VH2gRlOWV+j931SHRzWqehvFoP6h
51rN6QYFTGf3yDY9QGDTsmVFosUldt/rU9RIsCVBWduC6fo4zpXM7vPBaWr5eONwpbXOOqzwK1Vm
8s9UlM4JFuxaJvc4KJQSRUOg1xD3qUr6qs/C65Ap6zumuvy+T6Hor8ADw6hRb+pl5FTWjHbZxpHk
5wysJwQdvpKT7pi/F2wlkXGCt3AsHcikva4oVPmAPsB0uL0WNzqTGK1ThCRDU4JV+xwAf/UGu8RS
NSEsPnr4RfSGgvoBEbmkoCkrPE+uSNAbLFbt+OjWkDKMI2QpkqWLbiqTgfVnXpTuR3P8d253ozj1
gtYTJ+lYvZDiN/6ieF1krhmRjVdkW65yY6f23Fjbki+tJxt1JE53WkvNlLfoR8FckS369KhGfqtz
VaPG0P2jsIKSAWwqjxRxzgXOJnifvwdfrMxjlqkKTiWzCv9ANG4iKzXuTEiPzhkLEL9cDTDVRPUr
9JwVNKmoB7lIFgCH0hCU2W8KSPl42AAldBNCrlvUSzZrWf+gU98WqxoNDQ==
`protect end_protected
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C4 is
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end C4;
architecture circuito of C4 is
begin
F <= not(A);
end circuito; |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- Violations
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
end architecture ARCH;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ezlmHfThO2Un8MjJdXv4rT7MuQQcRdPWXb4trZUl5JO8dcJwSW55Zd7q8zUGGxsmm5KKn1EYwB1G
UrGONGvBKw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A1B+SR+o6IaBGUrz9igY9CNB0bWJFyCns/53ctROhMnOLoBxAM6Jfprm6SmK8OobXfVqp/RHQ7Ox
q6BRZ1iF6/yDLUWGK3odtfWFIpdEvccUOO3pJTN4+zz3MI3eFuIL/gPIpMDiGoYLiEjArg9ldgj1
eT8eK2aJ3isZTcbQkSU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
paSE/LL9LVyhT8P6gPCPVngrSZgpqLCD6j7n9uMAlaphzmiFQsqhvewMk6eTDeMbA6mFWWk1buoK
2Ow5CCszLZb2h3bnU+O1e76p0BmrDFzGt4FtS3blA2dcpT1MjEW2qMQv54d6JwHOOkKXMPcMxxty
WUQ8sHPqaTodiTGvxSrTbYOwZ/WjeGXYsYXm5S7FKYrMqsXthAoT4ZhEIbgsBfGmyhNq9tZa1DZI
TUQjxrjpsrc810gYJL9h9YAWx8dzrF6lTSKZEbhYuv7HOy4qtu0vgtKG9QFDhG+GHBSnHxm4d/QO
PLwTs9yjQNvfsvZ9V/yibeVJcm5amYk1vr9Ehg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y3mnedL1R+8DFRPX65B2EkmGLolKDP5A6/vOdR2weHwn3zktFHF9ghcwQEeXczb8URNzZrAEuv4N
d26o3znf2CQ11s4hi6TDbe/yLHHWah1tuVpDwlLXfzZXN0pqO78mxbmZtSnE21hX+NqUNnlVXiy+
rL8HASsZ875Z2w5FlFM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XbSu6jzyJWr0HQHPrzjx/CKtqiLkA4E5f3RkoiMATCyDadQRsdO6pYt8p/xMwcHP5FsRtLEY8VdI
LYsMDp3+8mlrsdKxKzFFiNB350NGihVuYYbFz+FYkhjB9Itil66du4H1PUFECaZ5tipGuOrR2wAn
cyR89cs7uv8FU7Xb8mWvXJA4XxvHID1TTd6qtz7xXY2Qj0CGnV6w/qrnhonTcr6GQawctOZzSq/G
nLbwZRh/oSnxOtqd5NzGtcAygiABKGmXhXfxfTqlXzuW4fMhm/hd7Ddgc2kRIQB9b+6d5o5lU6WJ
fhYimNtbhVHf+qLseh47PCrDdPxdB90yMWKE8Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8656)
`protect data_block
HrWCnN/ttl44DJHrHMFqrAC1en/UB+J/ELgxCwDzsSsCDt6aKKzOgOU0t5V5ejxlUb5f0/jXHryp
Ld0HLlBNoWHBhruMP5aijL4tvhusRtORXZBA4NZ698OvuiOfRm/cyz5b72923mGxPJj5qc6tZ61l
BF+M3uc0Rkj6bbmOXRcZgTLl7Ppt54YHOzxJ19x5/Fty54JA1JLSM+4RqOxoG/3PAoFTYWS53eJq
ULXd2boAT/JL0iMUB1UAmRbbyu/ShY43ialoZzVzzCYCLrogDwhyubSNNil36LaJdq/MILDbdHiP
9BRfyWwxZn8blpzd5Rd5AcXRazYpI2z3Pq1ywRE5ss27wP0sstdQpICDGindE1aCqrt/BjyDlY9a
0iiP3BimI4ziECbqVWwUCmA3ARZ7yoGhMcwtdfjRNhMhLDl5WNjfamvpspvdxEWMNyzXj6AxshfN
eU8J2bRLcEFPPZyszTwpi5iZZofKaehOwMEQEJwgTuUgTA0Fh+fZ9BCbg87+78XpOIxRRXDX1PPG
clsLDCPu0x8WEIGtvWSS1OceN2qgM2Bbb5eLG3oh+I5vcjUrc34ZDlVIKGiSFxj9oBoXSWLuZ63c
Z23gnWaahfZM+UhRzxCI8FXkGmFLrnUB+W6Ysu0SSslWLGU8HrywnueshqB/rBlDLiEwSrtl2kMO
4Zvuu5AefIZKRbq0cWPbLTSMoh8EeMDXRF0jg8kPj6x294yTijvWVcqkC0xEs2C6j7X48JfLpeIm
LDnOJzygl8LxpZjNzrOcBvEaEaaHT8P/WD7ZbpKg9ht5ccc+tm7VaaCWL1QysMvB8lfjYx03AwdW
+ai+u239t1BNMAQbQoIDjuffko/2ivTS1XVZo4uVjHHmowPLimgDBvG56NCkoInkewqY6NpF2tGf
xDeekBX4nnRtBNvqkun9CpiidCzY1Ipny3jfMcNc5pETuJKwq2pnaEN6JIYQoQIrUXGbxyj8av1B
pmhKxBwS4/GID58YywfQv7ndEnud910EgCGwd3+qzB0TacVDAMDCVrkkb2r8Zi2wei/rOtklfzap
u05Eb17EqTofxmvvi+iO8uFCFaq2Jjbqin8S1AN9CchrakIHMbxxi6NS+/jbEQ/S2COV6lwiqQaB
0504mGMAVGhyYAsvPWnbD92Sz6M56y6OcsRZOLuFtepFMWOZqp0kx1LpBqjGUMNLkNxDtYat+vjZ
osJ+XFI+LWPBPOIDbmXAxDsHH1amBtW4G5GVh7p0M80Hkct5PSbggs2EopR8gtilt6b3CSEEaz4W
EcGPloVi3wcnBW/2ZOk42Lp34fUOXe+55H1inGqQP0J7otmLA8BCpsYm8eLoG7BwoMqpf7WhMvSe
jHaNi9PTuyqidlJl/JYFbmDXP8nbhNkqnFB9KjF88/ik/jTOm5kzz0gguDtg5cYVNludxWY0JUa7
cOyPW2O+Y0fFToyYOftn/SIPr0wyrSrQZuijIiSG7ssUtiNeZwdPffYb2b5jfH1vYkNkrl84xxdD
GTOPCsyZmFoJ8I8mL+rpyfV1N/zrZfDpu0QoPPsKuVEYXJHQov2EcKvyiItm7OBUw154PdX86uRc
oamfvKEdTqC6zvTmbPf3YKQQwswNSOqcLkimcF7/bYrr6d1KoVYLIecYukkplMIw9vLPtN5MKiRk
ulEs8SDEo2Iv0qoQX2sU1oYOOzv1XTFTsrHD+rMxdOZraQlSUtQ71IRQewAsQK/U73Bc7OEVaQwf
uzGpNwhY6Byjf+FSZgFGkhWjjie1VYDYvm5RQm+/BVs28ecK/fKJb6YPDlmpL3r6mqLbry8xJkgL
AjMu66wyaeByaveq9H3EqfcT63f8rnFB35CJVFnZVtrdofQoyYO/OFVbIeMBwOlprk5RvFGr5TUI
gufpzXPmjmUZJVBLAMEBDKqvbfKKukhbzh/35NSppl/6Y2PM3z3runDFLWMMA5s/gV9nKJJbAEPy
ucaPAlJhCRifl9GyBebYvpWi+M/chOJKw2NgVnLG0jfG8g6tW4Sngw7XM6n6UUGzKqj0aVeTMuZ0
cZV9sFJTXW6eLQ5Tn6vUyBMYCMoo2tdfuZj8QI3p0GEDH8dnAmWmScvC/+WgSm98/a2UMLfYKZSJ
PrEbPIV1wR73Jq+eqUAfaElxKqA1hZD80m0KPClFnYRbISrZEYnkfFsi0Rbporl+Zbm/YYSYSlpQ
rPuek/TCg5SwdftC1WNs8aZBWl7H280+h/yyboPk5BlMmWdnQ+ZwHQiSTm+hspnTw4iNHezCn3f6
IZSAboQ+wst+ojzxrG9MRebpx8kzPiapb6L+mciw79fnGjLXQAPtMkDFLWqMXbzNxD02Kg3iKc8+
X15xyhteMK4du0IVUKr5j3yyM8S5C/DKYanh3ntpvipSCHQ8/CZCvd3tXKP0+6WqsLTPeefF1wsY
0AaHcc6tDYaiWRQD6pJeqhEiLYT60jVbVFTbgadsFM7Ce8cNitQgfHaMZSBZDvudn9pSoqlChL2d
0xtoKgJJT9XeXAvpMNziwDKUZ2JGpeLhPCwwLO2bMNxNwNn/ZCh+2sBCOTmzqByGDNZpbHQKkJlH
FvHxMJ5K9Nfrbb21elrFP8dxn/cLh8pJCucnQCiC3btbi/WCCelRYYu6/8drvS0OHA6VvYARdSbf
LUhpxcwyjK84l7nSEri/0sD12rd/exBhTUMyvy5UqFCfCWEHQWwukYi0h5VGMFhw4Gz+WE3glLf9
wIzT11taDHDIe+roGQNsCohmzF+YdFOfif8nV6j2i19entD549iCRYLn4M8aQom5ryKh00qNGBG0
QHB+f+egn7TTFyEIZICnOpOz9Que+wPZ9Hzgq+Xo7AtfTRd6M/2RXOmmsQIhzQ90LPNVXD52d0Um
KQjWgZb6S22GkJBM9M7sRuRqHkSFtAoa1NBdWH0u/ptSrQOoOhXOUuVx0kKg9SPX3Q4/BLCEAgED
9Q0hLpBO8Xy4008COljwSdMXmj51kJCNvt3Ldo1wTC5uv46A/9raEZWNi8IxLWe9e1aqZNUtGQDU
QBbFdcz0zstlhOtlD6NPP/HJ1XHLddXoixYhCufpZ+AOSc69ldXwNKq5xUj2Qs1HQ3VLJ/4uFlh8
ijhS3yvC7ytgUDYZDfs7Kn2T3Y2i7kA74fsXlUptcDM4jMQKIPMR25Xy92ZUum/cgfsZgiLlKB6h
se8UoydcQ2DWOFoo56DQdidb0rap66zwNOlVTqlDAI5xEB4sfgCYnLu6eh+7FX9+Qji6H8emdait
mFlBFjDQfK2a+nGsJS4PfOBrydIvXqI5zi46dicRWwiI/FMZZ85F5i0X8eVQIjeZszn+C0Uwl+of
s1EIdU4j+8R6pfffH2UW97L+Azpl+fNlHLXPn8+Cn8xG4qat7zkHfL8GnSBt/AW4qi1yHJ2qc2BF
h5pEUCUmOXKBXxcSIM0/WSxFYpUi321c7P62otZGIR2cm1m+iNKEUEDm1NLFnhGxAaiR/g2+wzXo
+wMzRuGOCuDF9UEmrhfY7FCQKsYcf0kVrYENQKULlb1jLvR0HkgA/s+uFaseXZSi/tKjOOdnHnAZ
1vnG50jEqI8nITWQjL2dY4VTgMge9ge/M/3mK0qVu6cG3HLOntYIBf7COoVstP60DUfjI+gkCNf7
iLJ6MqLTOEKn2LAf//3K8gtGSxcEhsUvspwfU6q1mTCoHp6wGnRjZSgJOEx82Gbqm/5jogZy2Bct
+JjVQXVIGHu9YyR2VhClP3is5sTzd/Cow/uHNCk0s1OXiTwY+BazAvRoXBZDOBwOD5cn64OOjqkE
Jh4x26olFmWqVjY5odAR942pZqMyaVYTbIydzLnBLC+cnr/Pm+wdG3D+Rba2a4DzSIDIUCe/n+HS
R/WkAKvMVPRyi0eVZYlSR0XVJ87viprMiY1zU4EzSsa4BGoYEtkERpVHo6AOpJRciodrjPgEGaD5
iqNlUCUR34wKRbae7TljuJT+1uFye4VMFfhn0RyUEjlUfs9b6Vz0zQz1hY9vHHFF/PBDORd2uWbk
zn9gyc78s77mF8jgfxYI3SHDQWn8dmG9JyN7ch+hkBNK4oHrtWlK8CteM/qjNiff3J4/vZ34A1qk
T8K/ib/hLdfwYY4CTP7tuFwaZZS8ZNJw0Ak4wEFlJOiFgzuN9qJy8sC3a47RB81mdYE5bWUe2tnj
Fmq96KZymUHWWNYlMNP13bD5ztnAkYZ6cKdhWJR3vuVNM3sfq6ZfTHjcuetkJ+JH7nPthDQjFn79
0tNoA3R6pwy8QE4n33AxzgGGRQWLt/F3gmHCuqL5z07O7O9iVkfGgAs7D1b/ZuvchuPitUCh/Dgf
CPb3vciDp3SnawWnb/iR1HOKb1GtH7jEBfb25ibb4cyIJBY/siPwed7E22ojHNLuta/qdn7Sa0gG
XD8/8zJEOOvprkVTJtlXp7eq3RU54cw1UyTD+5YWaTqfDcRvbbNf5KsxxBqjiercaLaj3mZCsGh1
pF3OrAw9POHbr+z2xKGSC7ZHyJ4b3IWwb+ek/ddBZQ74BFl5WK0obt2udRLHlI76zCaFQCSqZ7vq
hCX5dfFIe1Obp3M7i7W3K6KYY0pP/SFA1JzbuT8n8gjpzk4ra7qp7yBHLDymftYUck9GDHvuI2nl
K8IamZ7Nn+Pp7Ra509OotaaritYT+NBESqRFUaDtw3O71qiYopbuZElX3RbTqOrWeOr7va3Er3Cn
ASOBUeG1FO8/HvxYfWECByv+i44+fSgwkXM6B6kUoDGjAsRB1cv4RXQylYlTq8vc4+S6XpvZVHpD
RKDJUUwhHQlaMzx1CUpYK37JCHFePdOHZwxc5aHhH05pbnfLOkMtJKVl6UN4ZH+jFxdvl7dWaBZ/
qxqxcOQkzMUiaywJmZlAwNJXOcYCFnM0SrhWwWPbiKgBkXBPNHJ0E5wR/ihMO1/gDXxuAHuHDvsC
y/A02CmnHdzvTgtzy/Mkm+E6rR8gH4GIdr/Z0rVvy3ooTcStugrdQkGOYFMOBVdyEa4QoU8prsdD
U2EBcZSB1Q9kVml1ohOzu1TIG7BcNb8kpsDESvZevuAjBBBKSlF7oUlggMOQw1Bx9Jgfi3/7gtAh
giVmJKnlrn4W02ftKw+hiEn7RDSg1lQ9EodECXeHfL0QaC2yrVpmYOk5hM0VmPa3RvXNkROOIPpW
2kXHnGyPmJmUBKRvcANzaCzVDUlmtBhrhBnRi363o+hA9JuelcI50NVsQofdd0k8COgC+bMohUF6
cowmfdpBNL93+/nt+s67mh6sxHjcCJazvUc+svJZdNKRdxQJUp3iw7YyDEIrrI/eIet1k1GkPpwY
A2/+MWqK1mDiXibTw/cyZoAr2x37OxFKrSzt3klKzKRnVsUrb7I4jSpKMivGzovhAzSGw/9s/ulq
PdfZ+qCy2ClhG0rm6SM6HEywZd4/XMriO/nIqX2AIOXToZXizTE4aaOXad5iJOHAfSCkM+cKBcQH
IiZDTRI/ccnoiD2eFm7e+KLBNk3scXL9eF2toApTqhXvMIUERt1zDwpmd5yTSLYXiqa5mg9VsQfQ
c6292v3ssK0Nbt0SdxIPIfVpPAhbKZmwSZhKsVpY6ukzJJ9ULNRDwv828gV502Fy/kWAJFbiToLa
w+oIIjMPlJtijus0DnWSrgjJzEELehiEei65+jYjc20HVTss+Ge+a0MYkSwrFVobm+HxvsrqM/rN
Lo96QLOwkN7pekXs3goMXSDOlmCqTJRwNQfuRDkc4S4gPcPKdTfPpjNeOy/6FI5Rd+sURzIh3Cxq
qcgS7p0XB63jyZfT2zArIC870YEvQUzxclR46hBH0UsbRvlDD6bsUv8lqS0iVZfD9qinK8DuP8b8
LnrI7o4RTg6nc4mk6TLEPUBT1oCk1mPA+sGd4cPKOiDRz1fPiuSM2qe/ZNR3xBBdQ9UVzI5R0GlZ
1qBRkfuinYNEGCF1ObsmwQEbUwQs0OwI6hc+HX2/fVfpEpJmG8W24c7fb8XXe0fWM4HaOkPRxZZ2
GhLZsbaCR5YOBSwQuAWSmrwlExplarJLGxQwtma3ZW7dYk8xOFACNSWQyuYkELqhp3ph58qcbMW4
bwypbhwkzisqPdwLqnNHQPa1EuQq98e71Cq7Wv0KTEzbC26/I1Vo4mR9wBWmcIm07pWeYswn+zUR
zF9eD5csIsLB+cRoetYemoX4N20bMWNdUV/vGsbiZn4KOWVWfytnhG1Z85pYbKvDut8O34Tbzc2L
L2AwGY40BAY+xa+Vv1d4gF81jmaGBtIrxPy/o3cWK5IWV5A3Qi0n87zKuSgbHO1b03rxnmkJQw9l
Ys8WyEBSu3s7SZGQqw2FdR4gK2yb+mavgUsaBuHxSZdMi9Xg98zxpYEmeBvLfUwYkT4YRG9ONYTt
qQ5LgtVU0Dpoi6QqXzBsyKSrD9A43FKtw36pBenntjdSiInSlU57B7+kKgxIQjalLX6F/zXRSsKz
HKb+crycIVtBt62vbF+i4rQ7DpOanx7YvpVlqp60ozSTlAgg5zXzF/OIdKut80oYB8ZHMHwC1aD0
P3From6w7RmhBArKrwMHu+YKBezNFI5U8s5OFsu2o5TyJowbFRCgko5F7mpd0iIyKdGWCc0E/Nlb
dt4AglroR076xZ3kN1uvv8S5o80JpVp5XztpiX9r3ZSBMxv/tl353seEj0xpYfZf9wTSPcAjNm22
6nKyEwQW4+DKoaO2yzCjPWRyOr75QKbpaSbxDehrmvaI9WVbSZGLKdMAcuIjn8QosQg+38QmSM5u
fw38c40/QsuYQz685Jq6AzTAGC+JIqwUKj2kS3s3TGXttXtHJNXdQe0oQVhj6vu9UzLPGZzxve66
rwPO3mbFwE/jzyJC8CYyw7cnULpHA6Nlz2qqwC9efUyvW5c5hoG7eyU0ffXZY3zxGytucnqRuFZu
PENaMX0nJIZ8lH/lvLb4HyGz4fDn4+NzWi96lXZjmGCE5u7mvfmuhIkXs6FTp47PI8CZnGZ1OslS
8DHg8jPITrWtw/CJ8IzVgRk6V1iT22NVvhj64CGdIUdVk7KXC5Gkeen0JC3CGMgSY64glYpfq87j
948lrowwAoQ/f/T8u/L7m+ehiv+DFSkh2gQayIuVLL0wot1ZsYkVaGw4qoDSpt+pJV6o8P3PA3Gj
i3Svxcsovh/9AISp0pAssXK1RCQlXwsvY5fHzTb6Xboo3/QtLP9/id+j8+q7Y/8PYi0iK1Uzl2jq
V5q2nDbPQc1J7EsaiK2g4NJxTNcrf7ja+9ZQ/5GMxS5lkOOAlCYeXnKSsmUFC5EJweCKXLKbQho+
qWKbPiWc/ruGVy02TU29kqKG11Fi1FYXdxNqaGFKff67lU8yw1vp16H1IUbmg9t4sqWtRv6rbL4n
xsmvKzoTvx+Q3i/VVNOv1umbyGc4+jRDkQZeTkQvJldFtPCNVy4fFjqhvGqpTimizOgEIGKMXUFX
xWlKK2K6ZYqFY27/F0+wtwJPCtiImWhcq91ObfAkB1oLwkS/BBTGw3v4FjxNYl+I07K/kcW+udx6
kqbUlv9VsXhtlixjywBuLm9Rur9QFQYgmSi01R81Sxx0Q0CAimnhh5nDwgiaqJQ7LnyrLF2jJy2r
3OzQrUvqBCHlxWr83lb21sxslmB7RW6p41lKVAuMZqx+BnYJagVW8g6AM3RiYrmow7XfrDYsYbl/
GDGOJ4sPr82IJK7/Z+LLgXrjQfePCXCmDZSQJ9vePptQ8/HQWbqlWug/SE6eKfQSWjNPOUwWD288
9IVrr2YRmEs0lFwyb54Cvr+FFHMLyCbZ1eofF1UY+AKk9Wr6uvM8D0WelziROnvPdaDLBWNuPUZP
Hxc95bt6pNuoOWlw+kJFnLqVHjcNBF/SfRFNnT+A4JnmzktY8WYQeqvPZ4/0+6PHK/iz1KE1U/0J
5Ytq8y4cM7OsTrU7qCcF0m08Gg+CnB8xrV7SdyW7zdpKiiRR3EXC0h7530NO4gTkxTnnhQgQPSQu
XKwuOyAtcJshpKWu1RSK1ExQoj0dE0zgkeXTK87+UZxyjA8z1KDuVKe+p1aSdm/zWADvLGAS33dy
ftpB+008SF5a02GK6EFyp+mXKGCYzaivxOR++avBo3Kh3cnfQVihEIZ2mM7/OvPSshIpvcBAFB6r
ndoOFmH+FNXQGsAQSGfWZjEeqV8fqz8Oj3bgUEpa/8BlDGcVSzVKk96BTWQXKuFT8pUE3y3i/gVn
6rD1nRzb1p+AeDpt2O1tjlFVSd1RehwQruIbvKRP0afUX9sPhsv40h9OyxfFfLxImbSLgRnJyKmR
7+K+oD1yJQSGjxPo8yfYIKno9ark4Ua2m2OyBCqSEgygXCYi70TpfNQK7mv8T0AMd/v46tM6Cgdr
OVc3v09B4srhl/2SClbImXLbfXHEvxq2qjFKXUaewek4BofjK7tdD2BBXRxJOd5pGgBys1Z8J7cH
Xa/e98r3DSwVR1g6yZOHCWUKOUTOv1J9e0V+0u5EKG1LGGisvoU1XA4o7alxqRxj6ehIU7K5+Mta
DrRV+RssGrMYme1nsX6djwynLmyqj71Etutszoj6yC4O10Bt9ZRcvRSLlTbG2628LO13zjMdneWq
b3RJIDrZnx4ImhBSgFhD05DcmGn2cOex5TztJr+3jlH33IIHTDd3ZWPvbi4uICrdLmWOJo7xTCHU
n7j6N1rMe+4F1RKiGPaTDA2vepooRUmMHoOCXwCKIDb+4gNwLy1pEFpZ8CfNLq9POk1C53wLlVgL
1b+eAlU4GnXFNl9sjMAet72b7orgwMplVu1STo0ywObVSMwIY6IXu+2RW6ESF+3KcHXuqVCDfzhZ
g7X4sezB9MI1W0uxE52SJThoSxlpZFqCUD+l+HR+AvWpFnB/OlTheVlh0DHMacKeGo5akGwOsEjX
iuD2TBz+XbGyfb+xagtQhNPYY74CkWtPUqmT+4iC7NuKhYb46k7SGECfcFn4TcXTuQMTSCt67yPG
vEuyn9nWLQVzliyh/eMPHpe9ULWbtHFw4NuaMU+QccMCOsZPmKsrzEj0hC3VGDbR0aUjGrq/YJtR
iCX/1eEeOUMklqOOU1kfxuviv7n/a1LqQ/RR5NhpnSSblyng4KXA23Xi4oc0muUw+8ySelZUiwSp
ls2N3OtLnsgK4dXtPteXPz2FTvnBGcNzGwGrbT7CFsutRxkFBZ4J5x4dRIvwTkTpcvuV+fPZLQTM
OaCNvcoiwjBYNW8MmpQcBT+9byCfdbfXFyvZzQkdoT6/YsOV0w3kkO0hVlrHLQ8B9k2hv5fJIe++
DqgdvXYpua6ldJVSCMkd4+RvNk+mOy94sGokY7rw97gndE+IM7mC05e11N0C0mjy8bFocxp+s8n4
0EcO6Y5wppQOOBwPoCprqFf7tkuhV+ZxW25Xt/2yiX8lYrFDEAJ6wMtAn/wYauPlO5hIO7uDI5Go
N4yL3b9k0RNea97c5NukXD8f/zkfLTjZXTujZSEqnIBFd3UMqyiJpgQfOx35bwiJWMqodlYiD1Aj
1nHQedXGBYUPYynxIfmjmIWctDDXVsl7tmmPD8dmP62gLARot9B8xYLBo/YVH21f++Llb6P/7iXi
7SwuCxYle1mIvc1p87uaGGXOKnFmwlUfXFGT74llpBJibEbsDqXmHVTw1oPQ0HRMEDaiFpDlcIv2
jVBPaVEjcaCIwUx6Bp9ca7rlXbT/yroKr4126NytfDsaPHAznY/X0i5vvS8/MN3yWTMKkD65aUDa
35T1teyDRRW4YSMgJawLElWy8sNGLflLC3rLsb3//PYjE0L+/pzS5cBuZll8nnp9j9ps7noZBxdx
Hl2LRx+vCCYW8B25VhjdocYLHbZgveGmuJO2TUInoYGVHRAZfnK1qiRYeRzK+HjbYoU2QUTUwe6f
LntTu1z4HI+aKb3TOaNVPuibgccvK/7u/fxYlzDSlrsQ98c1/67pCbAsDuaDcBTKFj7/NdkY1adJ
jqsmZ8tQB//PMjmOrMH46Y8k4a1CocCTPyPKXcdopQYyUHD+G2jnYQkkah76+qNSUxegBPx6j4i5
ZAMCLz4Z7wLq7l8WvxgZdxjniCZzN9BcjDacDTzwiNBiVVGTcF4ffPXFrQd0haxQQjrM05u9rcs4
4aEAWBZsOLf9OS/GAw3tjHwaEN6lWm7dTiC8ZAooo0WY2KrEaoasp/57D+Nt0Erj9eH/GbNxvUDA
BIEykq3zy5eUjOcNmN2s3o5f3vy8AByTfDwRIydUVTm69MiSBA2KwGjBnP1bZGpIIDgBFRRJQXgT
z79bVRZw19cemBuSBBaCOvk7EquEeLSMWhJw6sfDguJrspsjIeyH0fUpp+wDUy7Bqt4fI3dI9SVn
AYwth+QK2wjqey9aIrI1RS96wpDzvzQ0W7FUEV1YkBqAfqm5W1de2t3PQDs7XO5A9sj0ZbXuJaBg
LThfmA7kWrQfYVbHiLTBBYjSK0TFaBZL1rZ2Zes3PNoDisBwGyM+QU3ygvBf8NDobVMiM7AsQs0Z
uwURtrhoNcrNpb9AgFZ5N3CANbUlVPWHZmkD7XOld4GAXKe+PyOR0a2dpbS3ZTpJNwA5nb8rB4jZ
LukoQmotedJwdxigciVkKI27IlV7qj0NWEVv8hdq4cbRqUFXp4MwEOV4N77Qkr13k26cEQA+gJ4n
37ahFgmlgFoF63vF8botKhKU8Nk00FVu1/QSm4AhoQUSHTxDMdCkc0itP4/Fr9JFLgaGCCyjDt+5
qveTdvE4qlQBjWEBGS37MVjVqi0bEDBtlvlNpAtzLN6eogFqEfYKWsSd7HKvd4GBU3twiri3anui
6OdvoewfpO6F1eXMnu9lWgm5gNoqg2WG8EHMSlHaopdhVOtvEWFuMIJmTcl7BCdnNQmBCRBEDaxk
dHF4LXQq6Z8HdWpQ7ULFlx3gazL8mWyXxNFtweReWR4QTCCdDWkAbzsbO2auz06m9Sk3h6I98E2G
2goe3NJ+oQYf1d5NhGxryoA+YXLLTZ7d6QGEy3MCWtgr4b9I2uzPV48OY8cpM7ler/czuh+aYLQr
cGi4p+muuJSozPgbiOHGwSXTB2VEIGDg2rQqAcDPdrBs7TvwoINf74glENwmRjxFSIZDTouxvGQU
mR0AHLhyU70rCwGec3YhssrfqPmbC1kCtrInB38E2hKEPwYtx/4UK9l8hDvrISH5ubNZqoUEM0nm
DX631aDJuVm4wWHN0SyN4ro+3kPZvQGOMlKuotb6veWeEPEFZJ6rHeb/8lLTktSMN8GlHsMkiZOa
fn/ThRsguJaN03ZLPkvuLObWVrThbnoSa1dkka3CWorNCYMWMgt97D54mKTjDSI4WdsJAtrdbx+8
hu+VXtDFH2K0VqfsA2ahc6W5ry3UyEWy1I0NEIBd9S/Y+Ynaw6/fSxr79YnqIzETLELYoolYIOFu
fsAFD5iKKG/pnOVfjRa4/7VWBCLBzKjCNHgaJ7psA0zV88iGpcFcKMMuGSAVF9ncXbepYmhhcnre
RFV6+0tIrw4/hAUfQ6+zTX7iJRt3RRtn/H7W6U11f4aIM+TtfxAVxUw9VJNTxbx/Jw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ezlmHfThO2Un8MjJdXv4rT7MuQQcRdPWXb4trZUl5JO8dcJwSW55Zd7q8zUGGxsmm5KKn1EYwB1G
UrGONGvBKw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A1B+SR+o6IaBGUrz9igY9CNB0bWJFyCns/53ctROhMnOLoBxAM6Jfprm6SmK8OobXfVqp/RHQ7Ox
q6BRZ1iF6/yDLUWGK3odtfWFIpdEvccUOO3pJTN4+zz3MI3eFuIL/gPIpMDiGoYLiEjArg9ldgj1
eT8eK2aJ3isZTcbQkSU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
paSE/LL9LVyhT8P6gPCPVngrSZgpqLCD6j7n9uMAlaphzmiFQsqhvewMk6eTDeMbA6mFWWk1buoK
2Ow5CCszLZb2h3bnU+O1e76p0BmrDFzGt4FtS3blA2dcpT1MjEW2qMQv54d6JwHOOkKXMPcMxxty
WUQ8sHPqaTodiTGvxSrTbYOwZ/WjeGXYsYXm5S7FKYrMqsXthAoT4ZhEIbgsBfGmyhNq9tZa1DZI
TUQjxrjpsrc810gYJL9h9YAWx8dzrF6lTSKZEbhYuv7HOy4qtu0vgtKG9QFDhG+GHBSnHxm4d/QO
PLwTs9yjQNvfsvZ9V/yibeVJcm5amYk1vr9Ehg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y3mnedL1R+8DFRPX65B2EkmGLolKDP5A6/vOdR2weHwn3zktFHF9ghcwQEeXczb8URNzZrAEuv4N
d26o3znf2CQ11s4hi6TDbe/yLHHWah1tuVpDwlLXfzZXN0pqO78mxbmZtSnE21hX+NqUNnlVXiy+
rL8HASsZ875Z2w5FlFM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XbSu6jzyJWr0HQHPrzjx/CKtqiLkA4E5f3RkoiMATCyDadQRsdO6pYt8p/xMwcHP5FsRtLEY8VdI
LYsMDp3+8mlrsdKxKzFFiNB350NGihVuYYbFz+FYkhjB9Itil66du4H1PUFECaZ5tipGuOrR2wAn
cyR89cs7uv8FU7Xb8mWvXJA4XxvHID1TTd6qtz7xXY2Qj0CGnV6w/qrnhonTcr6GQawctOZzSq/G
nLbwZRh/oSnxOtqd5NzGtcAygiABKGmXhXfxfTqlXzuW4fMhm/hd7Ddgc2kRIQB9b+6d5o5lU6WJ
fhYimNtbhVHf+qLseh47PCrDdPxdB90yMWKE8Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8656)
`protect data_block
HrWCnN/ttl44DJHrHMFqrAC1en/UB+J/ELgxCwDzsSsCDt6aKKzOgOU0t5V5ejxlUb5f0/jXHryp
Ld0HLlBNoWHBhruMP5aijL4tvhusRtORXZBA4NZ698OvuiOfRm/cyz5b72923mGxPJj5qc6tZ61l
BF+M3uc0Rkj6bbmOXRcZgTLl7Ppt54YHOzxJ19x5/Fty54JA1JLSM+4RqOxoG/3PAoFTYWS53eJq
ULXd2boAT/JL0iMUB1UAmRbbyu/ShY43ialoZzVzzCYCLrogDwhyubSNNil36LaJdq/MILDbdHiP
9BRfyWwxZn8blpzd5Rd5AcXRazYpI2z3Pq1ywRE5ss27wP0sstdQpICDGindE1aCqrt/BjyDlY9a
0iiP3BimI4ziECbqVWwUCmA3ARZ7yoGhMcwtdfjRNhMhLDl5WNjfamvpspvdxEWMNyzXj6AxshfN
eU8J2bRLcEFPPZyszTwpi5iZZofKaehOwMEQEJwgTuUgTA0Fh+fZ9BCbg87+78XpOIxRRXDX1PPG
clsLDCPu0x8WEIGtvWSS1OceN2qgM2Bbb5eLG3oh+I5vcjUrc34ZDlVIKGiSFxj9oBoXSWLuZ63c
Z23gnWaahfZM+UhRzxCI8FXkGmFLrnUB+W6Ysu0SSslWLGU8HrywnueshqB/rBlDLiEwSrtl2kMO
4Zvuu5AefIZKRbq0cWPbLTSMoh8EeMDXRF0jg8kPj6x294yTijvWVcqkC0xEs2C6j7X48JfLpeIm
LDnOJzygl8LxpZjNzrOcBvEaEaaHT8P/WD7ZbpKg9ht5ccc+tm7VaaCWL1QysMvB8lfjYx03AwdW
+ai+u239t1BNMAQbQoIDjuffko/2ivTS1XVZo4uVjHHmowPLimgDBvG56NCkoInkewqY6NpF2tGf
xDeekBX4nnRtBNvqkun9CpiidCzY1Ipny3jfMcNc5pETuJKwq2pnaEN6JIYQoQIrUXGbxyj8av1B
pmhKxBwS4/GID58YywfQv7ndEnud910EgCGwd3+qzB0TacVDAMDCVrkkb2r8Zi2wei/rOtklfzap
u05Eb17EqTofxmvvi+iO8uFCFaq2Jjbqin8S1AN9CchrakIHMbxxi6NS+/jbEQ/S2COV6lwiqQaB
0504mGMAVGhyYAsvPWnbD92Sz6M56y6OcsRZOLuFtepFMWOZqp0kx1LpBqjGUMNLkNxDtYat+vjZ
osJ+XFI+LWPBPOIDbmXAxDsHH1amBtW4G5GVh7p0M80Hkct5PSbggs2EopR8gtilt6b3CSEEaz4W
EcGPloVi3wcnBW/2ZOk42Lp34fUOXe+55H1inGqQP0J7otmLA8BCpsYm8eLoG7BwoMqpf7WhMvSe
jHaNi9PTuyqidlJl/JYFbmDXP8nbhNkqnFB9KjF88/ik/jTOm5kzz0gguDtg5cYVNludxWY0JUa7
cOyPW2O+Y0fFToyYOftn/SIPr0wyrSrQZuijIiSG7ssUtiNeZwdPffYb2b5jfH1vYkNkrl84xxdD
GTOPCsyZmFoJ8I8mL+rpyfV1N/zrZfDpu0QoPPsKuVEYXJHQov2EcKvyiItm7OBUw154PdX86uRc
oamfvKEdTqC6zvTmbPf3YKQQwswNSOqcLkimcF7/bYrr6d1KoVYLIecYukkplMIw9vLPtN5MKiRk
ulEs8SDEo2Iv0qoQX2sU1oYOOzv1XTFTsrHD+rMxdOZraQlSUtQ71IRQewAsQK/U73Bc7OEVaQwf
uzGpNwhY6Byjf+FSZgFGkhWjjie1VYDYvm5RQm+/BVs28ecK/fKJb6YPDlmpL3r6mqLbry8xJkgL
AjMu66wyaeByaveq9H3EqfcT63f8rnFB35CJVFnZVtrdofQoyYO/OFVbIeMBwOlprk5RvFGr5TUI
gufpzXPmjmUZJVBLAMEBDKqvbfKKukhbzh/35NSppl/6Y2PM3z3runDFLWMMA5s/gV9nKJJbAEPy
ucaPAlJhCRifl9GyBebYvpWi+M/chOJKw2NgVnLG0jfG8g6tW4Sngw7XM6n6UUGzKqj0aVeTMuZ0
cZV9sFJTXW6eLQ5Tn6vUyBMYCMoo2tdfuZj8QI3p0GEDH8dnAmWmScvC/+WgSm98/a2UMLfYKZSJ
PrEbPIV1wR73Jq+eqUAfaElxKqA1hZD80m0KPClFnYRbISrZEYnkfFsi0Rbporl+Zbm/YYSYSlpQ
rPuek/TCg5SwdftC1WNs8aZBWl7H280+h/yyboPk5BlMmWdnQ+ZwHQiSTm+hspnTw4iNHezCn3f6
IZSAboQ+wst+ojzxrG9MRebpx8kzPiapb6L+mciw79fnGjLXQAPtMkDFLWqMXbzNxD02Kg3iKc8+
X15xyhteMK4du0IVUKr5j3yyM8S5C/DKYanh3ntpvipSCHQ8/CZCvd3tXKP0+6WqsLTPeefF1wsY
0AaHcc6tDYaiWRQD6pJeqhEiLYT60jVbVFTbgadsFM7Ce8cNitQgfHaMZSBZDvudn9pSoqlChL2d
0xtoKgJJT9XeXAvpMNziwDKUZ2JGpeLhPCwwLO2bMNxNwNn/ZCh+2sBCOTmzqByGDNZpbHQKkJlH
FvHxMJ5K9Nfrbb21elrFP8dxn/cLh8pJCucnQCiC3btbi/WCCelRYYu6/8drvS0OHA6VvYARdSbf
LUhpxcwyjK84l7nSEri/0sD12rd/exBhTUMyvy5UqFCfCWEHQWwukYi0h5VGMFhw4Gz+WE3glLf9
wIzT11taDHDIe+roGQNsCohmzF+YdFOfif8nV6j2i19entD549iCRYLn4M8aQom5ryKh00qNGBG0
QHB+f+egn7TTFyEIZICnOpOz9Que+wPZ9Hzgq+Xo7AtfTRd6M/2RXOmmsQIhzQ90LPNVXD52d0Um
KQjWgZb6S22GkJBM9M7sRuRqHkSFtAoa1NBdWH0u/ptSrQOoOhXOUuVx0kKg9SPX3Q4/BLCEAgED
9Q0hLpBO8Xy4008COljwSdMXmj51kJCNvt3Ldo1wTC5uv46A/9raEZWNi8IxLWe9e1aqZNUtGQDU
QBbFdcz0zstlhOtlD6NPP/HJ1XHLddXoixYhCufpZ+AOSc69ldXwNKq5xUj2Qs1HQ3VLJ/4uFlh8
ijhS3yvC7ytgUDYZDfs7Kn2T3Y2i7kA74fsXlUptcDM4jMQKIPMR25Xy92ZUum/cgfsZgiLlKB6h
se8UoydcQ2DWOFoo56DQdidb0rap66zwNOlVTqlDAI5xEB4sfgCYnLu6eh+7FX9+Qji6H8emdait
mFlBFjDQfK2a+nGsJS4PfOBrydIvXqI5zi46dicRWwiI/FMZZ85F5i0X8eVQIjeZszn+C0Uwl+of
s1EIdU4j+8R6pfffH2UW97L+Azpl+fNlHLXPn8+Cn8xG4qat7zkHfL8GnSBt/AW4qi1yHJ2qc2BF
h5pEUCUmOXKBXxcSIM0/WSxFYpUi321c7P62otZGIR2cm1m+iNKEUEDm1NLFnhGxAaiR/g2+wzXo
+wMzRuGOCuDF9UEmrhfY7FCQKsYcf0kVrYENQKULlb1jLvR0HkgA/s+uFaseXZSi/tKjOOdnHnAZ
1vnG50jEqI8nITWQjL2dY4VTgMge9ge/M/3mK0qVu6cG3HLOntYIBf7COoVstP60DUfjI+gkCNf7
iLJ6MqLTOEKn2LAf//3K8gtGSxcEhsUvspwfU6q1mTCoHp6wGnRjZSgJOEx82Gbqm/5jogZy2Bct
+JjVQXVIGHu9YyR2VhClP3is5sTzd/Cow/uHNCk0s1OXiTwY+BazAvRoXBZDOBwOD5cn64OOjqkE
Jh4x26olFmWqVjY5odAR942pZqMyaVYTbIydzLnBLC+cnr/Pm+wdG3D+Rba2a4DzSIDIUCe/n+HS
R/WkAKvMVPRyi0eVZYlSR0XVJ87viprMiY1zU4EzSsa4BGoYEtkERpVHo6AOpJRciodrjPgEGaD5
iqNlUCUR34wKRbae7TljuJT+1uFye4VMFfhn0RyUEjlUfs9b6Vz0zQz1hY9vHHFF/PBDORd2uWbk
zn9gyc78s77mF8jgfxYI3SHDQWn8dmG9JyN7ch+hkBNK4oHrtWlK8CteM/qjNiff3J4/vZ34A1qk
T8K/ib/hLdfwYY4CTP7tuFwaZZS8ZNJw0Ak4wEFlJOiFgzuN9qJy8sC3a47RB81mdYE5bWUe2tnj
Fmq96KZymUHWWNYlMNP13bD5ztnAkYZ6cKdhWJR3vuVNM3sfq6ZfTHjcuetkJ+JH7nPthDQjFn79
0tNoA3R6pwy8QE4n33AxzgGGRQWLt/F3gmHCuqL5z07O7O9iVkfGgAs7D1b/ZuvchuPitUCh/Dgf
CPb3vciDp3SnawWnb/iR1HOKb1GtH7jEBfb25ibb4cyIJBY/siPwed7E22ojHNLuta/qdn7Sa0gG
XD8/8zJEOOvprkVTJtlXp7eq3RU54cw1UyTD+5YWaTqfDcRvbbNf5KsxxBqjiercaLaj3mZCsGh1
pF3OrAw9POHbr+z2xKGSC7ZHyJ4b3IWwb+ek/ddBZQ74BFl5WK0obt2udRLHlI76zCaFQCSqZ7vq
hCX5dfFIe1Obp3M7i7W3K6KYY0pP/SFA1JzbuT8n8gjpzk4ra7qp7yBHLDymftYUck9GDHvuI2nl
K8IamZ7Nn+Pp7Ra509OotaaritYT+NBESqRFUaDtw3O71qiYopbuZElX3RbTqOrWeOr7va3Er3Cn
ASOBUeG1FO8/HvxYfWECByv+i44+fSgwkXM6B6kUoDGjAsRB1cv4RXQylYlTq8vc4+S6XpvZVHpD
RKDJUUwhHQlaMzx1CUpYK37JCHFePdOHZwxc5aHhH05pbnfLOkMtJKVl6UN4ZH+jFxdvl7dWaBZ/
qxqxcOQkzMUiaywJmZlAwNJXOcYCFnM0SrhWwWPbiKgBkXBPNHJ0E5wR/ihMO1/gDXxuAHuHDvsC
y/A02CmnHdzvTgtzy/Mkm+E6rR8gH4GIdr/Z0rVvy3ooTcStugrdQkGOYFMOBVdyEa4QoU8prsdD
U2EBcZSB1Q9kVml1ohOzu1TIG7BcNb8kpsDESvZevuAjBBBKSlF7oUlggMOQw1Bx9Jgfi3/7gtAh
giVmJKnlrn4W02ftKw+hiEn7RDSg1lQ9EodECXeHfL0QaC2yrVpmYOk5hM0VmPa3RvXNkROOIPpW
2kXHnGyPmJmUBKRvcANzaCzVDUlmtBhrhBnRi363o+hA9JuelcI50NVsQofdd0k8COgC+bMohUF6
cowmfdpBNL93+/nt+s67mh6sxHjcCJazvUc+svJZdNKRdxQJUp3iw7YyDEIrrI/eIet1k1GkPpwY
A2/+MWqK1mDiXibTw/cyZoAr2x37OxFKrSzt3klKzKRnVsUrb7I4jSpKMivGzovhAzSGw/9s/ulq
PdfZ+qCy2ClhG0rm6SM6HEywZd4/XMriO/nIqX2AIOXToZXizTE4aaOXad5iJOHAfSCkM+cKBcQH
IiZDTRI/ccnoiD2eFm7e+KLBNk3scXL9eF2toApTqhXvMIUERt1zDwpmd5yTSLYXiqa5mg9VsQfQ
c6292v3ssK0Nbt0SdxIPIfVpPAhbKZmwSZhKsVpY6ukzJJ9ULNRDwv828gV502Fy/kWAJFbiToLa
w+oIIjMPlJtijus0DnWSrgjJzEELehiEei65+jYjc20HVTss+Ge+a0MYkSwrFVobm+HxvsrqM/rN
Lo96QLOwkN7pekXs3goMXSDOlmCqTJRwNQfuRDkc4S4gPcPKdTfPpjNeOy/6FI5Rd+sURzIh3Cxq
qcgS7p0XB63jyZfT2zArIC870YEvQUzxclR46hBH0UsbRvlDD6bsUv8lqS0iVZfD9qinK8DuP8b8
LnrI7o4RTg6nc4mk6TLEPUBT1oCk1mPA+sGd4cPKOiDRz1fPiuSM2qe/ZNR3xBBdQ9UVzI5R0GlZ
1qBRkfuinYNEGCF1ObsmwQEbUwQs0OwI6hc+HX2/fVfpEpJmG8W24c7fb8XXe0fWM4HaOkPRxZZ2
GhLZsbaCR5YOBSwQuAWSmrwlExplarJLGxQwtma3ZW7dYk8xOFACNSWQyuYkELqhp3ph58qcbMW4
bwypbhwkzisqPdwLqnNHQPa1EuQq98e71Cq7Wv0KTEzbC26/I1Vo4mR9wBWmcIm07pWeYswn+zUR
zF9eD5csIsLB+cRoetYemoX4N20bMWNdUV/vGsbiZn4KOWVWfytnhG1Z85pYbKvDut8O34Tbzc2L
L2AwGY40BAY+xa+Vv1d4gF81jmaGBtIrxPy/o3cWK5IWV5A3Qi0n87zKuSgbHO1b03rxnmkJQw9l
Ys8WyEBSu3s7SZGQqw2FdR4gK2yb+mavgUsaBuHxSZdMi9Xg98zxpYEmeBvLfUwYkT4YRG9ONYTt
qQ5LgtVU0Dpoi6QqXzBsyKSrD9A43FKtw36pBenntjdSiInSlU57B7+kKgxIQjalLX6F/zXRSsKz
HKb+crycIVtBt62vbF+i4rQ7DpOanx7YvpVlqp60ozSTlAgg5zXzF/OIdKut80oYB8ZHMHwC1aD0
P3From6w7RmhBArKrwMHu+YKBezNFI5U8s5OFsu2o5TyJowbFRCgko5F7mpd0iIyKdGWCc0E/Nlb
dt4AglroR076xZ3kN1uvv8S5o80JpVp5XztpiX9r3ZSBMxv/tl353seEj0xpYfZf9wTSPcAjNm22
6nKyEwQW4+DKoaO2yzCjPWRyOr75QKbpaSbxDehrmvaI9WVbSZGLKdMAcuIjn8QosQg+38QmSM5u
fw38c40/QsuYQz685Jq6AzTAGC+JIqwUKj2kS3s3TGXttXtHJNXdQe0oQVhj6vu9UzLPGZzxve66
rwPO3mbFwE/jzyJC8CYyw7cnULpHA6Nlz2qqwC9efUyvW5c5hoG7eyU0ffXZY3zxGytucnqRuFZu
PENaMX0nJIZ8lH/lvLb4HyGz4fDn4+NzWi96lXZjmGCE5u7mvfmuhIkXs6FTp47PI8CZnGZ1OslS
8DHg8jPITrWtw/CJ8IzVgRk6V1iT22NVvhj64CGdIUdVk7KXC5Gkeen0JC3CGMgSY64glYpfq87j
948lrowwAoQ/f/T8u/L7m+ehiv+DFSkh2gQayIuVLL0wot1ZsYkVaGw4qoDSpt+pJV6o8P3PA3Gj
i3Svxcsovh/9AISp0pAssXK1RCQlXwsvY5fHzTb6Xboo3/QtLP9/id+j8+q7Y/8PYi0iK1Uzl2jq
V5q2nDbPQc1J7EsaiK2g4NJxTNcrf7ja+9ZQ/5GMxS5lkOOAlCYeXnKSsmUFC5EJweCKXLKbQho+
qWKbPiWc/ruGVy02TU29kqKG11Fi1FYXdxNqaGFKff67lU8yw1vp16H1IUbmg9t4sqWtRv6rbL4n
xsmvKzoTvx+Q3i/VVNOv1umbyGc4+jRDkQZeTkQvJldFtPCNVy4fFjqhvGqpTimizOgEIGKMXUFX
xWlKK2K6ZYqFY27/F0+wtwJPCtiImWhcq91ObfAkB1oLwkS/BBTGw3v4FjxNYl+I07K/kcW+udx6
kqbUlv9VsXhtlixjywBuLm9Rur9QFQYgmSi01R81Sxx0Q0CAimnhh5nDwgiaqJQ7LnyrLF2jJy2r
3OzQrUvqBCHlxWr83lb21sxslmB7RW6p41lKVAuMZqx+BnYJagVW8g6AM3RiYrmow7XfrDYsYbl/
GDGOJ4sPr82IJK7/Z+LLgXrjQfePCXCmDZSQJ9vePptQ8/HQWbqlWug/SE6eKfQSWjNPOUwWD288
9IVrr2YRmEs0lFwyb54Cvr+FFHMLyCbZ1eofF1UY+AKk9Wr6uvM8D0WelziROnvPdaDLBWNuPUZP
Hxc95bt6pNuoOWlw+kJFnLqVHjcNBF/SfRFNnT+A4JnmzktY8WYQeqvPZ4/0+6PHK/iz1KE1U/0J
5Ytq8y4cM7OsTrU7qCcF0m08Gg+CnB8xrV7SdyW7zdpKiiRR3EXC0h7530NO4gTkxTnnhQgQPSQu
XKwuOyAtcJshpKWu1RSK1ExQoj0dE0zgkeXTK87+UZxyjA8z1KDuVKe+p1aSdm/zWADvLGAS33dy
ftpB+008SF5a02GK6EFyp+mXKGCYzaivxOR++avBo3Kh3cnfQVihEIZ2mM7/OvPSshIpvcBAFB6r
ndoOFmH+FNXQGsAQSGfWZjEeqV8fqz8Oj3bgUEpa/8BlDGcVSzVKk96BTWQXKuFT8pUE3y3i/gVn
6rD1nRzb1p+AeDpt2O1tjlFVSd1RehwQruIbvKRP0afUX9sPhsv40h9OyxfFfLxImbSLgRnJyKmR
7+K+oD1yJQSGjxPo8yfYIKno9ark4Ua2m2OyBCqSEgygXCYi70TpfNQK7mv8T0AMd/v46tM6Cgdr
OVc3v09B4srhl/2SClbImXLbfXHEvxq2qjFKXUaewek4BofjK7tdD2BBXRxJOd5pGgBys1Z8J7cH
Xa/e98r3DSwVR1g6yZOHCWUKOUTOv1J9e0V+0u5EKG1LGGisvoU1XA4o7alxqRxj6ehIU7K5+Mta
DrRV+RssGrMYme1nsX6djwynLmyqj71Etutszoj6yC4O10Bt9ZRcvRSLlTbG2628LO13zjMdneWq
b3RJIDrZnx4ImhBSgFhD05DcmGn2cOex5TztJr+3jlH33IIHTDd3ZWPvbi4uICrdLmWOJo7xTCHU
n7j6N1rMe+4F1RKiGPaTDA2vepooRUmMHoOCXwCKIDb+4gNwLy1pEFpZ8CfNLq9POk1C53wLlVgL
1b+eAlU4GnXFNl9sjMAet72b7orgwMplVu1STo0ywObVSMwIY6IXu+2RW6ESF+3KcHXuqVCDfzhZ
g7X4sezB9MI1W0uxE52SJThoSxlpZFqCUD+l+HR+AvWpFnB/OlTheVlh0DHMacKeGo5akGwOsEjX
iuD2TBz+XbGyfb+xagtQhNPYY74CkWtPUqmT+4iC7NuKhYb46k7SGECfcFn4TcXTuQMTSCt67yPG
vEuyn9nWLQVzliyh/eMPHpe9ULWbtHFw4NuaMU+QccMCOsZPmKsrzEj0hC3VGDbR0aUjGrq/YJtR
iCX/1eEeOUMklqOOU1kfxuviv7n/a1LqQ/RR5NhpnSSblyng4KXA23Xi4oc0muUw+8ySelZUiwSp
ls2N3OtLnsgK4dXtPteXPz2FTvnBGcNzGwGrbT7CFsutRxkFBZ4J5x4dRIvwTkTpcvuV+fPZLQTM
OaCNvcoiwjBYNW8MmpQcBT+9byCfdbfXFyvZzQkdoT6/YsOV0w3kkO0hVlrHLQ8B9k2hv5fJIe++
DqgdvXYpua6ldJVSCMkd4+RvNk+mOy94sGokY7rw97gndE+IM7mC05e11N0C0mjy8bFocxp+s8n4
0EcO6Y5wppQOOBwPoCprqFf7tkuhV+ZxW25Xt/2yiX8lYrFDEAJ6wMtAn/wYauPlO5hIO7uDI5Go
N4yL3b9k0RNea97c5NukXD8f/zkfLTjZXTujZSEqnIBFd3UMqyiJpgQfOx35bwiJWMqodlYiD1Aj
1nHQedXGBYUPYynxIfmjmIWctDDXVsl7tmmPD8dmP62gLARot9B8xYLBo/YVH21f++Llb6P/7iXi
7SwuCxYle1mIvc1p87uaGGXOKnFmwlUfXFGT74llpBJibEbsDqXmHVTw1oPQ0HRMEDaiFpDlcIv2
jVBPaVEjcaCIwUx6Bp9ca7rlXbT/yroKr4126NytfDsaPHAznY/X0i5vvS8/MN3yWTMKkD65aUDa
35T1teyDRRW4YSMgJawLElWy8sNGLflLC3rLsb3//PYjE0L+/pzS5cBuZll8nnp9j9ps7noZBxdx
Hl2LRx+vCCYW8B25VhjdocYLHbZgveGmuJO2TUInoYGVHRAZfnK1qiRYeRzK+HjbYoU2QUTUwe6f
LntTu1z4HI+aKb3TOaNVPuibgccvK/7u/fxYlzDSlrsQ98c1/67pCbAsDuaDcBTKFj7/NdkY1adJ
jqsmZ8tQB//PMjmOrMH46Y8k4a1CocCTPyPKXcdopQYyUHD+G2jnYQkkah76+qNSUxegBPx6j4i5
ZAMCLz4Z7wLq7l8WvxgZdxjniCZzN9BcjDacDTzwiNBiVVGTcF4ffPXFrQd0haxQQjrM05u9rcs4
4aEAWBZsOLf9OS/GAw3tjHwaEN6lWm7dTiC8ZAooo0WY2KrEaoasp/57D+Nt0Erj9eH/GbNxvUDA
BIEykq3zy5eUjOcNmN2s3o5f3vy8AByTfDwRIydUVTm69MiSBA2KwGjBnP1bZGpIIDgBFRRJQXgT
z79bVRZw19cemBuSBBaCOvk7EquEeLSMWhJw6sfDguJrspsjIeyH0fUpp+wDUy7Bqt4fI3dI9SVn
AYwth+QK2wjqey9aIrI1RS96wpDzvzQ0W7FUEV1YkBqAfqm5W1de2t3PQDs7XO5A9sj0ZbXuJaBg
LThfmA7kWrQfYVbHiLTBBYjSK0TFaBZL1rZ2Zes3PNoDisBwGyM+QU3ygvBf8NDobVMiM7AsQs0Z
uwURtrhoNcrNpb9AgFZ5N3CANbUlVPWHZmkD7XOld4GAXKe+PyOR0a2dpbS3ZTpJNwA5nb8rB4jZ
LukoQmotedJwdxigciVkKI27IlV7qj0NWEVv8hdq4cbRqUFXp4MwEOV4N77Qkr13k26cEQA+gJ4n
37ahFgmlgFoF63vF8botKhKU8Nk00FVu1/QSm4AhoQUSHTxDMdCkc0itP4/Fr9JFLgaGCCyjDt+5
qveTdvE4qlQBjWEBGS37MVjVqi0bEDBtlvlNpAtzLN6eogFqEfYKWsSd7HKvd4GBU3twiri3anui
6OdvoewfpO6F1eXMnu9lWgm5gNoqg2WG8EHMSlHaopdhVOtvEWFuMIJmTcl7BCdnNQmBCRBEDaxk
dHF4LXQq6Z8HdWpQ7ULFlx3gazL8mWyXxNFtweReWR4QTCCdDWkAbzsbO2auz06m9Sk3h6I98E2G
2goe3NJ+oQYf1d5NhGxryoA+YXLLTZ7d6QGEy3MCWtgr4b9I2uzPV48OY8cpM7ler/czuh+aYLQr
cGi4p+muuJSozPgbiOHGwSXTB2VEIGDg2rQqAcDPdrBs7TvwoINf74glENwmRjxFSIZDTouxvGQU
mR0AHLhyU70rCwGec3YhssrfqPmbC1kCtrInB38E2hKEPwYtx/4UK9l8hDvrISH5ubNZqoUEM0nm
DX631aDJuVm4wWHN0SyN4ro+3kPZvQGOMlKuotb6veWeEPEFZJ6rHeb/8lLTktSMN8GlHsMkiZOa
fn/ThRsguJaN03ZLPkvuLObWVrThbnoSa1dkka3CWorNCYMWMgt97D54mKTjDSI4WdsJAtrdbx+8
hu+VXtDFH2K0VqfsA2ahc6W5ry3UyEWy1I0NEIBd9S/Y+Ynaw6/fSxr79YnqIzETLELYoolYIOFu
fsAFD5iKKG/pnOVfjRa4/7VWBCLBzKjCNHgaJ7psA0zV88iGpcFcKMMuGSAVF9ncXbepYmhhcnre
RFV6+0tIrw4/hAUfQ6+zTX7iJRt3RRtn/H7W6U11f4aIM+TtfxAVxUw9VJNTxbx/Jw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ezlmHfThO2Un8MjJdXv4rT7MuQQcRdPWXb4trZUl5JO8dcJwSW55Zd7q8zUGGxsmm5KKn1EYwB1G
UrGONGvBKw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A1B+SR+o6IaBGUrz9igY9CNB0bWJFyCns/53ctROhMnOLoBxAM6Jfprm6SmK8OobXfVqp/RHQ7Ox
q6BRZ1iF6/yDLUWGK3odtfWFIpdEvccUOO3pJTN4+zz3MI3eFuIL/gPIpMDiGoYLiEjArg9ldgj1
eT8eK2aJ3isZTcbQkSU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
paSE/LL9LVyhT8P6gPCPVngrSZgpqLCD6j7n9uMAlaphzmiFQsqhvewMk6eTDeMbA6mFWWk1buoK
2Ow5CCszLZb2h3bnU+O1e76p0BmrDFzGt4FtS3blA2dcpT1MjEW2qMQv54d6JwHOOkKXMPcMxxty
WUQ8sHPqaTodiTGvxSrTbYOwZ/WjeGXYsYXm5S7FKYrMqsXthAoT4ZhEIbgsBfGmyhNq9tZa1DZI
TUQjxrjpsrc810gYJL9h9YAWx8dzrF6lTSKZEbhYuv7HOy4qtu0vgtKG9QFDhG+GHBSnHxm4d/QO
PLwTs9yjQNvfsvZ9V/yibeVJcm5amYk1vr9Ehg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y3mnedL1R+8DFRPX65B2EkmGLolKDP5A6/vOdR2weHwn3zktFHF9ghcwQEeXczb8URNzZrAEuv4N
d26o3znf2CQ11s4hi6TDbe/yLHHWah1tuVpDwlLXfzZXN0pqO78mxbmZtSnE21hX+NqUNnlVXiy+
rL8HASsZ875Z2w5FlFM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XbSu6jzyJWr0HQHPrzjx/CKtqiLkA4E5f3RkoiMATCyDadQRsdO6pYt8p/xMwcHP5FsRtLEY8VdI
LYsMDp3+8mlrsdKxKzFFiNB350NGihVuYYbFz+FYkhjB9Itil66du4H1PUFECaZ5tipGuOrR2wAn
cyR89cs7uv8FU7Xb8mWvXJA4XxvHID1TTd6qtz7xXY2Qj0CGnV6w/qrnhonTcr6GQawctOZzSq/G
nLbwZRh/oSnxOtqd5NzGtcAygiABKGmXhXfxfTqlXzuW4fMhm/hd7Ddgc2kRIQB9b+6d5o5lU6WJ
fhYimNtbhVHf+qLseh47PCrDdPxdB90yMWKE8Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8656)
`protect data_block
HrWCnN/ttl44DJHrHMFqrAC1en/UB+J/ELgxCwDzsSsCDt6aKKzOgOU0t5V5ejxlUb5f0/jXHryp
Ld0HLlBNoWHBhruMP5aijL4tvhusRtORXZBA4NZ698OvuiOfRm/cyz5b72923mGxPJj5qc6tZ61l
BF+M3uc0Rkj6bbmOXRcZgTLl7Ppt54YHOzxJ19x5/Fty54JA1JLSM+4RqOxoG/3PAoFTYWS53eJq
ULXd2boAT/JL0iMUB1UAmRbbyu/ShY43ialoZzVzzCYCLrogDwhyubSNNil36LaJdq/MILDbdHiP
9BRfyWwxZn8blpzd5Rd5AcXRazYpI2z3Pq1ywRE5ss27wP0sstdQpICDGindE1aCqrt/BjyDlY9a
0iiP3BimI4ziECbqVWwUCmA3ARZ7yoGhMcwtdfjRNhMhLDl5WNjfamvpspvdxEWMNyzXj6AxshfN
eU8J2bRLcEFPPZyszTwpi5iZZofKaehOwMEQEJwgTuUgTA0Fh+fZ9BCbg87+78XpOIxRRXDX1PPG
clsLDCPu0x8WEIGtvWSS1OceN2qgM2Bbb5eLG3oh+I5vcjUrc34ZDlVIKGiSFxj9oBoXSWLuZ63c
Z23gnWaahfZM+UhRzxCI8FXkGmFLrnUB+W6Ysu0SSslWLGU8HrywnueshqB/rBlDLiEwSrtl2kMO
4Zvuu5AefIZKRbq0cWPbLTSMoh8EeMDXRF0jg8kPj6x294yTijvWVcqkC0xEs2C6j7X48JfLpeIm
LDnOJzygl8LxpZjNzrOcBvEaEaaHT8P/WD7ZbpKg9ht5ccc+tm7VaaCWL1QysMvB8lfjYx03AwdW
+ai+u239t1BNMAQbQoIDjuffko/2ivTS1XVZo4uVjHHmowPLimgDBvG56NCkoInkewqY6NpF2tGf
xDeekBX4nnRtBNvqkun9CpiidCzY1Ipny3jfMcNc5pETuJKwq2pnaEN6JIYQoQIrUXGbxyj8av1B
pmhKxBwS4/GID58YywfQv7ndEnud910EgCGwd3+qzB0TacVDAMDCVrkkb2r8Zi2wei/rOtklfzap
u05Eb17EqTofxmvvi+iO8uFCFaq2Jjbqin8S1AN9CchrakIHMbxxi6NS+/jbEQ/S2COV6lwiqQaB
0504mGMAVGhyYAsvPWnbD92Sz6M56y6OcsRZOLuFtepFMWOZqp0kx1LpBqjGUMNLkNxDtYat+vjZ
osJ+XFI+LWPBPOIDbmXAxDsHH1amBtW4G5GVh7p0M80Hkct5PSbggs2EopR8gtilt6b3CSEEaz4W
EcGPloVi3wcnBW/2ZOk42Lp34fUOXe+55H1inGqQP0J7otmLA8BCpsYm8eLoG7BwoMqpf7WhMvSe
jHaNi9PTuyqidlJl/JYFbmDXP8nbhNkqnFB9KjF88/ik/jTOm5kzz0gguDtg5cYVNludxWY0JUa7
cOyPW2O+Y0fFToyYOftn/SIPr0wyrSrQZuijIiSG7ssUtiNeZwdPffYb2b5jfH1vYkNkrl84xxdD
GTOPCsyZmFoJ8I8mL+rpyfV1N/zrZfDpu0QoPPsKuVEYXJHQov2EcKvyiItm7OBUw154PdX86uRc
oamfvKEdTqC6zvTmbPf3YKQQwswNSOqcLkimcF7/bYrr6d1KoVYLIecYukkplMIw9vLPtN5MKiRk
ulEs8SDEo2Iv0qoQX2sU1oYOOzv1XTFTsrHD+rMxdOZraQlSUtQ71IRQewAsQK/U73Bc7OEVaQwf
uzGpNwhY6Byjf+FSZgFGkhWjjie1VYDYvm5RQm+/BVs28ecK/fKJb6YPDlmpL3r6mqLbry8xJkgL
AjMu66wyaeByaveq9H3EqfcT63f8rnFB35CJVFnZVtrdofQoyYO/OFVbIeMBwOlprk5RvFGr5TUI
gufpzXPmjmUZJVBLAMEBDKqvbfKKukhbzh/35NSppl/6Y2PM3z3runDFLWMMA5s/gV9nKJJbAEPy
ucaPAlJhCRifl9GyBebYvpWi+M/chOJKw2NgVnLG0jfG8g6tW4Sngw7XM6n6UUGzKqj0aVeTMuZ0
cZV9sFJTXW6eLQ5Tn6vUyBMYCMoo2tdfuZj8QI3p0GEDH8dnAmWmScvC/+WgSm98/a2UMLfYKZSJ
PrEbPIV1wR73Jq+eqUAfaElxKqA1hZD80m0KPClFnYRbISrZEYnkfFsi0Rbporl+Zbm/YYSYSlpQ
rPuek/TCg5SwdftC1WNs8aZBWl7H280+h/yyboPk5BlMmWdnQ+ZwHQiSTm+hspnTw4iNHezCn3f6
IZSAboQ+wst+ojzxrG9MRebpx8kzPiapb6L+mciw79fnGjLXQAPtMkDFLWqMXbzNxD02Kg3iKc8+
X15xyhteMK4du0IVUKr5j3yyM8S5C/DKYanh3ntpvipSCHQ8/CZCvd3tXKP0+6WqsLTPeefF1wsY
0AaHcc6tDYaiWRQD6pJeqhEiLYT60jVbVFTbgadsFM7Ce8cNitQgfHaMZSBZDvudn9pSoqlChL2d
0xtoKgJJT9XeXAvpMNziwDKUZ2JGpeLhPCwwLO2bMNxNwNn/ZCh+2sBCOTmzqByGDNZpbHQKkJlH
FvHxMJ5K9Nfrbb21elrFP8dxn/cLh8pJCucnQCiC3btbi/WCCelRYYu6/8drvS0OHA6VvYARdSbf
LUhpxcwyjK84l7nSEri/0sD12rd/exBhTUMyvy5UqFCfCWEHQWwukYi0h5VGMFhw4Gz+WE3glLf9
wIzT11taDHDIe+roGQNsCohmzF+YdFOfif8nV6j2i19entD549iCRYLn4M8aQom5ryKh00qNGBG0
QHB+f+egn7TTFyEIZICnOpOz9Que+wPZ9Hzgq+Xo7AtfTRd6M/2RXOmmsQIhzQ90LPNVXD52d0Um
KQjWgZb6S22GkJBM9M7sRuRqHkSFtAoa1NBdWH0u/ptSrQOoOhXOUuVx0kKg9SPX3Q4/BLCEAgED
9Q0hLpBO8Xy4008COljwSdMXmj51kJCNvt3Ldo1wTC5uv46A/9raEZWNi8IxLWe9e1aqZNUtGQDU
QBbFdcz0zstlhOtlD6NPP/HJ1XHLddXoixYhCufpZ+AOSc69ldXwNKq5xUj2Qs1HQ3VLJ/4uFlh8
ijhS3yvC7ytgUDYZDfs7Kn2T3Y2i7kA74fsXlUptcDM4jMQKIPMR25Xy92ZUum/cgfsZgiLlKB6h
se8UoydcQ2DWOFoo56DQdidb0rap66zwNOlVTqlDAI5xEB4sfgCYnLu6eh+7FX9+Qji6H8emdait
mFlBFjDQfK2a+nGsJS4PfOBrydIvXqI5zi46dicRWwiI/FMZZ85F5i0X8eVQIjeZszn+C0Uwl+of
s1EIdU4j+8R6pfffH2UW97L+Azpl+fNlHLXPn8+Cn8xG4qat7zkHfL8GnSBt/AW4qi1yHJ2qc2BF
h5pEUCUmOXKBXxcSIM0/WSxFYpUi321c7P62otZGIR2cm1m+iNKEUEDm1NLFnhGxAaiR/g2+wzXo
+wMzRuGOCuDF9UEmrhfY7FCQKsYcf0kVrYENQKULlb1jLvR0HkgA/s+uFaseXZSi/tKjOOdnHnAZ
1vnG50jEqI8nITWQjL2dY4VTgMge9ge/M/3mK0qVu6cG3HLOntYIBf7COoVstP60DUfjI+gkCNf7
iLJ6MqLTOEKn2LAf//3K8gtGSxcEhsUvspwfU6q1mTCoHp6wGnRjZSgJOEx82Gbqm/5jogZy2Bct
+JjVQXVIGHu9YyR2VhClP3is5sTzd/Cow/uHNCk0s1OXiTwY+BazAvRoXBZDOBwOD5cn64OOjqkE
Jh4x26olFmWqVjY5odAR942pZqMyaVYTbIydzLnBLC+cnr/Pm+wdG3D+Rba2a4DzSIDIUCe/n+HS
R/WkAKvMVPRyi0eVZYlSR0XVJ87viprMiY1zU4EzSsa4BGoYEtkERpVHo6AOpJRciodrjPgEGaD5
iqNlUCUR34wKRbae7TljuJT+1uFye4VMFfhn0RyUEjlUfs9b6Vz0zQz1hY9vHHFF/PBDORd2uWbk
zn9gyc78s77mF8jgfxYI3SHDQWn8dmG9JyN7ch+hkBNK4oHrtWlK8CteM/qjNiff3J4/vZ34A1qk
T8K/ib/hLdfwYY4CTP7tuFwaZZS8ZNJw0Ak4wEFlJOiFgzuN9qJy8sC3a47RB81mdYE5bWUe2tnj
Fmq96KZymUHWWNYlMNP13bD5ztnAkYZ6cKdhWJR3vuVNM3sfq6ZfTHjcuetkJ+JH7nPthDQjFn79
0tNoA3R6pwy8QE4n33AxzgGGRQWLt/F3gmHCuqL5z07O7O9iVkfGgAs7D1b/ZuvchuPitUCh/Dgf
CPb3vciDp3SnawWnb/iR1HOKb1GtH7jEBfb25ibb4cyIJBY/siPwed7E22ojHNLuta/qdn7Sa0gG
XD8/8zJEOOvprkVTJtlXp7eq3RU54cw1UyTD+5YWaTqfDcRvbbNf5KsxxBqjiercaLaj3mZCsGh1
pF3OrAw9POHbr+z2xKGSC7ZHyJ4b3IWwb+ek/ddBZQ74BFl5WK0obt2udRLHlI76zCaFQCSqZ7vq
hCX5dfFIe1Obp3M7i7W3K6KYY0pP/SFA1JzbuT8n8gjpzk4ra7qp7yBHLDymftYUck9GDHvuI2nl
K8IamZ7Nn+Pp7Ra509OotaaritYT+NBESqRFUaDtw3O71qiYopbuZElX3RbTqOrWeOr7va3Er3Cn
ASOBUeG1FO8/HvxYfWECByv+i44+fSgwkXM6B6kUoDGjAsRB1cv4RXQylYlTq8vc4+S6XpvZVHpD
RKDJUUwhHQlaMzx1CUpYK37JCHFePdOHZwxc5aHhH05pbnfLOkMtJKVl6UN4ZH+jFxdvl7dWaBZ/
qxqxcOQkzMUiaywJmZlAwNJXOcYCFnM0SrhWwWPbiKgBkXBPNHJ0E5wR/ihMO1/gDXxuAHuHDvsC
y/A02CmnHdzvTgtzy/Mkm+E6rR8gH4GIdr/Z0rVvy3ooTcStugrdQkGOYFMOBVdyEa4QoU8prsdD
U2EBcZSB1Q9kVml1ohOzu1TIG7BcNb8kpsDESvZevuAjBBBKSlF7oUlggMOQw1Bx9Jgfi3/7gtAh
giVmJKnlrn4W02ftKw+hiEn7RDSg1lQ9EodECXeHfL0QaC2yrVpmYOk5hM0VmPa3RvXNkROOIPpW
2kXHnGyPmJmUBKRvcANzaCzVDUlmtBhrhBnRi363o+hA9JuelcI50NVsQofdd0k8COgC+bMohUF6
cowmfdpBNL93+/nt+s67mh6sxHjcCJazvUc+svJZdNKRdxQJUp3iw7YyDEIrrI/eIet1k1GkPpwY
A2/+MWqK1mDiXibTw/cyZoAr2x37OxFKrSzt3klKzKRnVsUrb7I4jSpKMivGzovhAzSGw/9s/ulq
PdfZ+qCy2ClhG0rm6SM6HEywZd4/XMriO/nIqX2AIOXToZXizTE4aaOXad5iJOHAfSCkM+cKBcQH
IiZDTRI/ccnoiD2eFm7e+KLBNk3scXL9eF2toApTqhXvMIUERt1zDwpmd5yTSLYXiqa5mg9VsQfQ
c6292v3ssK0Nbt0SdxIPIfVpPAhbKZmwSZhKsVpY6ukzJJ9ULNRDwv828gV502Fy/kWAJFbiToLa
w+oIIjMPlJtijus0DnWSrgjJzEELehiEei65+jYjc20HVTss+Ge+a0MYkSwrFVobm+HxvsrqM/rN
Lo96QLOwkN7pekXs3goMXSDOlmCqTJRwNQfuRDkc4S4gPcPKdTfPpjNeOy/6FI5Rd+sURzIh3Cxq
qcgS7p0XB63jyZfT2zArIC870YEvQUzxclR46hBH0UsbRvlDD6bsUv8lqS0iVZfD9qinK8DuP8b8
LnrI7o4RTg6nc4mk6TLEPUBT1oCk1mPA+sGd4cPKOiDRz1fPiuSM2qe/ZNR3xBBdQ9UVzI5R0GlZ
1qBRkfuinYNEGCF1ObsmwQEbUwQs0OwI6hc+HX2/fVfpEpJmG8W24c7fb8XXe0fWM4HaOkPRxZZ2
GhLZsbaCR5YOBSwQuAWSmrwlExplarJLGxQwtma3ZW7dYk8xOFACNSWQyuYkELqhp3ph58qcbMW4
bwypbhwkzisqPdwLqnNHQPa1EuQq98e71Cq7Wv0KTEzbC26/I1Vo4mR9wBWmcIm07pWeYswn+zUR
zF9eD5csIsLB+cRoetYemoX4N20bMWNdUV/vGsbiZn4KOWVWfytnhG1Z85pYbKvDut8O34Tbzc2L
L2AwGY40BAY+xa+Vv1d4gF81jmaGBtIrxPy/o3cWK5IWV5A3Qi0n87zKuSgbHO1b03rxnmkJQw9l
Ys8WyEBSu3s7SZGQqw2FdR4gK2yb+mavgUsaBuHxSZdMi9Xg98zxpYEmeBvLfUwYkT4YRG9ONYTt
qQ5LgtVU0Dpoi6QqXzBsyKSrD9A43FKtw36pBenntjdSiInSlU57B7+kKgxIQjalLX6F/zXRSsKz
HKb+crycIVtBt62vbF+i4rQ7DpOanx7YvpVlqp60ozSTlAgg5zXzF/OIdKut80oYB8ZHMHwC1aD0
P3From6w7RmhBArKrwMHu+YKBezNFI5U8s5OFsu2o5TyJowbFRCgko5F7mpd0iIyKdGWCc0E/Nlb
dt4AglroR076xZ3kN1uvv8S5o80JpVp5XztpiX9r3ZSBMxv/tl353seEj0xpYfZf9wTSPcAjNm22
6nKyEwQW4+DKoaO2yzCjPWRyOr75QKbpaSbxDehrmvaI9WVbSZGLKdMAcuIjn8QosQg+38QmSM5u
fw38c40/QsuYQz685Jq6AzTAGC+JIqwUKj2kS3s3TGXttXtHJNXdQe0oQVhj6vu9UzLPGZzxve66
rwPO3mbFwE/jzyJC8CYyw7cnULpHA6Nlz2qqwC9efUyvW5c5hoG7eyU0ffXZY3zxGytucnqRuFZu
PENaMX0nJIZ8lH/lvLb4HyGz4fDn4+NzWi96lXZjmGCE5u7mvfmuhIkXs6FTp47PI8CZnGZ1OslS
8DHg8jPITrWtw/CJ8IzVgRk6V1iT22NVvhj64CGdIUdVk7KXC5Gkeen0JC3CGMgSY64glYpfq87j
948lrowwAoQ/f/T8u/L7m+ehiv+DFSkh2gQayIuVLL0wot1ZsYkVaGw4qoDSpt+pJV6o8P3PA3Gj
i3Svxcsovh/9AISp0pAssXK1RCQlXwsvY5fHzTb6Xboo3/QtLP9/id+j8+q7Y/8PYi0iK1Uzl2jq
V5q2nDbPQc1J7EsaiK2g4NJxTNcrf7ja+9ZQ/5GMxS5lkOOAlCYeXnKSsmUFC5EJweCKXLKbQho+
qWKbPiWc/ruGVy02TU29kqKG11Fi1FYXdxNqaGFKff67lU8yw1vp16H1IUbmg9t4sqWtRv6rbL4n
xsmvKzoTvx+Q3i/VVNOv1umbyGc4+jRDkQZeTkQvJldFtPCNVy4fFjqhvGqpTimizOgEIGKMXUFX
xWlKK2K6ZYqFY27/F0+wtwJPCtiImWhcq91ObfAkB1oLwkS/BBTGw3v4FjxNYl+I07K/kcW+udx6
kqbUlv9VsXhtlixjywBuLm9Rur9QFQYgmSi01R81Sxx0Q0CAimnhh5nDwgiaqJQ7LnyrLF2jJy2r
3OzQrUvqBCHlxWr83lb21sxslmB7RW6p41lKVAuMZqx+BnYJagVW8g6AM3RiYrmow7XfrDYsYbl/
GDGOJ4sPr82IJK7/Z+LLgXrjQfePCXCmDZSQJ9vePptQ8/HQWbqlWug/SE6eKfQSWjNPOUwWD288
9IVrr2YRmEs0lFwyb54Cvr+FFHMLyCbZ1eofF1UY+AKk9Wr6uvM8D0WelziROnvPdaDLBWNuPUZP
Hxc95bt6pNuoOWlw+kJFnLqVHjcNBF/SfRFNnT+A4JnmzktY8WYQeqvPZ4/0+6PHK/iz1KE1U/0J
5Ytq8y4cM7OsTrU7qCcF0m08Gg+CnB8xrV7SdyW7zdpKiiRR3EXC0h7530NO4gTkxTnnhQgQPSQu
XKwuOyAtcJshpKWu1RSK1ExQoj0dE0zgkeXTK87+UZxyjA8z1KDuVKe+p1aSdm/zWADvLGAS33dy
ftpB+008SF5a02GK6EFyp+mXKGCYzaivxOR++avBo3Kh3cnfQVihEIZ2mM7/OvPSshIpvcBAFB6r
ndoOFmH+FNXQGsAQSGfWZjEeqV8fqz8Oj3bgUEpa/8BlDGcVSzVKk96BTWQXKuFT8pUE3y3i/gVn
6rD1nRzb1p+AeDpt2O1tjlFVSd1RehwQruIbvKRP0afUX9sPhsv40h9OyxfFfLxImbSLgRnJyKmR
7+K+oD1yJQSGjxPo8yfYIKno9ark4Ua2m2OyBCqSEgygXCYi70TpfNQK7mv8T0AMd/v46tM6Cgdr
OVc3v09B4srhl/2SClbImXLbfXHEvxq2qjFKXUaewek4BofjK7tdD2BBXRxJOd5pGgBys1Z8J7cH
Xa/e98r3DSwVR1g6yZOHCWUKOUTOv1J9e0V+0u5EKG1LGGisvoU1XA4o7alxqRxj6ehIU7K5+Mta
DrRV+RssGrMYme1nsX6djwynLmyqj71Etutszoj6yC4O10Bt9ZRcvRSLlTbG2628LO13zjMdneWq
b3RJIDrZnx4ImhBSgFhD05DcmGn2cOex5TztJr+3jlH33IIHTDd3ZWPvbi4uICrdLmWOJo7xTCHU
n7j6N1rMe+4F1RKiGPaTDA2vepooRUmMHoOCXwCKIDb+4gNwLy1pEFpZ8CfNLq9POk1C53wLlVgL
1b+eAlU4GnXFNl9sjMAet72b7orgwMplVu1STo0ywObVSMwIY6IXu+2RW6ESF+3KcHXuqVCDfzhZ
g7X4sezB9MI1W0uxE52SJThoSxlpZFqCUD+l+HR+AvWpFnB/OlTheVlh0DHMacKeGo5akGwOsEjX
iuD2TBz+XbGyfb+xagtQhNPYY74CkWtPUqmT+4iC7NuKhYb46k7SGECfcFn4TcXTuQMTSCt67yPG
vEuyn9nWLQVzliyh/eMPHpe9ULWbtHFw4NuaMU+QccMCOsZPmKsrzEj0hC3VGDbR0aUjGrq/YJtR
iCX/1eEeOUMklqOOU1kfxuviv7n/a1LqQ/RR5NhpnSSblyng4KXA23Xi4oc0muUw+8ySelZUiwSp
ls2N3OtLnsgK4dXtPteXPz2FTvnBGcNzGwGrbT7CFsutRxkFBZ4J5x4dRIvwTkTpcvuV+fPZLQTM
OaCNvcoiwjBYNW8MmpQcBT+9byCfdbfXFyvZzQkdoT6/YsOV0w3kkO0hVlrHLQ8B9k2hv5fJIe++
DqgdvXYpua6ldJVSCMkd4+RvNk+mOy94sGokY7rw97gndE+IM7mC05e11N0C0mjy8bFocxp+s8n4
0EcO6Y5wppQOOBwPoCprqFf7tkuhV+ZxW25Xt/2yiX8lYrFDEAJ6wMtAn/wYauPlO5hIO7uDI5Go
N4yL3b9k0RNea97c5NukXD8f/zkfLTjZXTujZSEqnIBFd3UMqyiJpgQfOx35bwiJWMqodlYiD1Aj
1nHQedXGBYUPYynxIfmjmIWctDDXVsl7tmmPD8dmP62gLARot9B8xYLBo/YVH21f++Llb6P/7iXi
7SwuCxYle1mIvc1p87uaGGXOKnFmwlUfXFGT74llpBJibEbsDqXmHVTw1oPQ0HRMEDaiFpDlcIv2
jVBPaVEjcaCIwUx6Bp9ca7rlXbT/yroKr4126NytfDsaPHAznY/X0i5vvS8/MN3yWTMKkD65aUDa
35T1teyDRRW4YSMgJawLElWy8sNGLflLC3rLsb3//PYjE0L+/pzS5cBuZll8nnp9j9ps7noZBxdx
Hl2LRx+vCCYW8B25VhjdocYLHbZgveGmuJO2TUInoYGVHRAZfnK1qiRYeRzK+HjbYoU2QUTUwe6f
LntTu1z4HI+aKb3TOaNVPuibgccvK/7u/fxYlzDSlrsQ98c1/67pCbAsDuaDcBTKFj7/NdkY1adJ
jqsmZ8tQB//PMjmOrMH46Y8k4a1CocCTPyPKXcdopQYyUHD+G2jnYQkkah76+qNSUxegBPx6j4i5
ZAMCLz4Z7wLq7l8WvxgZdxjniCZzN9BcjDacDTzwiNBiVVGTcF4ffPXFrQd0haxQQjrM05u9rcs4
4aEAWBZsOLf9OS/GAw3tjHwaEN6lWm7dTiC8ZAooo0WY2KrEaoasp/57D+Nt0Erj9eH/GbNxvUDA
BIEykq3zy5eUjOcNmN2s3o5f3vy8AByTfDwRIydUVTm69MiSBA2KwGjBnP1bZGpIIDgBFRRJQXgT
z79bVRZw19cemBuSBBaCOvk7EquEeLSMWhJw6sfDguJrspsjIeyH0fUpp+wDUy7Bqt4fI3dI9SVn
AYwth+QK2wjqey9aIrI1RS96wpDzvzQ0W7FUEV1YkBqAfqm5W1de2t3PQDs7XO5A9sj0ZbXuJaBg
LThfmA7kWrQfYVbHiLTBBYjSK0TFaBZL1rZ2Zes3PNoDisBwGyM+QU3ygvBf8NDobVMiM7AsQs0Z
uwURtrhoNcrNpb9AgFZ5N3CANbUlVPWHZmkD7XOld4GAXKe+PyOR0a2dpbS3ZTpJNwA5nb8rB4jZ
LukoQmotedJwdxigciVkKI27IlV7qj0NWEVv8hdq4cbRqUFXp4MwEOV4N77Qkr13k26cEQA+gJ4n
37ahFgmlgFoF63vF8botKhKU8Nk00FVu1/QSm4AhoQUSHTxDMdCkc0itP4/Fr9JFLgaGCCyjDt+5
qveTdvE4qlQBjWEBGS37MVjVqi0bEDBtlvlNpAtzLN6eogFqEfYKWsSd7HKvd4GBU3twiri3anui
6OdvoewfpO6F1eXMnu9lWgm5gNoqg2WG8EHMSlHaopdhVOtvEWFuMIJmTcl7BCdnNQmBCRBEDaxk
dHF4LXQq6Z8HdWpQ7ULFlx3gazL8mWyXxNFtweReWR4QTCCdDWkAbzsbO2auz06m9Sk3h6I98E2G
2goe3NJ+oQYf1d5NhGxryoA+YXLLTZ7d6QGEy3MCWtgr4b9I2uzPV48OY8cpM7ler/czuh+aYLQr
cGi4p+muuJSozPgbiOHGwSXTB2VEIGDg2rQqAcDPdrBs7TvwoINf74glENwmRjxFSIZDTouxvGQU
mR0AHLhyU70rCwGec3YhssrfqPmbC1kCtrInB38E2hKEPwYtx/4UK9l8hDvrISH5ubNZqoUEM0nm
DX631aDJuVm4wWHN0SyN4ro+3kPZvQGOMlKuotb6veWeEPEFZJ6rHeb/8lLTktSMN8GlHsMkiZOa
fn/ThRsguJaN03ZLPkvuLObWVrThbnoSa1dkka3CWorNCYMWMgt97D54mKTjDSI4WdsJAtrdbx+8
hu+VXtDFH2K0VqfsA2ahc6W5ry3UyEWy1I0NEIBd9S/Y+Ynaw6/fSxr79YnqIzETLELYoolYIOFu
fsAFD5iKKG/pnOVfjRa4/7VWBCLBzKjCNHgaJ7psA0zV88iGpcFcKMMuGSAVF9ncXbepYmhhcnre
RFV6+0tIrw4/hAUfQ6+zTX7iJRt3RRtn/H7W6U11f4aIM+TtfxAVxUw9VJNTxbx/Jw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ezlmHfThO2Un8MjJdXv4rT7MuQQcRdPWXb4trZUl5JO8dcJwSW55Zd7q8zUGGxsmm5KKn1EYwB1G
UrGONGvBKw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A1B+SR+o6IaBGUrz9igY9CNB0bWJFyCns/53ctROhMnOLoBxAM6Jfprm6SmK8OobXfVqp/RHQ7Ox
q6BRZ1iF6/yDLUWGK3odtfWFIpdEvccUOO3pJTN4+zz3MI3eFuIL/gPIpMDiGoYLiEjArg9ldgj1
eT8eK2aJ3isZTcbQkSU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
paSE/LL9LVyhT8P6gPCPVngrSZgpqLCD6j7n9uMAlaphzmiFQsqhvewMk6eTDeMbA6mFWWk1buoK
2Ow5CCszLZb2h3bnU+O1e76p0BmrDFzGt4FtS3blA2dcpT1MjEW2qMQv54d6JwHOOkKXMPcMxxty
WUQ8sHPqaTodiTGvxSrTbYOwZ/WjeGXYsYXm5S7FKYrMqsXthAoT4ZhEIbgsBfGmyhNq9tZa1DZI
TUQjxrjpsrc810gYJL9h9YAWx8dzrF6lTSKZEbhYuv7HOy4qtu0vgtKG9QFDhG+GHBSnHxm4d/QO
PLwTs9yjQNvfsvZ9V/yibeVJcm5amYk1vr9Ehg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y3mnedL1R+8DFRPX65B2EkmGLolKDP5A6/vOdR2weHwn3zktFHF9ghcwQEeXczb8URNzZrAEuv4N
d26o3znf2CQ11s4hi6TDbe/yLHHWah1tuVpDwlLXfzZXN0pqO78mxbmZtSnE21hX+NqUNnlVXiy+
rL8HASsZ875Z2w5FlFM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XbSu6jzyJWr0HQHPrzjx/CKtqiLkA4E5f3RkoiMATCyDadQRsdO6pYt8p/xMwcHP5FsRtLEY8VdI
LYsMDp3+8mlrsdKxKzFFiNB350NGihVuYYbFz+FYkhjB9Itil66du4H1PUFECaZ5tipGuOrR2wAn
cyR89cs7uv8FU7Xb8mWvXJA4XxvHID1TTd6qtz7xXY2Qj0CGnV6w/qrnhonTcr6GQawctOZzSq/G
nLbwZRh/oSnxOtqd5NzGtcAygiABKGmXhXfxfTqlXzuW4fMhm/hd7Ddgc2kRIQB9b+6d5o5lU6WJ
fhYimNtbhVHf+qLseh47PCrDdPxdB90yMWKE8Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8656)
`protect data_block
HrWCnN/ttl44DJHrHMFqrAC1en/UB+J/ELgxCwDzsSsCDt6aKKzOgOU0t5V5ejxlUb5f0/jXHryp
Ld0HLlBNoWHBhruMP5aijL4tvhusRtORXZBA4NZ698OvuiOfRm/cyz5b72923mGxPJj5qc6tZ61l
BF+M3uc0Rkj6bbmOXRcZgTLl7Ppt54YHOzxJ19x5/Fty54JA1JLSM+4RqOxoG/3PAoFTYWS53eJq
ULXd2boAT/JL0iMUB1UAmRbbyu/ShY43ialoZzVzzCYCLrogDwhyubSNNil36LaJdq/MILDbdHiP
9BRfyWwxZn8blpzd5Rd5AcXRazYpI2z3Pq1ywRE5ss27wP0sstdQpICDGindE1aCqrt/BjyDlY9a
0iiP3BimI4ziECbqVWwUCmA3ARZ7yoGhMcwtdfjRNhMhLDl5WNjfamvpspvdxEWMNyzXj6AxshfN
eU8J2bRLcEFPPZyszTwpi5iZZofKaehOwMEQEJwgTuUgTA0Fh+fZ9BCbg87+78XpOIxRRXDX1PPG
clsLDCPu0x8WEIGtvWSS1OceN2qgM2Bbb5eLG3oh+I5vcjUrc34ZDlVIKGiSFxj9oBoXSWLuZ63c
Z23gnWaahfZM+UhRzxCI8FXkGmFLrnUB+W6Ysu0SSslWLGU8HrywnueshqB/rBlDLiEwSrtl2kMO
4Zvuu5AefIZKRbq0cWPbLTSMoh8EeMDXRF0jg8kPj6x294yTijvWVcqkC0xEs2C6j7X48JfLpeIm
LDnOJzygl8LxpZjNzrOcBvEaEaaHT8P/WD7ZbpKg9ht5ccc+tm7VaaCWL1QysMvB8lfjYx03AwdW
+ai+u239t1BNMAQbQoIDjuffko/2ivTS1XVZo4uVjHHmowPLimgDBvG56NCkoInkewqY6NpF2tGf
xDeekBX4nnRtBNvqkun9CpiidCzY1Ipny3jfMcNc5pETuJKwq2pnaEN6JIYQoQIrUXGbxyj8av1B
pmhKxBwS4/GID58YywfQv7ndEnud910EgCGwd3+qzB0TacVDAMDCVrkkb2r8Zi2wei/rOtklfzap
u05Eb17EqTofxmvvi+iO8uFCFaq2Jjbqin8S1AN9CchrakIHMbxxi6NS+/jbEQ/S2COV6lwiqQaB
0504mGMAVGhyYAsvPWnbD92Sz6M56y6OcsRZOLuFtepFMWOZqp0kx1LpBqjGUMNLkNxDtYat+vjZ
osJ+XFI+LWPBPOIDbmXAxDsHH1amBtW4G5GVh7p0M80Hkct5PSbggs2EopR8gtilt6b3CSEEaz4W
EcGPloVi3wcnBW/2ZOk42Lp34fUOXe+55H1inGqQP0J7otmLA8BCpsYm8eLoG7BwoMqpf7WhMvSe
jHaNi9PTuyqidlJl/JYFbmDXP8nbhNkqnFB9KjF88/ik/jTOm5kzz0gguDtg5cYVNludxWY0JUa7
cOyPW2O+Y0fFToyYOftn/SIPr0wyrSrQZuijIiSG7ssUtiNeZwdPffYb2b5jfH1vYkNkrl84xxdD
GTOPCsyZmFoJ8I8mL+rpyfV1N/zrZfDpu0QoPPsKuVEYXJHQov2EcKvyiItm7OBUw154PdX86uRc
oamfvKEdTqC6zvTmbPf3YKQQwswNSOqcLkimcF7/bYrr6d1KoVYLIecYukkplMIw9vLPtN5MKiRk
ulEs8SDEo2Iv0qoQX2sU1oYOOzv1XTFTsrHD+rMxdOZraQlSUtQ71IRQewAsQK/U73Bc7OEVaQwf
uzGpNwhY6Byjf+FSZgFGkhWjjie1VYDYvm5RQm+/BVs28ecK/fKJb6YPDlmpL3r6mqLbry8xJkgL
AjMu66wyaeByaveq9H3EqfcT63f8rnFB35CJVFnZVtrdofQoyYO/OFVbIeMBwOlprk5RvFGr5TUI
gufpzXPmjmUZJVBLAMEBDKqvbfKKukhbzh/35NSppl/6Y2PM3z3runDFLWMMA5s/gV9nKJJbAEPy
ucaPAlJhCRifl9GyBebYvpWi+M/chOJKw2NgVnLG0jfG8g6tW4Sngw7XM6n6UUGzKqj0aVeTMuZ0
cZV9sFJTXW6eLQ5Tn6vUyBMYCMoo2tdfuZj8QI3p0GEDH8dnAmWmScvC/+WgSm98/a2UMLfYKZSJ
PrEbPIV1wR73Jq+eqUAfaElxKqA1hZD80m0KPClFnYRbISrZEYnkfFsi0Rbporl+Zbm/YYSYSlpQ
rPuek/TCg5SwdftC1WNs8aZBWl7H280+h/yyboPk5BlMmWdnQ+ZwHQiSTm+hspnTw4iNHezCn3f6
IZSAboQ+wst+ojzxrG9MRebpx8kzPiapb6L+mciw79fnGjLXQAPtMkDFLWqMXbzNxD02Kg3iKc8+
X15xyhteMK4du0IVUKr5j3yyM8S5C/DKYanh3ntpvipSCHQ8/CZCvd3tXKP0+6WqsLTPeefF1wsY
0AaHcc6tDYaiWRQD6pJeqhEiLYT60jVbVFTbgadsFM7Ce8cNitQgfHaMZSBZDvudn9pSoqlChL2d
0xtoKgJJT9XeXAvpMNziwDKUZ2JGpeLhPCwwLO2bMNxNwNn/ZCh+2sBCOTmzqByGDNZpbHQKkJlH
FvHxMJ5K9Nfrbb21elrFP8dxn/cLh8pJCucnQCiC3btbi/WCCelRYYu6/8drvS0OHA6VvYARdSbf
LUhpxcwyjK84l7nSEri/0sD12rd/exBhTUMyvy5UqFCfCWEHQWwukYi0h5VGMFhw4Gz+WE3glLf9
wIzT11taDHDIe+roGQNsCohmzF+YdFOfif8nV6j2i19entD549iCRYLn4M8aQom5ryKh00qNGBG0
QHB+f+egn7TTFyEIZICnOpOz9Que+wPZ9Hzgq+Xo7AtfTRd6M/2RXOmmsQIhzQ90LPNVXD52d0Um
KQjWgZb6S22GkJBM9M7sRuRqHkSFtAoa1NBdWH0u/ptSrQOoOhXOUuVx0kKg9SPX3Q4/BLCEAgED
9Q0hLpBO8Xy4008COljwSdMXmj51kJCNvt3Ldo1wTC5uv46A/9raEZWNi8IxLWe9e1aqZNUtGQDU
QBbFdcz0zstlhOtlD6NPP/HJ1XHLddXoixYhCufpZ+AOSc69ldXwNKq5xUj2Qs1HQ3VLJ/4uFlh8
ijhS3yvC7ytgUDYZDfs7Kn2T3Y2i7kA74fsXlUptcDM4jMQKIPMR25Xy92ZUum/cgfsZgiLlKB6h
se8UoydcQ2DWOFoo56DQdidb0rap66zwNOlVTqlDAI5xEB4sfgCYnLu6eh+7FX9+Qji6H8emdait
mFlBFjDQfK2a+nGsJS4PfOBrydIvXqI5zi46dicRWwiI/FMZZ85F5i0X8eVQIjeZszn+C0Uwl+of
s1EIdU4j+8R6pfffH2UW97L+Azpl+fNlHLXPn8+Cn8xG4qat7zkHfL8GnSBt/AW4qi1yHJ2qc2BF
h5pEUCUmOXKBXxcSIM0/WSxFYpUi321c7P62otZGIR2cm1m+iNKEUEDm1NLFnhGxAaiR/g2+wzXo
+wMzRuGOCuDF9UEmrhfY7FCQKsYcf0kVrYENQKULlb1jLvR0HkgA/s+uFaseXZSi/tKjOOdnHnAZ
1vnG50jEqI8nITWQjL2dY4VTgMge9ge/M/3mK0qVu6cG3HLOntYIBf7COoVstP60DUfjI+gkCNf7
iLJ6MqLTOEKn2LAf//3K8gtGSxcEhsUvspwfU6q1mTCoHp6wGnRjZSgJOEx82Gbqm/5jogZy2Bct
+JjVQXVIGHu9YyR2VhClP3is5sTzd/Cow/uHNCk0s1OXiTwY+BazAvRoXBZDOBwOD5cn64OOjqkE
Jh4x26olFmWqVjY5odAR942pZqMyaVYTbIydzLnBLC+cnr/Pm+wdG3D+Rba2a4DzSIDIUCe/n+HS
R/WkAKvMVPRyi0eVZYlSR0XVJ87viprMiY1zU4EzSsa4BGoYEtkERpVHo6AOpJRciodrjPgEGaD5
iqNlUCUR34wKRbae7TljuJT+1uFye4VMFfhn0RyUEjlUfs9b6Vz0zQz1hY9vHHFF/PBDORd2uWbk
zn9gyc78s77mF8jgfxYI3SHDQWn8dmG9JyN7ch+hkBNK4oHrtWlK8CteM/qjNiff3J4/vZ34A1qk
T8K/ib/hLdfwYY4CTP7tuFwaZZS8ZNJw0Ak4wEFlJOiFgzuN9qJy8sC3a47RB81mdYE5bWUe2tnj
Fmq96KZymUHWWNYlMNP13bD5ztnAkYZ6cKdhWJR3vuVNM3sfq6ZfTHjcuetkJ+JH7nPthDQjFn79
0tNoA3R6pwy8QE4n33AxzgGGRQWLt/F3gmHCuqL5z07O7O9iVkfGgAs7D1b/ZuvchuPitUCh/Dgf
CPb3vciDp3SnawWnb/iR1HOKb1GtH7jEBfb25ibb4cyIJBY/siPwed7E22ojHNLuta/qdn7Sa0gG
XD8/8zJEOOvprkVTJtlXp7eq3RU54cw1UyTD+5YWaTqfDcRvbbNf5KsxxBqjiercaLaj3mZCsGh1
pF3OrAw9POHbr+z2xKGSC7ZHyJ4b3IWwb+ek/ddBZQ74BFl5WK0obt2udRLHlI76zCaFQCSqZ7vq
hCX5dfFIe1Obp3M7i7W3K6KYY0pP/SFA1JzbuT8n8gjpzk4ra7qp7yBHLDymftYUck9GDHvuI2nl
K8IamZ7Nn+Pp7Ra509OotaaritYT+NBESqRFUaDtw3O71qiYopbuZElX3RbTqOrWeOr7va3Er3Cn
ASOBUeG1FO8/HvxYfWECByv+i44+fSgwkXM6B6kUoDGjAsRB1cv4RXQylYlTq8vc4+S6XpvZVHpD
RKDJUUwhHQlaMzx1CUpYK37JCHFePdOHZwxc5aHhH05pbnfLOkMtJKVl6UN4ZH+jFxdvl7dWaBZ/
qxqxcOQkzMUiaywJmZlAwNJXOcYCFnM0SrhWwWPbiKgBkXBPNHJ0E5wR/ihMO1/gDXxuAHuHDvsC
y/A02CmnHdzvTgtzy/Mkm+E6rR8gH4GIdr/Z0rVvy3ooTcStugrdQkGOYFMOBVdyEa4QoU8prsdD
U2EBcZSB1Q9kVml1ohOzu1TIG7BcNb8kpsDESvZevuAjBBBKSlF7oUlggMOQw1Bx9Jgfi3/7gtAh
giVmJKnlrn4W02ftKw+hiEn7RDSg1lQ9EodECXeHfL0QaC2yrVpmYOk5hM0VmPa3RvXNkROOIPpW
2kXHnGyPmJmUBKRvcANzaCzVDUlmtBhrhBnRi363o+hA9JuelcI50NVsQofdd0k8COgC+bMohUF6
cowmfdpBNL93+/nt+s67mh6sxHjcCJazvUc+svJZdNKRdxQJUp3iw7YyDEIrrI/eIet1k1GkPpwY
A2/+MWqK1mDiXibTw/cyZoAr2x37OxFKrSzt3klKzKRnVsUrb7I4jSpKMivGzovhAzSGw/9s/ulq
PdfZ+qCy2ClhG0rm6SM6HEywZd4/XMriO/nIqX2AIOXToZXizTE4aaOXad5iJOHAfSCkM+cKBcQH
IiZDTRI/ccnoiD2eFm7e+KLBNk3scXL9eF2toApTqhXvMIUERt1zDwpmd5yTSLYXiqa5mg9VsQfQ
c6292v3ssK0Nbt0SdxIPIfVpPAhbKZmwSZhKsVpY6ukzJJ9ULNRDwv828gV502Fy/kWAJFbiToLa
w+oIIjMPlJtijus0DnWSrgjJzEELehiEei65+jYjc20HVTss+Ge+a0MYkSwrFVobm+HxvsrqM/rN
Lo96QLOwkN7pekXs3goMXSDOlmCqTJRwNQfuRDkc4S4gPcPKdTfPpjNeOy/6FI5Rd+sURzIh3Cxq
qcgS7p0XB63jyZfT2zArIC870YEvQUzxclR46hBH0UsbRvlDD6bsUv8lqS0iVZfD9qinK8DuP8b8
LnrI7o4RTg6nc4mk6TLEPUBT1oCk1mPA+sGd4cPKOiDRz1fPiuSM2qe/ZNR3xBBdQ9UVzI5R0GlZ
1qBRkfuinYNEGCF1ObsmwQEbUwQs0OwI6hc+HX2/fVfpEpJmG8W24c7fb8XXe0fWM4HaOkPRxZZ2
GhLZsbaCR5YOBSwQuAWSmrwlExplarJLGxQwtma3ZW7dYk8xOFACNSWQyuYkELqhp3ph58qcbMW4
bwypbhwkzisqPdwLqnNHQPa1EuQq98e71Cq7Wv0KTEzbC26/I1Vo4mR9wBWmcIm07pWeYswn+zUR
zF9eD5csIsLB+cRoetYemoX4N20bMWNdUV/vGsbiZn4KOWVWfytnhG1Z85pYbKvDut8O34Tbzc2L
L2AwGY40BAY+xa+Vv1d4gF81jmaGBtIrxPy/o3cWK5IWV5A3Qi0n87zKuSgbHO1b03rxnmkJQw9l
Ys8WyEBSu3s7SZGQqw2FdR4gK2yb+mavgUsaBuHxSZdMi9Xg98zxpYEmeBvLfUwYkT4YRG9ONYTt
qQ5LgtVU0Dpoi6QqXzBsyKSrD9A43FKtw36pBenntjdSiInSlU57B7+kKgxIQjalLX6F/zXRSsKz
HKb+crycIVtBt62vbF+i4rQ7DpOanx7YvpVlqp60ozSTlAgg5zXzF/OIdKut80oYB8ZHMHwC1aD0
P3From6w7RmhBArKrwMHu+YKBezNFI5U8s5OFsu2o5TyJowbFRCgko5F7mpd0iIyKdGWCc0E/Nlb
dt4AglroR076xZ3kN1uvv8S5o80JpVp5XztpiX9r3ZSBMxv/tl353seEj0xpYfZf9wTSPcAjNm22
6nKyEwQW4+DKoaO2yzCjPWRyOr75QKbpaSbxDehrmvaI9WVbSZGLKdMAcuIjn8QosQg+38QmSM5u
fw38c40/QsuYQz685Jq6AzTAGC+JIqwUKj2kS3s3TGXttXtHJNXdQe0oQVhj6vu9UzLPGZzxve66
rwPO3mbFwE/jzyJC8CYyw7cnULpHA6Nlz2qqwC9efUyvW5c5hoG7eyU0ffXZY3zxGytucnqRuFZu
PENaMX0nJIZ8lH/lvLb4HyGz4fDn4+NzWi96lXZjmGCE5u7mvfmuhIkXs6FTp47PI8CZnGZ1OslS
8DHg8jPITrWtw/CJ8IzVgRk6V1iT22NVvhj64CGdIUdVk7KXC5Gkeen0JC3CGMgSY64glYpfq87j
948lrowwAoQ/f/T8u/L7m+ehiv+DFSkh2gQayIuVLL0wot1ZsYkVaGw4qoDSpt+pJV6o8P3PA3Gj
i3Svxcsovh/9AISp0pAssXK1RCQlXwsvY5fHzTb6Xboo3/QtLP9/id+j8+q7Y/8PYi0iK1Uzl2jq
V5q2nDbPQc1J7EsaiK2g4NJxTNcrf7ja+9ZQ/5GMxS5lkOOAlCYeXnKSsmUFC5EJweCKXLKbQho+
qWKbPiWc/ruGVy02TU29kqKG11Fi1FYXdxNqaGFKff67lU8yw1vp16H1IUbmg9t4sqWtRv6rbL4n
xsmvKzoTvx+Q3i/VVNOv1umbyGc4+jRDkQZeTkQvJldFtPCNVy4fFjqhvGqpTimizOgEIGKMXUFX
xWlKK2K6ZYqFY27/F0+wtwJPCtiImWhcq91ObfAkB1oLwkS/BBTGw3v4FjxNYl+I07K/kcW+udx6
kqbUlv9VsXhtlixjywBuLm9Rur9QFQYgmSi01R81Sxx0Q0CAimnhh5nDwgiaqJQ7LnyrLF2jJy2r
3OzQrUvqBCHlxWr83lb21sxslmB7RW6p41lKVAuMZqx+BnYJagVW8g6AM3RiYrmow7XfrDYsYbl/
GDGOJ4sPr82IJK7/Z+LLgXrjQfePCXCmDZSQJ9vePptQ8/HQWbqlWug/SE6eKfQSWjNPOUwWD288
9IVrr2YRmEs0lFwyb54Cvr+FFHMLyCbZ1eofF1UY+AKk9Wr6uvM8D0WelziROnvPdaDLBWNuPUZP
Hxc95bt6pNuoOWlw+kJFnLqVHjcNBF/SfRFNnT+A4JnmzktY8WYQeqvPZ4/0+6PHK/iz1KE1U/0J
5Ytq8y4cM7OsTrU7qCcF0m08Gg+CnB8xrV7SdyW7zdpKiiRR3EXC0h7530NO4gTkxTnnhQgQPSQu
XKwuOyAtcJshpKWu1RSK1ExQoj0dE0zgkeXTK87+UZxyjA8z1KDuVKe+p1aSdm/zWADvLGAS33dy
ftpB+008SF5a02GK6EFyp+mXKGCYzaivxOR++avBo3Kh3cnfQVihEIZ2mM7/OvPSshIpvcBAFB6r
ndoOFmH+FNXQGsAQSGfWZjEeqV8fqz8Oj3bgUEpa/8BlDGcVSzVKk96BTWQXKuFT8pUE3y3i/gVn
6rD1nRzb1p+AeDpt2O1tjlFVSd1RehwQruIbvKRP0afUX9sPhsv40h9OyxfFfLxImbSLgRnJyKmR
7+K+oD1yJQSGjxPo8yfYIKno9ark4Ua2m2OyBCqSEgygXCYi70TpfNQK7mv8T0AMd/v46tM6Cgdr
OVc3v09B4srhl/2SClbImXLbfXHEvxq2qjFKXUaewek4BofjK7tdD2BBXRxJOd5pGgBys1Z8J7cH
Xa/e98r3DSwVR1g6yZOHCWUKOUTOv1J9e0V+0u5EKG1LGGisvoU1XA4o7alxqRxj6ehIU7K5+Mta
DrRV+RssGrMYme1nsX6djwynLmyqj71Etutszoj6yC4O10Bt9ZRcvRSLlTbG2628LO13zjMdneWq
b3RJIDrZnx4ImhBSgFhD05DcmGn2cOex5TztJr+3jlH33IIHTDd3ZWPvbi4uICrdLmWOJo7xTCHU
n7j6N1rMe+4F1RKiGPaTDA2vepooRUmMHoOCXwCKIDb+4gNwLy1pEFpZ8CfNLq9POk1C53wLlVgL
1b+eAlU4GnXFNl9sjMAet72b7orgwMplVu1STo0ywObVSMwIY6IXu+2RW6ESF+3KcHXuqVCDfzhZ
g7X4sezB9MI1W0uxE52SJThoSxlpZFqCUD+l+HR+AvWpFnB/OlTheVlh0DHMacKeGo5akGwOsEjX
iuD2TBz+XbGyfb+xagtQhNPYY74CkWtPUqmT+4iC7NuKhYb46k7SGECfcFn4TcXTuQMTSCt67yPG
vEuyn9nWLQVzliyh/eMPHpe9ULWbtHFw4NuaMU+QccMCOsZPmKsrzEj0hC3VGDbR0aUjGrq/YJtR
iCX/1eEeOUMklqOOU1kfxuviv7n/a1LqQ/RR5NhpnSSblyng4KXA23Xi4oc0muUw+8ySelZUiwSp
ls2N3OtLnsgK4dXtPteXPz2FTvnBGcNzGwGrbT7CFsutRxkFBZ4J5x4dRIvwTkTpcvuV+fPZLQTM
OaCNvcoiwjBYNW8MmpQcBT+9byCfdbfXFyvZzQkdoT6/YsOV0w3kkO0hVlrHLQ8B9k2hv5fJIe++
DqgdvXYpua6ldJVSCMkd4+RvNk+mOy94sGokY7rw97gndE+IM7mC05e11N0C0mjy8bFocxp+s8n4
0EcO6Y5wppQOOBwPoCprqFf7tkuhV+ZxW25Xt/2yiX8lYrFDEAJ6wMtAn/wYauPlO5hIO7uDI5Go
N4yL3b9k0RNea97c5NukXD8f/zkfLTjZXTujZSEqnIBFd3UMqyiJpgQfOx35bwiJWMqodlYiD1Aj
1nHQedXGBYUPYynxIfmjmIWctDDXVsl7tmmPD8dmP62gLARot9B8xYLBo/YVH21f++Llb6P/7iXi
7SwuCxYle1mIvc1p87uaGGXOKnFmwlUfXFGT74llpBJibEbsDqXmHVTw1oPQ0HRMEDaiFpDlcIv2
jVBPaVEjcaCIwUx6Bp9ca7rlXbT/yroKr4126NytfDsaPHAznY/X0i5vvS8/MN3yWTMKkD65aUDa
35T1teyDRRW4YSMgJawLElWy8sNGLflLC3rLsb3//PYjE0L+/pzS5cBuZll8nnp9j9ps7noZBxdx
Hl2LRx+vCCYW8B25VhjdocYLHbZgveGmuJO2TUInoYGVHRAZfnK1qiRYeRzK+HjbYoU2QUTUwe6f
LntTu1z4HI+aKb3TOaNVPuibgccvK/7u/fxYlzDSlrsQ98c1/67pCbAsDuaDcBTKFj7/NdkY1adJ
jqsmZ8tQB//PMjmOrMH46Y8k4a1CocCTPyPKXcdopQYyUHD+G2jnYQkkah76+qNSUxegBPx6j4i5
ZAMCLz4Z7wLq7l8WvxgZdxjniCZzN9BcjDacDTzwiNBiVVGTcF4ffPXFrQd0haxQQjrM05u9rcs4
4aEAWBZsOLf9OS/GAw3tjHwaEN6lWm7dTiC8ZAooo0WY2KrEaoasp/57D+Nt0Erj9eH/GbNxvUDA
BIEykq3zy5eUjOcNmN2s3o5f3vy8AByTfDwRIydUVTm69MiSBA2KwGjBnP1bZGpIIDgBFRRJQXgT
z79bVRZw19cemBuSBBaCOvk7EquEeLSMWhJw6sfDguJrspsjIeyH0fUpp+wDUy7Bqt4fI3dI9SVn
AYwth+QK2wjqey9aIrI1RS96wpDzvzQ0W7FUEV1YkBqAfqm5W1de2t3PQDs7XO5A9sj0ZbXuJaBg
LThfmA7kWrQfYVbHiLTBBYjSK0TFaBZL1rZ2Zes3PNoDisBwGyM+QU3ygvBf8NDobVMiM7AsQs0Z
uwURtrhoNcrNpb9AgFZ5N3CANbUlVPWHZmkD7XOld4GAXKe+PyOR0a2dpbS3ZTpJNwA5nb8rB4jZ
LukoQmotedJwdxigciVkKI27IlV7qj0NWEVv8hdq4cbRqUFXp4MwEOV4N77Qkr13k26cEQA+gJ4n
37ahFgmlgFoF63vF8botKhKU8Nk00FVu1/QSm4AhoQUSHTxDMdCkc0itP4/Fr9JFLgaGCCyjDt+5
qveTdvE4qlQBjWEBGS37MVjVqi0bEDBtlvlNpAtzLN6eogFqEfYKWsSd7HKvd4GBU3twiri3anui
6OdvoewfpO6F1eXMnu9lWgm5gNoqg2WG8EHMSlHaopdhVOtvEWFuMIJmTcl7BCdnNQmBCRBEDaxk
dHF4LXQq6Z8HdWpQ7ULFlx3gazL8mWyXxNFtweReWR4QTCCdDWkAbzsbO2auz06m9Sk3h6I98E2G
2goe3NJ+oQYf1d5NhGxryoA+YXLLTZ7d6QGEy3MCWtgr4b9I2uzPV48OY8cpM7ler/czuh+aYLQr
cGi4p+muuJSozPgbiOHGwSXTB2VEIGDg2rQqAcDPdrBs7TvwoINf74glENwmRjxFSIZDTouxvGQU
mR0AHLhyU70rCwGec3YhssrfqPmbC1kCtrInB38E2hKEPwYtx/4UK9l8hDvrISH5ubNZqoUEM0nm
DX631aDJuVm4wWHN0SyN4ro+3kPZvQGOMlKuotb6veWeEPEFZJ6rHeb/8lLTktSMN8GlHsMkiZOa
fn/ThRsguJaN03ZLPkvuLObWVrThbnoSa1dkka3CWorNCYMWMgt97D54mKTjDSI4WdsJAtrdbx+8
hu+VXtDFH2K0VqfsA2ahc6W5ry3UyEWy1I0NEIBd9S/Y+Ynaw6/fSxr79YnqIzETLELYoolYIOFu
fsAFD5iKKG/pnOVfjRa4/7VWBCLBzKjCNHgaJ7psA0zV88iGpcFcKMMuGSAVF9ncXbepYmhhcnre
RFV6+0tIrw4/hAUfQ6+zTX7iJRt3RRtn/H7W6U11f4aIM+TtfxAVxUw9VJNTxbx/Jw==
`protect end_protected
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
use work.mypack.all;
use work.myentities.all;
entity tute2_tb is end entity;
architecture testbench of tute2_tb is
signal success, done, error : std_ulogic := '0';
signal reset_n, clk : std_ulogic := '0';
signal counter : integer := 0;
signal memctl : MEM_CTL;
signal memres : MEM_RES;
signal resXorAnd : u8;
begin
success <= done and (not error);
process begin
clk <= '0'; wait for 5 ps;
clk <= '1'; wait for 5 ps;
end process;
process begin
wait until rising_edge(clk);
counter <= counter + 1;
if counter >= 10 then
reset_n <= '1';
end if;
end process;
test: entity work.tute2 port map(
clk_clk => clk, clk_reset_n => reset_n,
memctl => memctl ,
memres => memres ,
resXorAnd => resXorAnd
);
process begin
wait until rising_edge(clk);
case counter is -- write values
when 13 =>
memctl.act <= '1';
memctl.write <= '1';
memctl.wdata <= X"50";
when 14 =>
memctl.act <= '0';
memctl.write <= '0';
memctl.wdata <= X"00";
when 15 =>
memctl.act <= '1';
memctl.write <= '0';
memctl.wdata <= X"00";
when 16 =>
memctl.act <= '1';
memctl.write <= '0';
memctl.wdata <= X"00";
when 17 =>
memctl.act <= '0';
memctl.write <= '0';
memctl.wdata <= X"00";
when 18 =>
memctl.act <= '1';
memctl.write <= '1';
memctl.wdata <= X"90";
when 19 =>
memctl.act <= '0';
memctl.write <= '0';
memctl.wdata <= X"00";
when others => null;
end case;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity BistableElement_test is
end BistableElement_test;
architecture Beh of BistableElement_test is
component BistableElement
port(
Q: out std_logic;
nQ: out std_logic
);
end component;
signal res, nRes: std_logic;
begin
BistableBeh: entity BistableElement(Struct) port map(
Q => res,
nQ => nRes
);
end Beh; |
-------------------------------------------------------------------------------
--
-- File: SPI_IAP_TestModule.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module is designed to emulate the upper level IP for the SPI indirect
-- access port to facilitate the testing of the ConfigADC module.
-- The Axi Stream command FIFO is loaded with kCmdFIFO_NoWrCmds commands and the
-- data read back from the AD96xx_92xxSPI_Model is compared against the expected
-- data.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodADC.all;
entity SPI_IAP_TestModule is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
Port (
-- 100MHZ clock input.
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
asRst_n : in STD_LOGIC;
-- ADC initialization complete flag.
sInitDoneADC : in std_logic;
-- SPI Indirect access port; it provides the means to indirectly access
-- the ADC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
-- TX command AXI stream interface
sCmdTxAxisTvalid: out STD_LOGIC;
sCmdTxAxisTready: in STD_LOGIC;
sCmdTxAxisTdata: out STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TX command AXI stream interface
sCmdRxAxisTvalid: in STD_LOGIC;
sCmdRxAxisTready: out STD_LOGIC;
sCmdRxAxisTdata : in STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end SPI_IAP_TestModule;
architecture Behavioral of SPI_IAP_TestModule is
COMPONENT ADC_CommandFIFO
PORT (
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal sCmdTxWrRstBusy, sCmdTxRdRstBusy : std_logic;
signal sCmdRxWrRstBusy, sCmdRxRdRstBusy : std_logic;
signal sMasterTxAxisTvalid, sMasterTxAxisTready : std_logic;
signal sMasterTxAxisTdata : std_logic_vector (31 downto 0);
signal sMasterTxAxisTvalidSR : std_logic_vector (kCmdFIFO_NoWrCmds downto 0);
signal sTestCmdRxAxisTvalid : STD_LOGIC;
signal sTestCmdRxAxisTready : STD_LOGIC;
signal sTestCmdRxAxisTdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal RxCmdIndex : unsigned (kCmdFIFO_NoWrCmds downto 0);
signal sTransactionTimer : unsigned (23 downto 0) := (others => '0');
signal RxCmdDone, RxCmdOverflow, RxCmdRdbkErr, sRxTransactionTimeExpired : std_logic := '0';
signal sComandList : CmdFIFO_WrCmdList_t;
-- chip grade, chip ID
constant kCmdFIFO_RdList : CmdFIFO_RdCmdList_t := (SelADC_Grade(kZmodID),SelADC_ID(kZmodID));
begin
InstTxFIFO : ADC_CommandFIFO
PORT MAP (
wr_rst_busy => sCmdTxWrRstBusy,
rd_rst_busy => sCmdTxRdRstBusy,
m_aclk => SysClk100,
s_aclk => SysClk100,
s_aresetn => asRst_n,
s_axis_tvalid => sMasterTxAxisTvalid,
s_axis_tready => sMasterTxAxisTready,
s_axis_tdata => sMasterTxAxisTdata,
m_axis_tvalid => sCmdTxAxisTvalid,
m_axis_tready => sCmdTxAxisTready,
m_axis_tdata => sCmdTxAxisTdata
);
sTestCmdRxAxisTready <= '1';
InstRxFIFO : ADC_CommandFIFO
PORT MAP (
wr_rst_busy => sCmdRxWrRstBusy,
rd_rst_busy => sCmdRxRdRstBusy,
m_aclk => SysClk100,
s_aclk => SysClk100,
s_aresetn => asRst_n,
s_axis_tvalid => sCmdRxAxisTvalid,
s_axis_tready => sCmdRxAxisTready,
s_axis_tdata => sCmdRxAxisTdata,
m_axis_tvalid => sTestCmdRxAxisTvalid,
m_axis_tready => sTestCmdRxAxisTready,
m_axis_tdata => sTestCmdRxAxisTdata
);
-- Load the TX command FIFO with the same command list used for the AD96xx/AD92xx
-- initialization. The command list is truncated to kNumCommands.
-- A shift register on kNumCommands+1 bits will be used to generate the TX command FIFO
-- master interface valid signal.
ProcTxCmdTvalid: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sMasterTxAxisTvalidSR(kCmdFIFO_NoWrCmds downto 1) <= (others => '1');
sMasterTxAxisTvalidSR(0) <= '0';
for i in 0 to kCmdFIFO_NoWrCmds loop
sComandList(i) <= kCmdFIFO_WrList(i);
end loop;
elsif (rising_edge(SysClk100)) then
if (sMasterTxAxisTready = '1') then -- sCmdTxWrRstBusy always in Hi-Z in simulation
sMasterTxAxisTvalidSR <= '0' & sMasterTxAxisTvalidSR(kCmdFIFO_NoWrCmds downto 1);
for i in 0 to kCmdFIFO_NoWrCmds-1 loop
sComandList(i) <= sComandList(i+1);
end loop;
sComandList(kCmdFIFO_NoWrCmds) <= (others => '0');
end if;
end if;
end process;
sMasterTxAxisTvalid <= sMasterTxAxisTvalidSR(0);
sMasterTxAxisTdata <= x"00" & sComandList(0);
-- This process verifies if the expected number of read commands have been
-- completed. An index is incremented as data is extracted from the RX
-- command FIFO.
ProcCmdIndex: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
RxCmdIndex <= (others => '0');
RxCmdDone <= '0';
RxCmdOverflow <= '0';
elsif (rising_edge(SysClk100)) then
if ((sTestCmdRxAxisTready = '1') and (sTestCmdRxAxisTvalid = '1')) then
RxCmdIndex <= RxCmdIndex + 1;
if (RxCmdIndex = kCmdFIFO_NoRdCmds - 1) then
RxCmdDone <= '1';
elsif (RxCmdIndex > kCmdFIFO_NoRdCmds - 1) then
RxCmdOverflow <= '1';
end if;
end if;
end if;
end process;
-- Data checker process; Reads the data available in the Rx command FIFO,
-- compares it against the expected values and asserts a flag if all
-- received commands match the expected values.
ProcDataChecker: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
RxCmdRdbkErr <= '0';
elsif (rising_edge(SysClk100)) then
if ((sTestCmdRxAxisTready = '1') and (sTestCmdRxAxisTvalid = '1')) then
if (kCmdFIFO_RdList(to_integer(RxCmdIndex)) /= sTestCmdRxAxisTdata(7 downto 0)) then
RxCmdRdbkErr <= '1';
end if;
end if;
end if;
end process;
-- Timer used to determine a timeout condition for the SPI indirect
-- access port transactions to complete. The assertion of sRxTransactionTimeExpired
-- does not represent an error itself. When sRxTransactionTimeExpired is asserted,
-- RxCmdDone, RxCmdOverflow and RxCmdRdbkErr are evaluated to determine if the
-- transaction was successful or not.
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sTransactionTimer <= (others => '0');
sRxTransactionTimeExpired <= '0';
elsif (rising_edge(SysClk100)) then
if (sInitDoneADC = '0') then
sTransactionTimer <= (others => '0');
else
if (sTransactionTimer = kCmdFIFO_Timeout) then
sRxTransactionTimeExpired <= '1';
else
sTransactionTimer <= sTransactionTimer + 1;
end if;
end if;
end if;
end process;
-- Process checking relevant status flags and determining if the
-- expected data was correctly received.
ProcMain: process
begin
wait until rising_edge(sRxTransactionTimeExpired );
assert (RxCmdDone = '1' and RxCmdOverflow = '0' and RxCmdRdbkErr = '0')
report "RX FIFO SPI indirect access port command read back error" & LF & HT & HT
severity ERROR;
wait;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DEBUG_RAM.vhd when simulating
-- the core, DEBUG_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DEBUG_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DEBUG_RAM;
ARCHITECTURE DEBUG_RAM_a OF DEBUG_RAM IS
-- synthesis translate_off
COMPONENT wrapped_DEBUG_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DEBUG_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 256,
c_read_width_a => 64,
c_read_width_b => 4,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 4,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DEBUG_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DEBUG_RAM_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DEBUG_RAM.vhd when simulating
-- the core, DEBUG_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DEBUG_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DEBUG_RAM;
ARCHITECTURE DEBUG_RAM_a OF DEBUG_RAM IS
-- synthesis translate_off
COMPONENT wrapped_DEBUG_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DEBUG_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 256,
c_read_width_a => 64,
c_read_width_b => 4,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 4,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DEBUG_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DEBUG_RAM_a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity synchronized_module is
end entity synchronized_module;
architecture test of synchronized_module is
use work.synchronize.all;
signal barrier : std_logic;
begin
pullup : barrier <= 'H';
-- code from book
synchronized_module : process is
-- . . .
begin
init_synchronize(barrier);
-- . . .
loop
-- . . .
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
-- . . .
end loop;
end process synchronized_module;
-- end code from book
another_synchronized_module : process is
begin
init_synchronize(barrier);
loop
wait for 10 ns;
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
end loop;
end process another_synchronized_module;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity synchronized_module is
end entity synchronized_module;
architecture test of synchronized_module is
use work.synchronize.all;
signal barrier : std_logic;
begin
pullup : barrier <= 'H';
-- code from book
synchronized_module : process is
-- . . .
begin
init_synchronize(barrier);
-- . . .
loop
-- . . .
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
-- . . .
end loop;
end process synchronized_module;
-- end code from book
another_synchronized_module : process is
begin
init_synchronize(barrier);
loop
wait for 10 ns;
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
end loop;
end process another_synchronized_module;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity synchronized_module is
end entity synchronized_module;
architecture test of synchronized_module is
use work.synchronize.all;
signal barrier : std_logic;
begin
pullup : barrier <= 'H';
-- code from book
synchronized_module : process is
-- . . .
begin
init_synchronize(barrier);
-- . . .
loop
-- . . .
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
-- . . .
end loop;
end process synchronized_module;
-- end code from book
another_synchronized_module : process is
begin
init_synchronize(barrier);
loop
wait for 10 ns;
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
end loop;
end process another_synchronized_module;
end architecture test;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SettingsReg0
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SettingsReg1 is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
-- gpib
myAddr : out std_logic_vector (4 downto 0);
T1 : out std_logic_vector (7 downto 0)
);
end SettingsReg1;
architecture arch of SettingsReg1 is
signal inner_buf : std_logic_vector (15 downto 0);
begin
inner_buf(15 downto 13) <= "000";
data_out <= inner_buf;
myAddr <= inner_buf(4 downto 0);
T1 <= inner_buf(12 downto 5);
process (reset, strobe) begin
if reset = '1' then
-- default 132*Tclk = 2uS and addr=1
inner_buf(12 downto 0) <= "1000010000001";
elsif rising_edge(strobe) then
inner_buf(12 downto 0) <= data_in(12 downto 0);
end if;
end process;
end arch;
|
library verilog;
use verilog.vl_types.all;
entity Environment_sv_unit is
end Environment_sv_unit;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
|
---------------------------------------------------------------------
-- Generic dual-port memory
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Portable description of a dual-port memory block with one write
-- port. Major FPGA synthesis tools can infer on-chip block RAM
-- from this description. Can be replaced with a library component
-- wrapper if needed.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_ram256x32 is
port(
clk_i: in std_logic;
we_i: in std_logic;
waddr_i: in std_logic_vector(7 downto 0);
wdata_i: in std_logic_vector(31 downto 0);
re_i: in std_logic;
raddr_i: in std_logic_vector(7 downto 0);
rdata_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_ram256x32 is
type ram_type is array(255 downto 0) of std_logic_vector(31 downto 0);
signal ram: ram_type:=(others=>(others=>'0')); -- zero-initialize for SRAM-based FPGAs
attribute syn_ramstyle: string;
attribute syn_ramstyle of ram: signal is "no_rw_check";
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
begin
-- Write port
process (clk_i) is
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(unsigned(waddr_i)))<=wdata_i;
end if;
end if;
end process;
-- Read port
process (clk_i) is
begin
if rising_edge(clk_i) then
if re_i='1' then
if is_x(raddr_i) then -- to avoid numeric_std warnings during simulation
rdata_o<=(others=>'X');
else
rdata_o<=ram(to_integer(unsigned(raddr_i)));
end if;
end if;
end if;
end process;
end architecture;
|
--
-- VHDL Architecture lab11_RegisterTracker_lib.Processor.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 15:43:22 04/19/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
ENTITY Processor IS
GENERIC( addr_size: positive := 4);
PORT( operand1_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
operand2_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
reserve_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
clear_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
dependsOn_op1: In std_logic := '0'; -- whether the current instruction depends on Register value corresponding to operand 1
dependsOn_op2: In std_logic := '0'; -- whether the current instruction depends on Register value corresponding to operand 2
RegWrite_current: IN std_logic := '0'; -- Register writeback enable signal from the previous instruction (from WriteBack stage)
RegWrite_previous: IN std_logic := '0'; -- Register writeback enable signal from the current instruction (from Decode stage)
Register_Out: IN std_logic_vector(15 downto 0) := (others=>'0') ; -- values coming out of the Register
reset: IN std_logic := '0';
decode_pcval_out: IN std_logic_vector(15 DOWNTO 0);
-- *************** OUTPUTS **************************************************************
decode_pcval_out_TrackerOut: OUT std_logic_vector(15 DOWNTO 0);
can_move_on: OUT std_logic;
Register_In: OUT std_logic_vector(15 downto 0) -- input to be fed to the Register
);
END ENTITY Processor;
--
ARCHITECTURE Behavior OF Processor IS
BEGIN
p1: PROCESS(all)
CONSTANT ALL_ZERO: std_logic_vector(15 downto 0) := (others=>'0');
CONSTANT ALL_ONE: std_logic_vector(15 downto 0) := (others=>'1');
VARIABLE result_op1: std_logic_vector(15 downto 0); -- one-hot representation of operand 1's Register
VARIABLE result_op2: std_logic_vector(15 downto 0); -- one-hot representation of operand 2's Register
VARIABLE result_clear: std_logic_vector(15 downto 0); -- one-hot representation of the Register to clean (coming out from the Write Back stage)
VARIABLE result_reserve: std_logic_vector(15 downto 0); -- one-hot representation of the Register to reserve (for the Destination Register)
VARIABLE selection_op1: natural; -- integer representations, likewise
VARIABLE selection_op2: natural;
VARIABLE selection_clear: natural;
VARIABLE selection_reserve: natural;
VARIABLE upcoming_op1: std_logic; -- upcoming reservation status bit for operand 1's Register
VARIABLE upcoming_op2: std_logic; -- upcoming reservation status bit for operand 2's Register
VARIABLE can_move_on_var: std_logic := '1';
VARIABLE Register_Out_var: std_logic_vector(15 downto 0);
VARIABLE Register_In_var: std_logic_vector(15 downto 0);
VARIABLE decode_pcval_out_TrackerOut_var : std_logic_vector(15 downto 0); -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
BEGIN
Register_Out_var := Register_Out; -- *** currently saved Register values
Register_In_var := Register_Out; -- *** currently saved Register values
decode_pcval_out_TrackerOut_var := decode_pcval_out;
selection_op1 := to_integer( ieee.numeric_std.unsigned(operand1_Addr) );
selection_op2 := to_integer( ieee.numeric_std.unsigned(operand2_Addr) );
-- If the Register for operand 1 is the same as Register to be cleared from Write-Back signal
IF( (selection_op1 = selection_clear) and (RegWrite_previous = '1') ) THEN
upcoming_op1 := '1';
ELSE
upcoming_op1 := Register_Out(selection_op1); -- upcoming status value for operand 1's Register
END IF;
-- If the Register for operand 2 is the same as Register to be cleared from Write-Back signal
IF( (selection_op2 = selection_clear) and (RegWrite_previous = '1') ) THEN
upcoming_op2 := '1';
ELSE
upcoming_op2 := Register_Out(selection_op2); -- upcoming status value for operand 2's Register
END IF;
-- Preprare bit masking for the clear Address
result_clear := ALL_ONE; -- pre-set all bits to 1
selection_clear := to_integer( ieee.numeric_std.unsigned(clear_Addr) );
IF( RegWrite_previous = '1') THEN
result_clear(selection_clear) := '0'; -- clear the reserved bit for previous instruction's destination
END IF;
-- Prepare bit masking for the reserve Address
result_reserve := ALL_ZERO; -- pre-set all bits to 0
selection_reserve := to_integer( ieee.numeric_std.unsigned(reserve_Addr) );
IF( RegWrite_current = '1') THEN
result_reserve(selection_reserve) := '1'; -- set a reserved bit for current instuction's destination
END IF;
-- Override the upcoming reservation status to 0 if the Register values are not needed in the instruction
IF( dependsOn_op1 /= '1') THEN
upcoming_op1 := '0';
END IF;
IF( dependsOn_op2 /= '1') THEN
upcoming_op2 := '0';
END IF;
-- If the Registers for both of the operands have not been reserved
IF( (upcoming_op1 = '0') and (upcoming_op2 = '0') ) THEN
can_move_on_var := '1'; -- can proceed with the next instruction
Register_In_var := Register_Out_var AND result_clear; -- *** clear the status bit corresponding to the clear Address (FIRST)
Register_In_var := Register_In_var OR result_reserve; -- *** reserve the status bit for the Destination Address (SECOND)
ELSE
can_move_on_var := '0'; -- stall
Register_In_var := Register_Out_var AND result_clear; -- *** clear the status bit corresponding to the clear Address
END IF;
-- If reset is enabled
IF( reset = '1') THEN
can_move_on_var := '1';
Register_In_var := (others=>'0');
END IF;
-- Finalize outputs
decode_pcval_out_TrackerOut <= decode_pcval_out_TrackerOut_var;
can_move_on <= can_move_on_var;
Register_In <= Register_In_var;
END PROCESS p1;
END ARCHITECTURE Behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity EXMEM_register is
port(Clk, reset : in std_logic;
ALU_ressult_i, data_mem_i: in std_logic_vector(31 downto 0);
ALU_ressult_o, data_mem_o: out std_logic_vector(31 downto 0);
register_address_i: in std_logic_vector(4 downto 0);
register_address_o: out std_logic_vector(4 downto 0);
MemtoReg_i, RegWrite_i: in std_logic;
MemtoReg_o, RegWrite_o: out std_logic);
end EXMEM_register;
architecture EXMEM_register_a of EXMEM_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
type tmp_array_short is array (0 to 1) of std_logic_vector(4 downto 0);
type tmp_array_logic is array (0 to 1) of std_logic;
signal data_mem_tmp, ALU_ressult_tmp: tmp_array;
signal register_address_tmp: tmp_array_short;
signal MemtoReg_tmp, RegWrite_tmp: tmp_array_logic;
begin
process (Clk)
begin
if (reset = '1') then
data_mem_tmp(1) <= (others => '0');
register_address_tmp(1) <= (others => '0');
ALU_ressult_tmp(1) <= (others => '0');
MemtoReg_tmp(1) <= '0';
RegWrite_tmp(1) <= '0';
elsif (rising_edge(clk)) then
data_mem_tmp(0) <= data_mem_tmp(1);
register_address_tmp(0) <= register_address_tmp(1);
ALU_ressult_tmp(0) <= ALU_ressult_tmp(1);
MemtoReg_tmp(0) <= MemtoReg_tmp(1);
RegWrite_tmp(0) <= RegWrite_tmp(1);
data_mem_tmp(1) <= data_mem_i;
register_address_tmp(1) <= register_address_i;
ALU_ressult_tmp(1) <= ALU_ressult_i;
MemtoReg_tmp(1) <= MemtoReg_i;
RegWrite_tmp(1) <= RegWrite_i;
end if;
end process;
data_mem_o <= data_mem_tmp(0);
register_address_o <= register_address_tmp(0);
ALU_ressult_o <= ALU_ressult_tmp(0);
MemtoReg_o <= MemtoReg_tmp(0);
RegWrite_o <= RegWrite_tmp(0);
end EXMEM_register_a; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task2_TB\Task2_tb2.vhd
-- Generated : 10/18/14 16:01:26
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task2.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task2_ent_tb2 is
end entity Task2_ent_tb2;
architecture Task2_arch_tb2 of Task2_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task2 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task2;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task2
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 10
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task2_arch_tb2;
configuration Task2_cfg_tb2 of Task2_ent_tb2 is
for Task2_arch_tb2
for UUT : Task2 use entity work.Task2(Beh);
end for;
end for;
end Task2_cfg_tb2;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0));
end entity FIFO;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0));
end entity FIFO;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_3.c
-- reg6 = * function
-- reg7 = thread
-- reg8 = * attr
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread, data->attr, data->function, (void *) data );
when STATE_3 =>
reg8_next <= intrfc2thrd_value;
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg8;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- data->attr->detached = Htrue;
when STATE_8 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg8;
thrd2intrfc_value <= x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
-- hthread_join( data->thread, NULL );
when STATE_9 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
when STATE_13 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:55:51 11/24/2015
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Top is
Port ( Xin : in STD_LOGIC_VECTOR (15 downto 0);
Xout : out STD_LOGIC_VECTOR (8 downto 0);
Clk : in STD_LOGIC;
Rdy : out STD_LOGIC);
end Top;
architecture Behavioral of Top is
component Operation
begin
end component;
begin
end Behavioral;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_asap_entity;
ARCHITECTURE ewf_asap_description OF ewf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register3 := register3 * 12;
output1 <= register6 + register4;
register2 := register2 * 15;
WHEN "00001001" =>
register3 := register1 + register3;
register2 := register2 + 17;
WHEN "00001010" =>
register1 := register1 + register3;
register4 := register5 + register3;
register5 := register6 + register2;
register6 := register2 + 19;
WHEN "00001011" =>
register1 := register1 * 21;
register4 := register4 + 23;
register5 := register5 + 25;
register6 := register6 * 27;
WHEN "00001100" =>
register1 := register1 + 29;
register7 := register4 * 31;
register8 := register5 * 33;
output2 <= register2 + register6;
WHEN "00001101" =>
output3 <= register3 + register1;
register1 := register7 + 37;
register2 := register8 + 39;
WHEN "00001110" =>
output4 <= register4 + register1;
output5 <= register5 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_asap_description; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF is port (
D, Clock: in STD_LOGIC;
Q: out STD_LOGIC);
end DFF;
architecture Behavior of DFF is
begin
process(Clock)
begin
if (Clock'Event and Clock = '1') then
Q <= D;
end if;
end process;
end Behavior; |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Shift/Adjust Module --
----------------------------------------------------------
entity shift_adjust is
generic
(
exp_bits : integer := 8;
man_bits : integer := 23
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
READY : in std_logic;
FILL : in std_logic;
EXP_DIFF : in std_logic_vector(exp_bits-1 downto 0);
F_IN : in std_logic_vector(man_bits+1 downto 0);
--outputs
F_OUT : out std_logic_vector(man_bits+1 downto 0);
DONE : out std_logic
);
end shift_adjust;
architecture shift_adjust_arch of shift_adjust is
--SIGNALS
signal man_in : std_logic_vector(man_bits+1 downto 0);
signal man_out : std_logic_vector(man_bits+1 downto 0);
begin
man_in <= ((not F_IN) + '1') when (fill = '1') else F_IN;
pars : parameterized_shifter
generic map
(
bits => man_bits+2,
shift_bits => exp_bits,
direction => '0'
)
port map
(
I => man_in,
S => exp_diff,
FILL => fill,
O => man_out
);
--SYNCHRONOUS
main: process (CLK,RESET,STALL) is
begin
if (RESET = '1') then
DONE <= '0';
F_OUT <= (others=>'0');
elsif(rising_edge(CLK) and STALL = '0') then
DONE <= READY;
F_OUT <= man_out;
end if;--CLK
end process main;--main
end shift_adjust_arch; --end of architecture
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
--USE PoC.vectors.ALL;
--USE PoC.strings.ALL;
--USE PoC.sata.ALL;
PACKAGE DMATest IS
-- declare attributes
ATTRIBUTE ENUM_ENCODING : STRING;
-- to_slv
-- ================================================================
END;
PACKAGE BODY DMATest IS
END PACKAGE BODY;
|
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity rom is
generic (
DATA_WIDTH : natural := 64;
ADDR_WIDTH : natural := 2
);
port (
CLK : in std_logic;
ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
EN : in std_logic;
DO : out std_logic_vector(DATA_WIDTH-1 downto 0);
VAL : out std_logic
);
end entity rom;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture behavioral of rom is
type mem is array (2**ADDR_WIDTH - 1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
constant my_Rom : mem := (
0 => x"7640_5a81_30fb_0000",
1 => x"30fb_5a81_7640_7fff",
2 => x"89C0_A57F_CF05_0000",
3 => x"CF05_A57F_89C0_8001"
);
--FMC230
--0000
--30fb
--5a81
--7640
--7fff
--7640
--5a81
--30fb
--0000
--CF05
--A57F
--89C0
--8001
--89C0
--A57F
--CF05
--***********************************************************************************
begin
--***********************************************************************************
process (CLK)
begin
if rising_edge(clk) then
VAL <= '0';
if EN = '1' then
DO <= my_Rom(conv_integer(ADDR)) ;
VAL <= '1';
end if;
end if;
end process;
--***********************************************************************************
end architecture behavioral;
--***********************************************************************************
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_rnd;
architecture behaviour of dk15_rnd is
constant state1: std_logic_vector(1 downto 0) := "01";
constant state2: std_logic_vector(1 downto 0) := "10";
constant state3: std_logic_vector(1 downto 0) := "11";
constant state4: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when state1 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state2 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state3; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state3 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "10100";
elsif std_match(input, "101") then next_state <= state2; output <= "01000";
elsif std_match(input, "110") then next_state <= state4; output <= "01010";
end if;
when state4 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "10000";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tc:6.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tc_v6_1;
USE v_tc_v6_1.v_tc;
ENTITY tutorial_v_tc_0_0 IS
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_v_tc_0_0;
ARCHITECTURE tutorial_v_tc_0_0_arch OF tutorial_v_tc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tc IS
GENERIC (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_INTERLACED : INTEGER;
C_GEN_HACTIVE_SIZE : INTEGER;
C_GEN_VACTIVE_SIZE : INTEGER;
C_GEN_CPARITY : INTEGER;
C_GEN_FIELDID_POLARITY : INTEGER;
C_GEN_VBLANK_POLARITY : INTEGER;
C_GEN_HBLANK_POLARITY : INTEGER;
C_GEN_VSYNC_POLARITY : INTEGER;
C_GEN_HSYNC_POLARITY : INTEGER;
C_GEN_AVIDEO_POLARITY : INTEGER;
C_GEN_ACHROMA_POLARITY : INTEGER;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_HFRAME_SIZE : INTEGER;
C_GEN_F0_VFRAME_SIZE : INTEGER;
C_GEN_F1_VFRAME_SIZE : INTEGER;
C_GEN_HSYNC_START : INTEGER;
C_GEN_HSYNC_END : INTEGER;
C_GEN_F0_VBLANK_HSTART : INTEGER;
C_GEN_F0_VBLANK_HEND : INTEGER;
C_GEN_F0_VSYNC_VSTART : INTEGER;
C_GEN_F0_VSYNC_VEND : INTEGER;
C_GEN_F0_VSYNC_HSTART : INTEGER;
C_GEN_F0_VSYNC_HEND : INTEGER;
C_GEN_F1_VBLANK_HSTART : INTEGER;
C_GEN_F1_VBLANK_HEND : INTEGER;
C_GEN_F1_VSYNC_VSTART : INTEGER;
C_GEN_F1_VSYNC_VEND : INTEGER;
C_GEN_F1_VSYNC_HSTART : INTEGER;
C_GEN_F1_VSYNC_HEND : INTEGER;
C_FSYNC_HSTART0 : INTEGER;
C_FSYNC_VSTART0 : INTEGER;
C_FSYNC_HSTART1 : INTEGER;
C_FSYNC_VSTART1 : INTEGER;
C_FSYNC_HSTART2 : INTEGER;
C_FSYNC_VSTART2 : INTEGER;
C_FSYNC_HSTART3 : INTEGER;
C_FSYNC_VSTART3 : INTEGER;
C_FSYNC_HSTART4 : INTEGER;
C_FSYNC_VSTART4 : INTEGER;
C_FSYNC_HSTART5 : INTEGER;
C_FSYNC_VSTART5 : INTEGER;
C_FSYNC_HSTART6 : INTEGER;
C_FSYNC_VSTART6 : INTEGER;
C_FSYNC_HSTART7 : INTEGER;
C_FSYNC_VSTART7 : INTEGER;
C_FSYNC_HSTART8 : INTEGER;
C_FSYNC_VSTART8 : INTEGER;
C_FSYNC_HSTART9 : INTEGER;
C_FSYNC_VSTART9 : INTEGER;
C_FSYNC_HSTART10 : INTEGER;
C_FSYNC_VSTART10 : INTEGER;
C_FSYNC_HSTART11 : INTEGER;
C_FSYNC_VSTART11 : INTEGER;
C_FSYNC_HSTART12 : INTEGER;
C_FSYNC_VSTART12 : INTEGER;
C_FSYNC_HSTART13 : INTEGER;
C_FSYNC_VSTART13 : INTEGER;
C_FSYNC_HSTART14 : INTEGER;
C_FSYNC_VSTART14 : INTEGER;
C_FSYNC_HSTART15 : INTEGER;
C_FSYNC_VSTART15 : INTEGER;
C_MAX_PIXELS : INTEGER;
C_MAX_LINES : INTEGER;
C_NUM_FSYNCS : INTEGER;
C_INTERLACE_EN : INTEGER;
C_GEN_AUTO_SWITCH : INTEGER;
C_DETECT_EN : INTEGER;
C_SYNC_EN : INTEGER;
C_GENERATE_EN : INTEGER;
C_DET_HSYNC_EN : INTEGER;
C_DET_VSYNC_EN : INTEGER;
C_DET_HBLANK_EN : INTEGER;
C_DET_VBLANK_EN : INTEGER;
C_DET_AVIDEO_EN : INTEGER;
C_DET_ACHROMA_EN : INTEGER;
C_GEN_HSYNC_EN : INTEGER;
C_GEN_VSYNC_EN : INTEGER;
C_GEN_HBLANK_EN : INTEGER;
C_GEN_VBLANK_EN : INTEGER;
C_GEN_AVIDEO_EN : INTEGER;
C_GEN_ACHROMA_EN : INTEGER;
C_GEN_FIELDID_EN : INTEGER;
C_DET_FIELDID_EN : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
det_clken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
field_id_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC;
active_chroma_in : IN STD_LOGIC;
field_id_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
active_chroma_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT v_tc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "v_tc,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_tc_0_0_arch : ARCHITECTURE IS "tutorial_v_tc_0_0,v_tc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "tutorial_v_tc_0_0,v_tc,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_tc,x_ipVersion=6.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_HAS_AXI4_LITE=1,C_HAS_INTC_IF=0,C_GEN_INTERLACED=0,C_GEN_HACTIVE_SIZE=1920,C_GEN_VACTIVE_SIZE=1080,C_GEN_CPARITY=0,C_GEN_FIELDID_POLARITY=1,C_GEN_VBLANK_POLARITY=1,C_GEN_HBLANK_POLARITY=1,C_GEN_VSYNC_POLARITY=1,C_GEN_HSYNC_POLARITY=1,C_GEN_AVIDEO_POLARITY=1,C_GEN_ACHROMA_POLARITY=1,C_GEN_VIDEO_FORMAT=2,C_GEN_HFRAME_SIZE=2200,C_GEN_F0_VFRAME_SIZE=1125,C_GEN_F1_VFRAME_SIZE=1125,C_GEN_HSYNC_START=2008,C_GEN_HSYNC_END=2052,C_GEN_F0_VBLANK_HSTART=1920,C_GEN_F0_VBLANK_HEND=1920,C_GEN_F0_VSYNC_VSTART=1083,C_GEN_F0_VSYNC_VEND=1088,C_GEN_F0_VSYNC_HSTART=1920,C_GEN_F0_VSYNC_HEND=1920,C_GEN_F1_VBLANK_HSTART=1920,C_GEN_F1_VBLANK_HEND=1920,C_GEN_F1_VSYNC_VSTART=1083,C_GEN_F1_VSYNC_VEND=1088,C_GEN_F1_VSYNC_HSTART=1920,C_GEN_F1_VSYNC_HEND=1920,C_FSYNC_HSTART0=0,C_FSYNC_VSTART0=0,C_FSYNC_HSTART1=0,C_FSYNC_VSTART1=0,C_FSYNC_HSTART2=0,C_FSYNC_VSTART2=0,C_FSYNC_HSTART3=0,C_FSYNC_VSTART3=0,C_FSYNC_HSTART4=0,C_FSYNC_VSTART4=0,C_FSYNC_HSTART5=0,C_FSYNC_VSTART5=0,C_FSYNC_HSTART6=0,C_FSYNC_VSTART6=0,C_FSYNC_HSTART7=0,C_FSYNC_VSTART7=0,C_FSYNC_HSTART8=0,C_FSYNC_VSTART8=0,C_FSYNC_HSTART9=0,C_FSYNC_VSTART9=0,C_FSYNC_HSTART10=0,C_FSYNC_VSTART10=0,C_FSYNC_HSTART11=0,C_FSYNC_VSTART11=0,C_FSYNC_HSTART12=0,C_FSYNC_VSTART12=0,C_FSYNC_HSTART13=0,C_FSYNC_VSTART13=0,C_FSYNC_HSTART14=0,C_FSYNC_VSTART14=0,C_FSYNC_HSTART15=0,C_FSYNC_VSTART15=0,C_MAX_PIXELS=4096,C_MAX_LINES=4096,C_NUM_FSYNCS=1,C_INTERLACE_EN=0,C_GEN_AUTO_SWITCH=0,C_DETECT_EN=0,C_SYNC_EN=0,C_GENERATE_EN=1,C_DET_HSYNC_EN=1,C_DET_VSYNC_EN=1,C_DET_HBLANK_EN=1,C_DET_VBLANK_EN=1,C_DET_AVIDEO_EN=1,C_DET_ACHROMA_EN=0,C_GEN_HSYNC_EN=1,C_GEN_VSYNC_EN=1,C_GEN_HBLANK_EN=1,C_GEN_VBLANK_EN=1,C_GEN_AVIDEO_EN=1,C_GEN_ACHROMA_EN=0,C_GEN_FIELDID_EN=0,C_DET_FIELDID_EN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF hsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF hblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK";
ATTRIBUTE X_INTERFACE_INFO OF vsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK";
ATTRIBUTE X_INTERFACE_INFO OF active_video_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT";
BEGIN
U0 : v_tc
GENERIC MAP (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_INTERLACED => 0,
C_GEN_HACTIVE_SIZE => 1920,
C_GEN_VACTIVE_SIZE => 1080,
C_GEN_CPARITY => 0,
C_GEN_FIELDID_POLARITY => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VIDEO_FORMAT => 2,
C_GEN_HFRAME_SIZE => 2200,
C_GEN_F0_VFRAME_SIZE => 1125,
C_GEN_F1_VFRAME_SIZE => 1125,
C_GEN_HSYNC_START => 2008,
C_GEN_HSYNC_END => 2052,
C_GEN_F0_VBLANK_HSTART => 1920,
C_GEN_F0_VBLANK_HEND => 1920,
C_GEN_F0_VSYNC_VSTART => 1083,
C_GEN_F0_VSYNC_VEND => 1088,
C_GEN_F0_VSYNC_HSTART => 1920,
C_GEN_F0_VSYNC_HEND => 1920,
C_GEN_F1_VBLANK_HSTART => 1920,
C_GEN_F1_VBLANK_HEND => 1920,
C_GEN_F1_VSYNC_VSTART => 1083,
C_GEN_F1_VSYNC_VEND => 1088,
C_GEN_F1_VSYNC_HSTART => 1920,
C_GEN_F1_VSYNC_HEND => 1920,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_INTERLACE_EN => 0,
C_GEN_AUTO_SWITCH => 0,
C_DETECT_EN => 0,
C_SYNC_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_FIELDID_EN => 0,
C_DET_FIELDID_EN => 0
)
PORT MAP (
clk => clk,
clken => clken,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
det_clken => '1',
gen_clken => gen_clken,
field_id_in => '0',
hsync_in => '0',
hblank_in => '0',
vsync_in => '0',
vblank_in => '0',
active_video_in => '0',
active_chroma_in => '0',
hsync_out => hsync_out,
hblank_out => hblank_out,
vsync_out => vsync_out,
vblank_out => vblank_out,
active_video_out => active_video_out,
resetn => resetn,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
fsync_in => fsync_in,
fsync_out => fsync_out
);
END tutorial_v_tc_0_0_arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:26 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_sw_0/system_axi_gpio_sw_0_stub.vhdl
-- Design : system_axi_gpio_sw_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_gpio_sw_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_axi_gpio_sw_0;
architecture stub of system_axi_gpio_sw_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[3:0],gpio2_io_i[3:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4";
begin
end;
|
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F8MKfI
-- /___/ /\ Timestamp : 04/05/2014 20:58:17
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity IntermediateRegsConv is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputData : out T_INPUT_HORIZONTAL_CONVOLUTION
);
end IntermediateRegsConv;
architecture BEHAVIORAL of IntermediateRegsConv is
--type T_SCALE_VALUES_FIFO is array std_logic_vector(NUMBER_OF_SCALES-1 downto 0) of std_logic_vector(OUT_VERT_CONV_BW-1 downto 0);
signal intermediate_registers: T_INPUT_HORIZONTAL_CONVOLUTION := (others =>(others => '0'));
signal counter: integer range 0 to KERNEL_SIZE-1 := 0;
begin
proceso1: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
intermediate_registers <= (others => (others => '0'));
counter <= 0;
enableOut <= '0';
elsif enableIn = '1' then
intermediate_registers(0) <= inputValue;
loop1: for i in 1 to KERNEL_SIZE-1 loop
intermediate_registers(i) <= intermediate_registers(i-1);
end loop loop1;
if counter = KERNEL_SIZE-1 then
counter <= 0;
enableOut <= '1';
else
counter <= counter + 1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;--end if rising_edge(clk)
end process proceso1;
outputData <= intermediate_registers;
end BEHAVIORAL;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_hot;
architecture behaviour of s27_hot is
constant s000: std_logic_vector(5 downto 0) := "100000";
constant s001: std_logic_vector(5 downto 0) := "010000";
constant s101: std_logic_vector(5 downto 0) := "001000";
constant s100: std_logic_vector(5 downto 0) := "000100";
constant s010: std_logic_vector(5 downto 0) := "000010";
constant s011: std_logic_vector(5 downto 0) := "000001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "------"; output <= "-";
end case;
end process;
end behaviour;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1195.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01195ent IS
END c08s01b00x00p05n01i01195ent;
ARCHITECTURE c08s01b00x00p05n01i01195arch OF c08s01b00x00p05n01i01195ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k until (k = 5) rof 60 ns;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01195 - Reserved word 'for' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01195arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1195.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01195ent IS
END c08s01b00x00p05n01i01195ent;
ARCHITECTURE c08s01b00x00p05n01i01195arch OF c08s01b00x00p05n01i01195ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k until (k = 5) rof 60 ns;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01195 - Reserved word 'for' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01195arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1195.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01195ent IS
END c08s01b00x00p05n01i01195ent;
ARCHITECTURE c08s01b00x00p05n01i01195arch OF c08s01b00x00p05n01i01195ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k until (k = 5) rof 60 ns;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01195 - Reserved word 'for' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01195arch;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY programCounter IS
PORT (
programCounterIn : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
programCounterOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END programCounter;
ARCHITECTURE Behavioral OF programCounter IS
BEGIN
programCounterOut <= programCounterIn;
-- programCounterOut <= x"00400000" OR std_logic_vector(to_unsigned(progamCounterIn * 4, 32));
END Behavioral; |
---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: i2s_in
--
-- Description:
--
-- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF
-- Decoded data) and a parallel device (microcontroller, IP block).
--
-- It's coded as a generic VHDL entity, so developer can choose the proper signal
-- width (8/16/24/32 bit)
--
-- Input takes:
-- -I2S Data
-- -I2S Bit Clock
-- -I2S LR Clock (Left/Right channel indication)
--
-- Output provides:
-- -DATA_L / DATA_R parallel inputs
-- -DATA_RDY_L / DATA_RDY_R output ready signals.
--
--
-- The data from the parallel inputs is shifted to the I2S data output
--
--------------------------------------------------------------------------------
-- I2S Waveform summary
--
-- BIT_CK __ __ __ __ __ __ __ __ __
-- | 1|__| 2|_| 3|__| 4|__| 5|__... ... |32|__| 1|__| 2|__| 3| ...
--
-- LR_CK ... ... ___________________
-- ____________L_Channel_Data______________| R Channel Data ...
--
-- DATA x< 00 ><D24><D22><D21><D20> ... ... < 00 ><D24><D23> ...
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity i2s_in is
-- width: How many bits (from MSB) are gathered from the serial I2S input
generic(width : integer := 24);
port(
-- I2S ports
LR_CLK : in std_logic; --Left/Right indicator clock
BIT_CLK : in std_logic; --Bit clock
DIN : in std_logic; --Data Input
-- Control ports
RESET : in std_logic; --Asynchronous Reset (Active Low)
-- Parallel ports
DATA_L : out std_logic_vector(width-1 downto 0);
DATA_R : out std_logic_vector(width-1 downto 0);
-- Output status ports
DATA_RDY_L : out std_logic; --Falling edge means data is ready
DATA_RDY_R : out std_logic --Falling edge means data is ready
);
end i2s_in;
architecture rtl of i2s_in is
--signals
signal shift_reg : std_logic_vector(width-1 downto 0);
signal s_parallel_load : std_logic;
signal s_current_lr : std_logic;
begin
-- serial to parallel interface
i2s_in: process(RESET, BIT_CLK, LR_CLK, DIN)
begin
if(RESET = '0') then
DATA_L <= (others => '0');
DATA_R <= (others => '0');
shift_reg <= (others => '0');
s_current_lr <= '0';
s_parallel_load <= '0';
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
elsif(BIT_CLK'event and BIT_CLK = '1') then
if(s_current_lr = LR_CLK) then
-- Push data into the shift register
shift_reg(width-1 downto 1) <= shift_reg(width-2 downto 0);
shift_reg(0) <= DIN;
if (s_parallel_load = '1') then
if(s_current_lr = '0') then
--Output Right Channel
DATA_R <= shift_reg;
else
--Output Left Channel
DATA_L <= shift_reg;
end if;
s_parallel_load <= '0';
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
end if;
else
-- Push data into the shift register
shift_reg(width-1 downto 1) <= shift_reg(width-2 downto 0);
shift_reg(0) <= DIN;
-- setup for parallel register load
s_parallel_load <= '1';
if (s_current_lr = '1') then
DATA_RDY_R <= '1';
else
DATA_RDY_L <= '1';
end if;
s_current_lr <= LR_CLK;
end if;
end if; -- reset / rising_edge
end process i2s_in;
end rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router;
architecture behavior of router is
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_CTS_in,
err_write_en,
err_not_CTS_in,
err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_East_Req_E,
err_West_Req_W,
err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
err_North_Req_E,
err_East_Req_W,
err_West_Req_S,
err_South_Req_L,
err_IDLE_Req_E,
err_Local_Req_E,
err_North_Req_W,
err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
err_IDLE_Req_W,
err_Local_Req_W,
err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
err_South_Req_E,
err_IDLE_Req_S,
err_Local_Req_S,
err_North_Req_L,
err_East_Req_N,
err_West_Req_E,
err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel,
err_state_local_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
-- North
signal N_err_header_not_empty_Requests_in_onehot,
N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in : std_logic;
-- East
signal E_err_header_not_empty_Requests_in_onehot,
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in : std_logic;
-- West
signal W_err_header_not_empty_Requests_in_onehot,
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in : std_logic;
-- South
signal S_err_header_not_empty_Requests_in_onehot,
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in : std_logic;
-- Local
signal L_err_header_not_empty_Requests_in_onehot,
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
-- North
signal N_err_state_IDLE_xbar,
N_err_state_not_IDLE_xbar,
N_err_state_IDLE_RTS_FF_in,
N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
N_err_RTS_FF_not_DCTS_state_state_in,
N_err_not_RTS_FF_state_in_next_state,
N_err_RTS_FF_DCTS_state_in_next_state,
N_err_not_DCTS_Grants,
N_err_DCTS_not_RTS_FF_Grants,
N_err_DCTS_RTS_FF_IDLE_Grants,
N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
N_err_Requests_next_state_IDLE,
N_err_IDLE_Req_L,
N_err_Local_Req_L,
N_err_North_Req_N,
N_err_East_Req_E,
N_err_West_Req_W,
N_err_South_Req_S,
N_err_IDLE_Req_N,
N_err_Local_Req_N,
N_err_North_Req_E,
N_err_East_Req_W,
N_err_West_Req_S,
N_err_South_Req_L,
N_err_IDLE_Req_E,
N_err_Local_Req_E,
N_err_North_Req_W,
N_err_East_Req_S,
N_err_West_Req_L,
N_err_South_Req_N,
N_err_IDLE_Req_W,
N_err_Local_Req_W,
N_err_North_Req_S,
N_err_East_Req_L,
N_err_West_Req_N,
N_err_South_Req_E,
N_err_IDLE_Req_S,
N_err_Local_Req_S,
N_err_North_Req_L,
N_err_East_Req_N,
N_err_West_Req_E,
N_err_South_Req_W,
N_err_next_state_onehot,
N_err_state_in_onehot,
N_err_DCTS_RTS_FF_state_Grant_L,
N_err_DCTS_RTS_FF_state_Grant_N,
N_err_DCTS_RTS_FF_state_Grant_E,
N_err_DCTS_RTS_FF_state_Grant_W,
N_err_DCTS_RTS_FF_state_Grant_S,
N_err_state_north_xbar_sel,
N_err_state_east_xbar_sel,
N_err_state_west_xbar_sel,
N_err_state_south_xbar_sel,
N_err_state_local_xbar_sel: std_logic;
-- East
signal E_err_state_IDLE_xbar,
E_err_state_not_IDLE_xbar,
E_err_state_IDLE_RTS_FF_in,
E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
E_err_RTS_FF_not_DCTS_state_state_in,
E_err_not_RTS_FF_state_in_next_state,
E_err_RTS_FF_DCTS_state_in_next_state,
E_err_not_DCTS_Grants,
E_err_DCTS_not_RTS_FF_Grants,
E_err_DCTS_RTS_FF_IDLE_Grants,
E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
E_err_Requests_next_state_IDLE,
E_err_IDLE_Req_L,
E_err_Local_Req_L,
E_err_North_Req_N,
E_err_East_Req_E,
E_err_West_Req_W,
E_err_South_Req_S,
E_err_IDLE_Req_N,
E_err_Local_Req_N,
E_err_North_Req_E,
E_err_East_Req_W,
E_err_West_Req_S,
E_err_South_Req_L,
E_err_IDLE_Req_E,
E_err_Local_Req_E,
E_err_North_Req_W,
E_err_East_Req_S,
E_err_West_Req_L,
E_err_South_Req_N,
E_err_IDLE_Req_W,
E_err_Local_Req_W,
E_err_North_Req_S,
E_err_East_Req_L,
E_err_West_Req_N,
E_err_South_Req_E,
E_err_IDLE_Req_S,
E_err_Local_Req_S,
E_err_North_Req_L,
E_err_East_Req_N,
E_err_West_Req_E,
E_err_South_Req_W,
E_err_next_state_onehot,
E_err_state_in_onehot,
E_err_DCTS_RTS_FF_state_Grant_L,
E_err_DCTS_RTS_FF_state_Grant_N,
E_err_DCTS_RTS_FF_state_Grant_E,
E_err_DCTS_RTS_FF_state_Grant_W,
E_err_DCTS_RTS_FF_state_Grant_S,
E_err_state_north_xbar_sel,
E_err_state_east_xbar_sel,
E_err_state_west_xbar_sel,
E_err_state_south_xbar_sel,
E_err_state_local_xbar_sel: std_logic;
-- West
signal W_err_state_IDLE_xbar,
W_err_state_not_IDLE_xbar,
W_err_state_IDLE_RTS_FF_in,
W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
W_err_RTS_FF_not_DCTS_state_state_in,
W_err_not_RTS_FF_state_in_next_state,
W_err_RTS_FF_DCTS_state_in_next_state,
W_err_not_DCTS_Grants,
W_err_DCTS_not_RTS_FF_Grants,
W_err_DCTS_RTS_FF_IDLE_Grants,
W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
W_err_Requests_next_state_IDLE,
W_err_IDLE_Req_L,
W_err_Local_Req_L,
W_err_North_Req_N,
W_err_East_Req_E,
W_err_West_Req_W,
W_err_South_Req_S,
W_err_IDLE_Req_N,
W_err_Local_Req_N,
W_err_North_Req_E,
W_err_East_Req_W,
W_err_West_Req_S,
W_err_South_Req_L,
W_err_IDLE_Req_E,
W_err_Local_Req_E,
W_err_North_Req_W,
W_err_East_Req_S,
W_err_West_Req_L,
W_err_South_Req_N,
W_err_IDLE_Req_W,
W_err_Local_Req_W,
W_err_North_Req_S,
W_err_East_Req_L,
W_err_West_Req_N,
W_err_South_Req_E,
W_err_IDLE_Req_S,
W_err_Local_Req_S,
W_err_North_Req_L,
W_err_East_Req_N,
W_err_West_Req_E,
W_err_South_Req_W,
W_err_next_state_onehot,
W_err_state_in_onehot,
W_err_DCTS_RTS_FF_state_Grant_L,
W_err_DCTS_RTS_FF_state_Grant_N,
W_err_DCTS_RTS_FF_state_Grant_E,
W_err_DCTS_RTS_FF_state_Grant_W,
W_err_DCTS_RTS_FF_state_Grant_S,
W_err_state_north_xbar_sel,
W_err_state_east_xbar_sel,
W_err_state_west_xbar_sel,
W_err_state_south_xbar_sel,
W_err_state_local_xbar_sel: std_logic;
-- South
signal S_err_state_IDLE_xbar,
S_err_state_not_IDLE_xbar,
S_err_state_IDLE_RTS_FF_in,
S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
S_err_RTS_FF_not_DCTS_state_state_in,
S_err_not_RTS_FF_state_in_next_state,
S_err_RTS_FF_DCTS_state_in_next_state,
S_err_not_DCTS_Grants,
S_err_DCTS_not_RTS_FF_Grants,
S_err_DCTS_RTS_FF_IDLE_Grants,
S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
S_err_Requests_next_state_IDLE,
S_err_IDLE_Req_L,
S_err_Local_Req_L,
S_err_North_Req_N,
S_err_East_Req_E,
S_err_West_Req_W,
S_err_South_Req_S,
S_err_IDLE_Req_N,
S_err_Local_Req_N,
S_err_North_Req_E,
S_err_East_Req_W,
S_err_West_Req_S,
S_err_South_Req_L,
S_err_IDLE_Req_E,
S_err_Local_Req_E,
S_err_North_Req_W,
S_err_East_Req_S,
S_err_West_Req_L,
S_err_South_Req_N,
S_err_IDLE_Req_W,
S_err_Local_Req_W,
S_err_North_Req_S,
S_err_East_Req_L,
S_err_West_Req_N,
S_err_South_Req_E,
S_err_IDLE_Req_S,
S_err_Local_Req_S,
S_err_North_Req_L,
S_err_East_Req_N,
S_err_West_Req_E,
S_err_South_Req_W,
S_err_next_state_onehot,
S_err_state_in_onehot,
S_err_DCTS_RTS_FF_state_Grant_L,
S_err_DCTS_RTS_FF_state_Grant_N,
S_err_DCTS_RTS_FF_state_Grant_E,
S_err_DCTS_RTS_FF_state_Grant_W,
S_err_DCTS_RTS_FF_state_Grant_S,
S_err_state_north_xbar_sel,
S_err_state_east_xbar_sel,
S_err_state_west_xbar_sel,
S_err_state_south_xbar_sel,
S_err_state_local_xbar_sel: std_logic;
-- Local
signal L_err_state_IDLE_xbar,
L_err_state_not_IDLE_xbar,
L_err_state_IDLE_RTS_FF_in,
L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
L_err_RTS_FF_not_DCTS_state_state_in,
L_err_not_RTS_FF_state_in_next_state,
L_err_RTS_FF_DCTS_state_in_next_state,
L_err_not_DCTS_Grants,
L_err_DCTS_not_RTS_FF_Grants,
L_err_DCTS_RTS_FF_IDLE_Grants,
L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
L_err_Requests_next_state_IDLE,
L_err_IDLE_Req_L,
L_err_Local_Req_L,
L_err_North_Req_N,
L_err_East_Req_E,
L_err_West_Req_W,
L_err_South_Req_S,
L_err_IDLE_Req_N,
L_err_Local_Req_N,
L_err_North_Req_E,
L_err_East_Req_W,
L_err_West_Req_S,
L_err_South_Req_L,
L_err_IDLE_Req_E,
L_err_Local_Req_E,
L_err_North_Req_W,
L_err_East_Req_S,
L_err_West_Req_L,
L_err_South_Req_N,
L_err_IDLE_Req_W,
L_err_Local_Req_W,
L_err_North_Req_S,
L_err_East_Req_L,
L_err_West_Req_N,
L_err_South_Req_E,
L_err_IDLE_Req_S,
L_err_Local_Req_S,
L_err_North_Req_L,
L_err_East_Req_N,
L_err_West_Req_E,
L_err_South_Req_W,
L_err_next_state_onehot,
L_err_state_in_onehot,
L_err_DCTS_RTS_FF_state_Grant_L,
L_err_DCTS_RTS_FF_state_Grant_N,
L_err_DCTS_RTS_FF_state_Grant_E,
L_err_DCTS_RTS_FF_state_Grant_W,
L_err_DCTS_RTS_FF_state_Grant_S,
L_err_state_north_xbar_sel,
L_err_state_east_xbar_sel,
L_err_state_west_xbar_sel,
L_err_state_south_xbar_sel,
L_err_state_local_xbar_sel: std_logic;
-- FIFO Control Part Checkers signals
-- North
signal N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_CTS_in,
N_err_write_en,
N_err_not_CTS_in,
N_err_not_write_en,
N_err_read_en_mismatch : std_logic;
-- East
signal E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_CTS_in,
E_err_write_en,
E_err_not_CTS_in,
E_err_not_write_en,
E_err_read_en_mismatch : std_logic;
-- West
signal W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_CTS_in,
W_err_write_en,
W_err_not_CTS_in,
W_err_not_write_en,
W_err_read_en_mismatch : std_logic;
-- South
signal S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_CTS_in,
S_err_write_en,
S_err_not_CTS_in,
S_err_not_write_en,
S_err_read_en_mismatch : std_logic;
-- Local
signal L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_CTS_in,
L_err_write_en,
L_err_not_CTS_in,
L_err_not_write_en,
L_err_read_en_mismatch : std_logic;
-- Fault localization related signals
signal N_E_turn, N_W_turn, S_E_turn, S_W_turn, E_N_turn, E_S_turn, W_N_turn, W_S_turn : std_logic;
signal N_S_path, S_N_path, E_W_path, W_E_path : std_logic;
signal N_FIFO_handshaking_error, E_FIFO_handshaking_error, W_FIFO_handshaking_error, S_FIFO_handshaking_error, L_FIFO_handshaking_error : std_logic;
signal N_Arbiter_handshaking_error, E_Arbiter_handshaking_error, W_Arbiter_handshaking_error, S_Arbiter_handshaking_error, L_Arbiter_handshaking_error : std_logic;
begin
--
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N,
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_CTS_in => N_err_CTS_in,
err_write_en => N_err_write_en,
err_not_CTS_in => N_err_not_CTS_in,
err_not_write_en => N_err_not_write_en,
err_read_en_mismatch => N_err_read_en_mismatch
);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E,
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_CTS_in => E_err_CTS_in,
err_write_en => E_err_write_en,
err_not_CTS_in => E_err_not_CTS_in,
err_not_write_en => E_err_not_write_en,
err_read_en_mismatch => E_err_read_en_mismatch
);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W,
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_CTS_in => W_err_CTS_in,
err_write_en => W_err_write_en,
err_not_CTS_in => W_err_not_CTS_in,
err_not_write_en => W_err_not_write_en,
err_read_en_mismatch => W_err_read_en_mismatch
);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S,
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_CTS_in => S_err_CTS_in,
err_write_en => S_err_write_en,
err_not_CTS_in => S_err_not_CTS_in,
err_not_write_en => S_err_not_write_en,
err_read_en_mismatch => S_err_read_en_mismatch
);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L,
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_CTS_in => L_err_CTS_in,
err_write_en => L_err_write_en,
err_not_CTS_in => L_err_not_CTS_in,
err_not_write_en => L_err_not_write_en,
err_read_en_mismatch => L_err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
err_header_not_empty_Requests_in_onehot => N_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in
);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
err_header_not_empty_Requests_in_onehot => E_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in
);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
err_header_not_empty_Requests_in_onehot => W_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in
);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
err_header_not_empty_Requests_in_onehot => S_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in
);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
err_header_not_empty_Requests_in_onehot => L_err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N,
err_state_IDLE_xbar => N_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => N_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => N_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => N_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => N_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => N_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => N_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => N_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => N_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => N_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => N_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => N_err_Requests_next_state_IDLE,
err_IDLE_Req_L => N_err_IDLE_Req_L,
err_Local_Req_L => N_err_Local_Req_L,
err_North_Req_N => N_err_North_Req_N,
err_East_Req_E => N_err_East_Req_E,
err_West_Req_W => N_err_West_Req_W,
err_South_Req_S => N_err_South_Req_S,
err_IDLE_Req_N => N_err_IDLE_Req_N,
err_Local_Req_N => N_err_Local_Req_N,
err_North_Req_E => N_err_North_Req_E,
err_East_Req_W => N_err_East_Req_W,
err_West_Req_S => N_err_West_Req_S,
err_South_Req_L => N_err_South_Req_L,
err_IDLE_Req_E => N_err_IDLE_Req_E,
err_Local_Req_E => N_err_Local_Req_E,
err_North_Req_W => N_err_North_Req_W,
err_East_Req_S => N_err_East_Req_S,
err_West_Req_L => N_err_West_Req_L,
err_South_Req_N => N_err_South_Req_N,
err_IDLE_Req_W => N_err_IDLE_Req_W,
err_Local_Req_W => N_err_Local_Req_W,
err_North_Req_S => N_err_North_Req_S,
err_East_Req_L => N_err_East_Req_L,
err_West_Req_N => N_err_West_Req_N,
err_South_Req_E => N_err_South_Req_E,
err_IDLE_Req_S => N_err_IDLE_Req_S,
err_Local_Req_S => N_err_Local_Req_S,
err_North_Req_L => N_err_North_Req_L,
err_East_Req_N => N_err_East_Req_N,
err_West_Req_E => N_err_West_Req_E,
err_South_Req_W => N_err_South_Req_W,
err_next_state_onehot => N_err_next_state_onehot,
err_state_in_onehot => N_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => N_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => N_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => N_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => N_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => N_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => N_err_state_north_xbar_sel,
err_state_east_xbar_sel => N_err_state_east_xbar_sel,
err_state_west_xbar_sel => N_err_state_west_xbar_sel,
err_state_south_xbar_sel => N_err_state_south_xbar_sel,
err_state_local_xbar_sel => N_err_state_local_xbar_sel
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E,
err_state_IDLE_xbar => E_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => E_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => E_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => E_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => E_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => E_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => E_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => E_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => E_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => E_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => E_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => E_err_Requests_next_state_IDLE,
err_IDLE_Req_L => E_err_IDLE_Req_L,
err_Local_Req_L => E_err_Local_Req_L,
err_North_Req_N => E_err_North_Req_N,
err_East_Req_E => E_err_East_Req_E,
err_West_Req_W => E_err_West_Req_W,
err_South_Req_S => E_err_South_Req_S,
err_IDLE_Req_N => E_err_IDLE_Req_N,
err_Local_Req_N => E_err_Local_Req_N,
err_North_Req_E => E_err_North_Req_E,
err_East_Req_W => E_err_East_Req_W,
err_West_Req_S => E_err_West_Req_S,
err_South_Req_L => E_err_South_Req_L,
err_IDLE_Req_E => E_err_IDLE_Req_E,
err_Local_Req_E => E_err_Local_Req_E,
err_North_Req_W => E_err_North_Req_W,
err_East_Req_S => E_err_East_Req_S,
err_West_Req_L => E_err_West_Req_L,
err_South_Req_N => E_err_South_Req_N,
err_IDLE_Req_W => E_err_IDLE_Req_W,
err_Local_Req_W => E_err_Local_Req_W,
err_North_Req_S => E_err_North_Req_S,
err_East_Req_L => E_err_East_Req_L,
err_West_Req_N => E_err_West_Req_N,
err_South_Req_E => E_err_South_Req_E,
err_IDLE_Req_S => E_err_IDLE_Req_S,
err_Local_Req_S => E_err_Local_Req_S,
err_North_Req_L => E_err_North_Req_L,
err_East_Req_N => E_err_East_Req_N,
err_West_Req_E => E_err_West_Req_E,
err_South_Req_W => E_err_South_Req_W,
err_next_state_onehot => E_err_next_state_onehot,
err_state_in_onehot => E_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => E_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => E_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => E_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => E_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => E_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => E_err_state_north_xbar_sel,
err_state_east_xbar_sel => E_err_state_east_xbar_sel,
err_state_west_xbar_sel => E_err_state_west_xbar_sel,
err_state_south_xbar_sel => E_err_state_south_xbar_sel,
err_state_local_xbar_sel => E_err_state_local_xbar_sel
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W,
err_state_IDLE_xbar => W_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => W_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => W_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => W_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => W_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => W_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => W_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => W_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => W_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => W_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => W_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => W_err_Requests_next_state_IDLE,
err_IDLE_Req_L => W_err_IDLE_Req_L,
err_Local_Req_L => W_err_Local_Req_L,
err_North_Req_N => W_err_North_Req_N,
err_East_Req_E => W_err_East_Req_E,
err_West_Req_W => W_err_West_Req_W,
err_South_Req_S => W_err_South_Req_S,
err_IDLE_Req_N => W_err_IDLE_Req_N,
err_Local_Req_N => W_err_Local_Req_N,
err_North_Req_E => W_err_North_Req_E,
err_East_Req_W => W_err_East_Req_W,
err_West_Req_S => W_err_West_Req_S,
err_South_Req_L => W_err_South_Req_L,
err_IDLE_Req_E => W_err_IDLE_Req_E,
err_Local_Req_E => W_err_Local_Req_E,
err_North_Req_W => W_err_North_Req_W,
err_East_Req_S => W_err_East_Req_S,
err_West_Req_L => W_err_West_Req_L,
err_South_Req_N => W_err_South_Req_N,
err_IDLE_Req_W => W_err_IDLE_Req_W,
err_Local_Req_W => W_err_Local_Req_W,
err_North_Req_S => W_err_North_Req_S,
err_East_Req_L => W_err_East_Req_L,
err_West_Req_N => W_err_West_Req_N,
err_South_Req_E => W_err_South_Req_E,
err_IDLE_Req_S => W_err_IDLE_Req_S,
err_Local_Req_S => W_err_Local_Req_S,
err_North_Req_L => W_err_North_Req_L,
err_East_Req_N => W_err_East_Req_N,
err_West_Req_E => W_err_West_Req_E,
err_South_Req_W => W_err_South_Req_W,
err_next_state_onehot => W_err_next_state_onehot,
err_state_in_onehot => W_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => W_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => W_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => W_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => W_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => W_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => W_err_state_north_xbar_sel,
err_state_east_xbar_sel => W_err_state_east_xbar_sel,
err_state_west_xbar_sel => W_err_state_west_xbar_sel,
err_state_south_xbar_sel => W_err_state_south_xbar_sel,
err_state_local_xbar_sel => W_err_state_local_xbar_sel
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S,
err_state_IDLE_xbar => S_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => S_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => S_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => S_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => S_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => S_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => S_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => S_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => S_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => S_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => S_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => S_err_Requests_next_state_IDLE,
err_IDLE_Req_L => S_err_IDLE_Req_L,
err_Local_Req_L => S_err_Local_Req_L,
err_North_Req_N => S_err_North_Req_N,
err_East_Req_E => S_err_East_Req_E,
err_West_Req_W => S_err_West_Req_W,
err_South_Req_S => S_err_South_Req_S,
err_IDLE_Req_N => S_err_IDLE_Req_N,
err_Local_Req_N => S_err_Local_Req_N,
err_North_Req_E => S_err_North_Req_E,
err_East_Req_W => S_err_East_Req_W,
err_West_Req_S => S_err_West_Req_S,
err_South_Req_L => S_err_South_Req_L,
err_IDLE_Req_E => S_err_IDLE_Req_E,
err_Local_Req_E => S_err_Local_Req_E,
err_North_Req_W => S_err_North_Req_W,
err_East_Req_S => S_err_East_Req_S,
err_West_Req_L => S_err_West_Req_L,
err_South_Req_N => S_err_South_Req_N,
err_IDLE_Req_W => S_err_IDLE_Req_W,
err_Local_Req_W => S_err_Local_Req_W,
err_North_Req_S => S_err_North_Req_S,
err_East_Req_L => S_err_East_Req_L,
err_West_Req_N => S_err_West_Req_N,
err_South_Req_E => S_err_South_Req_E,
err_IDLE_Req_S => S_err_IDLE_Req_S,
err_Local_Req_S => S_err_Local_Req_S,
err_North_Req_L => S_err_North_Req_L,
err_East_Req_N => S_err_East_Req_N,
err_West_Req_E => S_err_West_Req_E,
err_South_Req_W => S_err_South_Req_W,
err_next_state_onehot => S_err_next_state_onehot,
err_state_in_onehot => S_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => S_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => S_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => S_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => S_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => S_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => S_err_state_north_xbar_sel,
err_state_east_xbar_sel => S_err_state_east_xbar_sel,
err_state_west_xbar_sel => S_err_state_west_xbar_sel,
err_state_south_xbar_sel => S_err_state_south_xbar_sel,
err_state_local_xbar_sel => S_err_state_local_xbar_sel
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L,
err_state_IDLE_xbar => L_err_state_IDLE_xbar,
err_state_not_IDLE_xbar => L_err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => L_err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => L_err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => L_err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => L_err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => L_err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => L_err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => L_err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => L_err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => L_err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => L_err_Requests_next_state_IDLE,
err_IDLE_Req_L => L_err_IDLE_Req_L,
err_Local_Req_L => L_err_Local_Req_L,
err_North_Req_N => L_err_North_Req_N,
err_East_Req_E => L_err_East_Req_E,
err_West_Req_W => L_err_West_Req_W,
err_South_Req_S => L_err_South_Req_S,
err_IDLE_Req_N => L_err_IDLE_Req_N,
err_Local_Req_N => L_err_Local_Req_N,
err_North_Req_E => L_err_North_Req_E,
err_East_Req_W => L_err_East_Req_W,
err_West_Req_S => L_err_West_Req_S,
err_South_Req_L => L_err_South_Req_L,
err_IDLE_Req_E => L_err_IDLE_Req_E,
err_Local_Req_E => L_err_Local_Req_E,
err_North_Req_W => L_err_North_Req_W,
err_East_Req_S => L_err_East_Req_S,
err_West_Req_L => L_err_West_Req_L,
err_South_Req_N => L_err_South_Req_N,
err_IDLE_Req_W => L_err_IDLE_Req_W,
err_Local_Req_W => L_err_Local_Req_W,
err_North_Req_S => L_err_North_Req_S,
err_East_Req_L => L_err_East_Req_L,
err_West_Req_N => L_err_West_Req_N,
err_South_Req_E => L_err_South_Req_E,
err_IDLE_Req_S => L_err_IDLE_Req_S,
err_Local_Req_S => L_err_Local_Req_S,
err_North_Req_L => L_err_North_Req_L,
err_East_Req_N => L_err_East_Req_N,
err_West_Req_E => L_err_West_Req_E,
err_South_Req_W => L_err_South_Req_W,
err_next_state_onehot => L_err_next_state_onehot,
err_state_in_onehot => L_err_state_in_onehot,
err_DCTS_RTS_FF_state_Grant_L => L_err_DCTS_RTS_FF_state_Grant_L,
err_DCTS_RTS_FF_state_Grant_N => L_err_DCTS_RTS_FF_state_Grant_N,
err_DCTS_RTS_FF_state_Grant_E => L_err_DCTS_RTS_FF_state_Grant_E,
err_DCTS_RTS_FF_state_Grant_W => L_err_DCTS_RTS_FF_state_Grant_W,
err_DCTS_RTS_FF_state_Grant_S => L_err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel => L_err_state_north_xbar_sel,
err_state_east_xbar_sel => L_err_state_east_xbar_sel,
err_state_west_xbar_sel => L_err_state_west_xbar_sel,
err_state_south_xbar_sel => L_err_state_south_xbar_sel,
err_state_local_xbar_sel => L_err_state_local_xbar_sel
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
-- Fault localization logic construction
-- Turns
N_E_turn <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_N or
E_err_East_Req_N or
E_err_West_Req_N or
E_err_South_Req_N or
E_err_Local_Req_N or
E_err_IDLE_Req_N or
E_err_state_north_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_N );
N_W_turn <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_N or
W_err_East_Req_N or
W_err_West_Req_N or
W_err_South_Req_N or
W_err_Local_Req_N or
W_err_IDLE_Req_N or
W_err_state_north_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_N);
S_W_turn <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_S or
W_err_East_Req_S or
W_err_West_Req_S or
W_err_South_Req_S or
W_err_Local_Req_S or
W_err_IDLE_Req_S or
W_err_state_South_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_S);
S_E_turn <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_S or
E_err_East_Req_S or
E_err_West_Req_S or
E_err_South_Req_S or
E_err_Local_Req_S or
E_err_IDLE_Req_S or
E_err_state_South_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_S);
W_N_turn <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_W or
N_err_East_Req_W or
N_err_West_Req_W or
N_err_South_Req_W or
N_err_Local_Req_W or
N_err_IDLE_Req_W or
N_err_state_west_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_W);
W_S_turn <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_W or
S_err_East_Req_W or
S_err_West_Req_W or
S_err_South_Req_W or
S_err_Local_Req_W or
S_err_IDLE_Req_W or
S_err_state_west_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_W);
E_N_turn <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_E or
N_err_East_Req_E or
N_err_West_Req_E or
N_err_South_Req_E or
N_err_Local_Req_E or
N_err_IDLE_Req_E or
N_err_state_east_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_E);
E_S_turn <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_E or
S_err_East_Req_E or
S_err_West_Req_E or
S_err_South_Req_E or
S_err_Local_Req_E or
S_err_IDLE_Req_E or
S_err_state_east_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_E);
-- Paths
N_S_path <= ( N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_read_en_mismatch ) or
( N_err_header_not_empty_Req_S_in ) or
( S_err_North_Req_N or
S_err_East_Req_N or
S_err_West_Req_N or
S_err_South_Req_N or
S_err_Local_Req_N or
S_err_IDLE_Req_N or
S_err_state_north_xbar_sel or
S_err_DCTS_RTS_FF_state_Grant_N );
S_N_path <= ( S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_read_en_mismatch ) or
( S_err_header_not_empty_Req_N_in ) or
( N_err_North_Req_S or
N_err_East_Req_S or
N_err_West_Req_S or
N_err_South_Req_S or
N_err_Local_Req_S or
N_err_IDLE_Req_S or
N_err_state_South_xbar_sel or
N_err_DCTS_RTS_FF_state_Grant_S);
E_W_path <= ( E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_read_en_mismatch ) or
( E_err_header_not_empty_Req_W_in ) or
( W_err_North_Req_E or
W_err_East_Req_E or
W_err_West_Req_E or
W_err_South_Req_E or
W_err_Local_Req_E or
W_err_IDLE_Req_E or
W_err_state_east_xbar_sel or
W_err_DCTS_RTS_FF_state_Grant_E);
W_E_path <= ( W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_read_en_mismatch ) or
( W_err_header_not_empty_Req_E_in ) or
( E_err_North_Req_W or
E_err_East_Req_W or
E_err_West_Req_W or
E_err_South_Req_W or
E_err_Local_Req_W or
E_err_IDLE_Req_W or
E_err_state_west_xbar_sel or
E_err_DCTS_RTS_FF_state_Grant_W);
-- FIFO Handshaking error signals
N_FIFO_handshaking_error <= N_err_CTS_in or
N_err_write_en or
N_err_not_CTS_in or
N_err_not_write_en;
E_FIFO_handshaking_error <= E_err_CTS_in or
E_err_write_en or
E_err_not_CTS_in or
E_err_not_write_en;
W_FIFO_handshaking_error <= W_err_CTS_in or
W_err_write_en or
W_err_not_CTS_in or
W_err_not_write_en;
S_FIFO_handshaking_error <= S_err_CTS_in or
S_err_write_en or
S_err_not_CTS_in or
S_err_not_write_en;
L_FIFO_handshaking_error <= L_err_CTS_in or
L_err_write_en or
L_err_not_CTS_in or
L_err_not_write_en;
end;
|
--******************************************************************************
-- @TITRE : uart.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY uart IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
tick : IN STD_LOGIC;
-- tx
txDatReady : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0);
txBusy : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
-- rx
rx : IN STD_LOGIC;
rxDatReady : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
datOut : OUT STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0)
);
END uart;
ARCHITECTURE Structural OF uart IS
-- TX
SIGNAL iCountTx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iTxShEn : STD_LOGIC;
SIGNAL iTxLdEn : STD_LOGIC;
SIGNAL iDataTx : STD_LOGIC_VECTOR(sel(parity = N, 1+dataLength+stop, 1+dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iTx : STD_LOGIC;
SIGNAL iTxBusy : STD_LOGIC;
-- RX
SIGNAL iRxStart : STD_LOGIC;
SIGNAL iRxBusy : STD_LOGIC;
SIGNAL iCountRx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iRxShEn : STD_LOGIC;
SIGNAL iRxDatOut : STD_LOGIC_VECTOR(sel(parity = N, dataLength+stop, dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iRxDatReady : STD_LOGIC;
BEGIN
-- TX
tx <= '1' WHEN iTxBusy = '0' OR aNRst = '0' ELSE
iTx;
txBusy <= iTxBusy;
dataTxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
iDataTx <= "1"&datIN&"0";
END GENERATE;
dataTxN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
iDataTx <= "11"&datIN&"0";
END GENERATE;
dataTxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
iDataTx <= "1"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
dataTxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
iDataTx <= "11"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
txControler_ci : txControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
datReady => txDatReady,
tick => tick,
count => iCountTx,
shEn => iTxShEn,
ldEn => iTxLdEn,
txBusy => iTxBusy
);
txCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iTxLdEn,
en => iTxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountTx
);
txShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, 1+dataLength+stop,1+dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iTxShEn,
ldEn => iTxLdEn,
serialIn => '0',
datIn => iDataTx,
datOut => OPEN,
serialOut => iTx
);
-- RX
iRxStart <= '1' WHEN rx = '0' AND iRxBusy = '0' ELSE
'0';
rxBusy <= iRxBusy;
rxControler_ci : rxControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
start => iRxStart,
tick => tick,
count => iCountRx,
shEn => iRxShEn,
rxBusy => iRxBusy,
dataReady => iRxDatReady
);
rxCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iRxStart,
en => iRxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountRx
);
rxShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, dataLength+stop,dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iRxShEn,
ldEn => iRxStart,
serialIn => rx,
datIn => (OTHERS => '0'),
datOut => iRxDatOut,
serialOut => open
);
datOut <= iRxDatOut(dataLength-1 DOWNTO 0);
datReadyRxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength) = '1' ELSE
'0';
END GENERATE;
datReadyExN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" ELSE
'0';
END GENERATE;
datReadyRxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1) = '1' AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
datReadyRxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
END Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity SubBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
LEFT : in std_logic_vector(31 downto 0);
RIGHT : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
SUB_OUT : out std_logic_vector(31 downto 0)
);
end SubBB;
architecture arch of SubBB is
signal RESULT :std_logic_vector(31 downto 0);
-- END DSP48E1_inst_1
constant DELAY_ADD_SUB : positive := 2;
--
TYPE iBus_ADD_SUB is array(DELAY_ADD_SUB-1 downto 0) of std_logic;
--
signal ValidsRegBus_ADD_SUB : iBus_ADD_SUB := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
begin
ADDSUB_MACRO_inst : ADDSUB_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => 2, -- Desired clock cycle latency, 0-2
WIDTH => 32) -- Input / Output bus width, 1-48
port map (
CARRYOUT => open, -- 1-bit carry-out output signal
RESULT => RESULT, -- Add/sub result output, width defined by WIDTH generic
A => LEFT, -- Input A bus, width defined by WIDTH generic
ADD_SUB => '0', -- 1-bit add/sub input, high selects add, low selects subtract
B => RIGHT, -- Input B bus, width defined by WIDTH generic
CARRYIN => '0', -- 1-bit carry-in input
CE => '1', -- 1-bit clock enable input
CLK =>CLK, -- 1-bit clock input
RST => RST -- 1-bit active high synchronous reset
);
validReg_SUB_int: for i in 0 to DELAY_ADD_SUB generate
begin
validdffLeft_SUB: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate validdffLeft_SUB;
--
dffOthers_SUB: if (i > 0 AND i < DELAY_ADD_SUB) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate dffOthers_SUB;
--
dffRight_SUB: if i = DELAY_ADD_SUB generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_SUB;
end generate validReg_SUB_int;
calc_result : process(clk)
begin
if rising_edge(clk) then
SUB_OUT <= RESULT;
end if;
end process;
READY_OUT <= READY_IN;
end architecture ; -- arch
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_async_tx is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud_tick_i: in std_logic;
txd_o : out std_logic;
tx_start_p_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_busy_o : out std_logic
);
end uart_async_tx;
architecture behavioral of uart_async_tx is
signal BaudTick : std_logic;
signal TxD_busy : std_logic;
signal TxD_ready : std_logic;
signal state : std_logic_vector(3 downto 0);
signal TxD_dataReg : std_logic_vector(7 downto 0);
signal TxD_dataD : std_logic_vector(7 downto 0);
signal muxbit : std_logic;
signal TxD : std_logic;
begin -- behavioral
TxD_ready <= '1' when state = "0000" else '0';
TxD_busy <= not TxD_ready;
BaudTick <= baud_tick_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
TxD_dataReg <= (others => '0');
elsif TxD_ready = '1' and tx_start_p_i = '1' then
TxD_dataReg <= tx_data_i;
end if;
end if;
end process;
TxD_dataD <= TxD_dataReg;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= "0000";
else
case state is
when "0000" =>
if (tx_start_p_i = '1') then
state <= "0001";
end if;
when "0001" =>
if (BaudTick = '1') then
state <= "0100";
end if;
when "0100" =>
if (BaudTick = '1') then
state <= "1000";
end if;
when "1000" =>
if (BaudTick = '1') then
state <= "1001";
end if;
when "1001" =>
if (BaudTick = '1') then
state <= "1010";
end if;
when "1010" =>
if (BaudTick = '1') then
state <= "1011";
end if;
when "1011" =>
if (BaudTick = '1') then
state <= "1100";
end if;
when "1100" =>
if (BaudTick = '1') then
state <= "1101";
end if;
when "1101" =>
if (BaudTick = '1') then
state <= "1110";
end if;
when "1110" =>
if (BaudTick = '1') then
state <= "1111";
end if;
when "1111" =>
if (BaudTick = '1') then
state <= "0010";
end if;
when "0010" =>
if (BaudTick = '1') then
state <= "0011";
end if;
when "0011" =>
if (BaudTick = '1') then
state <= "0000";
end if;
when others =>
state <= "0000";
end case;
end if;
end if;
end process;
process(TxD_dataD, state)
begin
case state(2 downto 0) is
when "000" => muxbit <= TxD_dataD(0);
when "001" => muxbit <= TxD_dataD(1);
when "010" => muxbit <= TxD_dataD(2);
when "011" => muxbit <= TxD_dataD(3);
when "100" => muxbit <= TxD_dataD(4);
when "101" => muxbit <= TxD_dataD(5);
when "110" => muxbit <= TxD_dataD(6);
when "111" => muxbit <= TxD_dataD(7);
when others => null;
end case;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
TxD <= '0';
else
if(unsigned(state) < to_unsigned(4, state'length) or (state(3) = '1' and muxbit = '1')) then
TxD <= '1';
else
TxD <= '0';
end if;
end if;
end if;
end process;
txd_o <= TxD;
tx_busy_o <= TxD_busy;
end behavioral;
|
entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
|
entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
|
entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
|
entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
|
entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
|
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.types_mem.all;
library riverlib;
use riverlib.types_cache.all;
entity tagmemnway is generic (
memtech : integer := 0;
async_reset : boolean := false;
abus : integer := 64; -- system bus address bus (32 or 64 bits)
waybits : integer := 2; -- log2 of number of ways bits (=2 for 4 ways)
ibits : integer := 7; -- lines memory addres width (usually 6..8)
lnbits : integer := 5; -- One line bits: log2(bytes_per_line)
flbits : integer := 1; -- Total flags number saved with address tag
snoop : boolean := false -- Snoop port disabled; 1 Enabled (L2 caching)
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_direct_access : in std_logic;
i_invalidate : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_addr : in std_logic_vector(abus-1 downto 0);
i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0);
i_wstrb : in std_logic_vector(2**lnbits-1 downto 0);
i_wflags : in std_logic_vector(flbits-1 downto 0);
o_raddr : out std_logic_vector(abus-1 downto 0);
o_rdata : out std_logic_vector(8*(2**lnbits)-1 downto 0);
o_rflags : out std_logic_vector(flbits-1 downto 0);
o_hit : out std_logic;
-- L2 snoop port, active when snoop = 1
i_snoop_addr : in std_logic_vector(abus-1 downto 0);
o_snoop_ready : out std_logic;
o_snoop_flags : out std_logic_vector(flbits-1 downto 0)
);
end;
architecture arch_tagmemnway of tagmemnway is
constant FL_VALID : integer := 0;
constant NWAYS : integer := 2**waybits;
type WayInType is record
addr : std_logic_vector(abus-1 downto 0);
wstrb : std_logic_vector((2**lnbits)-1 downto 0);
wdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
wflags : std_logic_vector(flbits-1 downto 0);
snoop_addr : std_logic_vector(abus-1 downto 0);
end record;
type WayOutType is record
raddr : std_logic_vector(abus-1 downto 0);
rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
rflags : std_logic_vector(flbits-1 downto 0);
hit : std_logic;
snoop_flags : std_logic_vector(flbits-1 downto 0);
end record;
type way_in_vector is array (0 to NWAYS-1) of WayInType;
type way_out_vector is array (0 to NWAYS-1) of WayOutType;
type RegistersType is record
req_addr : std_logic_vector(abus-1 downto 0);
direct_access : std_logic;
invalidate : std_logic;
re : std_logic;
end record;
constant R_RESET : RegistersType := ((others => '0'), '0', '0', '0');
signal way_i : way_in_vector;
signal way_o : way_out_vector;
signal lrui_init : std_logic;
signal lrui_raddr : std_logic_vector(ibits-1 downto 0);
signal lrui_waddr : std_logic_vector(ibits-1 downto 0);
signal lrui_up : std_logic;
signal lrui_down : std_logic;
signal lrui_lru : std_logic_vector(waybits-1 downto 0);
signal lruo_lru : std_logic_vector(waybits-1 downto 0);
signal r, rin : RegistersType;
begin
dx : for i in 0 to NWAYS-1 generate
wayx : tagmem generic map (
async_reset => async_reset,
memtech => memtech,
abus => abus,
ibits => ibits,
lnbits => lnbits,
flbits => flbits,
snoop => snoop
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_addr => way_i(i).addr,
i_wstrb => way_i(i).wstrb,
i_wdata => way_i(i).wdata,
i_wflags => way_i(i).wflags,
o_raddr => way_o(i).raddr,
o_rdata => way_o(i).rdata,
o_rflags => way_o(i).rflags,
o_hit => way_o(i).hit,
i_snoop_addr => way_i(i).snoop_addr,
o_snoop_flags => way_o(i).snoop_flags
);
end generate;
lru0 : lrunway generic map (
abits => ibits,
waybits => waybits
) port map (
i_clk => i_clk,
i_init => lrui_init,
i_raddr => lrui_raddr,
i_waddr => lrui_waddr,
i_up => lrui_up,
i_down => lrui_down,
i_lru => lrui_lru,
o_lru => lruo_lru
);
comb : process(i_nrst, i_direct_access, i_invalidate, i_re, i_we,
i_addr, i_wstrb, i_wdata, i_wflags, i_snoop_addr,
way_o, lruo_lru, r)
variable v : RegistersType;
variable vb_raddr : std_logic_vector(abus-1 downto 0);
variable vb_rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
variable vb_rflags : std_logic_vector(flbits-1 downto 0);
variable v_hit : std_logic;
variable vb_hit_idx : std_logic_vector(waybits-1 downto 0);
variable v_way_we : std_logic;
variable vb_wstrb : std_logic_vector((2**lnbits)-1 downto 0);
variable vb_wflags : std_logic_vector(flbits-1 downto 0);
variable v_snoop_ready : std_logic;
variable vb_snoop_flags : std_logic_vector(flbits-1 downto 0);
begin
v.direct_access := i_direct_access;
v.invalidate := i_invalidate;
v.re := i_re;
v.req_addr := i_addr;
vb_hit_idx := lruo_lru;
if r.direct_access = '1' then
vb_hit_idx := r.req_addr(waybits-1 downto 0);
else
for i in 0 to NWAYS-1 loop
if way_o(i).hit = '1' then
vb_hit_idx := conv_std_logic_vector(i, waybits);
end if;
end loop;
end if;
vb_raddr := way_o(conv_integer(vb_hit_idx)).raddr;
vb_rdata := way_o(conv_integer(vb_hit_idx)).rdata;
vb_rflags := way_o(conv_integer(vb_hit_idx)).rflags;
v_hit := way_o(conv_integer(vb_hit_idx)).hit;
if r.invalidate = '1' then
vb_wflags := (others => '0');
vb_wstrb := (others => '1');
else
vb_wflags := i_wflags;
vb_wstrb := i_wstrb;
end if;
-- Warning: we can write only into previously read line,
-- if the previuosly read line is hit and contains valid flags
-- HIGH we modify it. Otherwise, we write into displacing line.
--
for i in 0 to NWAYS-1 loop
way_i(i).addr <= i_addr;
way_i(i).wdata <= i_wdata;
way_i(i).wstrb <= (others => '0');
way_i(i).wflags <= vb_wflags;
way_i(i).snoop_addr <= i_snoop_addr;
end loop;
v_way_we := i_we or (r.invalidate and v_hit);
if v_way_we = '1' then
way_i(conv_integer(vb_hit_idx)).wstrb <= vb_wstrb;
end if;
v_snoop_ready := '1';
vb_snoop_flags := (others => '0');
if snoop then
for i in 0 to NWAYS-1 loop
-- tagmem already cleared snoop flags if there's no snoop hit
if way_o(i).snoop_flags(FL_VALID) = '1' then
vb_snoop_flags := way_o(i).snoop_flags;
end if;
end loop;
-- Writing into snoop tag memory, output value won't be valid on next clock
if v_way_we = '1' then
v_snoop_ready := '0';
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
lrui_init <= r.direct_access;
lrui_raddr <= i_addr(ibits+lnbits-1 downto lnbits);
lrui_waddr <= r.req_addr(ibits+lnbits-1 downto lnbits);
lrui_up <= i_we or (v_hit and r.re);
lrui_down <= v_hit and r.invalidate;
lrui_lru <= vb_hit_idx;
rin <= v;
o_raddr <= vb_raddr;
o_rdata <= vb_rdata;
o_rflags <= vb_rflags;
o_hit <= v_hit;
o_snoop_ready <= v_snoop_ready;
o_snoop_flags <= vb_snoop_flags;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
entity tb_tri_state_reg is
end entity tb_tri_state_reg;
architecture test of tb_tri_state_reg is
signal d1, d2, q : resolved_byte := X"00";
signal clk1, clk2, oe1, oe2 : bit := '0';
begin
dut1 : entity work.tri_state_reg(behavioral)
port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
dut2 : entity work.tri_state_reg(behavioral)
port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
stimulus : process is
begin
d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns; wait for 10 ns;
d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns;
oe2 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns;
oe2 <= '1', '0' after 5 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
entity tb_tri_state_reg is
end entity tb_tri_state_reg;
architecture test of tb_tri_state_reg is
signal d1, d2, q : resolved_byte := X"00";
signal clk1, clk2, oe1, oe2 : bit := '0';
begin
dut1 : entity work.tri_state_reg(behavioral)
port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
dut2 : entity work.tri_state_reg(behavioral)
port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
stimulus : process is
begin
d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns; wait for 10 ns;
d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns;
oe2 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns;
oe2 <= '1', '0' after 5 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
entity tb_tri_state_reg is
end entity tb_tri_state_reg;
architecture test of tb_tri_state_reg is
signal d1, d2, q : resolved_byte := X"00";
signal clk1, clk2, oe1, oe2 : bit := '0';
begin
dut1 : entity work.tri_state_reg(behavioral)
port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
dut2 : entity work.tri_state_reg(behavioral)
port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
stimulus : process is
begin
d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns; wait for 10 ns;
d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns;
oe2 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns;
oe2 <= '1', '0' after 5 ns;
wait;
end process stimulus;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SensorFSM is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
In0_i : in std_logic;
In1_i : in std_logic;
In2_i : in std_logic;
In3_i : in std_logic;
In4_i : in std_logic;
In5_i : in std_logic;
In6_i : in std_logic;
In7_i : in std_logic;
In8_i : in std_logic;
In9_i : in std_logic;
Out0_o : out std_logic;
Out1_o : out std_logic;
Out2_o : out std_logic;
Out3_o : out std_logic;
Out4_o : out std_logic;
Out5_o : out std_logic;
Out6_o : out std_logic;
Out7_o : out std_logic;
Out8_o : out std_logic;
Out9_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic
);
end SensorFSM;
architecture struct of SensorFSM is
component TRFSM
generic (
InputWidth : integer;
OutputWidth : integer;
StateWidth : integer;
UseResetRow : integer;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
signal Input_s : std_logic_vector(9 downto 0);
signal Output_s : std_logic_vector(9 downto 0);
signal ScanEnable_s : std_logic;
signal ScanClk_s : std_logic;
signal ScanDataIn_s : std_logic;
signal ScanDataOut_s : std_logic;
begin
TRFSM_1: TRFSM
generic map (
InputWidth => 10,
OutputWidth => 10,
StateWidth => 5,
UseResetRow => 0,
NumRows0 => 5,
NumRows1 => 5,
NumRows2 => 5,
NumRows3 => 5,
NumRows4 => 5,
NumRows5 => 0,
NumRows6 => 0,
NumRows7 => 0,
NumRows8 => 0,
NumRows9 => 0
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_s,
Output_o => Output_s,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_s,
ScanClk_i => ScanClk_s,
ScanDataIn_i => ScanDataIn_s,
ScanDataOut_o => ScanDataOut_s
);
Input_s <= In9_i & In8_i & In7_i & In6_i & In5_i & In4_i & In3_i & In2_i & In1_i & In0_i;
Out0_o <= Output_s(0);
Out1_o <= Output_s(1);
Out2_o <= Output_s(2);
Out3_o <= Output_s(3);
Out4_o <= Output_s(4);
Out5_o <= Output_s(5);
Out6_o <= Output_s(6);
Out7_o <= Output_s(7);
Out8_o <= Output_s(8);
Out9_o <= Output_s(9);
ScanEnable_s <= '0';
ScanClk_s <= '0';
ScanDataIn_s <= '0';
end struct;
|
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/17 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Implements a hash table. The number of entries is fixed to 2048. The entries length is configurable
--* (up to 18 bits)
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity HashTable is
generic (
entryBitWidth : integer := 12);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
NewEntryxDI : in std_logic_vector(entryBitWidth-1 downto 0); -- new entry
-- to be stored in the table
EnWrxSI : in std_logic; -- initiate a write access to hash table
-- the three bytes that serve as a key
Key0xDI : in std_logic_vector(7 downto 0);
Key1xDI : in std_logic_vector(7 downto 0);
Key2xDI : in std_logic_vector(7 downto 0);
-- the old entry which was stored under the given keys hash
OldEntryxDO : out std_logic_vector(entryBitWidth-1 downto 0));
end HashTable;
architecture Behavioral of HashTable is
constant HASH_BIT_LEN : integer := 11; -- number of address bits of the hash table
constant SEED : integer := 40543; -- seed value for hash algorithm as specified by Ross Williamson
constant ZERO : std_logic_vector(17 downto 0) := (others => '0');
signal Stage0xS : std_logic_vector(11 downto 0);
signal Stage1xS : std_logic_vector(15 downto 0);
signal ProductxS : integer;
signal RawHashxS : std_logic_vector(31 downto 0); -- This is the full output which is then truncated
signal BRamAddrxD : std_logic_vector(13 downto 0);
signal TblInxD, TblOutxD : std_logic_vector(17 downto 0); -- data input and out of table memory
signal BRamWexS : std_logic_vector(3 downto 0);
signal BRamLDInxD, BRamHDInxD : std_logic_vector(31 downto 0);
signal BRamLPInxD, BRamHPInxD : std_logic_vector(3 downto 0);
signal BRamLDOutxD, BRamHDOutxD : std_logic_vector(31 downto 0);
signal BRamLPOutxD, BRamHPOutxD : std_logic_vector(3 downto 0);
begin
-- first stage is: ((k0<<4)^k1)
Stage0xS <= Key0xDI(7 downto 4) & (Key0xDI(3 downto 0) xor Key1xDI(7 downto 4)) & Key1xDI(3 downto 0);
-- second stage: (stage0<<4) ^ k2
Stage1xS <= Stage0xS(11 downto 4) & (Stage0xS(3 downto 0) xor Key2xDI(7 downto 4)) & Key2xDI(3 downto 0);
ProductxS <= SEED * to_integer(unsigned(Stage1xS));
RawHashxS <= std_logic_vector(to_unsigned(ProductxS, 32));
-- note: The hash algorithm used by Ross Williamson does not use the last 4
-- bits, I don't know why. However we keep this
--HashxD <= RawHashxS(HASH_BIT_LEN+4-1 downto 4);
BRamAddrxD <= RawHashxS(HASH_BIT_LEN+4-1 downto 4) & ZERO(13-HASH_BIT_LEN downto 0);
-- reformat signals to adapt buswidth for memory blocks
BRamWexS <= EnWrxSI & EnWrxSI & EnWrxSI & EnWrxSI;
TblInxD <= ZERO(17 downto entryBitWidth) & NewEntryxDI;
BRamLDInxD <= x"000000" & TblInxD(7 downto 0);
BRamHDInxD <= x"000000" & TblInxD(16 downto 9);
BRamLPInxD <= "000" & TblInxD(8);
BRamHPInxD <= "000" & TblInxD(17);
TblOutxD <= BRamHPOutxD(0) & BRamHDOutxD(7 downto 0) & BRamLPOutxD(0) & BRamLDOutxD(7 downto 0);
OldEntryxDO <= TblOutxD(entryBitWidth-1 downto 0);
-- lower byte of hash table. Only port A is used
hashTableMemLowInst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => BRamLDOutxD, -- 8-bit A port data output
DOPA => BRamLPOutxD, -- 1-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => open,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamAddrxD, -- 11-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => '0', -- 1-bit A port register set/reset input
WEA => BRamWexS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => BRamLDInxD, -- 32-bit A port data input
DIPA => BRamLPInxD, -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => "00000000000000", -- 14-bit B port address input
CLKB => '0', -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => '0', -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
-- higher byte of hash table. Only port A is used
hashTableMemHighInst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => BRamHDOutxD, -- 8-bit A port data output
DOPA => BRamHPOutxD, -- 1-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => open,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamAddrxD, -- 11-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => '0', -- 1-bit A port register set/reset input
WEA => BRamWexS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => BRamHDInxD, -- 32-bit A port data input
DIPA => BRamHPInxD, -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => "00000000000000", -- 14-bit B port address input
CLKB => '0', -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => '0', -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- The Interrupt Controller.
-- It collects the interrupt sources and notifies the decoder.
--
-- $Id: int.vhd,v 1.7 2006-06-20 00:46:03 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.mstate_t;
entity t48_int is
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
clk_mstate_i : in mstate_t;
jtf_executed_i : in boolean;
tim_overflow_i : in boolean;
tf_o : out std_logic;
en_tcnti_i : in boolean;
dis_tcnti_i : in boolean;
int_n_i : in std_logic;
ale_i : in boolean;
last_cycle_i : in boolean;
en_i_i : in boolean;
dis_i_i : in boolean;
ext_int_o : out boolean;
tim_int_o : out boolean;
retr_executed_i : in boolean;
int_executed_i : in boolean;
int_pending_o : out boolean;
int_in_progress_o : out boolean
);
end t48_int;
use work.t48_pack.all;
architecture rtl of t48_int is
constant tim_int_c : std_logic := '0';
constant ext_int_c : std_logic := '1';
type int_state_t is (IDLE, PENDING, INT);
signal int_state_s,
int_state_q : int_state_t;
signal timer_flag_q : boolean;
signal timer_overflow_q : boolean;
signal timer_int_enable_q : boolean;
signal int_q : boolean;
signal int_enable_q : boolean;
signal ale_q : boolean;
signal int_type_q : std_logic;
signal int_in_progress_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process nstate
--
-- Purpose:
-- Determines the next state of the Interrupt controller FSM.
--
nstate: process (int_state_q,
int_type_q,
int_in_progress_q,
int_executed_i,
retr_executed_i,
clk_mstate_i,
last_cycle_i)
begin
int_state_s <= int_state_q;
case int_state_q is
when IDLE =>
if int_in_progress_q and
last_cycle_i and clk_mstate_i = MSTATE5 then
int_state_s <= PENDING;
end if;
when PENDING =>
if int_executed_i then
int_state_s <= INT;
end if;
when INT =>
if retr_executed_i then
int_state_s <= IDLE;
end if;
when others =>
int_state_s <= IDLE;
end case;
end process nstate;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implement the various registers.
-- They are designed according Figure "Interrupt Logic" of
-- "The Single Component MCS-48 System".
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
timer_flag_q <= false;
timer_overflow_q <= false;
timer_int_enable_q <= false;
int_enable_q <= false;
int_type_q <= '0';
int_state_q <= IDLE;
int_in_progress_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
int_state_q <= int_state_s;
if jtf_executed_i then
timer_flag_q <= false;
elsif tim_overflow_i then
timer_flag_q <= true;
end if;
if (int_type_q = tim_int_c and int_executed_i) or
not timer_int_enable_q then
timer_overflow_q <= false;
elsif tim_overflow_i then
timer_overflow_q <= true;
end if;
if dis_tcnti_i then
timer_int_enable_q <= false;
elsif en_tcnti_i then
timer_int_enable_q <= true;
end if;
if dis_i_i then
int_enable_q <= false;
elsif en_i_i then
int_enable_q <= true;
end if;
if retr_executed_i then
int_in_progress_q <= false;
elsif (int_q and int_enable_q) or
timer_overflow_q then
int_in_progress_q <= true;
if not int_in_progress_q then
int_type_q <= to_stdLogic(int_q and int_enable_q);
end if;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process xtal_regs
--
-- Purpose:
-- Implements the sequential registers clocked with XTAL.
--
xtal_regs: process (res_i, xtal_i)
begin
if res_i = res_active_c then
int_q <= false;
ale_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i then
ale_q <= ale_i;
if last_cycle_i and
ale_q and not ale_i then
int_q <= not to_boolean(int_n_i);
end if;
end if;
end if;
end process xtal_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
tf_o <= to_stdLogic(timer_flag_q);
ext_int_o <= int_type_q = ext_int_c;
tim_int_o <= int_type_q = tim_int_c;
int_pending_o <= int_state_q = PENDING;
int_in_progress_o <= int_in_progress_q and int_state_q /= IDLE;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/11/01 21:26:24 arniml
-- operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3
--
-- Revision 1.5 2005/09/13 21:00:16 arniml
-- Fix bug reports:
-- "Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
-- "Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
-- int_in_progress_o was active one cycle before int_pending_o is
-- asserted. this confused the mb multiplexer which determines the state of
-- the memory bank selection flag
--
-- Revision 1.4 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/06/30 21:18:28 arniml
-- Fix bug report:
-- "Program Memory bank can be switched during interrupt"
-- int module emits int_in_progress signal that is used inside the decoder
-- to hold mb low for JMP and CALL during interrupts
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EJqZdQq8nVnK5ypj58RK31/jiaVj44lXjMypHi70GZDkUwvdatIx32BwVlbE9cKUjJ40VFcWQyOE
NAQtkW9DHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
a2BNmJ0P/KDDphubQfjJh65LQONNGS+nPDI+FEBqVqVh3llYcPm9TEnuAyovIirerrM92px3IQSh
cFSpAPp4u/cd2TJsfsLOrPD9ZnxO7qy+e2JY5FpUi/XAqggR3eAOzMXj3D5VHeXdh19yOQmdTRxs
7IQJAFlwq6g8IYGzFxI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HJfCQzlhZ8q7ejhQ5EFzp0sqg3HtFae77IOdJeWcto54U3E78SpeEDF6pEhwACgUqjZfs9yzpiY1
EUUgScwgIN7Wbwe/7apXbfFWsLRTz8x5L+Yl5SnoyXFwvLOYWAMsORan8OWr23dd+9kfG7yc62pW
BjXmSWx7Wi0O9XlFgED4nL6YYV/M8k6xPyx0GNKFeG1doQNF6Utkl/sAjy9+NglHdDzTmALPsQRU
/DJUOlU3QqBR6nCUQMBlE1kkx7TEFVvhuOJDy0wsNIcbrlyf+PZm0ruu6wGyKsynW4HQx0weUNsK
ODzfMWLQQZMUTvWbLVYZberOAXQxSc+pXIpW9Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
22ja5ZdxCeErOR7hMWKMcmpZ+VKfeNCMU6DxuiFXT/HUT+7i9bqIzlJcz/hQC0EjyB23hZXTNzfm
c92ta8uxwh6+uP8+SBSMnH8ZueZAmLNf/5UV+aaOZAkmdYvLw6D4n5sDpBVVjloTF6tV/N+f8w/S
eAJYzTeQTy5nodOpg38=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bw67Aw1Vod4+yEV0TbTFZJaFDqK8HUTiXKh6QYc64hlfM5XHhrfCdy6yOxSysow3bXzUJqJGp6aw
tAeU/hA19lI2p12pRkyc7GhOjslb1ulgnqKjCqtr9jZL69HHOpRw/lg4xsvirSgCPOrQgZ5ou1ig
NA4Hat4XuLKzqjPgqzY3V1qTaS5VxOOfbavUc9WEeh/84FKAfghw7h1KPrezdYYv7QxJHnIo3IPm
sWfq56b9MNVhEvGehHmES9J4qHGzwAtzm6NNmj9TFZrDAEPLJ3yKCvXPBT441pK5ZYogHF4H18rU
kbxd7ZO/JjAzrLks2cKgQuhcXRvNBt+Vg6W2pQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74576)
`protect data_block
BDJkwKT7+i0ggT/c5enO4549jBinzkMmeYCLn8JCaIUC+BFLiKutNf75P/gZqJHJjylbcwi29Ppf
BoRPwwR6yCFQHaK7RK/tyJSqhrHrQPI0NPsTbFt718YfWa+7TeqaOGSUpzDj8X4fUIaZ0AZ3B/IV
7/TR9OZQoniDDxlFbD6m8VatDqxjUfIWhGeXwM5tCd7dS5U0gh/3yEPB1dtwryFS1mwpql1qkH1e
9LdwcEmdvg+BmV0DlJbPCILrqad9xhwl0RHqTAjf8Qrd/aJhjcCTz5H0kqrMesUAl6OOwWlSLqjI
nhAmzslqVQvJ5AJmHWE90wM/f2d17Mj0RAq7XhphqB3qM8xczw7JWNeeKGN2rN7KU1YqsPsbZ5sl
koEwaB0LX1kBvaxzCKWALvF1GMBq/mGZhmk0fmXBSU6Y//jBVYnwjB972EVPDOF+M04ERX1DIy41
WB9te1mX3OKtL/CRKvr46PJ1Egh+OnEHfg1U5ztlfhIL72c4cLrloBo++b6tOLTQy1uDPlkRVExP
n4jcamVdET2O9E1oPB3WHwLowos81mn/faGzKwSLfM1mQ8eKeMaZHInuavtF7TXhUki9R3bdK1Je
WycfLP0oj+a5HmmTi8NL1mZxnhX/FWtNr3MJyskLhtUA3g+z+toDjuS2fLQ2oyYlwtM2h0dPdRPn
imYSmVFxuZT5ZbFl6ZNg7cBPzbm57eOO6xGLkc20xn1Bus8uRoPQAhs0ib+krovRqaFlqM1mI7Ey
ymqjBI1Cmxe8CSww5RS9Nju/j03eFrGRC3tF5FmWzzUQsUTr9L9LMXwiIvR1VE+hD9/XR7YepGtN
QisrXFrMBTR3y0xnOJBUWqGWLZNTwMRcwcdE7eUnlF9m05Ho153OPr7IqeyeRC5yic5AXLpxNABn
FyfXQl68QyviGhOL7pDocNiXZeO9tD6fabEs2NdEO8P783KXZmgnpmtq5SSn1MfQW32C9yqrru23
CnqAVuoltD3sPjZaTdJxJN/Ay4St/uU07YcxmBOL3nxmiASx0waEjt/ms8Bz5/mWfRYlW+OClrEZ
+JyMy7sec6i531n6dPa4mUd9F/4Sl8lyo+UAfyFOD1fXMuw90RH1NO790kLrDa88IQh9r6uw4hHv
s3EWdMqQUPqFyqIhsE4Iv2HfAHjrcmXDu5f0hZ+WhAmN825ah2HfswcpIFZOsv0gflehS0jh7Vp/
r6JiKY4CPlB/db6KBbOiRbZQ9pDjG7K5Uc9q2W43xA00kzQ+QGIliU6qmwpCYLpfTWHEVJtlDjXI
pP9/TqGm3aXDmjnjzCqO3rcDa+y/koppwAtDQDJLo9Nwdv4WBjmJ3C0kDbrqJUgNgmYKfKOP3PTZ
CMm3s+bxeyyum7XVw7Zw1McZ0UrzKWoJDEGIwniKrvn+P122xAsxhQ64Bpdw8DISCXm06wq53KsI
MAMScBE+LBNzOLHWXaEhcgGC9LeRnmfxEg8RMUoJ/uZIx+AOrLxe6J1WzPTOF3KaXuPCQ4brhWuQ
kXb+bZk7Sy/+05LJwgxPXJd+nAAEkZrYLUvR6TCODUitqL835EIWzC/2fed6oTe3M8yP4WSU3POr
YpZ6sAlbKBEFJEFhxCH2nm/lzQNI14pw3iwzqbtAbSRj/QsrLYFs5u1vHk7Yh1m+NlyvFz+23Vd7
84sCHgKpQ8chs7N01inDLp+0OZ7hlWclTBf6sYTcLR1j76Fi5aaCTof1NUGqYt7tT0jKbHzdlP+5
ZBteEEDMur4YcXSK3PXyJr7ljZ7iifWIRTNy0r4KSsfCkC1kOofkffLYpHiF5qJTkqECwGtRcqv/
eiWMwwIdp6FXkMPDiy5CwHEWCyjZbNmM4qh5MWnWIt4QY3uw8rJAqkPXV3JZmKSMdhpSOnbgm+Vb
RYzooF4cSoCB7TJNz0cbffBP1CycaAt/TQ7cj35zgGFPvc7cqhZ6Rc+rTJro+UI9tH4TYJp3ix+1
Iz1XF4auMIe1+vh4Poo3Iuy72S15Cc3aA2NJHgV0LybXbNAq8TqbJ7FfNCVpCdnfe8PZlFvpLrZC
2M74hFtlop82Lb+MQfeMFzO+e6rS59J5OhduNXcFH8xqY3h2qad83o93MUsn+vmj9rKxSans9nwx
R7JRuaAbxDJOQyV3C9tu86ITxnrvJhxRFntI58oF2pR55AHA5XKYOlLyHW+mPOWAzFDCJui1b2kw
xK8d305fxRm3ZQBYz8AMebSC3K/EGYo59MmxnBTCZDa/NkvPhcC/lgeYmRoRQN1ohLjGtxEdtToh
sFXi6Lc1l4QF2OEmvLa8VCHkXnl2RD3gJoFapKfWTq8jtxbGIGKkrDE2LbiF0AlZtaAyBWxiQKPt
Yk91MKZCDWn28pIjkiJImRn1iWL/p1GYRTPy7m8Y0FF9LO0yHOe8qFekPpVZvViytES+jv2jTO6h
ZO2c0lCIc1QJm9u4tyxJNGPQjwDZd6EpgnEMMc4bmjGaZKlTNSQlM7/iLpp4bURGlW4YNUsxBA6g
Ce+ddLLVcERCgKNA+L3bYY53SMvL9XZzmdMJkWfoTKeJPqjhd821G6ijhF7TKj17Ln/0z2Dge5j6
opcEUlZ3XOpYKaELVR5haYD/c+qDZTlv8KcOf7AOwMKTqjaXP2hoP+zu20MKE+zgIckhZykvtbfI
QskhD/T+SCCJA/whaEr8xsYb/09kQ9sz345lvwHyFN2r6V2JXC7NPVnX9JFY4K0/1SmGfdnzaYDI
mm5+PsVxuS+D3e/uwr5t/lalzqTlFO8/dr2bgBq/I3jKJAAc0P8TOgdUPoIzc02TUrMeqXde+4l3
9Lh8navQepOYWnNh87rJXt4hnoqDmmb9UEsAe82XnpzBvwiUIPNB2NlMqprz6P8F+zGslvtnfe/u
La8UpsYuxWXqKtmnB8wmKm3+4wS2AMzFwEs8utnfDBF9i0v8lvDB8Xj/l+v2ogAlyVxm/9yI6KCz
KS6JKk2H8WbZaU56u8et6G8rJCaNEN2CVtmVf9J5/XDF4iikT/lbEq3+36e2GNQSi4FfP44MVUeJ
XisDkiXOoiPZahsU3xS/jOf/K4kSIYKr1yJxw3Hs8GcdvnVuvyIGLLPh3eUTmDOa5qUvzeKw8gik
4e5NpaqOz0uCP+ti11WrabFInBU5HAeiSRQEVnJKBGe9BiTCZVCN7S8uBuKGBah32I4KHWvW6+vt
ZahsYtjYqlB7a8st2XZ8VNGQjdTuOB8UdU6+nG1g8+dgMHwD9SCza8L0358iOR+AJN8aLPKJX4Bz
2entAXscX9KBYP1+AwhYRAhlOiEZYZfX0RaUYvwVnEFCUYGFZUaBXmNjNAAhg/mYCZiqkYwk20ah
cxfcHw4QKNdma/naxb406ZY3s/iIu6QOR8zlDzQIZTS/Zv301165UgJwjt2h6bV0uHE1YZQJ/+9u
xxUSNOLqcBChM3X4MOagSvEtbrsx4Lqor9ivh3absBFXgZtOB6yVLHU8l+Iy+t561GVk6qUHVo2t
R6DW8atkR01kd/prQTP+64eBtxiAmaInIcxpV0I0qmG1YXVAwmjKC7jHyusjhFLwywYlvNHObziY
Fwns7rZ6F8mQylAgeqNC7xAOZaY2mDvk0c0RExOCVh7VY54DFg+agvvD7TeoHUSBylu2oqK/iLQE
ay1YaeuZ3tNlRonLkMAskml7RTPikGdWefGUztPhsI+jZ5cNklxwhMJTpxXTimnGUr1RO6QNSgol
a9LfJYDyq17MgFtopiMGGY8od78VQoM7MC7Lzg0tl4hFurWP+3Mjjoy3Gr+rXqWnb+6CJM+V5zmQ
ZzrFjuvZIBVQ7IqTbLdgk4rs0+YjR1AK1HuF4nhjc5ZBWCB2X9dWajXxUZhlB66zgwTz/uUbsPFe
FxhNJPDMNdvBkL6PhKRmxCjAuTgBqkY1ONhrmYz35nrOv1S/D4NU+AU1wmIC+NP4r87GTgvCZFp2
U471LZ7Pd3Xve83LoDDVtizPxmbS6AA0rVFwmoozDwZlg6RA717qeqco3YQ8Y2dRcP0FpIC+5Ra9
6xm0cnB8qEfQt78L6eA8bmS7afFV0JswwQLY6rdyEwzgAMuKVD9+5k96Vb3ShR6fudoZk28eMknd
mcTuWoyNvbCvuGww7EHoTXrIFa8wHuVExDlImhXAXZciv+/Ty8A0w5lwwXuiDS/rvX+6sb1HkQcr
QzxDJKBBE5WCNXrX5YUnxpiPol9Z9Xzr2lTXCBQf8yU6vcxA1PRQgG2OdnbXftAXO2OUP801x/Ir
Pp5UOuIqnu/Cdwh8i+OtYG0PFAuWvaDgOF0DX/EDTkkcifXsGPyHI4MlsOOxitkdPzzYRj80Pb0J
BiI47ZC8F33DMVbGZ81ghqq3wsvx9gtp9pcecDYFglPGTEJjV1xIaoWastSpXNMedwBrOnRxdJIi
HOrIRk/M+0bqOpfNWMlXqhRlrFfiwZFIG3vNgBaspJ0jDLLeN9alCqyPJKWhKsupXV3/OnoVFfYJ
SMDyjn864nvaGiM8HIh29P1eOlIs/01W2Gkoh1833d0j4UllwKnA0+e8WhKRGf8gwWhPju+cZ13T
H1LW/NFLl3esSBAV5nquT/G7YZnCSfsH/icUsPK3pH4rZP122iiOb7tW5NjolYMELIMMJYEJ+x5n
QHJZm/YgfJP5DuFc71Ve4EoUdssU9sYJTLYxPc7yjmJquM/DBVR/GgaMfe8OD7B+u7QGYBBXmHcL
g1UEwGx795wc3sdN/jn5C41+0bWjKxbAI2vQQDeJFFY2sWDPX2AW5TpLS1VK3zi6GkrRwujVKDMq
yKDyAEZ9SQ2KXbpqc3jmohsQ1YuEPTh5XNYhOKtGn5BVAgfnCwdLecU2M4Er3BERP2AvQzWMGkCk
xcvv1FgPHfYgZwKh9/MIwc/vgD0CLrcTr0V5bOWHl+3RFy26/gsCfcugtTOlW1cZRspbiPldDC2f
DIbhcTcYNyZa6m8WzvjBTVJV/AHSgL1ESCZJpvYbxQTP1NOWoLvu4AabHkIqcwFONA1q2i4gVs9U
/w3Oz5KlllEbKUQYNcmaln0T+JNTZRa8FK8LL5k3M1T1ngQecEiGCUghRY1iNeG+502FKYPqB/dB
/PKDeCvsbQKlO51UjZlz8cgSMhLxzv3VK1SfbzExxYcriP37SqzBIMqPdpLgkFmxFWAWQQO164XT
wzWsY4zfmqAzj4MZjTdbh64PySoIhnXwfhsoJSRLGNty+sGJ4bbJMefaNE1PC0hG3w94pfztrRXi
Y7h8EkFFqaClJ5VsLsRmPZveo/F5QJjBd78/JlxSsAOr0mKQLJgJ3Nta7tyvXdOrtYF0s1Uf5hPm
xFX7orRGht9/LzNAjiBSH0yQVSPw1Cke3iCvYi7kiDolg5ty4Y+Yj6v0PYSbdwxcCDXzk43gNOym
8mgs0UdeUFa3KDeNY+P4+8xTctD/4EQ9oXiiyaNM7Lx23bMS7ACxX+4x4PRJoQpto4T6OS0jHKDC
s4n5bFoLD79Fa3DpCFE+skLXCSwThUiwIKPAN65aJET1cl95liga8/2rdgokVtLtYiM2+n3kAfQe
g0N9E6hzTiW5zygOtbhHGcoIRn+2RMPE34v9BxdotbuXu+i+13C5FSzzXDoAp8RsWDX1OsFMLycQ
Kz00OSfH5rLY0V4IKGsjnIv2E5/vb3chew/oRdh7a2Q+dy+RpJjiOV45wKuLmjn7Tx4hvKOPzmgL
vlesYU4guafpx2dlt2Pndo9DwzMDpDRiI4qYq//hUfSGhEVP0Y2jaKWrwxz+nZL8Q5k29bqRcBp+
RHX/wHhGdkuUAen1+ZjCTqGZiFbEt2uXNcgsjZQFe5TTnN8XvU3V5OvafjG0FE3r7Xli75GusQfR
XuVkkbYxNG6ZTIxU6Ld8woKe1nshgKHZfFBduxTB1PnBRgbkbtmeZUus1sCokZgLAHgpA1AnRedg
vVYmtNliojw9//l/pXEVQ5xM/aVKlVQP0rKAVlvT85iCvXiU8qZ1MDDhJSek4b79OVN60scXubei
CvfaAUPZty750FRaooIUfXHX8/hM5Ue4FRj3cCuKqp6W0xwh2g752St1MgVgzA4ysfjrXT4UXBOt
4aoY6ZEZxA5PTCyRBocyiBd6jCzSz+NKsAXPH8iglv2BhMR0XWD0HaLUfk+fuGDgP9gNyvSPqt+n
W/cV/SfgPefm8yXGAz+TKkhX3mxb4OU4tlpqwELxIQ5wbF2CEsl31u4r9dqqNYR0HcljisaEi0ce
FWGa42D23LrofIjuYUtCSAXhI3RBdKxuUAc1aV25aknIIocqQ9t8UonJUAkzZkJP37RT1IZBdMEL
qwDFrQq84eu40YKExZz0LLSlV8ScxmAjuBfGIuNibnH1m1AnKoiEU7HfJqJaH8y8CacLQTS1Kskm
FGdgcEKHud7s0z3m/RzwALDn7XvdACTy3GLksYOEdlNi9EadtDcYitHLlFe6oDxXkXTYdKc5ibOG
WeBpnXr4VowL7L6HXIdYvHIkM1pAsEuF4MnyxS+nadUolivx19FEjI2HWS9IhiRjZBNrZ0ZrQsP/
3ZNRyPZXbNU8eB4bj1wSnWwVMDIttrPg9tVSb5CP+nt0VJtBTQ/DCxyQ0iI0OOPxTg9ZASe7zcIH
ohbLACVaEdNn0dCscDmGrBoyYRdZ/i3zW+vMJwh8AhJu5U/DxmVQu1itwqHzAjirj5nSYBmKJRVW
Xffna/vFoLm8/s0qJFRShUD7d2iKo0u2SjSRD1TpqPlI5YPvI6Jp4kaMt+URrlJR9/YH2JNsRq6x
LPMtCwMe03b8FefsgukYYamxONH9ewjJYSIk/fDOW1yjTChJBC4IMvBznHYe2borCB/YM/aBJxtA
5fOF+9HL/iAwsReAa4w3Tyu2XdXknTo6Qqzz3RsPZPXu4w4PTftx7nF/AS93rW9DSw3Un18TtDxI
8bGPL+kvQ0xw2FPWs78CxUWAeB+MpLMdIMtXKQMi+MwqKBvo1/eGbEatDnyDwiZ1lQLQgFFdRKn7
aWPeo9EasIFB3kwkHFS+YkKeRt9JeNRXlUOyFJACn+EZikzER5dVxPcipf2C+pcKKSvmK7Zg/XJ/
UbQtLHHCU2xSSfqdZ4km2ywAi51Kd8sHMpbJfSGnk2ujS3w3Tker8Lnhwh+FhOSvaqLU6X4dd0Lq
D1Vn4HCueEv1VjGm1cJ7pvVsYxbqretjbhZzlnAbXSld52GZe4caXdhrrlFTUFPkzLxB6VGv9KSr
jvh/OKSIpIx+oqoCIWfYRYtu2B9xs77FZ/S3kuGZQ8Yo/R68HOjrOqvL97dQKgKmd4Yo7FEaMeJw
dA0ErPciY8SfQIZIAGg85AAXaO1HggMa4zhHEmsqhXFULxEOnp8USHtHogBSTljUDVFJ8b6I+EiX
e8drnYXzDUGTAciNiz8Qck1T/qL+2OC77Ici6obBtWTFA7C8QYldDYoR1nx0Zpv9DCbyhlAmY15I
CAC/62zJ7nwJejWU9OF6vEteucOLGhHhmU9IJs039fXOVVyWcvagqMj0mWJd672Eh54nqTY7WuWE
MnR3L6GnCWCv5kb2kkSMW6YHEy67E0ZWKpPXeF8Vx/8X4i3oRv14nVLavLDXgiv58Tt9tVTzRmKo
CXGGppEiF6tB+YVVA+ZoRk2R2PJz0U4PeOrLFGgj3/dYLXELuBVFXgMkTKFhmC4H3fJbOo7n+vtM
9UzBkK+hzaQFRRcbiNiY76iUh8mPV2aZKDEeInn1opKfIt06klvVdnhEMOwhzALcf/sJj7jlZ5CQ
mXnypCYMQDioMtPVL1JvDWncMJ75MqyCiC9/rHTQnnxAkiYSyY5IjCH/x14wP7tK1P9eurjOK6Cb
VDNmn79QELN8bRcW4TOMUW4P2KC1UG5+NJt7pfV9f5+B0uAvlo3X9eOmnOn18k0OuJMULfJctbqj
1NGeXfF6JwRpoG/2J0khOwm8cMyxJqyJaRgGp7z8SugFK1qD3dxIFXqWvtUo+Zgp9gbcSbeXf6r5
o8fftKhddyPfv4q4hIaxfX7Yfaw8IliPgkQCe6gHxAzndNUvs/semrNUycRXRkizoblItAZwsmsm
GuTEWllndkStevGuBC6aMES8vBBMUtKgar1RY5e1izCZmJ4V7NqMx85QSnOsjXMwaFZVDZhV+LHJ
ziwtomCX6CiBOAdNmj7TMPq21OKQaOlvWT1PD7q2PfoNfIEpNUGpJz0lVhtszz3pxXonaXom9Lxs
Aooo/uay3kuYB5g8JEsDuKpvtCgg+kGass5ki8KSsq0bcadLs/xumn3F09TiY7/FwS8rUxQYUwt4
rqvBnmI34Qj5dW/YpmqxBn/tMRTsTRusN36OaWkPoE5VqTMDMbqbsTTv/qwxKsEo4RCasSKX392k
85NfrI6Jn2WaLiJpsNKxdW/C2DiXTsQyK9AwTW8B6lP4TT3FHj1SrI2OLKsq3YaGR/u4AdF7Lfbc
8a/lOzlBQ8DlaCFKQSm3kDTbk6fnwIL1ob5Y/BIhTTEfP+NYq+D13WhQ45a4HJhyiRQEFLT/tkP/
J95rhMHJBftomA/jhKAGoZRMdxekLB1kMj0xAsyF4Ip/K0qZkwoBOVYZJU46dY/XWqYQEbJV0M5T
2FQkd+55ZIQi8njAtawe+e7N3fNi6LxGl/aXvQ3WghucOScLC9YZCS0HflAlOqC+lQsNVf/udm08
yY4emEBLgP1JXIFzVj56kqbCg3MqAavAu/XR4PUWNIXBSgJtGMFFRGWQ1QVwNHV6LsESpTVxAJd/
1uqShQtOKgekP8IzaF8ugYfglzxb803odm8NWadaVZLS6hyYEIC0pa1hWB6ornKPdCHv+q5555H3
+gfyKeoVWH9U/4mGy8xB3YRceNe9nQ5Z2TvJAf57Q3drdrMo9Omv1kXAmJLfb6aiNGqkRoQPeVEv
e3dI7yVKqfFcGr30h2hkAyR3yMT4WXuLpew9y6rCro9+XV+09w0l50K3cPdnloTelI6ukmqNA8Ia
glBrsRL/SN7zwZTxMH0CkC7uQHIJ7a7m68vhBmuApziHFNQIvdnipiDgW7r9atEdgeaHykNFND0o
5D5YDc/JGWQ6fpGf7WH5LbsoAlPmEKJvDHTysivvBZhNV/oR9sPYbyYtpVdfTlFOVuDbJlBx7uz9
NnI3SqQPgsUDHaXcqqykgxNWWrnK8IV5HcFiZAmKAvvoCsHI3OzDVwvhC27vo+xphnljCPUpQYXH
rSuFaSafoaqgTMz7HJIt48+TfUQy+4W36qLOOBMq3peC8HirMBKbqj/Ifs9NhzAr0C6iDslEW9EY
0lpK2I7n6YPuNIS69vjV8mCxfyAt4ZGglNwx81AvUXSxAVZy18nDOhhPMgFCJpLE/vs07kolm31K
jX6RrN+VpKOOCFZFtcJGqGiutY5Ltm3sx7aZ2gYoDpFBlvWBGlxsOGQlZnmLy4qwuK6s5bthtjn3
1TZmv05ujxvZGkUYu0oh//WlJU990FOV2VNfdIEcjfy0TnoxJxw3vjjtMRh0ZkIL7JBkbumdjdah
PHAMsqomhe4dd0Gw8UsnJ17C0RsV3JRVsn6mPvLZQaaHgEl17sR/g1uQAMbVKzZmKeVoT+RoxFAr
DrSoUY2SoaK9k7Zi4FQyHaZwSYf3Eo8yPuaNeNe20z8sEZ3svSfVzf+qa/upTKNZUUdXG973lqqI
k7JAKE8Nm5yn8nKwWHX9zjW9OZylqsHMP8/IYtElvaZRuc9Sg6Ahmj+Tcf3p4KYclk/tMrNfj6kT
+L0sHePK0qCb5J5pVpa7J01jTCTlyHHH6meOHAw3TYnG6bWntsu4qnG1lCJQPzoySjzb4Fsc4y4g
Y2Tqj0wUx8iqYXwfvpBprITmeeRU8pq/zZACXL0Fc7ulMQ9+b2kWDYfC5HgNMyOBHgzat8rZXVDh
jJKsqOB8gq77ljAuMsjVq+yjNmciTPG13INWCx6esI6kCjM7qQaUVcpVRVlvWPky4gkkUSsGiKoc
A1PtGaapKXNtAs6IGFgVaGujcU6S2+Po8DsFotExr45SHI0Gi1k7/7X+jlcoFeXEPzIcHNoALCVB
PeOkGASEPCfHh/S6ChFvRr5Pvo6FOk4RkRNcNe/1T8x2Hs7X/oXzNOJrJx2BIONdozsRpgtHrcVL
9YDOqgNkNZLNE1C6TSoGlaYGhL/imaPVTjIK5eHuvyj9hfbUBvqumj6ALElIO3EOxiokqxCfsAhi
jbDlYyEDzLMfgbJSwDu8oJfbPvsY0YTS8DGQifECMd64QsvyBjOu1SveZFxeUdqj7vt4x396XDLh
OZK89s8095h/fc72SnlI9hQUGsE+rEPtfgktR9xdO65PeyWsWmI/V3jB6lGtGYqsaZPYmiSlBlPK
oZ8x9T9dSD5zdPYtfTZUOe5GGdgMIktMBL8RWVXcS+qFYlP7geEZcURO1xMI/8Ar+YvGIkB1TCDM
eAqAmcw+LIHVAJrm2Iy9Gi6Wu3VVFt962HQcdfZyR+YYWRD9B2w0iISQpyEOmWZvXA2HnlAk2U7s
ZdPltsg6pEbao1jYAfgG4p09bQL8/0eyWAD1oH+3U7sQYSL/U4hv0vflgdUPJClLwqVRJrrDCNRt
QJCVs3YrLKRZnHHwUhvCUSETdTNuqo3u/afur6hg8JfKZHkoJB5vRQQYtBz8OselyIoL+O+3XB33
BVJeW7+XCrdr8nPzQye+rDl/Lfsim+5ElTLf4ylPO4ZqKHQpHHgsFEiIhtYRMv6p8ewRZMPgdOXC
yuP9lEHdkS1BtcAO1HwgaOA4MHiPNdcbQEJnjeQ+dIrDHf2I3tJ94Y6CIBfcy6Vbul7Lo6zulJNp
zvK/40xEn5IsAH67a0V54iLl2sBNZ6X0r4jXagARUZlNnt9abaw/dCkOgM26NMKOvlunF+2vWxCY
9Aq6+Iu1yIbufp/RfewjOiid2iPR3vRvwr5lupo5cs1TE8nj9P1gYIFUbyAwSME2zp+aJefmVJZG
cYuL/EGMGXnf92H1kzCWSXyGQ0CCtq62lgt+yE0OYWh1kLp3/M/2y3Ht65AZPnu8m0+6rKgjmnvz
PhS4LMLI/CVccKPvKgsGpPLIu/5ncto8DEkrcRPZNOlD6mIo8h5I6ItitpkBbb5e2lkIXSig0T5h
WXCT/TjuUfPIKR3wenVXvDthYGclcqLVbYm8aQz/GnJ2UwRGrtdb52BDpnnK8/dieTQlWqddOFSX
myuA6tM1y8Zsm5DfGslm9jDc8/3sREXi+YQZNB6ghF3bR/4kdWMX3eudifhY5eC9wUwi5Tptzk0C
husdwgCVRTmI1p0jdGL96OsOKl1Hk4NhVvE82y3O9+SGAt9BQvjLwc9e5z6f2BanWWxicZw4A7Od
q4/jvNW+loHcEb0C19iqbq7pYh4KahqCiwsJVt+Vpr/ro2KkJVbt5JAkWh8g7hYg5z7MiG3AHrnr
3QDvuRWGNhV1LpnRzG5TfLcAGLb3cxXFqDtbOrbgRVMYCC/qnITaojVvpNHvj06ZU2UXS9qUnsIB
L6M/eByKuy1+Xc/+ldQAIUviimL7zS9Kwy5HEcewcqGOx6lp+cz9qmGFjbxAhRkHbZIZ1MWxB6GI
RywNArtfml14Bck7e/p11ifqcMN3kChQOSAHMpYxpLyyzD5mlqLV4ZftaoOBSIyYmkqoDIJJbEYZ
s5r2ORb6Zt89LSDR4Mao3u7UJpdGucp8fPNvm75DqHASPQph/2lVnHJO/FCTNGoAHPmYsuLURnEu
e8FeloqUuDRbO6hhCC/2r7LTmQgjVRxT29a+sCJxw4TvOtebJUOZCx0txOYZlXanURmoMkEMmWAh
0H8WC10xSnzYOAz2ZthJrnxj9l6jirVZwhev+dSiNvk5TdI25xwsJzqQB532HHOXSDYTN4FvP+nn
pIGndFckkZjvt55I5PP9kZVdRFb+qnK2HuVwxfxazF4YCSbgFccOYlPU3R4GAzbpUQi1pzBZD1t5
lq2BIMB6YhZ3ocDxtMiqfxBQLDoT56nnUvjg1VrabY0m4f0HS5Ev9fglTgEWqTbIJUbDt0bacVFj
k4yA4unaZ0UWsj2Ml5wbCwPkftNQLtmvbM/nUUwznCQBq+n7It0cPzO6wbyCDg+OT0mJNSoeXRmS
VNTFtLEeu5sNoeApi1U89WuYXpKZY4oN/7OSd7FeLdgfHSE4gJXVfMac/EoMk0Mn7tRdRKdZYYnz
TTYgbGH+p4BBAgntezC1c3PhcFGX9t/ubZLWOri52t+48IvfGkUdTxLBo/jGCLznmGgIOlPwCSCz
RBvIHQ+4G1lk/YL/z7vZeem2TSsF/dAAcA6juhEPZhh0qC095N/sFazBoWJYLDZNMaVZQ3CkVHo/
licG2M7TGWaA/v3IaoTuhDjmmLZcwS96G9endECC2Z+TJbiqy8OCi8JkyEmWzdgrKk7TLOtExNVA
m70M8nbeFBWzs0Yd+WbZrSe6gnE0zZFLTaBDQSgw1q1W3PYYsygU9bl7smGjTAV+FKrTaM6ccOrq
nmUczTlJUD8V/tZogNHFU2jgGIPzxYRC+jv0H2kItE2PHDJkHTHmyvzxxshgev9hI8X+khvQkG5G
iMBYyuCMZt5wVs4maT8o/DuXo8Gii9AVSCiCFXPNitOzebFcc29XWUknh+8Z5vfMASecwXmDpyQX
PqRyxqdeuYUGP/I+Crz4IatsrHYoaKO5wOvzCoU6p5fEjzmGr2wASworEDS0hEkogyWF3bJ1U0b9
RGz/c4kBH5PCvR34/5X/fzQZh9ku9pNBnE1siKwoIJSJyYpz9FxMBEY/t7CbWkXr/8InEyxyP9iB
pU++3Cv73ZQ3euBhZMQ0jkS22WGpKDb/kn+SXUYoDS6oeg27ZDswcSarj8zRbHIKqtW9Nn81bUL/
xihiDWyxIStrcnjbK7xT8w9ZyrKAX01WYWCzRIinuJuNm1qJJPSYW14cyZ3uGX3M34HdqGRsCB/d
+fEMHpPjF3nmA1vUJj4yirFEe4SJkQXaGadRtN9pOgtOJ40tTK4tQtEA2ManxeyfHroHSDdxD6IU
7kVJeY7hLs3Sp+RrAB7EK8IcpmTto5U2gU0F84NMWPqlhdkB51W3ysVQhMEOSX7y1VipNQSaW+Uu
1BgiM9kDpczvd5aA0AS7D3zLEQBIk6LR+7DiEKsTJpfCFb6IP0tAxNvkWZY0Nz224Gxnbvb2EmRB
OryZ89OiHyiId3r7Ks2N7lfFGHYBmxuMGjX+f0khroxQXFxW3eGAZmW71OITfso+Drt1+NsEpaIV
V259q/3496tofwFyv94VL3vgPNIzrq+AHMpzGqnwRHy6C8JEO9/iI4IOO/RElDVjwEC6l5iQ1Wud
hY/3G/T+WYE1vyvtiU8hk7jrxntWreXUSEMmL8DghIxcY23q6Jjlz2yXruwogshIFy9VOb+j7pm+
zgnq7Cucm+E4XBxgr9uebugReq5uYKKxMOpeQQqgkCXfpX7y3m2+Si7xZ2WqcPgMDhMb/05g9Pk3
S5H4FWqQRW+nyRpPnXP/oOdD8hYOeJ6bwyvx3DenqtNDFejmDnGRqpa+Z1/hdk+QTrijN2AhiHqw
VG41ZZGvSVVUN9RLcipJTg259pdxjLdmS/uwBCD5yWr/xjeFwWiyziz5y2XLV+ozkxDHpRglJQjN
jOXwkA+CoOrQZrJee4eggVNhQ15sucMJViEPTMs4MGm3EhQju74QV8NbeMpSJrm785qK7EbgKxyY
jeYw1oZxrkMxrtCODe3Q+QXiQ2SQfLm51+xIvtmiCIx/iKLEgjuFoHyBysRuK4YaaqUd3BkIV0PO
hEq6kDP03j8ZmTz92fhEMNUW0SrSXxmAPJFo5o+hh2C4fVTrqJAKqrbgvkT3AKBy6oe+fAmj0jhu
bUVBuvOMgNyssgsxqoPd90eCFgHj+VHuY8Us1SLMzqHPgycQhUj3DUCg4h7bn0Kl8vocOKeWMHIy
Nr3z9MmzJ4iywlq2Qd2cvqnxmx9Hb8iHX+EcdRZnq7hljBXfaJt9EmkGgdTDljOjFwBM5RZP2l9n
F05oJQKVj+wntG+QA1Zre0uho/IKCIAuBOilgYLqVGmD5YYhm7becmjcV/VAC8eqx+KXoDZu9Ldl
wouXplyMeaVqkE3po/G1aATieMo8Gl5LNgdk8T3GQABF0T3HbkMii/zlsnrzCvdFwCAX7BbX0Ghk
CinBhzqEBh0IwucJDDNFL+FZ1OumbzMf7f9cBCqgiZturKOHG4nncJs0MWAoO7gQIc5oAC903IEb
U8Hg+Mxgf50gWKbRnGtSKns/uCmcm5xHQNiTE3Vj9CsxKTl4/sSsIAVoVbRR2da0m8oDas8HrBe1
UpeUoF5L4ksga7FlpubiOziXkAlsg13i61bvRuK1HAWXi9qQmf9fA2vEo+3bMZo9kqoEpIGj6e0b
8DbF15T5DBJReTISOdPKnil5pGkFxECrOQWkpTOOc6v/PyvMNv0RUY+SQVmPXUwOyq7CkaWgaIOk
GQh0Q9QHziQR3vmbsI3pRRpsTXHaqD1sm4on/6sHt1ScfXILzFAjQ6uERGDD9XvzZHBzn/GnTX2e
mFtNAfvVkWZ1oRfwBK8fW7nqcCgFP7NVBLNcc2lCEuJk6+fq070jtEK9KYs9bHWG5P7zxnLUV7mg
btR5OsEqQnD6Um+GA/8ihrZ/STD+f9RthBp9VCMYFATeK9CjoR/Zy1agoN5mwF9Szq56eI8sLn18
Pp/DegyirjY9Xugnptj1Chl6aLEidBQdSqdrAy2/su8/hJ1YHTg/QUiRMLnUZN+G4PwNMq6FlHfX
95J9+j48JbxI+67i7NEPDZTrDywwIUgkC4MriektM0+l9NMDCsemdFA9wBTSiwccbpa4ptZmEn+n
aB4d2uyVjPV2ziwpZ8Foap9R6dv3nPDaplNHdrje0Hpy80/SO6fehGeoGs6buKq8ralzUUBL5TtG
3KHIZamuTsOaOA8gBSknNIlnpVi44X+Fmsj+L9ozJyDDtFpTmRWzZpK58gDpNIbND9W7XtmAUvqz
7WkClPABLD2Rn/KqrIWTvsJXYMTL+V8fVxu/ZlftNoeTekzBS85ofKGOG7bHAki7uOYT9VPIC6KY
UnVNCS+VgL1nB5NsQVpBu9iDTK1+/L9P7pWahkY55CfdB1k2kdHW6ijeOb0fMfXI6jrihBnKafZr
/Oyk0wEmBUwCTzgQ6KIr1hXPOLD9uRxblrB4W4/nhsu7I5vBtjmkCM4xKWYM39a6bbF8nizAHtqF
1CmGZKsKYdUxbzOq5qGx+cVmYWC0f50IITM8718hCPyDuNjn2n6wCw6VdzZKy3R3sZnukyNGjnzD
8XPMirEafDLdR2HKAIbDEVlfX4uXyLjHYnjAkHZtZDwOZk/xQDZqevdtk1PF3YnT17QqSvvoD/83
v6Q3BCjhqXB57UFsE/Ewf9RKhbbbbJSdM2nmEL/5N8Kb9mUWmI2GUbd0n+lpB5dItdo93+eMa1us
2/2YvKBZmQgBWZyASrEKEqwCTQ2HhVqR+cNstucxrvRQmwAJMuou+dRFClIVpL7iGbpZio4BhXFL
yu0+YqD8un5+Zu2mlDIlTPPrGXlxFtpYQQeeBakDe3ojlSjvU2vQ7ZQfSiK5l3pMFdgm/oPK+6AZ
842BzO3wZ9UMoOeNKPeXZ6AnXJ9EEoEjpjsDzIvFNMaz9J8qMji2aMPzzLDUrYOlbj/GfnRb5sON
UjTUMYd2fy8mxnK1Mn02JTxNivCtVNGBa6/lJcC7QX9DoD6BJvRKRCuHyFVKsHD//0ghOOiCU2NA
9dq+w10WVMIBFCjy4SjGe7dTDnrZrsARYX2gGzu61nQcmqDb++sYc211n6QM0POeOwow95aA2dWQ
A/k8BbuSGRRQcVZInSCbS49sXslr1/APRmDRHZYnwyQXJMSV1uh0rHEhldejPw+IMNxCgFrWqIzQ
fT8RPINuPfwIw8RLFpRlpUov6m/u/o5uJdoZgZLNEx+bQXTtMaZPRemUeDv1N6t/LqeAFuq93peD
2Iv7Ng1dCrMmajF+43j6seXcR1NFRHmXFABSKx6G9xz/nQqSbAjgmN5dRwBM81q2YIeSE3953qQm
YLpA+eCRdhYaZTNDZlsLpNmLbx+c5kiHRd76Q5taVycBbIthPkS2wlz7+un67dFIU8VJNH897Fl0
hWayOaCnV14f4AEaHs2YN4jgMmWj52hG6W9p9gHHR6HWF8Hh2Jowu21+VbtWIGkQv87Kbzzb187f
/ns7C/04KNGghe8HFO/7ly7NYPzZI5CFfxIonBqh1xf8NpkSX7zG4+ocA52/F9eT18vGwQTU1YHI
7RwQLWgLtyjK+UUuPvZRcEutwwL3fzbxSibSYtrzyYfrr5xxRaSJSg0PywEbgvQ16N7NK1utmXE4
WdJqPBNMf3TCa73axp2vg1KLyqhHJ1JSRKRp3qG25pkIPP7bDvqqqztdAQKCq2YPjiqLt0SePcdf
1shZiHwkusnVhiiWDQA+hKfx+3BS8LI+4dXYxeQWkaEQ04MfaklsFczDJXJjacuhzBXKDpeDMcXG
276h9mXnWH6XW6Ql5+JMUPaEkCjC7Q3fszlqxR7Uhm6ach120geqz0LZ10EZcTzKAyBUV0CH/wsj
LPtLmTF/J53GPVYkCT9L6+zCm+nw2Uy/Gwl05wU8bGD7F2IM86Ad/sIqsCj+IbConWnz10NqjSHg
DiUOKAOqOKMji7Gz1q+g791hIdsddk/2cM9RchTWR1DfkH+B7FRA44BvIhktWuCPZkvTmpvpbzO2
P5TzpSHOx2XxSqHpW2bwQ7BfY1naRFnZOcqlJr0+yYLmvZps/o368poV1pjZZ6fRjp+0/wuYptFy
Cph+rYdc3IY/BFpXB/i6iu4BviPNhU8PRs90RwXX+nBaDHXY+oRy672bdWay4/vtZOZ76gFtbNU+
/uPHDudbtlWpN9ynlB4SqwKlQxnf3v4K//ttlWaalOaZp8OSvTNw5vJ8/CZ2OaPo0e0ZGWSDw3Md
Sj7a4SmdfthYqINqN1CYGZk2pQDHhO6g0tcWPCw7ERPjB7nDHN3lbHENOndqWLSTea9hH3Fyql1k
TvvliJaiQCTSaqtyPqC9xarNnfYk0uXngPZ8yNZcCadrGlfWt8C0x8ZLBuWcrq2i42cFJLNonu7M
8/UhBgizhz9y5lZqduUQHejGZ3EuHWPEMssiKDUqxoKaEQmJJtYX9Y41h0i15k+TSnv/PnvlVVFs
kePihP360X7S4lR9OCi+4dsVp466ARLfhYQzLyjDm7Ma0CUOlCPPjHog/UqBqML5T4V5Q2UYvDyS
QF9N0FpciJhFSSN7H/vUJP+3XtMRQPAUEu0jVvUmpAixmVz64ppmP0dyPDR2abMGxjgDwuejHvQX
Bw36YXuu4+jLfbpOJpn9ZdsmPXKRDS6f9Dat2jvQ7+DGLvt2kvNYeGieqetDPLniwesTHdkTPEpq
z4a9PZQg2b4xRNeviysB+cdWuGaKNify1rqjoGDGbcoIiExgF7ZayMvZydM5hbF+wEs5fQRHBO7Y
5NhilM17YQFEJp/5du8QydPDwRzqzW3Pt86cXB0yU5+3tsaAgNGFtBpX71zwXVRzXtf1PWIyb0Td
WO56LIx0+XT1mVu2zWHytlybciLOdooq/pD8xUxdhIikOkeLVA9mVc1F/zAihD2AnPEEiyqLYmww
OCov6g+ojPVZheB1STypemgMQIWY612iW7Yw6x5lJ9jFx+oyZwG1EEadIsqj9JCyMr+dyFGQNlou
oSL7q3ukZu5LAYxeTAQHNl1jPv2WKeFqQ8LiONLlUEB4cBiSAmVqbqeJHS3DoxNQ+DaMab17YOBn
5libykss/Gld4Ozb596zaM01UwEc490C5bTJbpzlpknkIC7oGf1fui8Oe56Q3fSufxTrRtzsHv4p
QqYNBRF5g9tx12YCBU/gR0SoDGb8EhC6ix18zBeXo/F3YgisYPLs5v+Qk27icvSArJ9j4ZSt9v37
24eMy9JYjUwiJI8vdGUoa8ryAzzaCPSfQD5utaEXg9R94LaND/ZT6Rnp2OV/+Tx/p6dtsqPIV8wq
F3qxVVc7fnsljDgKAdlDj8ACwZrce6NkW/m1roWILb3XKTozyWo7yvjD1LYLv/xCVp9LwvTXc8nx
PfQJQGr8hCJ+KuTsVOzT7B9Jd8q78OQHVadjUtppmceKQdCV6I4Kovs9KAM8Pq3ZXWV8l+0Q3uO7
HLzQhlL40HP3SFt0EJWkKQVOCREWcIhcDJZ+h+LmDxI4VYXTRGkk5TlWCedtz1jY6ehVG9rdaraP
Gj7N9JzJw1azTivfiq9kgeKs30d6ks0DpSg92XG/Fx5sMlyvu0N/HZFkw6t870+eM2mTNKKJsJp7
ypXpEY42X2HHzbqBRkpah/BQ1QTq1lOYZdBIlv7uyR63fishVRfY4BWTynSL3OMh3+5tCdaduane
5sRWhoM4MOB/l6ztHupi5Sfkf6gl455ggAjkc749vtJN24GSsbOtm32XTECXBRyI82AphEplZeMi
TlE2ZV892fgD96le/tLD3CTexC6PQbo9LL8wqeOHo17gAbh14XvFWRINywuU8EeCFsYGcD1sDkLu
U/JQjI7xLdorv/fAZ0y/kSlJHA5GWh/wY3oKfv0aIA2jNfXwb4iTsaEtybZhFueJcT1CsviOc6pF
BA+Rehn48w1ipN3UqKiaZzaOUhwkfJpu6QfqjXKMB07Gt30YpbGSpgmNaP/VCNuImA5epvsjKM7Z
z74Te6uFHugJ0sHDQKpxL+hGQYscIscW2Qd0YSEQKzcHtPMuEPP2l0A5mhrtmbTKCgVhpGDKtG5X
7inL0eiHHlFYXZmhpHuNkiGaBo/cban9HP9cBn2PWTiA41H7TM4a4atG0ssV7uMaNCv0mtKs/qBB
ZSoqlR+kq2U6SEWxronA1GFeuf1c7Vje874aU80B7g2hJ2k0zyrf1gHUIyaNH7SmZr/wanttFr8E
gRnKQTP7oYAJPPfjEp0p75wZSIGy5SBqmv5wIe2Okr0T6hnR/EtVCWgve2/YPlZVg34OZEGt8nrj
6ptPbegAvWcFh4uHEbgmkfkdkCkY/fdBgkyjl1q9izP2O/GNApKIU+jzSNyxHQt2uC4g80LmOQ06
tc3G8K9Rqk1+2nyvC1xM10a+vX6ZU/LzrG8OPCSRc/yuxUKTgPn8q1EKmdsrq/ZdKCZ1jRNEg9uL
e2NzlQDW7+rKcF5K11QxfkKdKEfRUsH+SS0MHpzdpxhLHk/X/Jo6ANzbTKNK5cb1ZmyQJApKaIjg
6ikzjSTCqPYq1Y52DbCjCAu8+q37pUaGgXb5HIazBirTd2J5bhKrVV/d+s5uAHUXJeK95R3/DeqA
OjIUFvelfrLdJsL9lWlgSZjPKuuFocDhbGrcDs5xmQfbMFCVx1+kvp2ed4ouzwyoHEHsaF7gPxvy
Bs5PHGNktdzz93C4057oGb2qWi4rGRszkJSeACJdyfRFgepGYRYfP7zrmI/MtQqrMzoajkmDzRuP
6UShINcAmLqdPS/HV2jwQIkqOa63ktbKxT4wp+uNTSvpBsTDqVZmgU1bw85gROfe6XkwaSWxFeRY
6MkmZSz7kOpq4r0NrboZSuHypBKPpCrUvnZTNFunPPNzR8ip93/MAsy60X/daJHvWnB2qAUj9sMF
v3jm3Hry1S/ot2vqVYNWoRXlPaJB5cqMasYJMy9nnf6ULs37rJKsC3AwK757uQ4qHX+GhAYJ+6FJ
vgv7qWRpoHqBWy2PSafuSbpCbakhYLxaZNnH+170HL6OEw17hlM9oVSSPVP/EIvQcLgv/PVV1EGJ
9emgfShRoc0OVvcoasuHWq4o1gSQGHzCoskpkF/cJDg+5tP3BO02PS9uuXJa9rJPvoEYxjEZxxg1
qHhM+lsgjsm1I8EAVDzNNp3RNKmaN0iE7htUQJMudr+sC400hc6x6JSU4y6vrrDRc4NNNaB4T8TH
yT3mjZw01sFF+M5fipoOSbN6UMWyJRrYzHJObEdMUuqN9qqx1/UPSR+WJlHhDnfsxVV5Ufmn766l
GxtO2r+VBDTw/N4CoPUncmZg4X7oHlScR8lpvNlzSp5lnYFHGg9/qMLNyOWFoH2S/R4Qga1ODY3C
LKkhorinlgqAhyqu5KS1I4xxiGprQ0oLalYB+dngYqsNafix+qiUsbOELdx4kJvjflvN63A2Y2qe
bckT728OetwgtF0l0L8L/9qhZHIop0QDV6LW+698eZETImGNsWO5H+eywFveiKb/Yt2v2eTz17Tx
C6Ek5ZAxp/YJMKsp1CDL4YAZPQR0DfkckX3KKKy+05vTFTHrQU8+kYGBfQux6XTKEl5Wl0U8YWZo
y0lMMMCKsjyTNcJPiPcNwVbSk0OolTKvSxJ5Uq+/s2DIqJBIVL9Uyc/NIuOPBfYQpxEqONCmJ269
4vkxq5J1lRvHILpKS6g9nUGFrHnCBse3GeDbWlXEapIcizZksN6RKxY1BG2yi995GxCTNDSHVpO0
uat2RRgIp+SSIlHTTPFnj7LSQ98qkCjkxuGnEAUsaGdoVObLm4rXDH7hAv5ZQYHtAD0nhppIzFEv
d/uF2yphdil/A7MlAiFUwET6ZiTyUmMoLr2NwpMLFPQTXg7kap5etN+C0GyClRInERrXltP24vvD
xS8DGrSatMRCon0ySF7OtDj8w625pb/dIN4aqr38r1TKM3mKBNMKPRHm8kintTjct9LKLkt53B7A
BoBkBcQlYeJJxSFvzxSAfsFkMpuJKOOVfnirqitrH/VN2LvkHOWgeKUE8/drXHPUs5/CpHgyg3yr
+yOUfDly4bPVLf7FG7tMb+EwgFSl/CLpQYF8johczZpDJZOjBuIVzJifHKOULdorMTQUs2Xak8Hg
Nuhh3N/2LXm1sXtU/I7nTpBbgcwAHdjBX5oMc6sVMrOVwEplGbtDR7LzO3WIlB59NsVty0o9hROy
YKtmv1aPSs65itUeyCsM682TBRMK0XyreA4A/bFx5LOiQVKTeevCwyvQL/BSbsMHP/mGnIbdN5ID
Jdi1Sah6mI/NZcCrNEyGyJjOI4yH1EvPshxtHLeytgIu3A8G6OXwz5FHY+zNE3vQv8LEzdnnnHix
d23MkX//g0hG37UxSiOchQbXBg2MUyN2xwJigRr9nDyNDhud54Jr8s9ewjy3ifR0X7o1tw0/g6N9
QSNIoOwAwtXITp3/6mNF+jCP4ezhqgxMCXOnM3yLvg/HrpNaAvzxn/hJUwv4P5UamDW2VvftsgFC
vZ929NuGXWdOO+Ogix5JTbBlZtF4lSTEs8T20B/7ztv0nmVh4LBkHUI5Iwhbt+Jnb/UMC8Nff9F8
A/4DuORgma9FqsPzyPTX+3h4n1u5Dc0a066nauafcbTF4iNwFvFkP8xLTHZvCjp2veDY3kimN4iv
7njYBQzCqRuIuigqG44XKFg2EsTYJMYkvLVdLjVrbUigu/EUNI7V9eH35EFNZWaBYy0P6MwOKOLt
1RSklkhciTICYOb4HjWyUL7mrWCXY48BchoKlNNjI+q/0Rspn2BlV1iddg7Hxc+7PrnZumg2ugas
ZKVIVqcvDdaJ3e1F+HWmi688+UHNFBCNdI2wLJUmE/QLOA8UhdyFHGHwGTuWXjUOQ2i+YOsq2yis
NRsAbTVa8MPCeTY0T1njPDLOIB4cgA9yQ3yhaoM//a97bb4u9PZaz6YdwpdvWKUG9Wc0quLPjvnW
L+qkD4lmhrGPbcjrt2mPIK3jY3PTLg2C8zkMFatGeTnWUzNLZ2TAP1vPlsgef0OLblTaEVxu7U0G
cgdtgevwoYfgaSfJDqdI45bef2C/JgrRJquR2osTkfQde4/SxUaxDH+3b6UpXteQMCjgoEV8wpju
+ZpmlKAZklMzYMqkg7xdyiJRoByiSUWLtI58E6zbEhx5v6kOUzcue+UEz2Yd46DPS0B0chVZuKpT
nUEwRdyK8NxJcOXE+yJEG2QrXLYXGDYoddR89HRJYzMM4fmSTVUJffd6ntP8DVfNmvkrOvKiGuYc
E+OlmtCQbum8g7W3s6kGOWGw3WH6Xeu7w2pOhPwNnazZhqZSMAAfuq/J1hvChgix6Ov5+dB7EdV0
kAm4YGLCpM66HEzWAheRkYO7aPqq3gxAkZh29FFRiatggY5j0enCquoVeYZl8MK5uWB0fUvSVFqL
DCCV9D9uxeeDt94r7hYf/7dLXyqrsqRz7Z5BcIIDcdQxveqbuPdO4+JfVrc6zRAgQ8yXyntBebBF
NA6rY0p1ZSKJRbuK0oq/hWdW3tzXheZ682Dh2L7GbwChASXsYKumA/GOWzDttLQsbR0nIbUWddbz
iz5iafuzBfogbhbCqDEFuU4X7E1f6BPGeU7RQfX9o039Czq0th/36G8GU+rEtkwp3sWDQ4VaJTK+
qjAfMl9AoXGbPVaRBEltrXMwY/quBUD8mcgohy4YNy7FEZxdqBlk8dfm17FCzYUxwJMnhQUZeDWG
G6oPoKNBzK1NcQFyIZo1wit0GZE01a7wp2Sy4IROcnRwiRwyO7TduO5mgMzvbaDZICpeBn5cxzqR
OKAd5RxTp/FrJ1Rn8rNlDJ8SvKqL819TWN0Hl15c0yVuWMiO/CmZSgHmVw55YGyffJx0oBcn4p/2
iH976kvXui4/HyKl1CC9OgkbWxAwwXA6CX4h5BP3FT3sn34buB0CNgRtnfKeyLrkTHKOk5kMEpUQ
uPcDlRf+yH2QZBPS17SdhxedJvcZFJD2NLQdXDkL7sENdL6a/55dbmmOm2nfzumM3Xud+mZaEGsJ
rVS77AHJSG3HLF6mP17CWjhdeQBJdtGEOrK5ZCCAoCAHOsaGsd7NmdXgAuoE/WorLJy3yBrTB2iI
+cEfdKPhoYxaj7XFvYfQ+0xGGlucS3S8420Y9nSJnwfYP2CTrluyyGThWDe/RMJxUHF3MPFjDcvj
Qr4rP/TVndVGBkzaU7EZZryXjUT06z6bsqzZaiAr3KW1A0MtVQZKFHwx0qK39reMvqGw/grEZgaX
8zXWyNq4kRb8QZz44hfJZ2R1ArWY4/roK8TkF/NynOpWWBIWeqyz+Uk1vl97+303qdhJ374OAMOx
3xIQW6RHlp72ATOb1za4ozf6mznqh4zA31NIa+aRzyaPT8fZpz/0+oACCJIsoOSaWZ0ZkZNMWqkT
/U/81tTwI0a5g44jbk6/ZiQ7Mpiw0W5o8wLrOscu9hNGjsKZZBj43D8yrMY0manbwyz0e2GMKOoI
vQjovnyWwsezAFbfHOXlew9Gg9aj5AIafjL1VXM2M/gCpbw2LLEeyH4ulV7slgtnRIJgsK0Bq82r
PWaOEROdJvq6nQMZZl56D1en/A2myKD1v+dmfHYrE240JWTQMG1lTo7V1YM+3NPAYxg3xMkri7PK
KVyfG43Zu/KvhaJc/T5DdZINjTeULo4O3VKFq1JKDiAGb0fDTm2Fi4UC+UlpUEJpCXxrud8z1Z/7
U6o6z6u/D8RhgE8ow9LuQ6HpuIyQ4ZLUZAegNoKIF5HilMdbje9gkHwsbDKkblLKFCtPnRNbJX19
9wphpTYq7wl67Nr6t+ZZQAYaH68paNwDVu8GhGfETyiI0kSpemh7xMjaQsJsc9mBVwgF8QXxPp3a
aPzgUS0queFtuJaBUUaFSEY2YHfq9W98wI6qmqrjIH1ybHEr7AEOMAQf6bWQdXf9jdXEr9iXvOuw
A1lZKYpqnbXtc3Yj6b5P/vJCtF1VehU5HyZvSY7ADPtirMhdgHz//JspyrIWB32WnXEUST/O82WP
/FWpqtWjFvqrrmALrvrpS5wfeMSGVfupKglUYimJ0pl5pxmzGyjRbZ7daBGWKuJ8r9C+i6dtlHjZ
rmg0y0JrpiuzCsijYNMnHS3zfhMje8cDoVgrANN3tSGrDiAfths5afAqKTeR8kO5X3pYT1ucUcva
iEkb17UAH7E8Tle0rRSL6jN2D+/TvVdZT14ok066PzzcUKVF53bX59XZO6IWja1JEJOZtRMrgjgq
D1zoBd6qyHYkYD0HuKghUa76/fCw/jXBjY8nGn93pgTKkMm7ZzLTfr5qi+BZ9Cb26yCzDfBf+9a0
Wt1GX2pMGmxph9wImJU4mIe2mnFHR93FngZ4mr7j5i2e/fUAyzPbT/JNzai77Kt+NhcT9TUQW/FV
zi9eb9RqFFRz51/HTOLpBehL8Q1jLgjV9LlYQtO9diad0sqELTnsQS2ViNdLN5rjdhYdbyWKFuqX
Anj2oiongjJF6R8NBcZ9+UvVTNBjUXoSgSWbNc6rjISK+4TfMOgSWIWl2/UQEbQ7/cOTniKsU2wM
JniszONiOMT/6Qj2I+q1hNUgZBJKx16rsnl4KCtnwr/IgvPkGIRFbHmY2YiZRC1VPNf5A8Ys/OUx
6PBAnNt3KybMy39lpus15K6HDP5DF4k5q88nSQR/0DQKUi/4lFLw6q8R+ypwawU6Ui0PmbE7qDm4
oPP6JkeJEjjeRl9yZpRkTMhDcXBQuVbfl1TiKNHPbc328ZWDS7TyqIPEQb6mzC2109tbPoSgUQp9
ZuDTAQUlnlzLWWiWIPr5rl6Ijl43hc4W7CJ1AFFHMPW5RYfYTHg/lG7YTkVDUScyWSxA9xpT9r8m
VCNOaxhPumA/hyrSZlcV83/Wg1GqqJQa2czWgTxJ8zYgiEaZAPbA4RD3X4dGAUmWwtdvo85GYbl1
0w0Ah/l9t2N6IvvSvTPBZ2j1oJwAz8/r0j+vo1b4u+SEV4OtebhLCvAmhgTvTdZMrNv93foTyZm3
DwWE++L9PTkY/5Zaxsvg7G7OU2/1vwIrAPyKWmLHfObV+zAWlJJ6wdvHEAIvwagXxN+d0RVmbPXG
NN3/GiJjX0pRvA6HGGZaLf3FjqrjdQo1mS3SnK772hf1dnbef5mCqVDdQPt5DAj5k+hiYJLnLnbW
uJhWBlndR/xaqFnxuvOK9/fPn8VAJSSUE00dEvwwn7003NC0owSlbiQyEuYgbn5MMaewRSXPqwcA
T2f4CI/G5AUPaFBDq7zEVqrP3rgwl/mRvlyK1AO7h9vvEjG5iU7FXC7/7/9u41I82VyEMjZKYF0u
8CISKZWNS2Jhc76pp1/wW4JVV6vUT/8WH7tWtjcEa1LBLhTtrnFFGibrTmqIA3z7YY+S1vvG0Nnv
6Yak39jtDcszKcPedJZDW/C7SUNNhABqtvdCYZ49px8wxOi2s5LBnObM/nmXI9tBfC8Q2R4ZDJom
AKiCa1GThjk7w7V/0wvkJ6VufKYNFKB5shTpSPs5tCn/VMCQJoswI2+BH1PlDVSpqog6eQhRE+u8
NunGntd2ArnCR2Y1ZbJUk+9It/zmG4VJGDnGQWz02jGfuSKxjAMHLNqvdADrM5wrl3uEhx048d49
njP3hldrrrtqzDb2zh84n7BsmLP+atCplIO5pLnUrB4eZboTkgq4GCfCHmKrbtBbIOf7kJBnFt3F
pTG+pAxTUIOm7INPR94Pf/XpsK36eeYyD7NXChO+WeD+0BTuLvZzxeXW5bY2TUECyJoqOQ3b0zKU
BRVG8Ts0gonfnCOURoCv93HUtQEYz01fM35FnV4AbnPIFIaaI0IEeyko6PQO995zwkS0hSQu/oOl
isXRDVcTeCcR3fupo2Z0u56HpmfGE6lRtg+m8VZF9weIWsg2WipP3cz0INQpFLLg1z8AC3FnCiJ7
zrT43cQZef7g4aqJvC2ahSh07VLCIQ3DsUOA87yXrvgUL7BVB5CJ6bA/TaKS1X9BoRx4LfjUs/ka
+crgB1Jd8UzafXJlaVU+j8TrlS98P0nv5Jm1Umpy601Qzu/fI5VhtBAlwXNXRWEf7aStPjztGg18
pTkVNjcd4XjEGBBn8W3vy+EsixFnFgE1t8uQfK3o4JuUG3Z+lnpj3b9xbbRLZcGC+yYU9EkZI4Mv
NNPpGspQtZKnQoVGT0SrMM/7K/34/IBBJmCFUqbgBduy4kQ8tQodM5hd9VzoqlGvdIcPo88OWR/U
N4f2biLbMhL0V1M0lzhOCxmK9ejl+kWQUYabiktnLC5UPGg169y5J79qOgGvu55WQSLS06M7ySxP
7/WogJ0mKBoB3oeBbfmoM9RUl8h2JOrSpRsUVTNGc++mv8Ify3QEqAoWOhxHyLumR0AXHcwNTjqp
H/S7cABmn0yZ8boMiRuiJ/9Vz2LrN+VAe7aBAKHyrqOHTDlfaJq7a2vUMxsQl+DsC7w9w3OuyUT+
VQfwxXdiQBUWJsjJtHz/ZXexsguKtOjTXe8tjxn4rK7RwWShjE4nQ3Y50yG32TeV5Yj1mIZxLrCw
fFCu49wDebVfMbP5h3rGN350Jp0ctLRC/NdWGuQWJazs5NPQHR8TOo/aMncxHxNfu1KUrtGTZvaw
egcWrCO0/JpJGllcR/5Sph/421JI5lRaBC9dLMJtQQTPsVRpuJv/p08IkW7mkjabUO9UlAChOd4r
2HS6FMkdDKcVJVwI2FlFXToSk4egWRJZ55KWoV3WsFS3+VkGnQKl7uuG6c3Z17g0I/YbM2GuCh+E
m5EjOocZYlL0HkLZf9fx/zd+x2giAVSnSKnuzEm+xd+JYUaclNkgmUif6Ac3+fM0BA9J6GzXgXvM
+EqwWLE8GNDcAuzFgGZ67oM/YKMHgNx9KKltT1DMb4XMv+EYYB81hEvfL9ejyJ20XXwFdXu/FFZ/
I7WCbm0cc6tDQ6YSKvHCFqPFtaRKduT741JgRoD16Cx6J5CZzobQ2zQptsc2MfUElzPupOBFgyZS
py0OIDo3r3Qwx+Y9tyRXnyqUgTkNNOSIUIXHrLVKj/t3kuHa5NS4XTWiYTS6hOskbKu2FJjb+RUT
49lUnmvIGAqX1BBKYPduum2pYd2JMAgVviWbGzsT9XEW2v/jCygIJ2elaBt+Nw87184r3e1fsV5P
l4NPeZAKPmvjQ+iPpCdhZTuW9PiTgEUT1SyO8XGzUcdiiUPNfONgT9Ud0AA8mkmU2gbO8eT+Az5U
esEQpACbk+50bo/HfcJ+bIin323tszbBWd1deqz3QaOhvrkSZ0D/1Lr3B9eawLcXGAfeb+Kf5s6I
8bMiu4l7FCNnuCoCpzCvppSNAP0eDbJ3Gxm+R7YvZ9sMU4sHs+B7/fFnSzRsY/SeV8WluzQNPODd
Y14dGsMjRcn7g2afgv7NIY0zxajElssrtfkFeXgXr+cn5zIwljZr5SJRn+rRgKnXdfxvLHYMFMTG
/UnbH0YtH3PfnTJhCATjOzT5KEj5RhCeRg7+lJ5+gS0nlpDtwa7O+v0+G71b5KwmYYntTYxztId7
pc0zDyr/kDHIaGwa4Cm2GFL9XmT2Ep5y+XFAIkoRcOh2T9HR62cZukloJQ6FLk6aNJ+lyyCBuCx/
NksA+gJUNSuxfd6yWxqsRA4wwCkGOZT1H/tSlGRcZjrtUK64V4jHwOcca/e/a+90Vqr/9E/9ygRc
tsTMbTWz0ATtzDMLdhJBV29GqT+ytFhINeQAGScz0j4zA/CW0rhbDqKzflI3cd015G6V+WekekPV
fAh7cwmrscOhFO5c7zZBQlCKUG6Fs1Czi7sXzntDsWIrwitEbM+f/RhD5tBryu9/jmOY8n6cuD9N
6UkDLi9KmaJfbYFdFg8AbJivLZppc+Wu0Tv0fhRJ0gqHv96t1DufLnCRFt4lKUypVVSe7gW+uBLm
MICDb63kGew5gsKFnGNoyxx1G1J7iycccA3JzMN4FK2ZJ9iyh1HgLSD/PFoqyTGzHKGg5/z6HGTS
w+kMcB0HMNVcccTDiGkd0/IM3Da4WweTGrhcGFQ2D6HhEG5onzG8OpIQVtkSNPpppYJ5oMHGxNjt
JxvAYIbVbmtFgqsDnEo+ws7O5XrccFQUDMztTkqUjolI2Xnj9GO5i//RPXoLt4eN/C6GqFb8gZlK
27Ch1IJTi9SVU85GTZJBkILJ5RhwH7Fz3B1Szqj07zxeXENgogOpr1aDyeSIymnCitGxbNLdgV+1
p+uD3pjc3KyLi5D4r2fH2rSn9sosS0O+88UqiG5rroOhzaC3lC2w6ha6F1IDAN5ao2DRDZz1Fpil
8pTgA6GbBjsDPLEWZPqvqS/XtYwnNGZ2N8A8MV9/EZ6Es+B/rD9JNyfRs/FOI0lVc+3ka1hg91M3
0I0WADIAtMVaEEzG/PYOrIW5kHRQDpcFRBE2rSqWiWYrdovMzvCtW2A5A5iKo86xCFhNTr7WN9EO
vqw9Utb+EKXOpUzEICrlTLRmSQzNEB/wK92kDW5gyypb6yj+RibeAH64o6ibc56+fiXFxJ6CA4bb
xyQFt0fg8WhNiT4s1wPLVtKKcn1WlMaUhnyhQD/klCXoj+3AryZiOYQMhapFqWmyf01O809amOPL
NbnnS+Nlm+fOT/jBd8Nr7pnwfxwc+jhr/ZZoztKsMd9eYThH1n4Br9wG+0fOMdB9DtISBlXaHn7K
yu9FMIdTU1d765ootFo8pDF0/R/a1dLoNMcJRzx2SMIQ6WNFxWxro9gD8tdFVTnsmsWahC/taKsb
ElXlNsXPNAX0KjtP9EEr44dUVEYIOCJvMUD4r87X5BZ8wjmKBuh++pnYwjTfK3+Xz/Bf+fk/v5t2
brLt6mWI2p90MHK4d6cIHrxr6Jp0NL0BeYOXSb+aJhjs1f2Ut9i6bsdlVJYgj7R8fe8r391LPX/X
qQogHq9OD337nCJxC7YXwnb6WOD8V4tzY3Q4c3KCiiDm0H64fw+nAqpzzVDTX/V1dfp/r66gk9qf
RJpIfUveaw4z7lzF640+ZL+MGNAKr7fZs/QlpsdXo2CxnO/t4i/XdMs4PpA1BAMwgSFHmonhfIuC
I1EwRd7oQdrUiNuW5lwVlPblb+jKeH40W5l5myC3mcHWGNYGOy28/D6Ya+08HWySS6cBOcXxYEGb
LagqmEuilo4Os9bFWEQumcWAgi+RNep8wehyadZjYyU4ZfFLuIz5yg37puyMgKEZyczwkmUu50kO
NcKkQmwsJLgDLskrocYpaHAAGy63a8/EDou3OLMTQxcv/z+rbxC9egg6/s6tGYJkO5AcLgCO9kuB
+SLIl7wa6qnySReGnOUL9JD6c65UupPLPm5OgYPyqy9YnS0Paz/WWYjFJ2I9/Nu6D4C6bq1J5GJW
ag1l77c00wk5Fgy7m9EyDe7lXBT1mn04DEktB7vj+qxTOYHiKAZSLeB8PbTY16U9YgGkDNjG3pVX
2oDAJZRtsSXnPniByAm2i1VT1JYdiSmmmkfq3VtEQyuOyQ0jQobE2aYYaJDluXl0niao+g2wAems
qBdq2RXkCzfQrZpAgnqWh/9ee7MFVbWdkIZHcZDMxC1g7nO0e444rv/7kFE/3qjmiF1HdTEWjLPa
i+26eExq34T2/Py1qKN9n1dRVv1rO2EzVCWa5M17dr9BBLQCuqIvfjDjFO5tSzv9GazFTXSznEXg
iQt0mSHug9+prM8SVmg7MBzcoPAcgZgRfCKeBcp7VZYHMjN79Xi+4QTTGKWJEDXwAo8Mawda4gOi
nMJAVO5sY56VkTO1F/48pExzKqVBHsM0dk/II6CRwlZsIl7XWUwnC8wDtkoHZzoRjSpMx3z6qS+7
cWotrwl8epCcoi6+0KbkyNs/QDcqBgCZIUe9Qsw31O4XIoa5+Cao0zvt4AeV4qgIGQ4rX1aK/g6d
v27ZDU1obUM1WR3g4XIcgs9BNoA3QzkL2Mda6wX6jyEhfLiX5M58A1DERey3lQZowBBSePdtwztZ
/UYvZSZpZ2kmtLa+ZVpqRWrnDzxxLaftVH/O59bbsPS0VI+xdNYZY/XafhNXTfbY0Y/y6GxukdEB
PGxLYNn+cnfyKLmBAHOcvU0EbEN4rxrRScvYJow8CFKwNAV6Rtyg+XI8itgwrA/Od0JxbUKYI0MU
biehd7rYAMHmjLjjcHAitLqbOrOKk5vD0IQDFXPRItk1pJeylFTfuTwfMvW7jOnCuQEhMImIdWAp
VMFaj+bAfm3O5KndLEpCTws4bkB15vCrf63nny8k5pS9NeLUdMKQT7I/2/iadWcEy1S8GjUzcPFE
MpkFIk5C9YO9dXxRlc+RKXKmOpoUOYZH17S56W6KithjGKeJxiUqzNmCGj5lfZ3iLSTsRL2B8E2h
rbGuRWf/gY4f8F9QH++6o85di2hbsLdQ+gscz8BETWeSHYrjWosDCUFqvFZtKmFVa+QdNPfq9w5b
45ZlPPbP6HBBvaUQ4jQP8pxoIh6NpPUrqTiZQm6KaScU/WYCht2rhRbWup+B9B77MYoDQS/O2ST8
jlYN/v/zMwPjyevO2rIj3ZzSvl+vioF/J0X8WgAZKhCAG/ZjamEr9TrieZORd4G7NrU/rxDYOs3o
U2/cvHIZ+fhGZGmkFwm6YAmyDA5dujXVhsPyO6OITZ8TDQAFyXbaB3S3qVVgpRlzZPasgRsVPszW
o+q2lN83A4VBGJqU1U4PYsjvgewLPbZL0NZsUe1fhM2DOijiJQRWevreXn1xoS4cncAGbG+vk5eM
8gP2TxnsJ1GXiUENacr7wE7YSW4ttpp3KyLo24vWmxGeNCysPZgTrZrYVFXAwyIDfJIUS2+ooZgB
XGFSKwDhSwkxL2LTzN53AkLoEnY2mA2hMA7uO+Svv7RcJATK0unER6lEWXVHDW9aZ9bgI/qPtq7m
R8CVNpC1bdCvfrgaOhXxPHo2XGVNsYV5S6oMJCILnxZNmJI1ri5WF8vD/TZYKUtN1npdVCnuuwDa
ng4ZPvHVWX/vA+dH9xtdlDdBHCvqT+awgK+ybggpUwnJzojG5qY5Vo33TR8dftMdFaSC9pFmmLYw
HFa80MhaL7tnXMCl92OzoW9RXiZO9OXbjFyn+RsSrz2Vz4zTkM0NJwVXViK40Qrj38H9KRwLDR7E
TNCEB1Ek/bzGgeIgklng48G3YEaZqotJP/Hbc04A/OpVMnbvu1I0xErQbBCR/Tnsqoo0ANznj8E/
iDfVDRplYGv1leY4t+6pqIIhVMdD2gQvefHdjd2vqutZv7QxyES5TjIblscpp1Yw5SZSF+n5ZDZK
Se+m/KrqDUZqcd6KvoE37fa11rP0mP3/OWZsrTESo0pjxRcB7+41su6zwa/KBCrW4gxhehHukajA
7//5g2wJw5B9zOk2AEFPwNvuOdc/2Uzf6VkE70Ajaw+QK5M5KaKgnfk5aoN7ZYIWwPQaqmeYTecY
YSxcR8Jb25vlVPu86BU0PlwnMiP1DI9XJj3PVumV+jPgVx94W56XFHLE6KoVMo7Wfk0ecWaQO0Zx
hdO6Refuyf/DqJmQerbCvbZbnohRw95J0iwchf/iuZEIGYSlnsTdOmx2uJvCH0pvWKgr0krwXWMK
rEh5gCcpw0u/F/M3DElH2DXcQ+Lcihj65XVPD7FrnG57w5FiGuCaMbGyX2Xim0pbgagE9McDYSp9
bYsGed8P4/Uqv204v4kttjg8im9pPK1BTObjMulbFiYm1CCVv/v2eYEM5SdYczGb1dZQ9slx1G0S
y+ZmWFobZ0ON5KkWsd4wfPqtodMkJ8e73tiP3Be3NpG/hsol2OxnUNar4c0d3K6P6ZH1RR5OdX+e
z5X864lPAX7vyzh+xfEeuOTLsM4pErxiLGo+9Z6UhQPfAYr750zMpR/kqyltX8ShL5blK/uaGkfl
tPlswIyeQCDgZo8uLk+smyLQaRewjv0MqYb4RAkIP1aPSj0aLbTDIacgYDmldhi9BMJyV6cHXNJv
E5RT7aU6/auyDPzqkU/ElVN0s22WHV5px5f9WWwbSYuZsmevF5Tja2IVk/y2D+iupcD+0AmuJAXH
LgngZzeOq789P6aeF1ykz4EajY9xhB+8aghHoqvySYB+SDYLG9HofOJnVNRbYzfgwJvH4BO+GbCi
Puu14J2HiGhgx2X1ur48bQ+Ftl+YDRMBS64Dm1a3tAl4wUrmRcyg+7OfNwSwYuWgvOw4qbNuwO6i
dBZ355jQJfOwzlPRKImvaqIrazLuHmfPtY0ayuESjpxi/erK/yieXHs7jr351+UhwbqF6XidcQ3X
aUzd3XnkX9Ev0lKnMoJ6iZdJMjvxM3Ry3BcNN9q2FPSCXp/1yR3JwhlvPNkdX90VpsRjI+MaX62+
/rBEZuKvItkw9R/7eDviWE7ziY/NMb7QF8A1OqR5M4qut/42l2wvpOvU1GjncX/zgJ1Hn3ZsM1Us
UstZgKDqBh70CNhvrHtCKVa9pRIqhgi87Vkiq54TYHjRccXMU6bZK/wAAImIV+mGbm3nJBf7Fxy9
ngrZjkxVeo5eUsnOYbKC6UAOEkqJdJbOKCKNICRriYr2w9UFAGyeUXP31hBNpmydY9x8vH6cUQXD
guNG0MqLKjn71N58puYstecNgp6HbdPrFx/Ubr5nDTrq9xFnIBIjX3IQPkQUN23lUQ1pNoEPbd50
hPpjorLU3qwP6u43A2uZHOzkB07tEKinH9mtRISIYNSxD+d3DGTx69pd9NsMUUisGW1BLnfTZHx5
WHSn5e+UTna0p4OV1G816XHj17M2goOQlIvfklPPTL0OZu0afdlZQRhLHH3VPxS+Ss00Jl2JuJQq
XsIrsDIuIb+3rnYbfGfWk9UHxcdKFvqT7LS2eMvr3iYZJ6u1ccrYzngRA8TOLpMGpUm64GP15kKB
JS7zWck7XyJ0cO2Qh3AET+Q8vCPb226yDiVZ/IjTjrwitrMEhgXetxxDoRZ0TbjvoMvrDYU/D4xB
KjK79hV9TAdxYYQ6w35d2RTRhn3F46LCZTUDFDIng9mnQV/eeLDD3Qtj3+8UmyywNZYVjFyf1OGG
Us1Xfui8dxjD3/uB+QCYDZo48uZ5+2hQ+IDwsVt09zXxBrqIaLLQ97VSxGM4QZgsAdrC760elirG
cQ+PSq9quKH2AP3kFqi4am2zV6cd1xaD5SUswHKB7rqfJsKaXh+F9aNYECq8T4l5mS1RbqNXAvIN
XF1TpsI1Zy+4OYoH7F5KzJ+gQBez2Gt3loDVDj/PGyO8y9hevSYlsbuM0H282qw2v83Cj+G7lZjd
Njpf/anglCUv9zLlKRRyJDd4eiJeSYdJbKjUCxfLuqvoCwiHLleOEPMxAtagnMPlxP1GJetSTol7
Z2jjkmDh0/qFHBNkuZY6vNjBRbguPx9p6LnRsxD5/VI47WakNDIekuz+dxg9IOr4z3I6hNbriFOm
MlKbZQ2q0Q62unerTZD+Ly5hAIT+5en7+gvv23aUbGSX2mQrecI57JRvkVVlTT1PZN49NglEb/hS
6BroFhvu0QlptGlI2tTucXyWwVOQaAwV15J7lCZniTLgCbIK2E76gr/DvkaqS/tJqF4iqc1mMoQt
der3aotSAiCsDxZxR6v9dOsF2mbiS0sCFt2egMyvEJ8SY7h6nozub3Yfkr7sGZ0Hkco4BIjJ+0XV
NRXmgmx8BCVluaTCO5H0dir8i7/gfm1NolniRii8B2FE9DU+cy5aFjb+DRtopwHDdLsZ4tW66LQA
fGurvzlDSKrr3v00+FbZLcqZVtl9yM/blUfWv8AGgN7PrsPJo8sbp5Sxamnmnl+DrvFE4VOQ1dE6
Gy0dcpVFFIuOLv/MEV74kb7dfHHTJ8U9GaIhIsKMn4SCNvh/EA7MBTljDCPn3K6rPOhKHpS5LTff
8a7LvTNVB595tHOAVP8HOgKerwSgpOougne10chgdELGCuC1SuSMvpNYjhHYaqe/df1m2cPh4x1a
EfTv/5mRYmsjqQn9ZQ44F/IDrr5ddviAhR2Qu802/a+59U7Fp9yuXCJWmhl+ggPV8tEdhCZqrcFV
UUd80D9y9vYR/N/4TrDRR1jmGnPjSie7z4pkXltriyZZZwq+JjHRpMc5gJBOvNFqRxEH1UsbGJrj
/gad3AYZMpvQiOJAnBayOP0MYrVSTi7IrW1QmgoqDnQNI5+iKxwjTvht+bwb40z5yMqOCB838S1Y
cHLnfPX2svyDDDF/q/bjiUlf3Son+ExX+9VI+UrWvm0J/5UW/LBG0QFQnGgPvlmx/nATy/tAb3CF
n1Q1facY1LKKuiacngcs7U8j4M6AdLqORMZri3BCBcoT5AJtRZEndr9O0eFLXJrfAooSgwuID3Mm
UJRP6KeSuIySYS0W7YBWC15lbVmI9XpgHDJdpybPPdF49lf6V1BRTP5tRU7xgEiOynWRaMgZLJQb
H+Cfri1W9XtKRlIGg4oyFz2oW5O2l1UyiCIZrSp9NELKVnbg4wVLkT2P2o5yFTiaU/19bd+jRTVa
JIqSYaeT0Hd5w1gtUrezJTqrfNQJ5wuXAthXkYO/y9+K9AvGikZbqk/OmGn6iVPJ/1L+JYIkMdfL
ll1abRVBwcKXBvUKVg3tTjW0Eo+/tzGsX9cMfH7er7r4ay20l18PXAq3+/GWwBnALkkt3D1PfM2j
EiBmnzpuNRU0O19r4nsIAI4Z/eHtryEYHj7h/IFtgFAiwvCQ4I4L41sB8ny/CcrimggCtHrzq9Wk
V3RKgPhOmszsbWDmt9RcEgy58FhHQyyMWUZGinKABmEfOA2iA7RdALz3xfGWuZhAVngq/OCfdf5g
8JDhboFhr8MggRwBFGNSiwuS0Y+x49Hx9DfU7r/rStA+JZi+fYfH3O56qIr6vHQJ+00CtIXX/mEw
a2bw9v6QRFB5ssjsOZFq46MVNwQz7iD8QrxblBNirCN8iQI9ida2z6KEPiiLyMlCtzs85iZIUght
T1Rx9tGDE6x2z3uSTMg1LDgjICWt4EQfOYIf/F3SihiWy2GLHeAxuIHh26me6Oz8MGnpz1FSuRA5
41H/B8BcfOahn9KKq5ufQb1iwPYCE3FDu2GsOPmvvkPQWNy8Kafk45gJYrCY4LmtE7FOIUBBrnPM
MF9qLW5YOmXWEr5V6oHSUhNieyhXzMF8UXBCdTwu+JpINU5vXcBW+dUiCHFYsLM/JMNhQA1vyhAj
ZLFXw9AYm1Ra5cTeZi4Az6tAkD3dML8NsrLarDhi0elccM39Sp9qWrEORNNQKtSyme8y6Nh0/YP3
fBbTzDnUXsuEIDRmoj6uDyY90izLjVC/e+gY0XBOUpJDh3+k9J1gXSu8NcvdbGLHjAAd9qrx1JB1
b0MvpBHs+Zz4lCJYGniSk/qTp3YZM70wFuSHIF0Eiyx4nwzWsauLTJzkZX8Vd/eeuA3QABk2GPtU
RUuGvp8Vhe180fpfKEu3lTpIc9u1QrWfrpq0C5qXqPLpBs/C2odGhRToqp9ba4SorWGwnpWaVZl+
Zs05POe5hKX/taQzSTZFXHg9nf08GQhtURR/d9yLKYYKxA52TqCliUyepBQ+AmykwAh+U1hS6Tbp
f1XeSQkfc/kjtKOEkzombE0gfV5Z+dNki791X8f4wk7a/JOCp7qL7n9BuhtBywWHytMnkGOpo2/8
B8M2HrHcmu48NbeC6yrtUGAMtc1/jaNrIXDwBOL1kZIYaa3ZXb00rd/n5xdmAsXwtkZ70OpiOWIt
YTz0zyzNiE7wBYfY3ZsrytO11mPl6C+kwdkbRdnckm0tk08eRCpPF/B46yxQ6OOrm3nmbF2pGBbv
ceyS1FF7kDDnP1vCO1jvGYTjvhbDugzhfN1GTRaiVHgsTh/PbXPT6zSxaTNuNMezCty52pqrnfAe
irFRDdTMOJ00sSQTizN6IaJHIIPuos5ym56mT9OMKrhmdXqEcGKwY4aicY7pBVpTluqSJnkpzAI4
LVxQPVVpmhOcnf1SKqq1WMHkWQ4dIww/yayQO6W/WfeCwb6lKA0X4wCZNMcWZIvK1ywficzMpLLh
yQ8qfhyrpSI3rnN0IPhDItvDujDbmrw63L3QkY7NhZ/3rbB1UUj5ohqs8buiUB3CeyMog7lXs7YB
3L3w2QWy2Jor8rDQNORHaf885ZqCuB7KxsgE5WBhOflRZXuRwJ9koG20nH10ObJvJX5il+PgTZ5M
P1vXwNyNQOuy9Hmr4kZ63U2euiIprk8I75N7Gs3WmVk8CbE03jVwSbxWzJ/QNaEjGHoJzfxTjNPG
NU0Bu6JAPu6tF9mEoxaCooXEaYbkxA46sVInOWi9gbG83kbTkyt8gq2jIfQpEInh45hP1PjGkZHY
/OzMpbUv35YHW8YnF3/uMzC8qn9seqUAnWxjd9UQP3vLnFK+3WAXJELqCwk3FX6/Zr4qnHXD36ao
U1N1mfuB75Lw4YjZR0P9uQ4UCJtKR0+ZXASI7kkhlDHpWVj6QXnzEIcNKPuY3JkcsJYhiQlHwUoO
jwEaxuzv9+xkrLw5zXKcp/Oie4b5dxAiY6V6jNUk8eC2ZxJcpUO4PBwAQ7J1IpcWjLIlOuZ0IscP
P5BsD08geKTAeXRnrRJ+lXnmDEbQ7xi6rWYkRKrm/nydemJVwaTyBtNZJNLjGOf49IPhE+jDYbfv
HjukiPZhiHWE76da+w0UdK8sJGPDPKYZB/miaQ6jI4Co4ga8pBsy9HFP6PaTvzWKf2nK3tPdg5zL
svF574IXGQ2zZBOSsyxKOc/+uEZYyDyGWwqdwE3oZXpkQFIIkcA6GQhvmSK3iq+VPGyJRyKJFLlC
/pG5b6OoLVS35ux9nKf3djePTDr1VmsnWWe3lgVbVmInjieXK1YtPD6a7YesRXGCcCV3QHiTAXkQ
1kY2U/+A4qJGw6X2bHmslIrN58eu3FH5yEh6dN4uVCOO35Xi1rN7KVgnmdI3LAYjuPEmKeSBizfJ
ow1R0xASxc0U0HuM58yZ/OpQKRGKtYPYGjXZLGkbtiEmSJ8KrezPAIZvABWrPLPtAzJh5pg/3yqs
LwSj0zKW8aXKs+C8RKCGx3BEPIOV9hioPxnNLfP7O1Ud/8FuetrGjupe3tf6c1Mlq/Y/+S4CyW33
SMc1pkThzK6xIZe+U4sFl0L2ChsQOr29y3DbAW6pdpuVLt+nkzd64SOeVrgA50sg+3lh/CtpdDVd
M7jz979e2m4Mepbspw2zm3vrPjT0tvL2ZjxY0z4yqSgSc8HRF8kKHetmP9LUD/FWpoP6Gmzu+KFI
v30jC/JvevnFSWRuvZYo1Ef1ixhI5WcitLoUHnNLnk+vrZu08fuCAS3jWtlxe36G6IB6iWKZu2VM
lcup4FwToZo9beT7hJp2XzXsvyAbGJ6tnGWJ+AcIW/DhJs8JXTwNXUiCybb4JNz1esm0Qj791tQF
XpjUFPLWalCj1QS4fsoFJItpJLN3IWU1Zxok9OrnwyXNnkmC8u3y+kTotm4i99CRpj9WGOJ4WNb0
wx0kSvDWyq/jNXsBffnmPB7Gq6ZNs64Ob2fJtJu1eTzdv/BS96OLdOLc+GDg2jPoUZkbRVJS7SZf
cfs/o0YoM2EQrRfCBMPSrxFWEWEJmkNlcaXXK3x3MqpGCXlnLg+uEG5o06Lhb/m4qksgrSzLvcMc
YJOmgBILMGr6wmfCFAbImKEXaUQIslGoWlrSPsnPxAUdvMR520GoBQvJmwYQZw9jX14XP12+Y0x2
3cHvGGPeEQAls5ntDaFJ5v4VQoO6vLfng+DkeiXaQwm/HBxf94ANPqJ2cuEZOLzduC74NiBGjEZE
XtegkCJ3Z+zwej71SA/orYcTclf5EOg15sShmPBa13BQvW66hmj2dEbEOSeFPj9BK6T8TWpRRoUf
2o3BgWeO6gPy5r3JjhSU6CyLc9J078orwV+o9soh1T5+7v9qasMg08bzMSX6hbGsjgPfgBIxXQht
Xk+C+dBI+bkoe19zKRbtjpMZl5lhsDmwtz0MNM7Z/cgeW4UYlA9VwmKs8oAz2kCiyl7h41Mnhnnf
xEixgUU0GVreF9Sd0d7M6CLq7biZ3tSQroDM32w0v+aRRXIwIQG8Ld/yv+2OyTQVl2A2OwPMrOJy
H6g2fjLkNPk+SE0Xa4QEpo67qZtQqO1cODfdbYHFdGz3PBL/OCDS7fznKJ/XrtfRY7Zww0EWpfEv
QCLdY90/B9xUSzvZuOsLjXdY/f1gGAufEWkxCD4Bsj1r+ro+Fr172NrL7SUhf8qSugNfWIi/AFw/
fVlAlmE+2/m0FsM2lHsMX8kQNBfBiOVr1uKLMJrWRQZLdCtdYfhV1sQzi6rblFVFNgWDPs51UpBm
SsauH9yWmcwd+aayPHHZy1PMo+CvXrv1HD6C6dV7dB8r67pdZ+madV7AHdFBa5qT026ImO1gw5u7
tKKKaxcbPn9dlufilX10W7LS5Iam5ldnD+4gSkt9ptQsRINgTXaA12zt1gDbndnM+qHEK1Rhv4Rt
8RaOcpglfBeb+vsTSQamEy2m0YYgwqfhO+fmGxPx+NJ8OeOmiR8/8mKtffQFDqqevdtQbcqh/e6F
ekWrzujKKyihnfiOZEdLTWVAAnKCzDa8TSREOulE4HVh7BQhN+ZWu3cmhtLt8M3/gkzw/VWq6nMQ
odq9BBdwT84AmN5j2XnshfCMLqQqcQ5xs3u58oZI9sQyYVGXca10EKPnysKUMoZZIH0WoSLIKz2z
W325e9Mb3h0JAuE7ejc4jJzzkQOIeDLmFrZw8wGA5ISpfxvBb/ZRDot7iDztyX+za3Ie1GRyn4EY
2Axa2xPZbvtkPrJzmia6qLYZcCMRrCYGFHPf7iNZXu1A7sf10h4H9mLPrzicyN2Dyzwth5ExDyiO
Io04R0Khc3Y3E3IKKERT0WG364Em1dZolYRJSFr++mselrPcNW1uYdjruYcmEyHB+rH2iEYp+ppo
XoF5KT9r9I3AoeqkuNBnoqorNaid898LCpXq7bwLFf2i9mzkveJYuXN4TN3AlxRNu+c+Q1DGfXYD
EsGtjz4OnlXlg0goVpS2Hu0tSS44pNBzWHmhJIfJkGwaaXG2IDvWot4K2RtnBaIHkCZuFbXWbaP0
P7nXKVPfcvMqb2JUxz/fcNYxw6GMC0Wx/aRq0VdwWY90m+t7qZOXCMASB0V3sUHKLPFJfWLoQ8+9
8IiKz71gCwkGATz5n5mvTsLO3Z6xUH+/X02NjKZd1gSHrsWC1l4og+Yc15Djk42rqanhRYks6YwX
ck9VEKxv+pq17KIcm/iX3vqtwjQnYwU3iOGIRSNo/hJ6Vc/B7fVjvAskO0OWUoogOxhYtl5U6wu8
ami7ukubPWijKtoQZX+r/488WKUWBuTevyLsvjaHeqFq2oszeaoWBSaJMYYAPjc+4ICSIHcZGlmR
Z794Z/r1sXlNdKItLza7gs3CM7BEBcQwF45+KU8ZlqUAO253UsMZ6VMv2vrTIikFbXZjhvbjy5Xy
5iBCrbdNEX8Ib7ZFzRtt0vimXu9ZqTnow5fDAaj1hk0Jj+NsvgqaOO/r+zR8HVxwhiQIqczuKoS1
RajzU8jocqTGExqL2cuw29FgMWENvJei4jyeAIPOZ/M831MD8dmOKqTsUfLgafSgCWJFmSgH38E9
gS2HVOomxFs50+Bn0nnT6eUdVjkk8uvT/5YgjA0Y8Vu050OXy5p1P380DxK7nuBcRH7u6+Rd7jgU
kFPuK+f5JwUiXl5MK5t4eYQh2Fr69vXf74UzYWkxdWoynoZMkNFT+uXgKM2NKjNuoZPRtN1vwlDn
sZThAt8QRmC02lphNJeCihN900jswwmrOKIja6FB9kpmRnjhjvmQtWeOQySc7qaa1BqQgIE/213I
x8J8nFi+enyNMiHa8Ijlb8SWtLFxEFrEx18KrX38v4OjvdxW69ShN4C/0y6EUNmFBUD+aNMSWgyH
ASoAYBQY5dbnO5jQF0aDQI4iVxNHEXKTHKOfbXAvBKYg8l4dMWQpDZ7fDjjGLr1hRzKU9FboOG5q
uds2cpL+f3ghWwEro1jHtPJM5dkltxHgO1kRvCl9U972GnAOcaGY65S4SOKnMyy8Oq1sCO13girB
QwMo3KE40uoZpRFYk2kx1pbX2raHVdRIqp0uhD/S4aDlq2T+oAa1NC2z941gyO4+wHn4+XyURnIa
Q0g337YvcPNEMZXY4DD1v7MiUyDsYyMNr1ziLKcIH5oiU7I/R4gIE6Hfqsz2xSRmxYqvxoiZ3c6G
z7Lie/KWYcb4I6HCgovADkzuCzGHT7HTHFdyMEZW5C7v38ET3WI7nEDyLWf0b4tfat+tUHQ9XNp8
WeTrhZBJRUXg4/BEa+4st3F41O0Yj5Gmjp2J/GZXTYaKi9zGrAzGQMj/hnXPbcFEAq9LoQEDl+u6
BV1BP8Y2smn0fUMXF4QkaCLqR7edm4NAm2d8DWnvASSnLrA3RUgoZSczDot6QZ3pvuo2jbDc9FdA
h2XrR7EBkWMjjMaOw/PVSoOz4Gl7LGRritLkyvbmgC+WrF0rO8kISsSAsPKY4SRzYE2y5DTkh9/V
R+lGbpCc5RQDegQFpj59NmmZsCfJSfa3ORKiKAwq+YvdpvzhW4FR/6YKYDM6I+1LT6+1fLvav3Vw
1ZKUpnIb6CNDzapUMzw6BuPJcrQkTJsnC+1Qql5WVmfe6cY7ScgfsVM12fm0Ay8Hq5FzbmlX37UF
EYOyT9r9HibjBhTFLRXJxDv7JmIqLcBdzGGaxXlTohaM8XH+Z9/6alGlJb6dj64Z1IXaQr1WfENz
cYICZX5vg+vr3YX3CMCx8OFGsOtJIfnnboX59PMjjO4gTDcV3ukJNc6IZMhiC7lsPAXgVoQOAHpq
ckaFz42CZ9VQI3VSxFOqmgfxFn9cr122h6PmLKQcu9LkiFDGS/MbeuQA2vejt1OtIOUEa2yDP3y0
jVqJk1MDg92ej8Ea1kWeHOBDYZcrEC/1KIQwNzED3nL9CxednddMdXmJNjzdXrC7bMQPSkYfavS6
qoLke6kCpPXSXVb2CRwNGRnyjedNJynESy0yHZnc2cGWjKDWj4dQN2y8lizbpAMwJvlK6hd+Yrr1
1+E2en0k216+3reX9NvwZ3NJYzZ5LDMyFVhLDqTqvZUEeZ7xsCb3R2nUCTAdEVL8k0o9mmj5QVVz
UnXoG6ZhSlJvglGxBGX2MIQSkSF5DC3Qcz8L4irECX0rs4OLzVPHYh42XqU/olRU7S5AyU78FuC7
ntRReZ1QtLPNXTEWwlvcRuUeulZ9xFznagKKhQi0QKHuhHfyownLVXvU3I4B3PGeWTQ+bEKP41j9
4G1p2gN/lvccOSF5hVBGlTxa9yFoHktb6BUccLMgRoxvoJT6eODtqiK+kJYW+H6D+t79cZ3HqdtC
WZndHbcMu3fUL7eSt5EOMTE719BlB8W+XgCogV+sXNgvVgJA3QJkExY776H2Fkt0b/HBAlUodCod
xk7sp+ldDTAR9Lx2KB/TgXIFoS3WiuDVArE1yNQ9nleDu4ShzQowavyPYTdo/yaOrk5g2+LSHOly
50ulxJ/8YRRfaCd1NbT+C6CK4KpVEKMGr4ogbwIM6uHxh4S1ldUAhHHp2UfX5HIgkP7Zzcf/ZaBX
ZrmLhIlaE62J84vp4l4bPiTLiuceEedJimmJv8RvDw2wop4PQ8y7KzSaf0qrkoTYHTwAWgMGG+R7
WXTrh96Rr5CwwPeonxLfDHSw9EaB4FBy3/GRPNQabc+ErqZnlI0J9nbJuVXy7zEnYgfQ7B57Ns32
BUT1lp27nw0FBgbAUuiaT7ooAJ1FQAzcNpzFUl2udwMyaKd61ZngUXxp8oL6pv3U1nAvopr+WeEf
7QLYaMIibmco7GA4uuv9Ztfb+xVwm8llcGZPcnJ6vdLcmju8G6IbACZTMcMTmZ3cVW4sTz+BrwkS
mNzn5+DrUyy2c1l4tbQDrqdxg7F76ePumpmVIPp/2mXwZDCvAWwqSoFfBF84adpaiQmghVOyqLZM
rADx1RGB2V5+jmHFO+rxEQm2KpyrNIiN+VTy8dNUwbBt4ZV2p7Y9zbep9vmGD+lRHuWXJucSiSEY
Mgqf39UqXegYVUdmefWOozG7gt4mR8ZtdCcpQLt5U3YXtnfxvsJPKgdP7KcIEC22NiOADGS+ax+3
QwS4WHHL2UF8D7TRMHDmKvmam+grtoMJllFQDY5f2IUa96krNroaPJLpKxGaJ9n6vTmEXSsA30F0
Ue5MTnewLq4grdzL0UU2tXGCA65nuSeqGpX9mPLabDVaM0Z2FY1qf/Z6huB2/eSUtdsv3kQLWMTE
4b7YyxMo6ZVb6Tyfa83e5RX1B/0mfyilAuZdb7IMtonr3hx7k5xrxbK04MAMQHQkT/+80z6ey8x0
YC+JkP8tb1dWQZ+CN9DK2jZHByy8jbAjIqmr71N53TV2OUhTcKUVXxrpl26/vRK27FsGeOk5WypT
yvLj5wKTvdjAogpgZMSAdmheiraDrtLnrh/FO8FT5RMt0F187v4q0Um45oWYIKAjbKLH6E93+DCg
FTPNxFRYfUJqNP2Rs4io8HXQGwh0StpKBMixifKUFmcUPb1JnQ9e6tNZRUACP9uDtQyOdFfft5Ys
rQsWIdPOSf724ugA4iXqjOpjF5JBGRioM7km0f+T6qHXe10542yUgCCdhxJ4vY1dLAWE67K8SoVG
Q7xUi5uXjli7r8hc24BeGJSniYTIfZiPvLe9CG0HlXPTEtUhXMZzPxV2mewkZyfC8IBtTCf3qYQm
+dfYG0i/D2FFrTWsJz4Z+E85JDLPRtzE2oMGs7SR6sfN3r0pV5OgAzATUbQBMXRhuHxkGzuRX6q4
nWMu47iRUY3hJtYkCWdGsdBVSbN5ZZqlYV1C3Htir3nb8SXvBcWUWOG93lEsWH1taCp8lO1AZg6j
X1edG5FxEgz4j3rh6E8xdpRmeiNaJZXj9SV2yIYuBzQcw/4QwiibkcDh9EEbR2W8r8qGCzXiEz6W
Im8v4MlQRNkFm60KBb/9fEzpx8rbLQirwFwQDdkAXJT0cIsZMevnGSKUIaC009YE+3eX1eyjV9EL
4uraY9ktWbpBGhIKyua3U9bB62BgRDBPUSyGyvygCef3JsoHhg8M/PBpJ7COJgoiP1bc2igA//9u
tSprJe1l6biKPiOFiD4l4drAbJ5d5KTgeELdDawa3IKCs98Z8BlU74HHN0Vjcc5Bl87wfZPCjDuJ
/8zAGqB6kk5gCzHz5xM91YSFktQVmg2SKIHHu5Cux+HK1pLRrTfREpWDFMPwnhO0QP+LaMsfxF1/
n9Mk3LXIF4YoJI/prvXu9Bh+YTcaW7bpXDbYRFD/09Hca8MKCQF9z+KTKRBG571YB9Fmw95Adxb5
blfU7MJqt5SjnCDcTik78pZ8fMQXWUwjFwrCyhRdk7C75jS6p0Jn9xwm+8psQJFPerHeJgsKvczR
zsu+PYSPsvJydMGq24irDU/gtveGsGOmnPSWsSpeUuHOL4n374nw51w0f3qR3bPA0FINUwybCs7i
fXgeE1+zlADPc9kkvp2CGirluNQ/MQxYcm3rUnYxTfpLv8jGqzsVvzRXiJaHgtFXzh2evzeHoHzm
WyBvv5s2iVvkwmbpAnbNqm8N0L5dFDEuRI4iL+RKl5BcHKTJFEOC45MFgp43v1A3suQG98zvycNZ
mLcPRHu/mVSDq4/B2Jkzk+xHZdPxzcVF45dh9f+Pdey4T5l7KxmDz6Ak7dCoRli6Oyhs3IaAtkJA
A3+jvoMz1x3cLvRRECrgiFENxupytvaiNXWeyRqqlmj7zdMfYo8Lrlp/Sqy+IZXDZTMCWw0daSSH
AEz+1sKt5d7nrg7QrvySLxuYCyPXWH9zIifkTBqxJh8pUaZ0LWiCu7Vx/FpwOqVH2vXUF7G5qGDl
/4fNBzRFf7f/bMa0eO58pNbvA/LPme2eHW7GuLHMT7fC72AMf44yu71fKztdvAcnOeY5+qqfTqs8
vetY4HW0vMdKuw+4339J97slrMVv6YlkTnI11G6eEAGGj4SWYjqo303OT1FlNK2is/cS6yKeQADb
rtrGeBn0qZV6qiKOYMCgpASrkacWi3btZa1dG0dtvzwEuUH5Oc9ueyG/ajSCrbrnpZ7dJJQJp0Kg
SYx6MCm582wwclQwnlI8Cl+mq2NPyPXiE4a3E2EDx8PA9z5TJUDA2FIwsvKUcrTrPvzmgHBSNdtb
WCC38ieVyegNHvs7hlAGfWfg5jB/lIR6AosKUNFnOHObyJX8CEukYr3N5wj0pZpLfNoKuV1La0xb
on+Oc6XrF5zlMIVb6ZqfUhBFXIoWufQVUx21n+IGl5fLZ46yo9cgS8cJ43vI61290N5qXNMUgi+R
cdDR9xRzxO1r2HZuS5FJhAX5xjHft4N92u+AU1LgG4XsUeyLuThPStZYiDcXoR6faLgHezRcmEs7
nt90J22putepN7WxPfZ0d02WkiCMuaC/YmyoVilTI/xNqhwDkoc/0610fp9fDLixIQ6Gwp2Q2wbO
+4BL1HS+MUKSQRspqHSYhUdlSO3NzM1PqH9EoFVvsdxBdyALt5O+mhy/TX5WziEemyyXOmI81sPA
srdpOhYeK4B5HMOGDoTBjwQZFffM/9JB4PLV+6G/hRcpXcXSu7iUJtmzbNiTcq7Z/V0Oah4cXyna
6Fc6pZ3q7zQx1n+hGVv4ZN+E4egishxBqRvu3w2L7a8aDH0dnAdpbi63GO3O4xMW4M8j9rkUyC+o
pGp0gxrxG64oBKxeMcHy57/qg2kgauN2W1YiTiBbqGzQ+afFR7Yb1VfJryJoHIdIjgxQ1YyUQ6ss
+rCKnTbLa7HIKWjuoqrnM5BbrgZjXlLnOZt8dGz01nTHK4Knv7e6SAtKlIwZjJFzI0UdcwRTybud
ECx13ORDJzr2+SZt4dUPSVSpeUUBcT5lZHQKhOCZX8Pr9p6Yi4CnBF3x1DCx8veyGTzYpFqGTB2T
AzJw8pa6AopKobNuFwGmJV1lojPq6xq5FD7tPykiMpoT6qAo5te7hAlmb2/FH+63YfL5Xmz5swaU
oV3yaU8pdzwmb7BuDNhV8FuZeHoKvoCPEaed3/VHNyhQVoTOS8NowHe/7m/CskXQ0SJytSxRYXWs
SZmKaG6/mGI7kMbIKY+rTUDRMPywxMWBJRt0ichLCgNcluHwXJDGKZH40v6Q9MWKyxXMwYUBJPrw
FwHBbQUTAZ6KcMLyqr64EPTDXfDa9I6J8gwhojgYph/gOtRut6yDZd+scO/wY1w6PjJrfmWcZPds
CWkC3+MIpUsiXnzZBKOPumshpm4o8aQtZ09G+8fs3RGPqf/GgZOXMpkCLuTyzP0Ix0Q+0nEdBhWj
dYx5VMbZ/hrxspZqyoznoTRPY3GZo7iOW4zugUkBbuOXDOH8cWXbtx+Vt14TxAMkJfysS8P8byw8
enAJb4++Vjsb1EFpRN8Bu/OU1NFWCRsX2hnebKQJd0B3isE2E/IxzZtdD/9ZVjLUBNz1DXY9Pn12
Fz5n0Yf2vHtnCmaiEoF31Uz5A225G7fHP6BvARsabAbjyGd2Qulpvk60/fTw99+IY6+Y8D2UZJXX
D0LMcl9AXhOxY+VjCgeNc48Ab9AEjqh6E3kPeLqZp+NP1CypX1hf3XQNej9UfFa/4lQWcaBZA6eK
MdUdsZ26VKGefHT7mEoPgECXQUHHZMxV9+eFJn4MSSx3aFevY97FIDeTeuWT0/Du/+cL0Fwt3ioo
qajuV2EheMQJafro7KjqDJmwdi4RimLQxrOJbm/LOGaAe0TkePewbioC6q0H6lfpyzP05TjfKuqE
AKkXLW1rCkx2bPK50T8e76Pldj167pA/hHEmE/obfM+YVUNfK7YQsmeNy3OyQi9PiaD2mvhkA1Qk
rVhXAUyzDtyT4r3U9JfBHrnM5BBO1tVhIlxf4eTDWZs6SA4/mDZfArTKou6SZKQlOSnWFprd+Lkm
nY2B74MNaMkusclebwBfB9ywErQn9mU7Rxp7F/I7amlZ+3SgQLoFWILmQaNgw060aQWGjpcMc9RY
nsYmPFOSjZMY376CbhpugpsadRiOGS7i8gJrcwCkSwUIjoxdOaMlmZkAtXhxw3iZ2Bp84lfHVpdN
JmdULpHoKLbj6M4/RNfvxEGC8dTZhdUN2IUuc2W8r0irjnz99Rg0ibAKs4BgKShDVo2VYXhHnT2E
IDrhwQ/8WeOokslfQEvvhYcPpYhKDxoNC36xcQCo0GSETShq4+D3txJ1NRe2wR7k9kdAXQfmNCyr
m0fOQ9U51OnfG4TSRnULcPKhM+VMuQydQVk6rfborMHgUyB/oUGACSqLYm2jNX5wPPuzFw93U3Fs
gWlNtgG0dZZj46ELbb9at9wroPGrxUWBiG1Xy7hH0wXIpYIKmi8x9FRVtoAiIHf5HQwo+zR+JhwA
TRrDviKdjyusMolrm1kkLBPc2q37baapVBXoLIbslUHnpp8Kch68fHUBwUSLguPzHN9NHmZqqPJo
jVYeuX/XXahh51qHjra8/wX61wHRsJM4ir0Y266U0fm7fNnj5c0hm7a6U2FDsjjsP3mwxhj4g8wm
OTp0PJvoPvdwi1leVVJUPY2pxXTjMRKMWFFE6poA1t0pqRP7EKED4urNYJpMXLiY4OZItUV3mtIX
kgS34emZuA0zCN53yhRJ0xEsZ19H8R90T/YkK1mnwsftQQddbOyZn1KeLcGfvqhHeSufc7UTrsnM
kIDafSlDPsJMF+e4OGAkNk5YJhchCsHXYxdnEtB2NJnAkJogWjek6lnJYeduZEYiyATDxWQ7UEh2
85RpPWhWRN+UORfDXsjbGuwqxL9FaBugbOpaCNH7jfRU/CKGakW8giHCGHKLRhG+Avm9GekSgN9m
6RQwNW6f7kuDlyrlE67fXPPujz2BRQ0W57Tck1hX1fUksSGQwyBNHAPfSsPGF7LcJyr62Jrcobth
WJNwaqg4b2qgEnsHxHgMhLYYwrJJFU373XB+NBZMSzWG6IcTBuQPBuHzYNbUz7tqQmK+3Yf0AL6p
A05h3ViKQRq7FaZGn2xVmSxJex/AkM42a4OJ/ohm63E9eiTDcBBMcrncdJI/rsqL8P9IjrTnwJpF
lYIp8CkzRqxV4AVFlYS9GaTzfrptJPT4LMnqJqxeNLQmCLM8cC9Oi+r4zmaClWYixZkBNzsqKgOC
k8CtKZTMlc7JUPgecncz3Fw5En2LwH15rPTVjsF8900HjeYcJenIIKzrKl9hr9GBQ2cgcOWBrSfj
NIXydf0RoC/TjmH+xR4DjVjrUbD8S9oiC7+7B3BbXYZOaFSoKJdpqm+dDTwIo7RS2uz/AA150u6c
Mb/zdP9LbBNJRDqrq/zj2fvNZyFUyoK6XHb3arBkVUjaPVZwOpP3eYx3tgzLKKlKzB98FNdmfSnW
ITQI3dhmcPisCBbR9leFoYU7Y67n58brlPdN/cZlzKfOTv3Is6EQ5CI3yVpJgagKxPmD1oKL2aXP
agI6Bgnf8RiVDun/tchxb2ZAUaFhPKRdu93tpKeDiDrSNS7ayPQ0s/ug3HQQylR9yg0FoD3EOAEI
qrVpFizBj8EQ8FMAn8ANTs5dUKAcLUiOS3GNLU/cuTrSwcsTbHGfoeEmvyHQnnDiPDAJeO5mGcQE
D4yISSc9woYwWNv0aHZydbgJ9pSOLEN65kJpeA7NATU53EY37S/5ODr6EEVExkmRL5s0AvxoI8K+
EA9Cu6vCudBx3Wcc0/eIcd8wdExd/xGwmgt4NtyqyiRubrjcGjwvTFQElEBk9YOTfgtTPjWtwtpH
kjJEwJJkt+8HWiNmsu8Owy8+Cj0brlqrkf3DpNjvoHrk6yoBJJTnNbLR1htNFLtYzCdZSPHAEQHB
WqDBl5dM7aLwCn8pw2VMdZUNrIp/PMMbgkefvC2GkRNbuvTS7Txycb9zJ4NlSyT81maGVrMz0T33
k9EkLbg5i5rHbL0Hts8l6Rd2pAre9K9vOJvUEwObqVn6tnuy749K4V2JkBB94Ad0no59K3/UyexY
nzEVVgfwO5V8eXdSB6mXQ/rbTHl9UJeab0gvmH/gKxOtg/KqPNp46cpcpYmlw6eAHc3EG93ioSi7
A+IPd7nrlv7o76YMrN0+m1TACVMNSvXsphbDVEK1HF79dB8LWxyIet4hsL3Wzi4im4nUDF2fzl8T
8g2HvmyIEE6tTC95uaCM+4gHCjz1S5TBtWF5NQkDc21U4J3/RO+1eF/wXkC0cz369g5BYApdwW/o
DUOugQnp/7Yw8UeOk6KGxCSa61pcR2SNjQFbbOFrxh9jqiRXEfV6VM+IuTRfMhpu7wQV4Y69V+p6
vNYFy5uI2QHOkT57BtS5kqNrQvh5KOeSnnC4eUt/DgLAAZALhFxGlY1i5XlimExu4BKnkhZxksGO
3+jNgEnY8TEvkhCtRXQcHypMyT2b2svCF2UIX5GOpaKSIyByv/virFe/0SldYF+7hY/GaliE92R9
LrWsYKBOerGUPjLMEDt3cpeXJREExmXSC+PkOYW3c2XR+/pOQMRp+vhM8WoTSatCUguu4hOK7fHs
/RwHaRaXVJPeCuTfl/6QEl8xEInqtb3MtLX33UcsPkNVHZTkLSFl2aCG+mbVbTnqSL8p8EOtazRp
5cRq1FpRWoBdBxXE7DRokVgnm6gfaMiiKwV6NTB7BRlULCxOnMSN8h+dCRoZb4lMGJxKf5CaQf2C
BUEoveNnllPEu1sAkdRXPWIXtMy980fDvi/qA3gqzg57+kUUropaRKvFCKCmKP011AIkfhcHQNBB
ZvhWmwI1N4U/tOCcoKmAvrSW0JUg1c53lMJzkfiOMz0CBwLjsxahRoLKaGBvi+56DMXY0NuxSapu
E8m8+myAWdp2Rj12j+piYib0jQzKF0MV8fEgtwBjwHtIz8mJ/2NZX4fTexoVaKljEVpqUnzMbvvA
ThV9xi2cEpFJ2OGcpJMGSL6WJBYBlCGxN3dPOpGEirW/sjgq/2oVcIaW6HhSjsMdAnQygc1yL1We
FuPQsy+3TKAsIjnn1TsZOFuhqH1KXmnBSSRs45VxMVpNO2ftLA226EA7PfACAp3i6G7mfw8kkdO/
/IOYtLuONxchI9/qAHrI0IBwLc/TjmHbJ/p3zeTSBGVbeRyKD8g6n5FgaKPKTM17/AnXB4o9VGHN
dfRKifD029GT5qBXW5umQ222huJawT4ivMdEnHFitOkwghC2YyYN+TTVR2FP0YFlHRbHfk50/E0D
1rnahowjmJ48DzOuq4dbWXXwJtFON2GZQwGkPm1tGHWivzyH4ItJ+eOOP6CU3/ZftrlMiIOnDEBE
PxxOnt03tZMDq59bTIFe3cEZvpLo3KDc52+LBrea5vQGdmjf6qzlrRgZml/YNt0ktvA1XRumtAlM
ioQiIy0J58o1MKvlhdctTtSzM9GIdd8qaiIJ/gaTDfNnB44g9Ig09AifvJWolSeQmZdLAiXTM6xs
Kyasr7UzZonP4lhEgNYNrkhWZmorfoOoo2SID1yjI/Q24WJMn3A8SLpKclAUD/Xmw5/bfOqEe/ux
ar7WX5GOpcvaLbjM3RYMrotytLdTP/pr+f29RiIANopXMqqD59yd6QY28A4Nt7uf+MNqY15g75RP
9pZhfQn8FOgzOCtFV7vgCc1sIHN+kuKlRp5GfRViN0wkzamaq3SKVDAQtT0hLIA/3zgqQ9sZtfhD
SuULWm607rp2ZFtV33xkBcLsEwnoDZELYmQ6B/qVzwAzKlc5W9lbI4E8YCGCfJitP5lfJ8UVi4CU
X7/buIywF9w8sS1Z3Xb9HJcj0UgewodxfgzNu+bFpyWdX0hmD7lGXfOwbxZ6nN0FR7i86NpLiIH7
0IO6hCSExiKZEO054GrT/XReIshfWnkV9J8Hli4spK27lt/nDjj2dCy7YgjYGw540IA5wJpDXeLw
ISZ5YEV4NEDCND4Qqc4gZ587EYjpoJsEREqwuTMEGXrzAv08hYKEOL9yokmXCWtOjhrp1O7i1MA+
U/IxhPMFTk3Kmg91wugA9INcKHjBRUUhzkE5gps4wEM1R5PuWLS8PISRHN/xnZm07cK6y3KkcL2O
/HJVIhdwkQ/KLGJCOmTpxQIo8h31EXYj89BYzXtkNpr/updosojPQpByyj41P1rbt8LpGRDRm0QD
VhniSz3bt50K1sC2aUVePBKGpae5P1cxE1TqUZZRwIkMJKoTO6JTkfnsaS0gsnJ2T4sVrpKjSEl/
bOC4aKSeIQmivTeWvWoomi+piNzaG6WPdd0q5aa9Wnv91inDz+cWvbbzygusgbLGo86X/VWdqUeY
lWov/+HU4zWT7duPknVFNfIe4HH4PQ/yEQ5N+eaJ3xJXlQ9hIYkaCms+ps8m+KEHDpcjuJy4BbKS
vH+FgCTjrBR/TVBvXjq0pJvSc6xddB2sYYvNTeb8r1L/AR2vxBar3WxE0EyuXTQLXpEIC569iiKL
XBriffU1b9hBk7qjvjvheZHJTW1sB1NatMw8HH06LMMiHJ7z20zvor6/KAaZZ0ttsIft8Rp+Hk8z
9lVxumVdvg3NR5kLQQLC8RvU2mCWkPPgdK9JREDq41V7kBQIspR+xESRN1Osqzud16TlRxlLRbx8
APmvF7v7J/yd9nxlRgjUtsQ1KjW3jaXrhrLLzg4lu8RSi5iXSmbRFkYrPvlCIQnQJYU/evhLIftU
Q8DTQpL4JYo6qYBXBpcGRtY6WoAYVOWoT7HQ0x43ZWV2G5u368mKWHXdyP0ljIg9uL3bqbE/3l+8
Gdl0CQoBYrRL2AHOPsonYn27gq/mKUJsaHuAc+xXHV+j/6PhWHlG6rR1sPrVmrE/TRjZqeQtRdQX
gf3jXi9U50TjQTK/uyqvaNHoTcyiWI6UK3rYDi4WQMvdxQnAvHAYZ3bJYQA4fDjrA7c79bEX9LQz
TtrY0HI4di2FCIZrH7k/juq7LHxVYyEJblIsp0jrp+ykpC4jrIOrPQGHtmpBJZ28MLpNeVxv8MDJ
cVGSV6IlGqvhJizBBWXt7M1guEPpiqFltXvZtEYcJrsTWftY5j+GkpT5bz3katIiLhsFi/N9vZMv
tlu3D08km8IXYJOMS/L2dB2uabv9oqklOQyRbrjU3LhhEEAaCRnktRdL8os3pAzoyyfLuKXsy/RX
NiuZWlXV6AhSOZfuqGzkSK1jvKMLdDv0ru+A6zq6zFBRMbvZ3dS2ZKhPrA9s+WoZmHXEt5eNtXtn
zrupg9qmljxBtjV8mfd4C7842eIjFwmQXIe/RVABwP01CDiRYNnYtojFfHeTcGEGY3EcUumgIDN0
7QvRAvWI83dHpcoO0RE0ki+TpCNMNVsZ9lOq3NLDmiYNQMYICxZPuX0EQxmN93wl8dCFoGEak46S
qQp8wzhfpmnv21/5R4wlqLd/AqN+oHky6cH4zt3VSYFetXZfrWUD3YWB3WWdEk47Y1/eHFB+Zw8E
DCqpsfxzXibFn/OdXzWfVAD96LsW+6EGYPVtYS/HFc8ljtvWGmd1nBZktK5OjVyXD+Scs02CKRal
baH0xDTTr9nHz+Tk4LPhOiiOIiIutHThG5nm7k0HaWvdbvjD1li6H6X0TQmOsi8mnu5vfYlIF/6Y
hJGDdofu49WN9NhQ7jJ8N7K9WiHxz8lQTYaS9n9k4nFRlSHB9e/u74ZxdF1brIX8wE4iQSjRE196
7/N3LviAN6MUynAL/xPDabO0RPQWs9M2L/etIsut7n3mu+Amu6WPvOmKz96Ek6FlDWyaluJJAXko
C9JQpTmIXwGcdh1TMg2exlL0yQf2mKmcbSBOPKF7uujr6UlRJ1ySgKSzWj8abNqLZsVvI/xNsOdo
c3Yclp/BtylcKkORlqaXGDdO83VfisrB7/0QyjWjD4Zb7TuEL58tjrzSQSUdTUQWEq9LYfGwYs9m
41yC3a+T+qUlg7p8CWSpqKLwZA+QUVlvvb24/mSMnH+1q0xaFylGylMb2KC726lN2IfgIWPgbaPO
hip8i268o6Jne8N/46RaLHm0EypwZzROhVySBBcNmZAVhmyeH4K1jSpSvhxdifgsWVvbX3zTSo/J
k1rXKF4hkqCombmsBvnRyNuB4baD5zUo9XeTn+U9kLiiLb8qo35MXnru/QK1Cyk3G/dcwOuNUl2B
CZVabV5KLax6C3JL0cHmY4bGkQuI2r7y2EtLorj5yFzKYy1tBgggSuAnuAQYeMLDGowM3K8HqCwu
UMxGMHoZnE/CDXb0oyFLCXk4STEbsCzTYREjffwjfFICJiIjbI2njiXsmGQX4Kxlgl2rjqE9Mmid
KiefKUeThpDx8qCibh0+CHQT+qNYe8O3QkA1dHav9sOICRW9XCcHuC3VdjGM6oXQXIVq+q2M7gfg
tE4Sz3QYsAUhIpH21NIZB2N3mYbElmyV4AVI1BJG2ze9s189aquw3J8LfIoqHTipL1yEeJAigAUy
wVw8aOlBPxcwEOMJEQnxZEN4DYPZaEQe1s/kNfuN7XmrzLz9/N6NcWSw0BRuqWMYEqIygZC4y3G6
hAowAqs0EGoIPUnJbBp0+o2qElDLb0V7cyaHljEiR1QI/UrkAGeyjMgjUArcPF6yLveUzjO3T4Qv
XIiE0jSt+Hqyp39bo/ySi4sMHDHU/64p2XQW9yQ/YrWQaL+sq0nGrIWGlczEnDvRLAMCLS3ikzCX
oislXashkI9/S0RM1NA/35eChCn8LocyL+X3gZ1ezOmGnzefiJ8m5CwP9Vj/6QkaD2ix077WdQ7C
mGUmL2mapH2XkJtlTfoRxZZyLFhOa4qwa/hkqmzTke1Iw9fujAfZJ+IYTWJUnbIBDn68/5wMmNLC
CTBmzCGMtpE9k1gVBBMj/sdMOT1ZluckL8av3Jf16qXCN3PxhM4MZPkMKRQ0lERjjKAhRuHEVrJC
gS2FWxF/aeIxk+UOyJQ4uspdki06oVbAd8STeFwVetWKXBMJ52/rZ4FwFrL7cn8CXjobw1qJnTO5
e3t8mSGM6MHU5+ay6cBptXdihHVjCT2j3eJUr7Aq7sm/Ebl3tsfGPR0CErqHbM1LzjWkUXKNd4bH
FpgjIuRhX9DKyaqQ43MJjpYL2W5r2nrgovghx5gifBlgkHkkaGjhc0jUikyFBlPmTDMAfI+66Coe
njtlgSBPL9kvGseBvCiYsUfYIM43aJRYy5lawY1nKmH9EZSRmpnV2XJLyDsgcJRdscaBds08F+pi
F/As+Qnn6dbk+bWNXKQKg7itIY/msP7TaL+kN1HsJGoaXYPLHDzvEFRCQWWaxFGqdsgWdMTYtfEE
GJXm0pCRaGVyQ4wni/XtkPK81zSmLKUY/+dMPmGfl2JY0/3OJaOzq42BNHDqZaVfGtKP6F99GNi8
pvb9eeX3HZcgIgyxxR/BOdyabs9J2vUbGjR0qUCEzFO76ksKPJrCwiRALcYbnfDO9OrqDlnHFV2y
rxjI0j5DAgx+ONAmPdJ2ftCDEhb1gmsYWLcySdGbFuDXiIj0zd+9tnm/WFnV5YygR6gEF9xsAMoz
3IXMlQPTE84t3V9UKZO+VjOyGSsa5F1zPdSpTO3xRWH3MtZPCppX6RHRpL9KZyknYUgGb4VBauqx
0vzn/iqnyt37oARLsMSJNyLgCOL0BfmbJeRX0qfjsaJj87O0RGQ9O2ta0WgrowJzgrj6isRFjZzb
DOBT3fhevKW2koJOWVXKufGakGZnV5UYK9Zm9H/ibDeSf+K+7583/bkKHZIQPUd8ExS5o0mXUOeA
+D5nqsotku20GO+RLs3NBOGqXUF/74qbKBwv79N5u9yiU5bEIDCWbU5rpsJAzoFd4IkACl4dYcx+
9non4sAwWF6np00M0gjOzB07hwnVDhimUmt5ND4NfoJCEK928PFFzR8ZA+QVcyS9Ku1XyfVIjDOz
WfjJkqpCaX5MquLX3x0Pa0MmcJy3TYGSBIeXcs1X6Ml7AUWto44S/o+2eKYknzwWD5SaJnC8Q8Ew
9wSiSlzR711vtdYmyppr6jTkPYmLbqxUxkeIwKmPyxVqrnw2gNUa7Dbe6K+0OqCfIV6bnt+Aj8Yp
ecJKpGBMWq6bP5u6aZODgrHuQJRx7HpsqinHbYQ3LJiGrBPknI+q0aMMRjgD6e5JQYD8IZDanhTp
bOGAHr1ubcTSUkJzsZqHQEMnI4LpDGff96le/Zkp4ySjAEp42wNcteHqkDKWrjzrtw2Oq6cHqezM
efkISE5fUJXWwphX5jPehyU3C/hWErcBA/9sMraX+eGcMz5y4F87+L/SKNzHDygOg8qC1WkHRxoz
z3eN1hoY+7NYp3OxA3bLCQBxkjm91NZ+34Yie7GlECnOvkwJzLEsmQI2dpX+uHF1s9tJ80hWdNmc
LtGpHUiG4wvMz9cYyAOb+RVFfodGdqBKx4Lgnf1phxAr6Ba88Y1OIeBH/PQFqDVABBOPVmaaSSK0
xSziDrkar0JQlxXXeWfmomlhQ7Xhwpi64gHulCwieFbtirHG5ycL4sqQVvsTvYnziKIsRJS+5ewY
v7Wru2jsdfiyUgGJBfiV4XSBLhtpOqOrJomAFGXmuXxhFn0n0hsBL/yU4clOmSZiEFzQiWaa72bD
PSV0T2pxXSHtQ4TqvQceI8FBLxQtXM24ew0Ecqns+eM0w1uJElh8BqLQ05rG2CMHKpuX6XaFtDxk
Pn4umJluRFVMKT3ejRsvVmCd09z25mRNIoHzesPwMvvIzgvfi6dxja971UBQwGiWSNvWAlioAjKA
+K9fiSx/bLUOOR1Q+RGTjXNz45QD6Tl7Y9BnHhNzrXN1bWkfnGJy4X8i2dY1Mmj7j9+Nz+aSvblB
RkNwqe30j2nGlLNoP2sEwi1xrmApa6WIZlSOQXiKYvoBA2G+rID99KTS4pFkqjao+g4fUUSfcoX2
MotZa9UXrTHtL0sNxXl7YN6C+Gg3zSEeCRkb5h5+vk+WZSUpeyRZ36sN07rDVI2iQTIm67x123Nk
rVuSHLRwSi3ot6ZCOJK/HgaGH/2DUTnrxHctUmnp4CzAx4JuawBwbH1lBYLZ/BPXIGMw4YPnJ4FJ
vr6hVhnQ8G5jkSL3F0jUGt+ZvUSWUFqG/Rn/qshwkTCtG/5SMNjTyNNBuu0Y95v1G81MJ89csmY6
ix9VlsqPVZzQe6Hp+hBETVyXxUBJltfepz6LghFfDfeaBNJ9kTgtUZ+ovOWWbVOL176vCG98mVdG
fst9dUH32WTmWAvAsOL6U5HchAS5Qzc18cMsbjv8hd/8HiaL+QxG9TWsiKmw2esthSZDYMpUWiy9
lDcQGrxQKlUvLY2w+XUTybRJ2DyuQB4PX7CsFbnobcq7//8rx/L+yKHLvBYDtl65IjLnL2aYrovI
A98wd6Y3yZva7ORs93XL4LgxE7helWOZLaF5kLpb0dnSxL4l56JAj9p+YvdPi/c4420ZIy3VNEWv
a9qX1QfSk4PBVdZnkD19tLQwvZ9airaoe8rXps8MSFE+2Ssd+efwfG84UMD+1Zc4/qIT2ceyXbRT
H7ij0xCHwmHYO7POvGli67Pda51WSQ2GYEtIlyj9/il4JbwMw8YvmkOkxh7ai9VRMjC5I8hoZpab
ZvgvFDDuu1hEiQ0MSlZ7wAV9Msvkvptc6yZBJQkKQEna7hwtljxgBZbjZfNWnov1Q2m3+gl53WrE
11Lr1wNXY6YeYt4QPXcFDleU7CBgCh+9dMAqhboXBzvMDRY77i3OpopreLlwIqRCoftSfjPUeCiO
KGpfDPfEa2WYtG2dk0fbStBFACtF6R/hiR98/ejrXE2lp3xyUeQpZoThdCbpxkjFJ7EiV28HlwFc
lCWCisRYdD0QjX1ih6m7fnxF2isrBU9JlT1/xd5xHb7L456buxWmzSupx3ttUWjpx0TXLSlvLe4t
kTVYKtinX+A0vBiBqg5YVmXkM5pC1juzUia6CVaX22L7bfe+KQFtm35De0wU4L24j6UbbUuMPbzX
f3R36a+yn96v/QrsSBxApy8YsVjtUnHfwxrrK7Ob02VEJchoWAEMi3QTo85e+P9NeYfeiQg3HEar
719OrnyYkT+rdhwHS+DVVoFNK/ZgcbjMCvdkBJNuaH3gHyVxF+eSURsQovI2Zt7TmEwicGkLETk0
d+OytkdUEt7oyG1wd5xP24mm/S/97u5JQN3msYaJLccdK4M+O1YIo0gLpk04K0kZtbb2DBfsUnoq
mFPQ+XRRSwBh5mJU+YtD7/Ve/XxuIGaQgNe6sQTPCZBb7Goz9Rvj5RtPrRG2osoYbIHAXVjwgfkn
PgmJFb1e6tOH1/ZUataPXoL8IrqUWZCv02sy4tYYxw64nIrQU+I7DYbE2O7FTVyoFXgnBD9oj2J+
bZss4mqMel/1//rGX7zacVIo9p9JaNK0cQ2sh6pItoR73ssqEayI6L3Q3XfZjwMxfuBQ6vhbUmbm
KGxNLXizwPMTV60Wk63kbud+6uMO1hxw6wnR2y0xUDxBNYwTnIUpZJcIqcf8NJBM7C8uJU7uPDEv
W28ieBqRVtnN/7ozqJ7RjzhIwhhZTMknDqgK0oCnz1h5Zr1bLUmD7zxR7wxBYYnF2LOAqm3XXifi
oEz/se6ry2q1FZ5gsYsFhpc8mc3n9DFkCpto3K9jHcU+fezybV061GPpoBVpD+DJaGCZXmA5HmbO
ZWN8D3UETtogQk0FUy3+Ltrn4bkLaSLmxPllGaQlSaaK0C+4FrIU2sM9Sta7N3s5+SMPEBxoS+rc
Bdh3w/vSYx+Vr2MM2QgUCrKvkjx8cUifXfcepmsK3bB/O7MwRmvvHvyZWV2Km4aWbKBwCZq+xPnc
hH9TMNP3HBq8GyhAbBJO1Zw3vIxxZmOAZZZ787E1TOqwJbBkEa4uJid/+jzCMRTJUuEtRZ58fSU9
1bBbjZd7w8bgaPQ9sflHLGFhLA9HuiQDYB5OY6zm0KIQoNn3uG2YHd9iRYgUdfT+sgYcp1j73boO
2boO23t0y0hoxM3SFeMpcq5dQYyJZRXdgv9CY6J7X6QzzLBhPtYZ+mAMb+6jKD+rmaa43L+O1ae1
H1J3nh3C8dJaEadkpgVHfydNYEJmwLLEzERXJrLy6V7vzngiObBjC60wqZqo5IJG4b9DLn4jflHB
bL19OtL4pWG8ZytuehxfAYFUg/QhnWgO8pMQkQkmysOLm1lKd69fTEKx+yOzPQ3EgxgUFazG9Xj3
Ezgf/qs2zoJVfECqw+Vy0xv/0KrNYBxCcn6InfxkFj1iooHEkB7Pfe7vd6+97Pm8eVWvtvCoAzcV
qVEA6/u8t5LgkWiFgXaxOswDLs4fmHd7wQ5Mmc1/XRDNVjFZs62/Ll3cjTcu3iTcGQywZgpRgT1P
2vMAFPm2rGLet7aaognw2IT2s20YZG40vxsy6aZhC0IchegAZZ0bF0n9t+H83+N5+0fQSrMXBeKB
lQWvSvXlUXBua1a7FW3ti0o+C3y2qptyO1F/W2wOKETFujaeb8FqrRa204/LpiYHs5ybu3qEzqPC
8QNFCMHHuzCnnnFhcfhWHcfcjjtzp4sz42oygIlGoe3KjCzGgwXBqTMbB8TLMpUhiwfp25JqIk8a
k7T2d5+acaDvN7P3nDLVXfeaycuvWKUGDja03G74Dbf/xXOfkIrADDNUf/14CCZ+jEmAT0HN4au6
nHt/YsWPjIYkkgY26VJpkdIPvy2i60F/e8kpzouvXhZbe9xezn5hiX9Tnej0NfjYUldHKwVQNc2Z
J2pzaxEIZsBqe05idbT8EIV/qE2aQwWLRYCoLSCqpE2bP55L+Frun42bdpCrFipNy8fYJxHOePxO
V5L3NVDkjEj0plr4mQGvQL2t9qvws8pyNlJ1Hzctz23u0OF6PJQH0Sr8nLJ+rJzbHcZkqhXVyYQF
HVWzyuJNw/HO0tEkpSM2e4GCEE5ZVLUvb324StuQSA1WEF6/AfVoouQ1NonZbQIoeeDo6kMl7k7V
UhgrOM66ZGdcIJPeOaADccrjC41s14y8AYIbk9KUm7FhRyIWXjLAqY40xND8DMi5H41bGJN6S9+8
l4fK97UcK3nOsb3scrxIif6XRPg2OPWGcCAxyI4NIuVmXD0T+4wQNxRo80u9gLCEwNk2w6wrInNt
wMnK6denIYxh9YTsaICG6hDnt6LO0xrTpzJeYtfehw7qQcQGaphccfSSal1wVoqvCYLp2NgpaAn/
M62vjvtoV5F1uYxDPLcpxX/d6CRBL8pIEWViyPSrXdWfT+tj7pCzk7eic/U0NnsYTH0e3e0UjpoN
3YQdfELrRWcLQlMFvQVC4qZRsx7JNbvNylp40LDcLylJ4IJ931O0dYTUhmHwItl4gHX+Chm160TQ
M/KhW3FGay4zKVC9Tgk0ItbrdfNQppS0mLC2PG5pDZRmhpX77V0iXHBuEZA6KE8xhpBAXnuGm36o
bgpqlkydwihUpxvIzA6GrfgyNyiBsX2vJR6w62T4GLP8bsVGy/1z/qsPhZONFq/SUZy5PdJdLIAG
kYdgzfE5o6nYVRfSKFJ9fWePyuVYkkboVMTc/3uFyhhd3+9ZYLUoUtZt/PZ5t5HI9n84GW7vnp79
JTQXegq9q4WDWXIMf9lEQxQZ5SRuUXlJiw2/7eLpkm3uN4rrhja2mF36IWT2fRKv3LxiBpaVRVp9
4XyjuJdbeAix3ZnN5gaPhFxOqlrAn/5VTBADk1jixdJqjDP31X8RVOzr3NsOT2B6/RcecdZGv+Rf
kcJpa/I7AmnLGueHzqQ9XbDCItFLTuf2cUevWnHGWvCZz5YmSnrsecc1EUj3MKDhpFOvuGhoNNar
JZimuKkurzQykl6FoDcub939GkQ0amOv7WxF2WuypRXpV+nGsrdGv9jNvY9uqoLsRQSkqZtYMpUM
IjrkpDr4V+pbT1ARqUnZ3rCZPiP4kMq5G/r4WVs5fGN6BBkf8bVo8mDwSnq6OVFujTe+u/KmYtXW
6Z/ml9y5Wpg1H0pAWZ1p3UojkDaSnJ1prZY9kwW9Qv9nvbf3lEHsTlQ86I9i47D2RDv3m4n4u+Fv
Oz0vSExZd7x/mj1/lrJOoDiXsDnHheFA9Y2vmsuZzsgnxgSlocRQhCpsLXb+sYqNAcaAHq6tjd7I
rtVidxPxkQFD06Yx3DHpQLgA0bQT2C6+Z9478pyKEMKYfP4hpp7G55pIHPnfZA23wmkCvjS3LixS
D7KuuqKWDW+8+NlJPrU8UzvxDgkNQX+M3y1bAxSTbj/0Ch0HqS1dvaZL/YvGg5MTypT275Ptnyaq
pFSHlZGmKwWhf/DT04egQPwDx3Pi+dYbtTi+5TEFWWKUc75FJYdQyewVyd21XnXvX8nk9EjU9a7r
xcahZJXDx87vVJ1re0V57O7cEz9JidXPr5picZvY6gOPh7wf8JSHtBBKSEfpMFgBpMuqHuv0gnDp
WIlfATILvjjwyihZnnLUceOt9FLr2DeF5Q7TyPbeYLTJatC/34ebA5iUdZLs6gPUbdks5NOoR/5W
oncYuPq92Y2Xk+OEda4iqKMu14UEEgXyaczviU89Qia199S54AxCieEskzVmstBocsZ4e7elAoCT
lCUFHr76dieSww6nS1+EmIsgeMjFEqxm88Wiafpb1x3c7R8KytUxeVdHg7W7n5Oj0LsDFNxeVGOl
PbmjgfOAi0LASl7IzpsG5Bb7pm2NgQWVrkzYcCyDlQ2wkBiljNSGtlDImNr3S1pjDPvuk1KAz0GH
W6BnoY3ww7QDyZIHPxmLqgzJFrDxDi/tGEpyJFcjnw/r9G5YE/D4RHMg9X3aZG+V4sWqvpkuRUDe
J9DONKT1A58mTG3Acgut85cPdRa1+bdczHwyI7raHAsGlzuJ7gHqcxdpFESPYP8xPpP/SO87cyiN
xXmTAzQOq0XA3eKMKEd1O7ZoB4tHSwbCBpN/dHDioe0pv5B1GWCtGBKgUvncTojFDQMJDCm4WLb0
05pbDxVW0Z3nvVjq1QxBLxNfibxD4YlOi/xGTzzbAlbRBRud+zcXtyjyGq8kCsYZJuCr0KLX8jFc
EQ8nndWv0BuaYnN+t1vYpV8+783wMXZGovHIaEMc81Au6AwY98xQ6UToLMCL1/Bw2bbySxy3BKPx
pO4IGs2NVGRsa8+X6w7E0LHWMfd5+JqQDNBlpYydYhuq0oTKi1wh8B04W6S+y3Fc6el+G+yRPy6I
lrpwlFO3lQCYJ44v1h02mCBcgUUI9hmqmN8YMpfdDKq7En3jRXQxCOiUWHzoREaFkA+5XGXnRMnY
IsDSsMKDP9JLflBl2IDL25OjfnhZWgoBvt5mXMCmS7gUBgaeeoQcLPs7uuh6NH+S7POW3TJVuF19
pZCqP/uiyVEfGPgwYFSLrpZlovlGmhnq+Xb9e8VSONpm8gdMIz9sC/OZ2mcWJz765tC6CaDStWXP
Ax0Vizk9EZUVC0HnfFGDmKVmdCVfzFz0pR624vXMf194O5kh7tpdPhOZXR7QVAPTGq+JeL6Vqdiw
3X8YoSxStKa91TAOdUXiDmjxj/i6FewlS3KeNCQc3ZNGMELBc2b42K5nnB19/u5bSmp5KLpL46yw
r6Ksb4FflTMPV3/WjLaikjA/q2ZBk3aX8HaZXi4RICeytiBCoGKNnOqoFSq9re0zMqRQGxI5uitf
+V1+d9R6klBwuU8m9WGa2aH76ffZSNPzUxwnwcj2WUkE4Vi4VAgD2zlIp4Rb+eE0KKIq0OU75bk0
iFFLeWn9HfP4oGpK0fqQhhck6NZA2GU/ilXm15OVzHA6Th6gULdkanIquBMF7fK1qd5QtQ3J3pj8
35DnSMv5971xqYQfTcy+QLZb7D8e9xgR5NM4vmylR8tXteGhTR6C4Qs1UcEq2688/kK4ZJ2VeA/R
uKFLVniZKKtd+rz4GbwozBLsRDuQSCZiY4cGfP7N2Fym6fWugK2An2AeU8wJw3zz6d99iennc35h
Q9sAuPKy7AIz8GHhDhWdy8grV2EUxUVT5pY/OBndsRAnD0I73ZjSImqi+WIlQ4uC+aYSXbSvoIXk
1Zn+1eI6kdMOXf3Mn7n0OMKB059HU6fuEv6sVVp8dwbOyKVRCFYHnhlb+xHeajvPpciIGzdtGk0U
TCKtzrFWkVkG3+U1XJpkN5dSJbE3qyyiUqfw+KbgSbe913dJOHB5pUNo/H1sLm+XBetaUy2Gm2+l
X9d7Fo4rNycKAJqysBfamGRGLnozqh7SAD6fGRZw3ZyDsabExs87oXuC8tk6ZW5DHuu+m5tug5qn
9JApOMQWMSpkK1xMHx7w6NzwVQwtpD4yqIf+vDUTRptLopGVJY9eUXlS69VcegI76PAZYnYP2DZf
Wk+2eliSjAy4BJA/GwB4kz0J+fEdcD6FdwOydhlFUQJFD63BJVUrbdV3SylqigEqqMFuunRRt2mb
s0ETIIxF3OaLspHJTI7vuQcHNsVpCRCb5Dlx7FLkIGmLrMGegoYNuwZ8FF3wUkNJ3Erht8IqTvXd
kyT7AC1N4ueVf6vEFMQppx6J1/uKm9kc6YsFC9wAaUdXsd8ZFmDlVXNPJLM2iuwL/pnzl8S5B2f8
wjVwFkYYrywrn2JktLfjSs5cARKRLDN1vddiIwi4TyDRTWTv9HgCqubN10dApHNJoPZVzG9IcWSN
8Ov1acPRxtfoEG0vQ9IpzfEGPXOXQ051UwLo7C1p/Il7lcdOPqZghc7e1vbm0/oHR3zMVoAGVlNg
HkYp7Dl11AajwFU3JJMDAQCfzfgsaPyg5/EEs2lk1L4z8l6SQ2b4breEb35/nGN6Dt4VoyKTitq7
RX9kd8Kcn4Rfw/Igiz1jbLpveAXFMkyEHExnzcaCqwNvVoazse5gfGzJg168gaUqJr9/odHUZSUJ
7ql37YeUbcdJOUQaj3rCTGm6NzilqL2bBY2a/6V/Z6ViI7YvyWbJjzk0JUtUuHjvdurQybJHI+jn
zT7oCyNkDJB5/RyGO6MVbZcNI4ia+vY1wd4+AVOnKeL5rSNoOIpMcNb4NXmQ0y6LFzkR3EzGGD81
y5+HFWfS4GNQUoTXchGqVPNw2AeaS0qjdX5wE8LeuA8Btaot2OnCHrO7fd2EMAloPIe3rrcYDXOg
EiwbFrCXHcLjL4v6cD1ON88GbX28pyV3LqKSDqK8zckEDbOnDIc78gwg2rLoeAke4P7SP7ajijiA
YIsw6TJNdR564uXq/oo8KTD0KhIvna5OjJ0utWle/o5tm5dpv4sf9AdMGoqwiW4agpAH3C/FPgF8
XOC8/egKfc6BGeyoNKOZv/QHGVsXswEl4sZP7xgM4cvTFRNTB4mUGUt70QDaA1ddoH3DqRoDE4Hw
wtgSGh2i2bcMllYSg6SWzMXYSfSVxFw4yThynfFDZsx5l/ee2fMDGaoc4NlwTMQEEDcitCtKSW6k
voQFkLoOkP/kIMFYNZQlmPkgOCf2+QvMDpDD0tlQdfMQ8L4KLMQ7TbY5Elzvc1W8kuWogzRZeCv6
B+U3Ul4BNtBC0nx1EshBihzzo/+Qnr616zyOnB7FzJO8E6rK3O9lPynePb5TaW7VU+9W7OQ5q7/X
mwSCSieBR7De+kARsXh+yHCL8i/BK86rEyBxtJ9+j2kz78clIIdDrthnK86AgdQMfOM754IHqQ4k
QPPvEEQvjrLwp+1YSPVpnCbI9xzVKz++EL0O/IsQN2dLdz1A0OsS7ButImfnNrkYUnkzJtSeF5sP
ZIwvPh/HxuMsV+alV3I8WjomGRS19gHkpAlcQl1kU803Mpe3uqNyVhcjYHewkZ81+HlOSok9zOyc
DPQznpogEsbjBK68paSBIES6UBo+sJ9qllvw1TELofn72BpyRtLhRoPSZtdG1k5bj1+FKmnaDHCX
SDE46JddYzDupPvSQD7Ks+yhzh2x1FncfGbr8PJcdZ68xBPM5Vo7Iu/cb4OdWBR1LEz0mB3urMmZ
qoG//slCOdjnmZPCecjoE31vcOd5I43uQkkI4oJMn5ePObhbjUCYYbsikoHawZ2XZRBj5l3IcBjJ
U8BKLVtp8t3i9KY/SHIs7IkqQ2A1zWNYuTg52sRrUV+T6Te7B/QA+CRh3nAC6NU2ImbqXJlB1B6d
AyCSfk2uoeXNBtVLqNNvu8I4E/+fd13Azg7vA8slGVpRjqblRyVzfaCZnaqJg+XH13113lDcFq/W
uuBraTV3BqLUH5EW5bM6qDyEojqNMwGo8/yeXFW97DAhIJWU1MQeEB3n1yyPLBANnzCgo6WFz2Qc
WXhwjtRhZyKgvRbRLziDHtZvSoV6iZzRl07hoTW1jiNTxl7tUxU4/j/5GOVCTLIG59AH1ESAvxVj
nlXlwc3P28hN9yyQxIb+G9GcgnUnQ78ACSvIRswVjGEMnTDW41eAXwqAqW/dHYcYG4EpoXivbU2j
SBy67o1FgdFpVK6PURsckKHGzPnXni9Fvb2I2CTutW0U44/PVFauo97Nv+XeaIGa/HiT3hbja0Wd
iMvdDJWLON4X4ugUk4+VtBfHpvLgq4pRQ+Np2Zzk2VbjqKYshN7e69mF+OJ7Nx7WsXCGoBjf3fw+
1CsnSK/BSiGqXU/zlj6fSXc5R485sRgLWncswBr57l41grFlQwEL6n+pUIrxtKPzSags7ZRoy8eD
PkhZbrhaga8MBrXUguYqK0HgVow6VYDD8gYM1TalXKN5wKXMUtUBex4XZN4SAef9KyJ+EbuEMVZH
D3adz8ieiQ3WnaDrqTksG/yBubyStUeM1X9e+ye8gbZiwD/eS2BES2US8rKIUnOep0eNb+He6iCM
7SHOOW+1cu9QI8lTMO3hkYE5UJ2w0UCRyIyiCDU5nNZGH286i7dgm1gT+DZ3OoE/qF41HOlxowIZ
U7Xxk6YotBaoPO9asQhHyzi85yIJP9Xmf605s0agmqR405xIZ0vc3Q5DFt/0BfC4/uDnFfAKWvKn
MkiifP9mwy/GUbk3Z72XJsJM7YCbE5lpbtNQzZFwbjXK4CnR9dNYSj2RLfqr2FO9B8hLhJcLZhZa
XusfEahAh8tnD53KnM2xJ4ExkDt2z9hoObdVvhodKvoxIxCkaHsrPJpkZtSMCF21QXo5GDsi5LU7
IdNXcNdK7g4sLM9mOmLCSt5NVMtYFJtM0Gy5xRqSIvFxEnrzm6B3YOjeKujBzr7nmgaLAXozKUFJ
y8kyyEJBkcNdLkaG0xukL6Hi0oN+jjcj4fajwD5KAs7DIF2lP7t0ve8Zf3jp1x9BXtQwjyCJJ2nl
gHUYGCsoK5J7hYyuSsTlq7Env6udJa+oOYvaAnhZ33ZI93DHZ7T/vc4RCP9vMcLtvR6BV79gwq9B
RmJQmSg+YSgLurku3en8oXBFpoi34CpmczxylGAqEvKCSoY5ZaO+lH2sXgphy1R3QC7iqWKcFTi2
0RiIdbArVKRztBguS4s3gdzWq8f8dQL4XKnukh8V9jcOAtRT7HkQAMf/oBS26sX6oCFsHvz4K4q+
08zBUE0i5jVZS50rt3N73JSWNRzQHfPHykFOrQuRERWogXnvz3WTvJ6haeTdMV1VBICcxSXUcPUu
dAmKf0m7fgCNnbG+dZl/Jp9+cOo8Eh9Ts3fOwnPRCVza57srrlkBtwKR0VJTO2k5N4JJkEnGoQnv
ub5jxFHqAGkmTj5eu2FeXGvbP2h1tHdyBEC+0bXx/fM/XWEYve+iUtWKpstHmCjrzw1Xus8bx7zd
6a5IWz4I93JZtdGWh3LkXP8j3hDiyDIcyrRyERuJq5TokkgNTjZxgQXPlaTI/qFSBrqJ79HaH2sc
wqnd9cvncWXVZaNJ6Lo4+z2nplz4gjHcgWS7hmSYC47a6OgTPYYAVc0Bcn+YKT/KWGPKC8lTm8A2
1Mj8iGQrUvnhCGOftsmR4Y3lgq/Z8kIkF/aiJ5dP37lhts739o301jNs99V5WxkuyCH8FxjFnevk
ZhACYC1yD0FdLRuw2WLCQ1OlIW8XxukcGjyfr8Jrej4Zm+NjPC7LQC2WLlj+Nk0D2qezfKjvOEAI
boWCJsf8r9rY2x9rb2HXx2RwmofYC0xzQkeB91fDn3p/AU47EDANKWsVDxiuKueM9p61kQr+4CTT
gKEV4Ib5Bwdb++LhVyd77W/j+3Gs3yL7o5QrsUtlKszEK+KKumWLyHBm62WJq8CDiULrj0DxQL0b
L5RPeT3gO9xDBCWiw+4bCgBcIGrHQKt2ZTDZEEhGyDrV4Bj9Npp/WFrjuhPJ4q48rN5DlsnK3eD5
dxALGcqnLypY8ODvPjD+Vm6cak8mMoMq/VaJC7gp8BZdWsOim98uCdnCPg0a4NcEHpDpTUG9Hxbf
eWIGeSQs/aALQNFxmdykHbOdT5naKG8eBJqEQk7U1Xiego74tOWS5xo9fbtJ8SPPcG4Yz5SxPryo
Szf8Ss7JDp56aTqhVr57DPvUPgl580eZUKnY3iggTlIyzPh0SlCfCUOFQ8SfVIkYhQRmWsYbUl2w
Ali3eTh7e359eiLB/xuprjvd5ObYxamZjyLx32Q+nzrm/mlBAtvAnU3B7Gnr5Euy9oPpQhAkDK/3
dG5phO+BFD3qa4Mkf49d6/ipkaxiUH/7viCNOcADiAdkDyJIVTslRDfIHQU4ZkIWm4NWaY6gktAP
JI8Q5UksqYEhs3VVl0VBZrROjfIva32bHX8s0bmZOkS3LfCn1LqtGWEHVPbDtE7Qfd7E4AR3Z9VX
o1WRREIea+P51lUSfsEK++40RXfHZ025yfYa4YauFp6H9/IvY7lMOkKa7e47JPUXmtIdL/3m5zPg
l5i9Vq83CKbig9nT+ozM+5lYc473c0r14O5wPtkLHHIOdBzzkD+g337gu5o8kEodN7woFGxfq3v7
Em5aocX84z0eXdLZBxuv/okL+1C50OzMDLnXm+R0ym//ILgdFCNgGuFWmAvgvMyZvLQxGXFVaRU4
Zh2TmONFsqzWIV+YsAhYLubR/VQM8oqO6W7iOCKGev4BJtfPKSR23ITZj9l1E8lTAHiTh8XiDM+0
zczr57pn09KKiFe/lWEewCL3XWwYHmE6dm0Baosp9dY3mVMXo4GZZxnHa2x3gFIsnEQqLrPSIosX
nJmsZXon1douSGf05j5AT9ZPPXmXejN/ev2eg4FB2mK4UQY43vJiiIAwLNcSIf8WDKtRyjT8FwkV
qTLXy/Qsw0/DQR3A71SEzDasBdyo7+BHdA20lYqncskaGeSKpfJgPyDZyUBNXJ57YS21+Vqli55k
lgDbLO2nFaCzupqkfEE4DM+86N7fsI3le8yxUowuBoWp9867e4eMeprmZvcY42CXB3tQqbfkA9ok
B+d98jGX042YWAcYiaTaT2eiZYnje/VbXmiwABKTElahh31fqW2dcQ9JE28k561t2jetmMNbdobf
VBmfNhnyUaStE6OCQBW1wJYQHtlSm8KPgZvZi0muuzSIi324oZ4p02+KDwJmO4BEpqGgWKijMFt5
l8SdK+b7+jud49VTQoz36QjMjrV4NyiEtMiouHiZQjdHU2Bhak1vUETRB5ERNhWJnRXcJy89lwOc
AihdCdAer/CrkAfWgPnDf8KKhd5MqTM3rFDgrS98euJBAgN14lTaCEw1oKkq+JoiECRW5sVQkjQC
kAQHuqEuSzovhuioG+d000ZuOwIP6rM2EUGpEXv/MTJQM7HK7yuT3GWg/SZZmq8qwt2K7VrhzXPq
dElNCN8yrWNy04xRgpM3pCOBMRBdf0+dnlEMEDIjpYdnF+tLgiEZ8RNRrVwFCuS9YxFbd71fIkg4
6OR5C9f1jXzkNZicRCF/p6NUd0e0oLQbEZzSUKAP7yAJKQNsYhsJuCiwyWWXsRrHchIik/8hioGl
4zysvvoE3jng9iwe3zlMNQc8VT3JkKw8l2D2lTwnOjO3CKHKr0tthEMb5FgKoQnfCEdt+dFTOdIY
dcyyWFzTxGjL3zNtvArWSmUCUB49seVmNwU68ygR2XwiVNKBJyl2EViP40je+OwA8PZ+Ux1/gm32
sl9wiEODJxuj+8PuvPRM3mC0DTJKYu4/7dtsCYtGQO4pYjbl2pb2I2WPSpeYKhrAFVWoSUqlsbWN
Xa8iSlF/l1+P2rU6NorIKpyc2s9F6j/TjThP8O0OjG2jo7OlYmgFv3O2S0KIMRDVm+m8UMNA9OO+
XG65l8c0SYRpECR02Xlh0PDkzjexLoYC9RI9SQ0HN0qYhIt3r2rF/TSwXzLGL4bAsj11CdsM7RWI
Oo+1Q6WoiPusA/otrD9FjLomg98hJ4CpelWbtWUl+finHvMSpUntB6UvLC/fJokfbOQshVV5Pepy
LFDdh46xI89ssSeGzQhC8MLnpR01JPltIqTqcyzXllXgRafOOVo+WLJz677jFpDgxJKtjdO7VWhX
lYaloVUsqwDW13JFpX3bEfexQZW6AbrA9lIjpmRU+vl+9IeVvjioWmjSEkYJbRR/KYOprEFmeZDd
j+uVTpdkFD6Fv8Y9T2elLtTt3A7IX52yxpuUkeeT/FGL8l0DTqMpZn3lhKu38U8JloyDs3DMi6nb
5NaDNZNd8JiUbFkc+QAW3Cv7zkgEBOLQME7dGnzrVVhidvUVwH+i8p/5EjbMPt2v0TMF3F1z7Ahx
adByAcHFmMh6MdolFgJEX4dfx7yhar4Ge6Vh+t0MgzM7Z6IG4bJrmSTgRrnmsLy3n0ZtVaPO2C5G
Ff7P9GPZQpeP9u+cPAXWAzJAzqGb6dK5hreqncStgx/gSUL+/ygxquVTp9AkkuPssWuc5T01nSil
6yn89PFjd2NUgmfJjTTjislpA2zR5WzG3c06dZ0GbPGHc6YPUMHc/Opy8UJqXufH6PZ9dHxggLkT
OulDhElM+BLd+AP/t8d+56vNZTd+v6EBovp1nvu7dNsk4gd8DFHZhFSHa5o9yAdCTUP20Gsg1jR4
Bi+3m/krV9EOWK5/6KB9pxyM81A4va57mSLHxHe4XiF8wXuIXTmMT6YTHqtP4hmnMXS6C7mgy30P
u8wNglJZh/8CQkzqmY/hOilyWDZsN7PhAYdto/G0Jo2SoNLhA5q35k9WSVZRpyphsfpOzTRm1s5I
rh3yGRTAIgSOffIgzTFkZl+8MsG23cKKjj9s08DWL3T8uDNvQhZuv8VA0HtmYD66dVYOkMEzW8JC
qHKG4IyzsHkz2KT58lSKAxm/7Uhb+ZCfggaxh+DjeFlPs1RX2puLN3t4eoGXuu9t96m6pynnPuRt
ZtgS5e2OSW3Agh40DOtigvts9q0dp3G7e6GSNyPZ3gxsPQlep1CpRKtu9UWVPiRJDNSh5s6zAAc2
qihs5sk7xpNFvw4vHufVi/xQ1eSlxUMiB+Rpc+b2xv2zSa2h0Gsx14tFNFIbxpHIqDbl+SrP9UEd
hxQ8MW/wMCyGeRP74Y+3LcpFqDiNdVjf9JqhLuWe5iSwTuKaeQQ3oJBnijLPkwXJLrMyYT9EOxTP
PuHD1U++oa8spniEHuXqarFWWAnfqbCc569KzhJQROk9AEsssS6bqgdo5Jqp2XP/JBn22LX7QR2G
WBXUDvYODjSS9mOQ6k/ERVcw+E4MOKpYfcIwHhtHJNmtCArZlLK84BlqREaDRdN+0NEANoVN/en/
JDYfPQ17knoUbMVeHwGEj8EZ/6QxvL0/pNVjNR6lvlR5/Tz6bonxlWEXBsQtSt5c2pRRqPprr+gC
3MSigftNHyS9F6wfNb2wVyleLH9vSEIje25/uNO0/F7QYAGqjkPgZ9/+QSz0aYBsYc945TQqGpIc
4+VdW/JXrcJbKB6mklxZcdithsqPHDwIXnu1UItCOyeifmQeRyUNu0dXD55NBEwOsIRFpOmRwP9S
lbBmr+CcHdzYJ7UvNxJNcQ1g4WproeJu2KVJw0wsGaHLKCKqlVpyLCkIgXodQkHaQHBKaWJ2npbN
c+gZ73TKFT0PfhWsFqwixqnMdNNpH8oC7m6qjNi3zlIlAEdfolQrUJPF55LjuD7Ln1/lLfVd4H75
+sD3ASYpkUXxfvBlCZeBGLbWPh/Cupo0qmLKctZ1j8BocrsfBsL5GeEdmb3cy3bNhqx/J0/Xqi9z
oL35NoQsJ+s4gVkvg6b04XSCQ1T6aV0IcHO+9or1c1kCnnxqZFW3MavHW4D5EXuGNCesqLY4PQqI
CAxX221wzHB4Tmqr/LQNTQOSryCUCMvlkXwqzzb8A7qGVp+Jl3vCRAUl8mil1THJN17GtCd2Z/52
krAFTyI+f7B7Nnyd7ooLwpwcozVkHZ9/AJBG2iHX5VoQ1xWDomcWC+71alUZjHk3TAiEfEPgCBOW
09XjpECd0VTicHAu45H/8qrIQmDDEek5KdWoyuXwVCy2VPmRJyJ/XDdguTQK/UPjet/1WgrOn+Gw
KiYjQBwRqLRzyrxirLIRWa4Kf6uyrCB2LQy+br70uowgChQbzFL5pGOgV1zJk9uWrXD09Dki1KAx
kApEvvmqdn5p6NUc5sWeyNpU7hemcgmdfcxokZP06FYSph/kR+gSWSAW3eNl4dvgj2QbVIMSGlig
zxTgkSV1cxfEMvqhWPK7RRy7xctArUUaSJfy5Vo1dLJ6oCEe8Au7FYAT9Xbo0JFy9iYHdbOIElb0
PDKDJaC6p4x5kMqyTPMk5ltVNEekhmX3Cx2F2oK4JcFI5YFtpd34GCnKoWZR4buzjnRgbug0K3b1
VmLTCHraUhwtS+/M8z0gMaugok5gh5EVmYVjQjURyA8r4XDELDM7IMBe+5lvs06vNnqgy0vRK9hp
WNPJv+C2ULNJXFFFh3UfKmWfxu3qtHKPglrs+JuSZulx5drPFzVaoaqRrsz4QMGjv3vyOqLzHxWJ
YkNlVZv7L+34RVk7WytqBBZRWtzMEco8LVKU1w3S3BiojChZdZZS+Oupn58V/BEVHXda34B2L3J8
muhLyK6m+KoAftQshJP95XoXTnBvD2k+e3ob0WbGV7vpHLX6/pjKPDoLz3oCVwIkG4neJlVtHJxl
ViWPnbN3MH7qDW8WnlVISea5mLYHv23K2mlZZcUq/FNNSmy03U87G+9neWgmPhO01Di4zIlqjNSE
45yRByowWWezQCpL126XhVdaue0DLgl5UhvjLsShqbvb9RxMrY0RrW5+Bv+IWU2As4UhNi5MQVrX
IjR9CPZ04j8xB64lKiiwgkEwRQzzjT5QqKXKchur2bMa+WQClUkPkQqCXF5LTS2m5v5CqPw2EHpZ
TMpH855k4/veC86xvi9Fl+LCx0LZmqQKFUoBggzE4lll5Wkx8lqZrlEiNbkUFSbdb9j4j0tNRdlV
ty4iuawMt/lvEUCn7oyvkJMvV749SE0zkr5mGA+ArDQp4EDtCKcAwkWF4F/1x87c8cCrNI3MViYl
G0gPaQQQkJsOx7npLrJhLs5P41EMJb/84rvTye1pi+gGud8+3/Eiv2BMYTAdeF3ASudQCc5jztV/
4AjEzitzzI5ggutrrar3FeHgTpJyNczG73ZqJcHZHLa0goCpKzaFQ7WzKLgYa5a7RPrgKe4yZS33
uawEOo4zK4gqJaJfxb3CuEmx/eIbdd3onJJXyuwIx5PJeNx5ftVEt5Bf2SqNCae1VkO/JmyX7svZ
PzfXpVmqEtipAJk9GQRHgEDCNNy50NLdSRXUujZDaTvO4gnGPtoWR41YnzEx9ERrG4E5jtauEPSZ
IESihgDZI3+qK3Fqe9StO0YG6J+3HkVUotVn2+CSA1GzJTmDBFAsyewSVEde1fKc9dhhGUrVEqul
Qq16LrfnyGklS5zE5AtRYq49qZzH9evh4P9TEYjPlSuk73ezYkZb8PQx/mZbDANYsVHKeaXz+aYn
7NaWD6gTM5lcksDebIeLtmYPfchiYqYcMr6n6e7icCikRtXY7BxO/WKyzdo89+W0BcoDZ0JnogmN
sRpJ3raC/HchpiT+/tyxmm6MDuTljki0vqQrfta/OsW72FhBsQvaZFdlFzB03RX8od1N5k5wnMUq
2aEE27UXLIKtRodQ6a6sjUN9UY2lUyAJtp0PBEc7k0arYok6F2pcZClmoH7OzU+UmJ9OeMf6j6aV
42vHZn3BLsdSSWNzYQgWY9rf6I4o3BOFEW6ZQdZjCe0XJ+BXLO4Uxp3+FFqMgFrOA2DX0jNhFgEC
FhxeIy+cGS0x9wIOATinI//TbJ2R6eNHCKDa+I5nTycN4pFRMZHaJxmlkU8ePYq53Y2R2+wcpeHT
Lc0AB1WAMmCXPu/Ep4hinsT6ABxcrKb0eUQQ3vncMX2tpv0jGzrDCsJWwBWWTptTA6WxT9CAxoTj
EB/PmJG9qc4UppsOEvuZGbqUKarHfjtiqV6Bd0KTyXJ1GrX0em5VdZKRTGPQoC89JisuE4q4//xr
Gdl9nBEUjlwjHFRQtfyDXZXZ5tkCPoN94dZ5Ghi7royNPga7FAEMJVGUcEZuVbnqa9xlS7AYn8/v
rr5wK4h68reUf0dFjJzkYSrw0v7o+NKXhjl4onHzFo4t71hxa0wWmPOhU00jssOFR5s95aO+NOQU
zEYiqPmBcS+FcmZutyeBkZGm86XqzwaalpO0oLn7rf0LH8/E3wJZIa9f3aLRJ4Yvk2V2xSwnaX/H
3Adf9z8WArVAnVNdaNcmv21jvtXjLEcEhOb42BnXI1DyZeLfbRpw0UVV2zZoE9kf1t+6t/rAGnv2
wevdLQOcNKnrT/lhQdUr5bg0j6DnUsFlHst7aMnEjDdKzKvOo/pt+FPcs6sEJQZ5lGS4Qgbz4B8I
abbjDFD1w/5mCf3K9mFsQeGKh3Edo6DUl2UQrF3FRQNi4F6xNfkFSRez3xvX2d8c65t3JL+uq14p
LNR4/SF8INkCvSU1ZwXJeFfjZY50V68CO9Ks6h3I81yX5nlGFPt+tqCZxp+oFcg46w7p+CkL71u2
ldxl040hAOiXWuopGFZJ8RpFfSMxiWTNOi6k+dlpgOUebmcaB5ng5ksPbtmB4ibCJXjOLuwisHCl
LvERyVHeTAs5G5dqPmoa1dKTSVJsOtVmX2Hl6aubLenhCbTI7zQ0dhKkrIRlmFPmGMJ5EZ9lJCx/
CqWUiVMwx/fSgzyzxAyB4LGrA0PpZVhjPjpTuHMvWQt5VUvZSiiYryQs/cs5OicQ3QWvCQtm2cXd
o7d/rGHh8+zpH5gFjnqeftvDXD7zVoPLJxEuop3Jhjz7Z0HfqGhmAyHcjViWpOzoihc2KCT3WgQE
MNSUbWqd/1YXGz2QhRlsQqRAoqeR25Yu5VVf61o8UlLnpDEJpnKRzQHOPmatDWkc9lIpS4I3KJCq
sgaSgoAWvOeHdR025BWj9Hs7n7qDhqiivaiObZSiCYaCWVWx9QNd6YBnNctxsPTceBOdDUkevuPc
fDNRLPMUk+JI06nB3WTdMnzfajhYcAygVBruK32qCJSj194R/XaxJ6FMQeKs7ZJdJxvuaFbHhzI6
XMhBVm07nQ6v8/2IhPMNUOnS7BLSrgfJDcvref1vpNh8Km1d3z47Ic9pFnhidfCl3D4qIbEq/JjS
w52MdbWTQn7zOwCMxpZyQ74V06h5BVi7g5p9UWl5m2l7RoMGfqjznRGst2l9psp86ldbl+pQlKFZ
5i4ZG4/Yee5Skxmm7GZx5XsMpio5hGLE48e/5htTskHviLZe6kaWOHISOET/nYFFozLT/Cyl8RU4
gaVnn8s8hynRJcAMcEkfoJu1daoFMzR49K1LyTDH2nK1VkAhmeQR35odq9ngS8a5zdf7RNBSs2jj
AIvHItpWV1FSQbrUuyv0yLqZnybsVN3BkQc5BkbVZuN7/LbyKQudE5W8bXsOHow7EeS/dElPA9Si
wFfA19hNzl5fkeKo5emPqKjzCOA4oz4NqbNjp1682XYrJZ8WogfqSbjk5CdDbwGBpF5b+iBr62EC
Os5EVieQkRUlQQPnP703yEwSdYziNX7MBjEboatF2tnI0Mca9ygxxxd4k59fPtzmDxnE3sHs6H+Z
1TnvRa+SmTQVe70WJG7PMLNidsR8VWR9CfYl1OC/I2aj25hm+awW3Qki95R90iCKZHJXD95JEP0t
s6enuYItQUCMFI+z66kGSvcx9BD1BR9fO4tBtYDudyYhMqHbxvNtBPip++WEglwiw0RMdbig8frG
0WciTi5u+n6LEN919bGDLTBOUDil8jEiJ3zuO0yT5QHyjcaZRCKut6DOg0idcvBy5XMfbIhNIaq/
B77HCvxV99bqIwS6oxv7f6UAk4AZWP+ijIL3qkEdLTz5FYPCC2joGG0djqkjjjORXDdZvkV62YAF
5TQwM3GoIMs/bK3G9zlGa4jO3AGslozJJsYknngtDIiKDMnSoQz8xbZsC63CErvVf+SuFE/uKPL9
p9dhtRemK2H+Pt1ZxbEoGoUvJW91MINCFWDqemE/vNb1eyFZaGl8H27XrbQ+bK6JFat2iVxxFQ4V
OCkMezOx/1FQtQeOPWzivIO2qi/LKGVrmdDeGbjN9Ww1kmMzi/cMOUWSxGTk1ZgziLi8Idmano0F
D9V6S31G4oZVfbFtfeQUaNn1aKhODm8m9c5/sBPzssSTreMJqTXvqC3E/jXaHljLRfrwhtMti/kN
KxLbCndZX6ss8eMw+a/uHY9xzAhikhUQ+0gkOYZWzsARHbZsci11j5EA0+QscB+Gu+pjCO1VG4ds
chLIR9rII4/tX6pMXkbRtM+Ii5tJnMSLCZmA8EhbtHzeHZRl776i/x1bvQ991ezDeeqqVqtQPTT9
TgyS3nWcOl9fOUItNf9uftAZ2djCLqprDv1hadSJWq+Evy+ScRrs9yGrHOPld7BWaleq88EjchrQ
s0KwO7ZOfBzLfd/Q+Vf65a97+nK/xZDqtRuhg8/3pFPEycxIOCpmBlAFjFi80oUGuwh7kbgESaA1
EX+8rujWM3PniSv9540e8xftKC8ze6XIFbxYFDgWuxDVrvJQrCWr1xT+B37/P4MQcSIBA58aeVDt
Gkfcb/JxTFW3hA7tNWtgfggN0j2Jw0f+hndpwq+ZSczowrYgFbQ/NaHTcxW3eY6mUgljy9HXbfxQ
DwqEHtRYfGnCnjDFoFpvX7BOirnu0NdpyNNhKK1mzVi+/t7zWCwMd1NTA8WJgIJzXJcjSe/b3bP2
GIvD6iYAwTgac8vSLP86uOUk+cdzju6cQiBK3N1c9T+uXhifYo+hGaAkyT2CzyN7bUmUIa0qU872
0DVRnqgmpVo+BF6lb7LWWNmFOV5sVqRHbb/zgDXliocWNThnW86Q0u6VBh3o2tTGkbgy+peZoSDA
QsS91p9nac0QBiyd62VPJ7e8IUA1fUllpIE8TvHr/NaWRTGWnk048neAppQ/rJWflcdgVA8KVg0A
tMIN3cv/GKP5yh50jikUfM8EJRttGezP3P51wnSxXnZHkb5D1NTtQQYJyjAZRFPc9b6zCdT/vSCN
VrIf1t8/LSGRGoVGcYAgpBEzgezWwXpMr/jQvoP5EqlXQl7jlSpIOac3HG9kyitv0Vbp9QyaaE7l
BG1SLowGaq8QzUveYeMmvnnYQRtNLPBH9bUFm5VGdye8I85cJN52FL61m34mCuEToSRjUapN6BTJ
fZ5Cim4WSEA2kSMXk8tpE3xHbvCf1HcK711h4itAEUwJ42z2YCA5DcVs+MOC3agbC5PRISnbL+k9
9+kAVC0RYaBaBqs0ZSKE1CJ8dyaFGnPEcbATktGqU/PlXTFj2oaZQrXC/1XFP77vc/V9I2kpSZbH
BUaFFroOTRxXGeHB6kYipMZpvTjlVJQsHU3iHsjn9y0mCtjmUpyxamkz/8eDDEmDFq0Cd0y3vaa+
O93EXx7aFML346uoOP6PT6n3QXk713oPQgkY3uu3NU7Pa72ncPCSGD13UTevbDB4XvwjVHt9UAyI
xgGB3M3NzkE2WGTFghQW9431tYjcZELAybqmA5277SjmsqKVt6++kt9n5uzbXmgS+ps1668CDFmG
GXdaWFnW30j2pjJjkFrhbPi71xe/+kSrVXFpe+xEALFWvyRBUnEMIklTXN9IqQ7KzjbRHMTnZH9m
M/Ove0L1kizwRibcum+xtbRbGYHlJetCGriL1GIDqCr/XU6GGpRlzZALpqdzISkj95eQM2Ct0ljA
FBgXt8BqSBUf6QDCQwpM/FR8tZ4/GwWCQ8LXPDuiKGi+durUqRp/7DeM4F9D4QMS9GoimRj6SM9A
jQ7laUtiS/b8HNn/0F02MX2ib8sYLftxOzVpmlv9/BKRuxdyYKPnvNu/x1c6wC+zUJmRcq/kxi2e
PW/oE5vXrJX0BmcjBtnkGobSLQ9DN7ioU2HNaj4Cb2Qk0/PIdZo++skROEjojmL1Awzb9WxSH9BR
bBmsHNQh+YiryFtbanBhn9r0Fq9JfDbsD+mYfZb008VrnnpdoiG/ITpfDe2lD1Z7JK/WV3ahwD3y
hh93ZH2vqRJKnXM/ZZEN/BqJjRfO/ppenpyeMml9Z3MXETW689FAYGO5BwH4GAljjF0G62TM5fC0
253ItHNxvzGoj31F7ix71pcGrFHvmPvaPhZzAV6rktrd17ZgWMS357p3nU6wtYlAj7wb3h8xufDV
JktqiUWM8bsv5wciYh3RZjqXBgfWyWQfbwkCg5+RTMBs95EOTvCMVGyHiTh4QhM8JD7U2TRTcFqB
NZN+M+ekk6CuCPoWzwyCunv8BeXpW9cdUkWvJ6srG8Qgiw9fRV7m712H4uAy8owz9+LhJ5Kz5TCs
5+xm7X0byXx5r6W09mqhnHyRNMEDuzY52nBXga77oRy1XUAALYt+5GZR25A7YHhXtqrWu+Uvddva
PKwcekTuAfqK4fVatXEQrjTD3NVimK4lu/TsW+QhDIzYYmLY3e+TSbsTtjujAq+BNoizv+Uc5JdT
aIAGv0XQ1oqjPzALEtskIVlD4gmi2LiEfbAZ26wRx6oDj76z0wzGnDXFj8kWjgaS8bbFcCwbd4RB
7C2jCFBW8am1CIzj/yeJFa51HxUD/3HSLmEissLtVwpssETKLxKCPl1OOaGGWqN5If5Gq+A1LikY
zkezrWPfTugfwQfEhF79JSSefoL3N0dx7rZYuzDhjHYoEUaHMEkSYYNqpBH+DSlkSDunr7v+YefH
UBGoGe0ocMv/UzUu70QvSe3V01kMSFwfEBf48fjq9dqI1rFo8O2tt9f1WRrf0uu2lvEv2imOlbHp
ujHQ1U6wTeSFQcWrojgRKgoURS/mPnDBoDXxamoFZRtfiDZ28p1WGDTIkgNydLJVk9T1fwbCtwL+
u26RdBnzy3QwgEYiDRx2hnf5YG+kRIeVcpbH2GI0fy4FzPLlQBTuN4vIs7xecnlwhkpHCAhZOyfx
TTGnpXCscs+n9dpwWT0Xu8O27Q9OFEmjQWXJmPZa2mwYNfAtuorT043spMrJjUqoFJTO/ARyFcCj
eqgq8tG2k7BdL/tH2MzT2bYVnIie+EIZwbs9K6eAFXYlLlpyIKRfBu/X4DLlolKaB/jnkQmWoV5A
XxbyYKI40yQhKtbwvT3W7bvKlzAAFZH6BgAHpdL3xtmkibi6Owv/k/b3gVVUubNldIJu+fTJ9mXC
JeYky/H2vom14JSG+eiMwbk5oMXU4ZnIjRV6Ws799X7W6oWz0HcmdsvrUZrW6D/RmDHb6npgfET4
tE4UsNvYCZSEGkVhQ5xDw2WsOFqpmElbGxMddRYR/orE1JHZv6JvBvS09Yy3t88aFxIL16zHMIOh
oKua7KnFJy35j88xDmhY1cwq9n/Bt9tQMkYcf3dH/25viKZnD59k860X77UQxX53UET/q8ZFVUCE
yrpW2bwLvlsNax7WxVO7HjEzj4lTATy0Vrdczx7FFLdq+1mPeGk83tphSSljFBMrYVOQy7KIYtjz
N+zsSfFXqrx7qeCYDeruLtGJCj7IinP6Ns9DMYNyDAJyF1ADb0xlXTSRis58i6ZzK7uzBobNFuau
xkx4/LRwsX6qVHKKmiElTQfvK1Z7fKQXqU5G31z0sZMivq1HlZP2SON4CN93nBP7VoiVAL7WhP2q
fD4ZpYQOGGu1IWCBgmocQDmSM4vnVWJ4qo6FyzLDOIFmje5wylJxdV5CkMpbbBfIDYWjCfeWCnMG
4PJy9R1mHaTdAkLXzMw6VehpF52mBXtwb/YoBBIz09TerYg2ebUZ8tVN8Bpjhg30Bbp+JPgYzOGt
mF4vb0oMclJKWPCvNOGpFRGHmCIubyN3v5aDwoo8q4+PtspQmpx+OEIuOhFWqkp8VZNPJ2N96CZd
gBDy42dF9QAz5DUmr+9VLiI26E4vPCRUViAMpeWq0lM4LmuSFNf6GuL+ZJG9G7W2KAOSe7h12y2J
0nXeo7X0yrWb0agGGvbrOteE0r9p5zlmyW5uyWoY1+qGvtynOTOmxfZPLMSl7peJWhUQ45yGIWB+
gWpaVB8sym08BOl4Oq3LjKKAawLMrsjr38O+0661k744uHiYX/pqMWhUtpsQwyjYqPKJOfO36wbp
llqmvre2QIKvxQEuMswTev4oGdg2GvEgI+atSRBXdeGzBnOP27HiwyvX43+lQKnyMrqZECq21Sdt
nI20VdRIeJOIwe4xtvQPZE9rwQFG2FqTMxcL+e5fhg3c+w7NdQHyFfUdb7yPSeagn9UwthHhQBsC
XwsEwmHr8gqrbE1MhwFoeDuRl5ACmK0tjMFAm2ZfKqbt0O4k5EkzXVraSBkLq4L4wi8xmC++LTKO
0be1UMu06+7Nt5iAZMTo1JiLRwLnovvQ6rm3x4FE07UvcaunTnfSDCp1Ue7MlqZ1E037RVUyry8i
Nb8FZt+LVXhTIPhg94eRYXl204IyCHk8aXcMPIZi30Auj2gh6kccPSfm/tdp7JBqnmeqIAxm2pys
9ZFRc3Z2UiGiAAnMDmv+CY2qPeawywjiIvSUHKrv4Kc8aeS59h3EHrGsa4WyCNZThLSU6+gBmalU
TvEoq/CAy/vk4vHlmUd//HjMwOghEniT1uA3OWTZS+WX+o6nVJ5opzlACdX/eDJcEQDpL5PAteLn
cYGEMVMbkpc8ycxEuU1//8ZUh4aLm8ZnM9x008AaPL7pHP13PL1em4OwIGJa21jO6ju8cI6L/7mB
ctmyDfFCl8ggcgZ7bqG34+oF8C5DOfhwVZvkOagkL7SVyDxz7+buLrsTCgtnjxaeu6V+3u/UlLPP
pG9VrcNOyvFSSNOJZMHrtVNtpu3p0Pm07k9gqalI0hdkAYdLvX9rquh17Eck1ria3IyyPMjiZjrQ
bjpTT44MMUbEAJiRoMRh0VObVJt4o9Ej9OtABVfY74uFmL8mCd5Joe+0k3mo/lRzMb3JpckKB1ha
hl+SrP4x61yLc9wk9Oc96PTuk0ZgmYljdi+aYIpY6BFuTJYS1FtbuI6tzW18XG6VdRh34+1PwlTN
qVmRdUfbmv2ClU4MH2sq0P5nvwb0bnCG5BHk3yFPVZUHdnhbjyr2DmqDZuV6qd2V64qd0nzvVYZi
zYseTQLxz0Kn/7rK+FfI4aoDyXrr6MWnBsULcaEKkitXPDkVQa6NgYtKt9n4k1ikWGwoqkeqdKtE
MSEdSOVlgekx0X7globIdhlIBj4uvxL8sbVtGpgRsakjI/TOal2t5IoLJ5wNb4Q1zOHbS8oynQom
zC2gMwwAXrH+gCwroa+5QcaMSdA0aCtxGDmA9boeGcUmnctKyKn4lk5kYxGZCA5jp3K8mj8oKtc6
37B0Y1+B1knbBzwkfkZd78nMXZj5frSWg206lBg9mEPuMTVybhL1NFDrF+sPOCjQHi0oXbKJYee4
IQSVau22ampPYxlWe4mxJoHGRrCsDEviAfVHhdxXdzyGvwfINxTGFiiNlsKVVJg77tqFSLSfJNEO
FMQyjWuxLLk0QfyqzI9fRqt+HWaVNIAwZthF49Y4zrVW7qldkKAb020HCfR4WSbu5IUaZhJ9N5PV
+ZXDtxknjLJcGFxk+bCr3n2hGdKCfqIl2Voquz4ijCMYIdGDTYKAYxa3W6vChtPJ1yixozIfcEzL
8XHwvkw43+7NLTGjVQoeyTUoFHsQwh1in5MkNmOqLCCtrz9qEhn4zhKkY+FHuByaitV54lWWGZJm
0QXzp420bNrOMRkrGpqjGNfGC3NgwLL8ZwSekm9QLvuBfAm9GTnh0wlvv3sTu9bLe6tSpnvmwred
VD7qtCrcmg04hfQjDWEbKrCr/0w//QThrp7/4o1qgmxeh5H250j4VHkYUaPVgFlZqkbWWsjbvlD1
eC/oHnGGhDB4ramVy1QEYlz3NB1KGtkMWX/mcrtfZbppC+9nwEQzScSLieTgaYRAQ2nZrtOFt46Q
9pOOwnA/Bs3ONOFUrAlKtql6vNtDmwXWah5diaknU3hZNly1HkGpVdI/NbiA4CxhTMs0PngrzKpW
ZKfZlEnR+d4x4hbz4lA990nzOSN97TOsYFTDGIJKWTU87un8VQEuTpOO9xkOJGNs15ZCnc0aFUc8
ZWY6mPgs4XP+kT3oqPvORjjjvyhbxR3FGpy85CrW06eYDywLbJhOW1NDVxRIYtrYJRENReBxpSp1
HiAOt9lAEKBffnM6ew8iQtpwksjDRXAs+pgtIsXyJugzntpgxUo4xXNixScwiwWPIjhdlsZXpUse
eRpRiUy9Zy3oGT8lSaImcMXhW0epd6mYnLlLJiPaxMKeCg2mxxSe+ErEEJbyn/ySQ3dortWJOzWd
xW4a2xX/AA4K1ecNkZVVdKThYEB8wTGxiX1bzghsvND+Oat5SewLJ6heFouq9MRm86iCTUDUHcwt
mmS0p3tq4m94JmdxG2P2fxmJ42WTHlcLGd8So49ePYpqfP+lpB1+A2Wg/1junW+VZr+knrBfkxxq
U9NNSdE0puaXws9mC4K0RjR+YniEIjyLO5V2SVst7zHtwjBfmbwK8DUJe16ywxYMqQH+npklIfuJ
oykxvFMYTFtuvSRt2jV/akoeOlw+i5U0qytmdI/M8r5ED6V/TYLmb67tbPrMGzx2yLbzLo0bmnMB
VJVs/XvGWzMt+wHoi/3SoKFz50/+Nt/ISYMAR9R7qAotzPzBFgKcGmn3rhKyxGVhwZeY9AWMuhSw
yF23UDC8MU1CfqiPkF1eMjl6sCzXHU2vkH2ZC4iEPY4LoLgG5IDfQz63bLrJY+/stdcsItMk2f6Q
1jEJJ1vDCOGc7U2CWCnuylcwGu4JKg1676/30iXPvPC30CR70irXGvLsZek48SbeBO3TdKqOXB7O
KTiM2sM6SlKA9Y5iM/NcWGhkHPUCLhxPe+er1lW3GXQe8MakV0X5TYvijaSja6mTaOLpVw+mgyS5
fn59xlFm88Sb0QSAiqb8++xnCRWwlwBPAba7tALDrptTs8S4hyX00FwuiBvSD7NaLMuWL7ZvD8t3
JUrEUloMXSc0HJNrCBT4KbJ58ci0FbEcr/1LjM43WbPaHNKV6JAnR5RS5lbYjnOzdV66fUbQ37V8
IWV5T6wcWDTU2oP8LcaKLXw3i9JzFB1e4Phsq19xby5zy20PHW5x3c2jyV+35vys27qCzmKwsWA4
1JiO+6U8IGEQIXv8j+uO3MB8xe5JF+W81sCdcSEJigqhK/h6sJGy+NZ4jv+3IWmdkuZbUQtd0pLM
8EywZCWkQXDCBwToRXNP6kmF2fB9SVGRduBmfV6PQE0hjAoDqOKXa+5/mB0HQuRysult3pkqQ77x
T27h0s1d9cM1ssqLLDYK7tg3XM107d4KQOWsJN2P5rfSe88UdMHeZByw/aT++BQC7s0EUjdfu8MR
Ww6KAYKGlW6dI/szzLjbrEt6pCHjBmtiSt8nkIrFDTGAriDCGvPIAhzeBKJZwrPzmJ6vi6i925/Z
MZ7TBfAfgpk/CDj3Q3xr4ZAvOf2wHbwYz13pRYH/M28NDxQGoYMHJQerX6icZ5etbxEKMN3hKPGc
5FdOJlhVsFJ8YIlblKSZwTWiH/T5sU8nzN8uZcGEw+KEiHb1Gv7CdUw2Gi/Ly4C8ny3PtGGpQqDk
bvrVYAg6w7fgmj7XmSriQbipC77cSJJXo5b/TaNE6OymkppRqbc0JCJ33WwlRm8qqWwoz4dm+Hwk
r0AmQn443JINIYcnDpZSXpug2M6f0N2jB8GbtUQjNgOWAXtEjhwJyPrE3DraT6wY0IF53wTezUgA
nxSRsn5gUaYKYyVVi5SM2U/cUv237382QvUVA+RQPe1Uy32FHcNa0F6najpHon6UOaWr18JLWlF0
UplGylPNGAdrMOgeG/hKdGQDyGU2GM6J6rnBcgfze7eo68tUdmkaYQxERBZ3f51qS4IPF0l48Gig
v+1hbZgiLxr0LII7yzfYDSZ6M9UvhuFI0PsZLU2buEz58P5fz0pRQOl62rRIxFYTY+4nccB1tqte
/txrQL6UY9lOxkB5En+LgKc+9eENMgwy4kmSI7bSc2RrE8FfWYyE8UdU/XhNvI5S8leWGSaqSdCO
g9uIYuwUFWyKL9wizebZFKmlXoqsqumdOska564k3ia+NGQyYps8TE4okPpQreGpe6F6OTxM+FYj
Ka25szg2hJd+TxLVSMaNmw2x/e7z0sw7FAWhHlT0w5QxjMfM8jCdwNUR3XRNQ/fU8k8V+Gp43Oom
pqECR7kvVVK4eTUXhNtedxLL3QJNufohmqdsM+pdIUOju6lpNzDc6Kc/xn52HTjijN2C8t4cEvop
xhTfCfntii+/Ld8NsAiZrOHv3LzK9JiFW0za4+2SD9FL+9+Dea//0LW8F4Nnmc4YwPJcghqed47H
XqiK+ayTEyxihYZpHWnUwXSUbeK+vT61nrhVKAhm/5vJxC9Sg7TuDqpph9bFFSaHG9EgNaw1G8pi
C4YYfgVCIWgNwvoxmwakdN4n7NiCQ3vdfVw70fWX33yMONFwLzPUdHiUPeEAA+qPTooNEVKa76vS
jC2qd03bcUNixX8ADUfyVNf1E8FaEZhz6rpBCGhayVCiDCireTIPPOKCrKt8EODMEHE96OmroIbI
CmxV0J5u2ySiA6efed3K7wb7uJCgewqx7ZdlXfNHg51hg3jzxFTQeeUw5AWo88ccVtvovzn8Cjpb
8FAWDFYprEcAhxa3jrn8kyoqv9lShuEXMVhH1o5T2HHkbHOoaVgGXSHK4vrGLWP6WIz0pGGPfAof
eQuJ0q1dvMU1sQrlA3po3NTGO0cAnRTeEmu6iGS2yfZRLLZ3VXqMNrjJa6vA9la8N3Jw9S/pUBrt
OoID1p7WF1FMdphjHxq9c6C0XO+rDZ8cVRiihFnBhi4viFGqpwV4qDomh2qiI9LNIJ0bfszYvDHf
//PiEZuEeRigNcz54K9oOvizKBe3WJqiwGLYzkOElU3A7pyvO4PKnZzyiYs1D8I6fo7wnyls+yLi
MZ3i71L7yTXXH2W2tvEKq7MHyxPHSoakraVVX7nBRLENjXIDuk9fNu1uoNEGMlNlW1doHqX+m8Qa
KOuvyU5qvpXhie9aitCC/zuD6FW30jP8lajE61fWehKrndBdKuKTeaYGDQCtWSzPcyRCbHHTZxS1
7FmQRxVvOzFTRPlrtamzvsZEHHZB5frtBwcf8AezkMfUNesINaun7JYg9Z683R+FATpVELJmSu9s
ICjVAhitXYwiyQ92zOhvY+TBLJS9oBfTtzmY+Nu1pn+O5DCLL/hQDwHaUft1DAsgRd8UwG5N8yxl
NWak4B0hBZ4djg58hJqxIwNRkub2IMfzBx/nJMpo4qoZd3+WQueRry+gUYglv016OAX4aQzI2dqZ
Am30j6dvF6QJznMXlHrKTj+bG3QEb/k0Mdwdue7IavaUmkYU5ttp8MXWqLYmO2KZQTEX0eUPW0cA
frzpZg2yPOBFhTOWXGHusgkwG+iXn643ylJ0K+ioiUExhukxrNaxyH5qs2cJgO7V7b5u6ITy3CII
ExK8eecJC6d8/L7UEBPrFggLPEBw2DchZB0/BB2DscSfhLJ/H9q0w6T8vRMXldK1g+JEC6M1RPaj
kkxeNbU5+XPDsbx2Y3+yhzkB9Ye54pqshRXTNeZBFDzhJq6lMLG1tI2hLX1dVpRNfznPCevyr5fE
8MD0jleQUcPO+YasqcZOaT5zZzk5ZimrNtyxFhbwmX256zXowa3/mlhlyLHGB9QvoPlKHhWTM9Bj
APJvc0ncE3ck1QBHF98xfvVyJNFRNVowCT8NiMvCOfjOHWaHaL2B+sRTduWwOKts23Ggvibbx8oP
2AzGiIX7pGl+8ERopOO+q3xY8xaKTX3OAU8Zu2ASESvv1CQPvE0DMABfr1nstgshrXlBUOGHjzxf
CnhLy59WR8Pvu2leHBLLYGCONRE/zuLHyKkLKHGBk1wPKMIF5TwYaLwK1pTgjc+pNLysHAnRt3x1
ZqgifvmKTUOh4XciqApdW4VLXHKI3zE5ct5LJKixldntm5v8ozeO8Sp6euiASA1GqSAO1kGhD7BR
tNApNgqkE3duFwB5rCflLzWAC1QbYnRuUHSkwxj5+DA8IikE+vh8z+VzSQBl7rYKH/TgCfIUpUW1
ZqdkVIv8HDY6F9piNpE4SqWPh81Z/RyYqtN/qy9TQMfNyRQvsthhvWpRm+aOQu2HAZ24wFtY/6Yh
Qw5zlASjkN035RHxHFpxP0200w/GOHpIFRRAIIMBQUje0vk8RwwvDOHTU9TgU9PDf2HxUbHCHsgy
3la8PnLANNq4bMujodde48LMSBNdmyF/+U9TqaXayVd3uakREil93RDH3OoNxa5WNsF6muhz/oDq
OJeQaqoM9aEE+Cv2/kNlj7HLEO0vUhgMLrf9GAJecwTT09yC6r4nMlkFWI0FgKewCV26P9ytvn3G
/37OTJot4orqT+3Y8RCyv0g1kMs3Jhisf9YoDXaSqEq4+GNPRBWWU2YW3c9vdK2lVYQWiPm5twsq
O/dhdBnm5UhkGRHS2ie7Z3D2WCi/b2aZ6oA106wlVLg44Psb/dfuy8HMA+it3eD/Xmyr6RpLkAb9
D0/vpiUnn4DY+jD5TDHfYzzFCRJxCIRlsEZBNFLv32tSKgdIfJ9QNSXXRrOh7/pdZzOAS4fxy/xA
ioOYBIoXJYnS/ygvRIdEJ74f3O705u93jNENzJq7dvJfzu93pQgbFvAksxAanuo/bEoPP5MI2Cmy
txkWK2MnY6zsTg1jARROSrVgCM9oES1zJ7F6FKZGIJ/o08IFe9z4aDmcYSxjAeeh4vAlAz6YTWdW
WTWh+K/kC0XkcfgfLBjXNWqTwbQiggvjGgGY61pHHDa1+PlucM+K9hR1mHlfzSXgqJ70hqpQKmjX
xz194YoNRE+Zso9FN0jDDHxQpfGkvcitpX0WLEOqaTPpoMrcShF8OCrMN71sqk6raOC3ipHvThsR
r8SXsdagfcr0OkNhWHk1eoNXJ2LNQtpSlITCtYwxwCUJmzm5OtQUnT+1g1QSEaJyYT5TAEA24JC8
16sfqAaEGR0xBOul7p9eAMUJUh23ClTb4ulXR9oCYg7pwelLcmMnac+/9iXmsuHdZOp1OkI3k1BG
ZqhhbEnlOnZYKyZBPw2R2m7yr3oALWniD+NxKfT3vMzcQ8ffb+XRLBwuzSUuBSwyD2uMXugRs2QF
Au3Qs50BoULJfXeOWGCmiGo2KoJVwLDvJ423YSr7sYHkTVa6RTWZDfIU4sdcT0xnbfVmQJk+oZ/w
Ai+JoZiVsLnujgbZ5fs+nra7/zOxy1lpZL2FL18NERvVSy0qV3IS/c6TUMwnwoO3kOUPCzx0qSjH
kd4/21uUEtkH0Kc6PsY2EGqiq2iHT4LjriGuW1Bwlqs4Nh9l/3ejPaWN3ox2J6UvgjB5JHf44ddQ
JR7jHDeYGLYonRc3GtHoTas0nrGrM2PfPkwjr+f9lWuvowFEg0+ZSA4dy9IpoaNrS+zWJ8vYuCQY
5lW7UHeOxxnlMoZVUher1EP5PB810KL7xfBsHJy8oDjD1Ooo3mFam9VXCsZT48uwXC/aKLZYVkWz
eKNXdRddDbMAjOcw7z7yWpXzV9F0RL6+WSJMzXnusDIDvyrs1/Sv+lrCPR7Ax0ibtMj590DWkP3C
ou3I3bXCQ1Z58WQP9I1n8ds/+fqWTkzyedCJUMxcc5TSZm5cGgoGlxYPEtFgAO2UY90zR6Xh3MLx
COZ+BkwJDLRC3zxjjsHZg4P/mnN/V4SGsWpGIhd7N0vV4qighlh9nd/lg2OJ+RSjK/ASGvReFg+Z
6Ti8XTZf/LX0od3SV0y9rgnff4mu/4kJIypYQEk9QH7h740dKLQI987l+Yp2Pk5+JzF6IhueGoh4
HCYJoBdyd4P+xxN/saz+smL0rSR2jL1/HWmvudC/fc8gTiIOIDUIzSYoD4paQjICy33BD/tZC2l3
BJhX4z12oFw5Am7YNirA05fywDqBD5iwr/LYoEOIcYwDxGrTysVLHAEX4BcHh9VxkYqFLSh7Ofln
++5edoi8ln/W6hXoSvTE5BLaN8kLvpvgaS0iSoMPSLLeTG9v9PLWJSyqsqgVUy3R1WZpyiErzjTp
avUMNH4GerKZ7GQBB2QvNgQpQWIuSRBzUUIgzolR6LfEgyF29bNlyMZs/UspGzVVKF9W/hfXkH2U
npo5neZzNnf31icab8BWcuvYo+8i9QTPi5SioUAXRun82OR6ZLJ4GuDtF6uP/tCjsBRK4eCQMmPP
eEzzILttdLGucc2NlajrjlpL3KwGdA/UCsJyZZMF6Xvr7vDWJLARL/ke2l1L4pgCAA6QpxEHinO7
poAnsntJttn7w+20G641TrF+D2q8dhOM8XDGEjGNv1BTPTjk9D3yex0gHEOy7IN9J4HCwT9CZFEE
mn/aVaKclAsug4WE89YBIxUdsJICvjantA9iOtvGuLSDtCsYqA3SfGWAAuTyL8ZyJKchHQFcmszc
G55Vb01Gzmd6imZ835zUXohgUYa4iDB8b3L87s5rbvEcn3k7x6mXxcPyW/g19afxAukSBnWrL+Ay
KKVOisvgt7ewcravWfjsBRIahqYn9wCcHB69vGO1y1lpyPNM3G+pWit+jj1Te6JZ7Es47YUzLNhn
Y90jaEG0ewNRA3WI6yVXzPJljjEkc/kOrMZYa/b1xkzRIrY5jPw2hhg0eiN5lAZYW4TilX5jNGNJ
XilLP00M2zMT+eqe37kgZV5ckCEwQFbSkRVd4XThh+wd37J2hR8BDrxALMnx0h0DIZ1XLQuEjY3n
l6dRb4Mud8Bt1Y5ogGepYaPPn6/Jn2EMv2rJ/UUoLgBL2O4elAh4G0tVG1SXvs1bmhhE/xJE5JAf
x9CFLqTXzLkQ0JIrwRYO024zPXvta5T2ZJvW0bto7Qroslh3TMC8m0OrpfiwSjFQXUx6q4NSK/Gd
AkpnYoQvQpNo4MHG+OC6iFY7ysME/eyYjDEOUSTdiVXCTbqBz7gnw7eT1sQs3VFs0REPkT/OeZyj
SFOuo298pYXmPBru8WMidcSUGK1kg7+tI03vN5p1WuH4nC8UceiCW+KS5tjAEop+Ayueil/XOp18
Z2E0rgoWtD+9H3Olqpr1ih3YulenFiHHuLeVqQlF1bf9NxQs/7oNNVNdRa/veovcPVZvNZj2XENO
zcZ2tb/oj6dfFdwF/3Kt3btRVMg9BJm4zSqbfYkWoDr8XP7J3dycK37UgvKL16a5G7H0fiiVrT8U
gy2gIdiOAezDNEZPu2J1b6KayoM9G1e/huahIP5VFKBFX9o99nq+9OguHi+IBt8CQ9ilz7N7yDcf
OySyqpqdEllCOqNLrcVPdr0V5jja2itdsvF9i7kRSHb6Rue1QrQhiUSs5JkBYEmxEDY8x28wnh3x
BXZTAurcKR3GPaJ7o86CgdXtCevYGF4sgkrNITmulLwz1YPmOsEgwn2vZdp8/e+nb57vQuosVMlg
mrik28o+drn6LgOEjCBjC/fEFFJUOAi+oMsCEjDUL7C8MAkT6yE4LTti8T16QsKzrX1SqiEuH+ud
HOJGa4IokzZ05cJzR6BfwJ4TIZpKR9R9hDiN08AEe1euCn1dz4sRSKqLGhXZm4dxpVK0ROzNm2a0
k1epCbAjEjxhcF065/eFbhIwryBkjXOYyyzJDI7N5oL/YVzXjYLLZSl5u3N2pBbJ4x3HhkrJAEtn
ltytSJ0HkWSEMXesHic2UYKt4p6Ee7eHOVb3cyVCWddWlW/H85F9Sc0uxiUsxVaZt1uKCirBbIH+
/v6AtGqlWdhNPvEsHwVhqelkn3k8NEQEYs/Yb0t2Qlgd+a/hhOHUV4HtdRFUbB1P7XsYDTOZ4tui
NORbERskw+FNyG0UEuwELL6s79qdfh1cy06BJyM5U3UOwHSnjXE+LnzF9CO8UpOaW8z2nikWtNPL
razMZCaw1Eq8umdjWd3UVm78nj91i454xYdlQ9e4ysGSjQr+viv5loxnTN/0T1C81rFVNXrOgUEM
1aNbsgZ4pVrDNh5EZlweZ9pQC18KMeXBTo0aS/P7OUtjC4lQ3x3eLij0YfGvuGzvcX1jwEE2pJTk
1INF2KR04KShuW9X9NiVBflzxlAZSbxQE65T2g0OM+yFRixVs6naF/s5lW60IY+gj90sNN17bQQM
87cX1ULfsZXUsm3g2yDK7QgXatHhpmBJ4VAVq6BWsiXxabIzlCA6M2CZktm+1JcscvGrsNMy8Usw
6jupPaOIHkHAdpK6vYWiYhBm6BQhqNVa5JxuULNiN6ekzeL2TC6rycmAPhU1b2InbMgQvW48jW19
ZST4mUxEKtfNyf1N+jdVmI3LL79gVivLNKs5JLQcSSAp+G9v6kxyiFCISu7E4ezqBsWxH+6INoF1
CbOuUiwi+Vt8c3eBR3o+eaMR+e/yohMF9UizZjNk8L5LQeyUeQJx6HWDoI1goC2eAxgLzURKZ72i
686pBNTxKIcNRhBsqPyCVGPRYG60bPjg3fm3K54+a2wrOxDgnxPuGy1dsvs9u1mchsbgz+kfH3zC
kSpKlsLoBtRmAbgivDCstDM0wecxPfXhHME53mUsVwZSnHOqrcOsCpQc+Pl1v10qxryCgozEpC9k
HXFn/WYWB64Z5HFd/t2nPKLPHpTOGNDxIE4Nanj6nThvcjiF/ZxsOx4QAXWopr2KSSLyPd5OegDL
8ZZDNle1WLx54uTK2tZ+p0niRTrDrgGMR0sOtYLCX2oAoTkR2y3wgNQIHluoteLzaNz1voMX9xwS
Oimfm1wSw5i4VarUn8xF1G+cmlo14EdXVW+r2DkOnFelA9j/dv9Fmffj526d9HDMZDWAJqdU45qn
t/mgnwhrZoYFsdKqByhtZY+9A4B4FHWcG8x6mRpW9Ao3Leoix6mNmJ9g1YvqYL2Fd7Pzzay02XKQ
YQ0hZOKdpoLmVF9Mkd72InVFyYv56s1vide71sFECTshBen3f2Lc+m4DwNqPfv87d+/No63W0xRF
vKIz2YAEB5ru8zzeKn9ooovfh0nP3Kl/OP6E61pgLQNd84zAN8Xvcv2Nd+wvKV3Yk1yFjgMulim0
MGi36zx6emDz0pPtheurZghJgbVKM5JFrwSsfT8uHn2eNYJAOdft55XWu+dkIxKtGP02U622ZQos
F+8mG6amKPXW+OByiUVVjh/iDm+5w3QP4tj9mnU1sVt+/kl3rXT/PTy1N8pJyP8m2tkqKJyYjGr4
SKur7XNZDwLLF6Shq9DuGjGakKrRAxxKKIYLpPFpiWuChWVZhcqYjN8jaRuHi9updR+OJfoMva76
WMW+XKplTVh1/+uF91glbUc5hazuqvsRRAwJGSqVKzsCYB1FNkHfA50ri8v+5Dak6ikZdgrlEW44
Mpg12tE91vj6BizsYzDu7lAH2LKNnNLOEhyh5sWJeKxxamSRr8T1JFT8BID+6dz/KYskNYIbugvb
btRtAjSioWzKjYIdqfqkyWuqa578LIImMg9V+vK6g+k+/uHAoZqrNDucdJCZPI91rgLrt2r/dTvf
jjr+sQn0L9s8dPwgR4tYvLn1Ywxzqog7M/hQ+8GSjqiwp4PbNwbpEVpEjPlvLP8HnhCPM5+QHYlC
L2T9zgce2bHlr2mEirgs2nK8Jl0Sndn7Z7bsJjgpSfmT2Vy5tq8NUPAroq03YzpmxXaM3KN/L+z8
7zcPMNn6pFqgyobpF1e1RaXgNoKHwWUNfqJ/sRipVljvLN+gZkIQuEHBticZi8VVjn4WSwGG9Zo9
0N2eFoRfGV78xdYxJU8ugxffBwwJwS4qhsk3m+ZYWPQ4FiAZ1uxB5MmEY6C8NHp4z8int9lpqkBF
ckz3zU+ItKvew3ECXT60yVZ6DYx9RiPnmK4c3Jm1APpv8GJyJ+5DZvKt/dHLz/gxnIfejV8kZ69U
3oPdoKCaaNy6DKF9kjxCLHttwTFMIsBNvgrAuH82Rorm1cdINo5XeSRIZtan2TTm/Stp5Yf4r6gB
KWbYOhGPfT456OyTBwrTvI9ddtwAb2PYEIBnvAdLJL5gKWo5iJEsmv/MlOLvwA1LWzKZPB7vH1aE
C50LhIzHfXOybAMPFYLU7r0H5LI3BWAHAqsFSY3ikV0JMKckTLEuvpnM91Csbbz+le7mpPlqlsAs
HN1fAuLEPaw000Dwxf44uH7GXaTbIr2b5w1zQFbagfaw1rMbbrHfQ8tXNbj69gEJGLdwIxGf/vEK
ijbCb07jqgmgX29nxffBNz1wPy7Hnv11PU+csLV71GggKcZiybRhAM4MN6r0oBkG/IShcXxzwLB2
9TSXtQqWqCKXpZOl2VyfWn7gmevdHaXPAwvhFR2lzxquoC7T9uDtFQVfWL8ihloDSHffhEP+0JMw
N1gZaLyifCia+nxFkyaum5q+RWMu02ie9m85+roiL6zenUx/Zm+rZmRik9xZyy1HCrquOKk7HsiM
W8p6fJKYbifFnXgeAJumfvl2wZP8peUajTua9di2GV0F7avEwS/BS/WwrgijYv4Y55Y6jia9Qk+V
u1GUfxirdm8M+OpKxbSi+5piNtGRD1iLMWgZil4suHNPBy4IEm7u6JAOy0qN4i0llRCI/G2a9GJq
wL9iWDni15782vovW1fUBNftEsuFMFaiiryzNlwdH2NiLmxcv1bNX+3axrrFIl+Xsic2cUCRFLWe
Qlk4ZQpsc6sQS6O2JvVoKUZL2mTwGpvTlbaA/7hUrvkO8LN9L317CYqJpFBnrcHoOtnVphLzoJg4
lXqFojUzFrUk2uU8GcwWoN+5/B+G3niTc5+cnPKWXYOdg5c571MTJAXlz9lGKoZK1/UBVdyBeVY/
3DSeIuIpnZQXSJXIhGdGjhVvcu8bbW0epn5VQFYnUnLC+qWWqw9IzCYYcRL+80q9M4npEIiJlbLa
1jL9uKdKbaFItTs7BM+anrdrNx5T8vf1+CEQnbUd71sH5npxzSVSnqythlUYHx1OfGo2182xrBPM
v2Ok78XquyYhk5alHnjQoFv54rkSgxL+ynpS/G+2NlE0Sb9nkjMI5LkWo5PE9R/KvWqQPX45IZPn
CxRBcduMCbwBsBsS4y7/KsxArcYjf7WP/X5KTwQYWOKWJbivmn8agvKBeQQOBe8+d5JPqhbEb+R3
s82cerHqu3wjlWikMiNnXraj6B3cEvlWmvsF6fBa+dojKRVIkHGd8o9auIMaqyH5Rua3sx3IrAsX
D6eCFM5ifznCjGK4erHeD/N5SqMFcoTZTMKVrvuvA42+txe0vwSimN0omTGvZwdmqkGSEehEoytG
MAqqrm5Rfovh4rHw+1jYRwObPIp5XOuzCVjK8r0XBa1f/nofVgoFOPdUE/0/vYe396U4ky35Wy59
n1/DNkPz57GqLm9hF0q1RByxIrL6Cb204AWOSxIk5XLX98i1Uv0Mlg8BjgRMnpSvMNR4sgVg5wIi
UddWzPMvPgbglSw1lpAARzWMsPwj7VIVospXXavUfYDFx6gS0DqDLA+vjB/kHwZlKR/7Qsbo6/jC
MLh3pgVELPLSy49XB9rI7hAU0ExDGv4VoAWSncX/IBfK2/9LvbSN0XwSj8XyGPdNkqkSXF47ZzSx
9cmlQ1pSgMhoxnvnuxtfqOi1KQ1yk479yDVGlmC40/kMdrYPL9CKfk3tHIJNKEt/fInPVEEeOHIf
yZ7J4sGEHvQhyY0PAD5opEer1BTN6JgIkETP2NxDr0michgqV5aiy2EG+sY6iHs169QRmyY+QsEJ
o4WoCyN5EMvSYi39isAx5+TiWNb1pR5RqcglSg8NYtVcVfkBrqpCfCCjGwWcomqXkecvLP0xPVMe
CqyIRHihb5lyu2270ziVL9tSs3A756P1rvjWM/uoxbVu0RW1+agBE+Ezhl8I72+7Ni+C5cjo1SWz
yIkJ4xrrb24gC7Ff9+DYenS+jVsr6vQn4fPVs1bwtnMH1+GRwg2Z9gBQleTU7nHD13ZAnMlWRdl+
6QKItJXdL4gp5wOF1nk5tyJAO28IlAnI9kx5PzlX5W+zecrxDhN1ILI6c9zpFhIKTY82jrEPVEW3
mmHJsMcyh9kkMdpqP81fBIf6FrLAIvTvjS453HMIGBz0hmR5MA6/0RMWPmS94ouNUIxJvwKj44f2
kzWsaM5TtfHK6FF2CfBbvKmZyBmiAMKB/iL5kW23NDGLUA70mwWiQNMSGxkCWp11h7CkQPz4WnWs
X45FJPZLErIcHMyuByXvAninMDWhDCZoTjc/ppD6kEOPsu3scWOLlhqESLpoRzU7ZTRC520sY+ja
nvzEUcoKEKYc5Ml6GArhjUYGKV+Q7PWqaJdQIrJEaI5WXu7tw901DcKm/HG3bZpWLIMVWukPKCQ0
nmFCbf0MOdMqx0xnRu5nxpkQOqQ8/9RPvCVr+3t5ysbUXlv2kgKtslACJbg5z/yonbDTVHbc1gDW
YvxK3UmbzAtGP1+YFqitSqMlAqooYiC09FoZmHWcnbF5EWCL5c4MLStF/ZigyPXY2YUIrkzmuDq0
9SX90IRc0U9LI4YmcsWZh6pOWV0KDKMvWwn0lMacRh5PdWOdSQQeMXE7OiPbl7689gqpr02/0SSR
xDfRBm8URigHrSgH6Xmc/vBzXc8cvS5LZoO5nv6uf7uBf+WBnTI8H+hKjHCbgc5zDv06q04Du2KN
kVtmLnK/qXRZmQuxedMcLh87/9g2QMQOo0cWoMyGH3+xYKj7C6SUNnv5Wid49q7O3ixgGdWRqUeh
5i/mKMtNIierj5CiQd4rh+2kfyzElCyQ/fYhdzZg1iLG1WFeGi3TUxeweGsu0NWGetV/5X1zEg34
PA7jtqJvkjWl20qfgVsbOckHFHMpcJrCi0Hs3aOHDI/p5oQ0gAJBgZSDEVPEaG/x3w+isXygMi3L
4OOhnQe46ksDnnEtNwVVFCk2MyXUVCRsdz7b1tU7EbBgpftZ3n/p0DeXeyovS8RJ+rrfaYAtd1GC
Fqh2+Hp6YRHZV4/80WQgHFkyDcj9aVkxYecJ4g6iSIoK1QOoJgT0QOpcnMf60wbNgippFyodliMT
QH2X5g3exs3uR0k2udEtPXUj1cfyVmzoJVVjIhHrGSFne5ce76JuXQVkdfnWub9l04UIMcd1TVg3
8tyPzCbmpfMdjMXhlNF0lb3QlgdOBwLiWPU4hl0/JZWZPqaj9VtsHWJdwncBXeZrQxy7myH/FLic
uVF/E/e2N71lue7rWE7WEjgF5ib1A6buoR9he38u1P68H445vZAkeGDxgevn5tKbsnmYgbdfZr/w
Ci2iLARWxcQBnAZfRg3ESMifsPe24HkWuvrd/85a3wfpWld3Voc7CYxrOmheRhUWBl4+W+uyIDTo
I6XaqGmHLAgfmWafsKduzIseIrWQ4CQJQHMcpMc/TFCnrhOJNsaMFEwMZPfM1RefJqtqSftNxzBl
0C8YJCLtcZeANdwey5K0ls7cBIiGMT2tpGVctAvdqjgvncr3bg8REqlu6+yHXsFryQ6LMxA9u6Qv
eDkTAc69EeSVxyjW55XMAKsfdez+sDnnmNAWzkZ6RGjG7e7ACJvGfslkNwkvTm5djcyemYN/oAKD
FHnJ4uukKMueC/KrZOqcIOd4scAbD3uLW+A80niiY4VtoU4k7x4+PjaVUCnt4CEq/U+p8lehTt4l
nCrQP5J4poEP3ChNeJ+azOCx6erEqESfVgSKSpGtLfpUwrmWpU2x5si2MQz1o/Hc4ipc9AxvLFyo
pZWcseNEOvw6OS6sg3nlzgXJKgtXRPuggYBgel6nFRTOmXsywD/gVs8S8FdTtELimxkjpmJEltLj
0R5r1kfKypYX5srcV7yFWFh2xLhvFOouePD5Th7b3WPOrkhH3M2oSKstq7f6BwpykWlgMhrKPdM6
Zdh/TqxuUGqrXgy3P0ay+br92B7MX5WQRJzGCjSuR05fiOXXji26nuz0/+tzZci0DsTgItgjX9By
F6nUnNB450OHgsyNx0g3CqNmy4hLROoSDFbEVRClQJdtlz2uSZIxQBsp7UgxUz27x74WFweSiNaF
PNsChQyUaaolX3MHXxNbfeq1uID4nEGKHG+6abY5VyPVSq9Ykf4FngigyLcfZy0XHuv9CXdT/zNo
GadIIUcOqku2NFSMjhQrM2QhiFPLxESnlcuM2kMbB1NVHYajainzi9ugMzo7YIXmayciH+Pvp7qr
YVye7wI0eWr9iUB+WABxY4Ka80cBP9VID/YHsbr+a5CYW7jDYpp8yXRwflVN1BvOgLwweR+GBHCR
Jzn0ItvgXl2DJEpcR5Mpj5waWDQqUTIadVbEFXLcZg91tvupjvs3Dpt7YUkf4yVpveyEUNQWYv5E
/BwHipuyYibWP+N7HMhVUYtbdu3U14x1eNancUXwgFoCY4aKNPEejBBXNEmG26VT06u0I7x6uf7s
M7NSsEub8mktEa83wQJxQyIE2O/69MDm995fqT+1o4kohGPp9lGII9BzypuHN4QcjX8ErSHTbJJR
dm7SvTU702waHVBTj7f6OWjLlhNalwCKPXrC1a6FxeXy/q0U+lRFOxHGDIHg/dHRfuZz5oMB6G/X
nKkoljFqE1ahHZ4xBnXbf9Ue5sviPxvgRtPUQlVWvldcFGqRgPTi1RBpohZ6UU/HjIpQOmo9gjwW
9Ft1MOM+DaXfImT0zys/TU7c5yPL1odi4wdoZJF0LCAPJiVPg2kayRKLfxJ/g5oQICUCoE11TjKi
udfXONvWMEm7z4t+wmQqX+HPopMgXn8ZaJtqf0E4Cz3Mjf89f3+UF4yncK61ET/5D1Lsm1n4j9yC
wqw8C9wjeOWWX/hPuiOhzTT0ZwuvivCOIHotTpdGg72ybLIyKG725EaZeLXnoZGRxQS82qyO9HP+
H053dxSVoaZn1Lg2xNZY8krDsxNvfid3f3NL0J7nRGXRwXbR8/J2SNYvFRc6TpB+gXF1UlI+Pe1n
aSv+H6Bg0HdRRhVCZC/Iwz0mg6l9y1lBh3GvH+KANV83OmmJJemA3BBLohUG1pTlHqZZ0iVudgxk
KsvP1QxnggP9E/fjxGphVU5KnrqoOrtNTLkJL07YRQ7HkhP7pG7wXL3hlm8EacLr4d6Qo3L0YNxl
D+04HPE+IgemEsJwaRmBFCT+00XX9H7QBG4IPNAVX6vAf+GOhvqMLd7x+bCg0OPzOK9a/wUixRB1
gZKjJEl/IN9Wh/OgrmWgFyDKNWnLXh1iwGa8fppMnHW3TQs/CkIgjgOQSINm/ZgTDnp21E60wADV
N+bTX9mAHrYAzi/ZO8QXHbhIFwjADKB8sS5Wg9AtP+TZDLPob8QmiD1WGKyuTaxKg92L0eTGKG0d
ajXRUW+ZGsLF0QnxAgM3cUPwXy+Q9Ne8LzxLyc7aWG45xlGC3Li+bhVRtq1q6Lji4/StAjPmQKlc
Scii8++Vf0l9R8hQZZrPv9mSsLHjyrwZv9gkT3Tg+rMoaDultqU1OclrTIwr4b21yeZpDZa9MUGR
iRf9PFqcUqxPZuCuTIn10NaXbxcn+mKjg9VkQ2LCYP5ZALeY6eosLEaSOAGXE0dx8OS9fhoBeXPq
FjNfE+/558DBi7Hj2FjIo2duKcAHrpFFktezcv2pn9eQKdzP4DB2E6ggtkgJGDaaw2j7cNRZePGh
J9im8TazgNOz9KzcNVENFrqdi8f/awLZNIMk/Q4xQngLE75qbwwy0AJaW7tX6VIQyQ1Ow5+g51DB
jY7ytXwwHH5SjwMCwDUp1pyhDD1xod8loz3QtnCBwwUM5xfm/t6wlN5476q/g61HnBjuKeyJsslN
U1n3eVkIzpyi7uJRPbNlEgVUk8vqGwuY2OTy0YKFQ9VdCCqPtwFgktbfu962dK+J2CBqzK6vAJBZ
IyHDZVhBlNbhgrG0fESdVOrA7F1Djn5bTkym1tvOBpWLmLPHAJ2ztFhz3p5Ch0KvG4+GxL8KtzIY
KEnwFbhPTlZuSk8/ofnbPIEbXkptUIzvDB4zjaysuwiYCmIQ3FOsigWNQxHybthobAJQKUG/XByf
fkqM6H9pq9gYc8ry+2WkmHp01fLKJEJsYoIBZjMMutURPoPD9+H+WL9wtJmNdp4FHP/LlkWJF+m/
N+Yu7fYO966OH73r7uYO1+u10R6rvEqqLA9A5qS0y/vkEoChXFmC2HhAtQmnBIYRfhMgXQwQyX6f
UvnXwzMGZKyInOjOzyyWqDPBcFMtVx+kKKFc7qfM2cEwcaCs/VsuTLYNgdlBeC9cxlvXjo+mb6aA
zePgi62H2t/4+i6uXTFAGo1m4voKtna9WntQ6sBXA0IbJbbQykrWPt3RQLCsnizh56mEGODxBwIH
QO8rUqf+rBGRdrHUOIvhYumjJt4RTIGpgPr6kAXf04gyRz5J1UGQovJXbdMNW2UiEidA6nU8ZLYF
VXjkxpCJQk8ORGfExHP/v0LAOgLBouYZx7avimtSPHz5dCm+BaV7b4QoDYdSKuORS33HFIm12Q+A
jtgP76Fv0uN1YEHdsRBjZNPAfDdGNaS3vFVy0qSmFX+i/DAW6bSxgpWKRJX9MhYWAcF1LmRGIcAG
zd0ThUDtaBTXwzNTk2qlE4Gpch7/8r94ph7lQVVsmneaUtybyzra9OXSURpccriY8FicVL4GaEW/
uUnYaW5ABEeXzQGNgwbTwtmycL6TkxOcGDyUDMLzMHj2Ahb7HYGPuW31StlRQb+htxTN0o1iVSuy
TdGo1tuKRfO10RWwlv/jE5jY34nwXcnis+88UqLTLnV8b13t1zd+cWKzyBvgfbc5yog0XXpGAr9W
bCDeOo+SDebfhvLFb/10Fg0/rcfr7/hEcowzS0a63gi5RrHEmk7+k9Q2zamnpVpfZ/0Qyusk/IR+
XGjNGcOLTvkmFFlHaNDYFstF01UMYhCd3UC8eEnDsuFz1LIr8su2QCYo/Nhjwrlk5wy1LgM4m8KF
oJrdJ7PMT1guyIHJDSHsg9sO4PhXa9l+l1+lXHsXBSBxSvhBurzWSyXQuv4JoIhwmlwBCFZaUnPr
T2OAWwAd0TulZDnqd2zoSzcvL+zcdIt8fJfyRhMdGbbmEGplIkOgt1WQXjRHQanPgp6PLQSZN8OF
2xYn2biEOtCEydwz5NZZPMC3PCs2ie7i20mg6wPl2rCJuh/f1y4SUHs/BfTw4wjUnUA2qBTvoj2S
6oXMsBD/OK4Eh1gWZBElhFo1IQz169vRAROopergmJ4LkBllShDVBf1NSSfQQhaaIE+FoiPXwoJF
TP8bK18OiZwYFdTx1XlMKoSeolXYGqehcTIcY2rLeEqY2EllN8pfUZQCLQncTKhkqEE/cPSes+l5
5sSGiZxwHO5rfxQmwFD8pcHoCLD7kHB8/fY5FywGBI/DhN+GpzLJX3fZFHV1K4SYjXYwhAusXepO
3JYhgdVN8BLxsRmAf+kt4TQx1BCn2mVJ3CEvK6oKkJb7aSt5bXCH2FKPy3EXDNI9bOSECSSIdhl9
8UloODnQp8TvQFf+SpXaCP9ZVHS1Hpc9LnowaLzPhjEkkyQUk2NSBPjeNmRgnMz12/ES2d9VrN0u
ElxIOtNVjFaZusrogpP4J64eTOwbDCmf+nLie2Z3WtN/0pRwStcc7+7Jv0M9gMtbtIX6VDjEu/RV
uzLXmSBh+hx7hV+fNzkJpD3/vhN3WvI/qsL8HxwA0Uix54ujqOVm5t76DWenBFt0LZVWIB2k2EZh
exhTP+S+Jr2erVnxBp6ribKuF5QUFK1uIE6Z3HE8ceWavLwHCiFrgdOLv14Ucy8XbJqJ0/sdt4XG
ANC5pi+AwuKbex1WYeuR6qrlp/9SKjbqrzDgdW3JvSuS6gAy/s9AUxuSR8p4k/S5Cvmbk9t0N2UN
DusqNdLtQn8nLoMbGrfsqz0y3Eqx5xTyFErunddbKfJheeXouI4JMeaZTDvcxsaqoelYmxtrTP9b
3apIBlG5q8JsJIbM7QVPgui74BADBbT8UFpGY87djNgNCI65OLNbPZo/WQgRKBl4ehFjLRLfDcBD
XGs3MfV569mraU5eFQFx4j5nTXCLLGnpz3An4L5du07soJnJwoZqw4fjA/KRuXPkv9v0Xn9sfXDr
evW1NIbj1NgHYv2kceaEHDKMwTIp0q2TQVw9ULsWLVO6JPld6x9DiAzBiv0J0uYhIuYdewAjRLCk
wNyO7ifhG+Q/P1Xnf564LPM0GiCyC7tFYjyuTTeqhLQ6zKbYYYyj2aWsb4sHqhENSMUX+JV5Xkqt
tzUOuVb9+M4+U52a1LavSg8Leu3vzj6F+hU6E8lOdmLHLnld3efLn3uV5+SErXBsO1Fa8cNAUkY8
K38EAGLXFwjvRjWJD9dgVFoHsdxMfUamginZ2lhYMnp5JlcPaiQi9tNYM0HlcZjw260QXm+iMVDB
iEHfbGpyPsIkx+vdbMYW5QgTzIfr7ExMT3m+msX3XN+8ZI8Dj+KuwGBhUX5a8gTMzW3t+TD3FcWU
A1LBoTHDPvOhUHkTKhyVjtrIs8iGSoO7AZvKgBpc6CHuddL9hyyt7rCr5pTAn+u83+x4D+SPkKcw
3VyQUtMRTlzympC+MZTO7YFAWyxmDu8AZFneQa3nwgSP5jnwC8sjJyuIEdGMQwmto/GvhU+Ib7gI
ohyGPoGudBn/DesZkIGV/GUgWPxpz+xqAFDMvGM3Rj/ZNsBBb66ZK4fEESkV97bLqgE1PHN8998o
7HSRigyCQ03il4oWyd6ufkWvCxJL/5N9nl+dTloAQOJTPBLTs+VvYB+nPV3Q6op80m8PKrzHHDQc
BM+RWurk4f7O45C0E2awmUluLt1LxS3jMwdIoLlWGf12EDh9np42MMHi500sppBbxmy4d2/3Zbxa
vi0VZ5mPjf376PP1AduhYSe8z4BzFHaFQkBgq10QkQOdNuv/mb7ttVerGIwlW3bwfqZMySdG9qPj
ICjtI6yPtBnZCwUv986+dbEY/gcI+gpRoV5BQR77q8mJ6Y+UdRg9cK7AJ38HsrkDFqr2kPGcIbtm
KXVf27Hlpa+hBpiw7jXffP3qI+QLXU1iDHbp0yeoTLQd11iH240XZN4gf9OT2DXSYaCiiQFhDDQq
H4jqD3TeDAo1U0h22LiH6pviRoGjjvcGxaGeZbLiipIJPC4JUQX7Ib0OQre5x4HdvklEazYeIY3v
g2W8fn7j3Pu9FMQwgbIs58D7vZVKJ2XtGISITxltXRSHJgvNKQ3pAeUNnGp8Q8G/yFPqIT1wG4Kh
O5rXllYqhDlYDoqIpCIw9V4xL/v2U1GsWOaQkrPo8QCWJMdhUwGbTmUtcJ5cXiGYFTcFNCGJd/sv
WZ59vfsfzMnDYGyei3sRwUDcfmAXMkPQK23BKOSu6kee7Nm+vSPPiVbrRXSQNnOhdB0CqqQOVTFr
uhbEu4lbNlByOIUNiZphwuMBBMUTxvvsPaNNkhV/x9QxGI4r0/QgoPMCh/nSleYJYTWatJuHppbd
ZLzt3hffx9iQxgInqLTVfQ1g5MZ5VNgvD3wAcp9IIMMHOoYt5njrqBhJt1X6DsDO5qmu6ucPPvmD
Bn+PyQIi7lZJXeykRj/OTATFGdmYmmdtju10cd8bartPLiThYdPCj0QIqlQ+EGkKA4yJ3ZFZqudn
G0hbrwIncmDft/SBefQzPW6y9Ls+A9D+O5QUM54MV2ST5dJPa8VbBlm3B5EWo3GLyiWnub6oRDlt
UmMDmX4KhuFpB93p2ue1LpwGB3xigesycfyK9oGVWkPyhiR+6b3ZEua3qg/RxRODqUcoo53hh6CB
XgXNr78l+XF++uRoyfE1VveiRb1kZVmBd6R4IhYEldXSH30V58yM0BS0aaa0NxNC+YiSbEX/50+1
RsypA3EFM2/a251nCO0BxnproVP6KnBGRSpQaJJBzfo3DbBjvRV+vdIV9eRm0iFcu9p0+hynOqej
u7lsFolblpF1xEkrzslc80QN/Rt2qh1GfnvQZ9v7nWjgOlR3W/lXXIcPf/r6nBrT9dGFe1b8hE6K
dy3JCSbaKVAL3ulX2qxS2EIAq+8fLoD5HHEs4RuOCnE5PGcfQEsMpH/KojeWUqT1t1QUeD5CRZy+
N0DeYLuZEo+LLgGfnrADVvuUdHadqesW5IWR8pAb+3Z8a9puzrGaLlkDDFSq9gKKJvJ5NfX5dWkn
CumMScnfuwz5R4VNAwuWS11FsZsMCip66d6bwU4b4xhCjKN0KI2kFhYEcb2kQ1T9Gt72ImgeWtnF
jp7R2rQQz7SyAPBCq2oDgUOebsOgdG8bnOm+6QvFlSw5u0PpCFbQ08eleNwakzUriDrMEA+vev5b
AV16HAUS0Mtg2oXPVJcCeelHXYSqBCPSRnj0llirjRpkyeVo+ntHtitabcWbWG2wKCFGzzbHG4ec
h7pf2eL5BAClLc6t7vkwWVjxBD+okHHq/nF3E1nVYgaRLPMN2d9BV1QpkVIFI9ZQSSh48duyV3Z/
8/GmEOygl8Q21UaHyo2Byd4RkDH2Enpjxkfh//6C+/3SEtANNEJtQbBIZvrRm4J0ZnM1Ez6iWoyz
pRPMXwMLdpz5MKbUdR9si4PST09iZpi15VCGL6kejTuCmeEMqYjGk92ve31aLubZnDOdEwtakliB
Oe0Jz0J/sDWRoGwL3lq9gOKU1sD4n1X/zgiFlAoGPnUH3xqojQeaATGkbsweP0exB9wGhu5l0CtU
phq98KqNCO2oUdCfnd9eUsrcmLjUxJA7SwTjBupLywX9md0sBqS3Dgg0Wk+W9QqugRn6KNOS32nU
dgo0XPBZeY+SRgqJK01oDv1o8Rg=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EJqZdQq8nVnK5ypj58RK31/jiaVj44lXjMypHi70GZDkUwvdatIx32BwVlbE9cKUjJ40VFcWQyOE
NAQtkW9DHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
a2BNmJ0P/KDDphubQfjJh65LQONNGS+nPDI+FEBqVqVh3llYcPm9TEnuAyovIirerrM92px3IQSh
cFSpAPp4u/cd2TJsfsLOrPD9ZnxO7qy+e2JY5FpUi/XAqggR3eAOzMXj3D5VHeXdh19yOQmdTRxs
7IQJAFlwq6g8IYGzFxI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HJfCQzlhZ8q7ejhQ5EFzp0sqg3HtFae77IOdJeWcto54U3E78SpeEDF6pEhwACgUqjZfs9yzpiY1
EUUgScwgIN7Wbwe/7apXbfFWsLRTz8x5L+Yl5SnoyXFwvLOYWAMsORan8OWr23dd+9kfG7yc62pW
BjXmSWx7Wi0O9XlFgED4nL6YYV/M8k6xPyx0GNKFeG1doQNF6Utkl/sAjy9+NglHdDzTmALPsQRU
/DJUOlU3QqBR6nCUQMBlE1kkx7TEFVvhuOJDy0wsNIcbrlyf+PZm0ruu6wGyKsynW4HQx0weUNsK
ODzfMWLQQZMUTvWbLVYZberOAXQxSc+pXIpW9Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
22ja5ZdxCeErOR7hMWKMcmpZ+VKfeNCMU6DxuiFXT/HUT+7i9bqIzlJcz/hQC0EjyB23hZXTNzfm
c92ta8uxwh6+uP8+SBSMnH8ZueZAmLNf/5UV+aaOZAkmdYvLw6D4n5sDpBVVjloTF6tV/N+f8w/S
eAJYzTeQTy5nodOpg38=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bw67Aw1Vod4+yEV0TbTFZJaFDqK8HUTiXKh6QYc64hlfM5XHhrfCdy6yOxSysow3bXzUJqJGp6aw
tAeU/hA19lI2p12pRkyc7GhOjslb1ulgnqKjCqtr9jZL69HHOpRw/lg4xsvirSgCPOrQgZ5ou1ig
NA4Hat4XuLKzqjPgqzY3V1qTaS5VxOOfbavUc9WEeh/84FKAfghw7h1KPrezdYYv7QxJHnIo3IPm
sWfq56b9MNVhEvGehHmES9J4qHGzwAtzm6NNmj9TFZrDAEPLJ3yKCvXPBT441pK5ZYogHF4H18rU
kbxd7ZO/JjAzrLks2cKgQuhcXRvNBt+Vg6W2pQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74576)
`protect data_block
BDJkwKT7+i0ggT/c5enO4549jBinzkMmeYCLn8JCaIUC+BFLiKutNf75P/gZqJHJjylbcwi29Ppf
BoRPwwR6yCFQHaK7RK/tyJSqhrHrQPI0NPsTbFt718YfWa+7TeqaOGSUpzDj8X4fUIaZ0AZ3B/IV
7/TR9OZQoniDDxlFbD6m8VatDqxjUfIWhGeXwM5tCd7dS5U0gh/3yEPB1dtwryFS1mwpql1qkH1e
9LdwcEmdvg+BmV0DlJbPCILrqad9xhwl0RHqTAjf8Qrd/aJhjcCTz5H0kqrMesUAl6OOwWlSLqjI
nhAmzslqVQvJ5AJmHWE90wM/f2d17Mj0RAq7XhphqB3qM8xczw7JWNeeKGN2rN7KU1YqsPsbZ5sl
koEwaB0LX1kBvaxzCKWALvF1GMBq/mGZhmk0fmXBSU6Y//jBVYnwjB972EVPDOF+M04ERX1DIy41
WB9te1mX3OKtL/CRKvr46PJ1Egh+OnEHfg1U5ztlfhIL72c4cLrloBo++b6tOLTQy1uDPlkRVExP
n4jcamVdET2O9E1oPB3WHwLowos81mn/faGzKwSLfM1mQ8eKeMaZHInuavtF7TXhUki9R3bdK1Je
WycfLP0oj+a5HmmTi8NL1mZxnhX/FWtNr3MJyskLhtUA3g+z+toDjuS2fLQ2oyYlwtM2h0dPdRPn
imYSmVFxuZT5ZbFl6ZNg7cBPzbm57eOO6xGLkc20xn1Bus8uRoPQAhs0ib+krovRqaFlqM1mI7Ey
ymqjBI1Cmxe8CSww5RS9Nju/j03eFrGRC3tF5FmWzzUQsUTr9L9LMXwiIvR1VE+hD9/XR7YepGtN
QisrXFrMBTR3y0xnOJBUWqGWLZNTwMRcwcdE7eUnlF9m05Ho153OPr7IqeyeRC5yic5AXLpxNABn
FyfXQl68QyviGhOL7pDocNiXZeO9tD6fabEs2NdEO8P783KXZmgnpmtq5SSn1MfQW32C9yqrru23
CnqAVuoltD3sPjZaTdJxJN/Ay4St/uU07YcxmBOL3nxmiASx0waEjt/ms8Bz5/mWfRYlW+OClrEZ
+JyMy7sec6i531n6dPa4mUd9F/4Sl8lyo+UAfyFOD1fXMuw90RH1NO790kLrDa88IQh9r6uw4hHv
s3EWdMqQUPqFyqIhsE4Iv2HfAHjrcmXDu5f0hZ+WhAmN825ah2HfswcpIFZOsv0gflehS0jh7Vp/
r6JiKY4CPlB/db6KBbOiRbZQ9pDjG7K5Uc9q2W43xA00kzQ+QGIliU6qmwpCYLpfTWHEVJtlDjXI
pP9/TqGm3aXDmjnjzCqO3rcDa+y/koppwAtDQDJLo9Nwdv4WBjmJ3C0kDbrqJUgNgmYKfKOP3PTZ
CMm3s+bxeyyum7XVw7Zw1McZ0UrzKWoJDEGIwniKrvn+P122xAsxhQ64Bpdw8DISCXm06wq53KsI
MAMScBE+LBNzOLHWXaEhcgGC9LeRnmfxEg8RMUoJ/uZIx+AOrLxe6J1WzPTOF3KaXuPCQ4brhWuQ
kXb+bZk7Sy/+05LJwgxPXJd+nAAEkZrYLUvR6TCODUitqL835EIWzC/2fed6oTe3M8yP4WSU3POr
YpZ6sAlbKBEFJEFhxCH2nm/lzQNI14pw3iwzqbtAbSRj/QsrLYFs5u1vHk7Yh1m+NlyvFz+23Vd7
84sCHgKpQ8chs7N01inDLp+0OZ7hlWclTBf6sYTcLR1j76Fi5aaCTof1NUGqYt7tT0jKbHzdlP+5
ZBteEEDMur4YcXSK3PXyJr7ljZ7iifWIRTNy0r4KSsfCkC1kOofkffLYpHiF5qJTkqECwGtRcqv/
eiWMwwIdp6FXkMPDiy5CwHEWCyjZbNmM4qh5MWnWIt4QY3uw8rJAqkPXV3JZmKSMdhpSOnbgm+Vb
RYzooF4cSoCB7TJNz0cbffBP1CycaAt/TQ7cj35zgGFPvc7cqhZ6Rc+rTJro+UI9tH4TYJp3ix+1
Iz1XF4auMIe1+vh4Poo3Iuy72S15Cc3aA2NJHgV0LybXbNAq8TqbJ7FfNCVpCdnfe8PZlFvpLrZC
2M74hFtlop82Lb+MQfeMFzO+e6rS59J5OhduNXcFH8xqY3h2qad83o93MUsn+vmj9rKxSans9nwx
R7JRuaAbxDJOQyV3C9tu86ITxnrvJhxRFntI58oF2pR55AHA5XKYOlLyHW+mPOWAzFDCJui1b2kw
xK8d305fxRm3ZQBYz8AMebSC3K/EGYo59MmxnBTCZDa/NkvPhcC/lgeYmRoRQN1ohLjGtxEdtToh
sFXi6Lc1l4QF2OEmvLa8VCHkXnl2RD3gJoFapKfWTq8jtxbGIGKkrDE2LbiF0AlZtaAyBWxiQKPt
Yk91MKZCDWn28pIjkiJImRn1iWL/p1GYRTPy7m8Y0FF9LO0yHOe8qFekPpVZvViytES+jv2jTO6h
ZO2c0lCIc1QJm9u4tyxJNGPQjwDZd6EpgnEMMc4bmjGaZKlTNSQlM7/iLpp4bURGlW4YNUsxBA6g
Ce+ddLLVcERCgKNA+L3bYY53SMvL9XZzmdMJkWfoTKeJPqjhd821G6ijhF7TKj17Ln/0z2Dge5j6
opcEUlZ3XOpYKaELVR5haYD/c+qDZTlv8KcOf7AOwMKTqjaXP2hoP+zu20MKE+zgIckhZykvtbfI
QskhD/T+SCCJA/whaEr8xsYb/09kQ9sz345lvwHyFN2r6V2JXC7NPVnX9JFY4K0/1SmGfdnzaYDI
mm5+PsVxuS+D3e/uwr5t/lalzqTlFO8/dr2bgBq/I3jKJAAc0P8TOgdUPoIzc02TUrMeqXde+4l3
9Lh8navQepOYWnNh87rJXt4hnoqDmmb9UEsAe82XnpzBvwiUIPNB2NlMqprz6P8F+zGslvtnfe/u
La8UpsYuxWXqKtmnB8wmKm3+4wS2AMzFwEs8utnfDBF9i0v8lvDB8Xj/l+v2ogAlyVxm/9yI6KCz
KS6JKk2H8WbZaU56u8et6G8rJCaNEN2CVtmVf9J5/XDF4iikT/lbEq3+36e2GNQSi4FfP44MVUeJ
XisDkiXOoiPZahsU3xS/jOf/K4kSIYKr1yJxw3Hs8GcdvnVuvyIGLLPh3eUTmDOa5qUvzeKw8gik
4e5NpaqOz0uCP+ti11WrabFInBU5HAeiSRQEVnJKBGe9BiTCZVCN7S8uBuKGBah32I4KHWvW6+vt
ZahsYtjYqlB7a8st2XZ8VNGQjdTuOB8UdU6+nG1g8+dgMHwD9SCza8L0358iOR+AJN8aLPKJX4Bz
2entAXscX9KBYP1+AwhYRAhlOiEZYZfX0RaUYvwVnEFCUYGFZUaBXmNjNAAhg/mYCZiqkYwk20ah
cxfcHw4QKNdma/naxb406ZY3s/iIu6QOR8zlDzQIZTS/Zv301165UgJwjt2h6bV0uHE1YZQJ/+9u
xxUSNOLqcBChM3X4MOagSvEtbrsx4Lqor9ivh3absBFXgZtOB6yVLHU8l+Iy+t561GVk6qUHVo2t
R6DW8atkR01kd/prQTP+64eBtxiAmaInIcxpV0I0qmG1YXVAwmjKC7jHyusjhFLwywYlvNHObziY
Fwns7rZ6F8mQylAgeqNC7xAOZaY2mDvk0c0RExOCVh7VY54DFg+agvvD7TeoHUSBylu2oqK/iLQE
ay1YaeuZ3tNlRonLkMAskml7RTPikGdWefGUztPhsI+jZ5cNklxwhMJTpxXTimnGUr1RO6QNSgol
a9LfJYDyq17MgFtopiMGGY8od78VQoM7MC7Lzg0tl4hFurWP+3Mjjoy3Gr+rXqWnb+6CJM+V5zmQ
ZzrFjuvZIBVQ7IqTbLdgk4rs0+YjR1AK1HuF4nhjc5ZBWCB2X9dWajXxUZhlB66zgwTz/uUbsPFe
FxhNJPDMNdvBkL6PhKRmxCjAuTgBqkY1ONhrmYz35nrOv1S/D4NU+AU1wmIC+NP4r87GTgvCZFp2
U471LZ7Pd3Xve83LoDDVtizPxmbS6AA0rVFwmoozDwZlg6RA717qeqco3YQ8Y2dRcP0FpIC+5Ra9
6xm0cnB8qEfQt78L6eA8bmS7afFV0JswwQLY6rdyEwzgAMuKVD9+5k96Vb3ShR6fudoZk28eMknd
mcTuWoyNvbCvuGww7EHoTXrIFa8wHuVExDlImhXAXZciv+/Ty8A0w5lwwXuiDS/rvX+6sb1HkQcr
QzxDJKBBE5WCNXrX5YUnxpiPol9Z9Xzr2lTXCBQf8yU6vcxA1PRQgG2OdnbXftAXO2OUP801x/Ir
Pp5UOuIqnu/Cdwh8i+OtYG0PFAuWvaDgOF0DX/EDTkkcifXsGPyHI4MlsOOxitkdPzzYRj80Pb0J
BiI47ZC8F33DMVbGZ81ghqq3wsvx9gtp9pcecDYFglPGTEJjV1xIaoWastSpXNMedwBrOnRxdJIi
HOrIRk/M+0bqOpfNWMlXqhRlrFfiwZFIG3vNgBaspJ0jDLLeN9alCqyPJKWhKsupXV3/OnoVFfYJ
SMDyjn864nvaGiM8HIh29P1eOlIs/01W2Gkoh1833d0j4UllwKnA0+e8WhKRGf8gwWhPju+cZ13T
H1LW/NFLl3esSBAV5nquT/G7YZnCSfsH/icUsPK3pH4rZP122iiOb7tW5NjolYMELIMMJYEJ+x5n
QHJZm/YgfJP5DuFc71Ve4EoUdssU9sYJTLYxPc7yjmJquM/DBVR/GgaMfe8OD7B+u7QGYBBXmHcL
g1UEwGx795wc3sdN/jn5C41+0bWjKxbAI2vQQDeJFFY2sWDPX2AW5TpLS1VK3zi6GkrRwujVKDMq
yKDyAEZ9SQ2KXbpqc3jmohsQ1YuEPTh5XNYhOKtGn5BVAgfnCwdLecU2M4Er3BERP2AvQzWMGkCk
xcvv1FgPHfYgZwKh9/MIwc/vgD0CLrcTr0V5bOWHl+3RFy26/gsCfcugtTOlW1cZRspbiPldDC2f
DIbhcTcYNyZa6m8WzvjBTVJV/AHSgL1ESCZJpvYbxQTP1NOWoLvu4AabHkIqcwFONA1q2i4gVs9U
/w3Oz5KlllEbKUQYNcmaln0T+JNTZRa8FK8LL5k3M1T1ngQecEiGCUghRY1iNeG+502FKYPqB/dB
/PKDeCvsbQKlO51UjZlz8cgSMhLxzv3VK1SfbzExxYcriP37SqzBIMqPdpLgkFmxFWAWQQO164XT
wzWsY4zfmqAzj4MZjTdbh64PySoIhnXwfhsoJSRLGNty+sGJ4bbJMefaNE1PC0hG3w94pfztrRXi
Y7h8EkFFqaClJ5VsLsRmPZveo/F5QJjBd78/JlxSsAOr0mKQLJgJ3Nta7tyvXdOrtYF0s1Uf5hPm
xFX7orRGht9/LzNAjiBSH0yQVSPw1Cke3iCvYi7kiDolg5ty4Y+Yj6v0PYSbdwxcCDXzk43gNOym
8mgs0UdeUFa3KDeNY+P4+8xTctD/4EQ9oXiiyaNM7Lx23bMS7ACxX+4x4PRJoQpto4T6OS0jHKDC
s4n5bFoLD79Fa3DpCFE+skLXCSwThUiwIKPAN65aJET1cl95liga8/2rdgokVtLtYiM2+n3kAfQe
g0N9E6hzTiW5zygOtbhHGcoIRn+2RMPE34v9BxdotbuXu+i+13C5FSzzXDoAp8RsWDX1OsFMLycQ
Kz00OSfH5rLY0V4IKGsjnIv2E5/vb3chew/oRdh7a2Q+dy+RpJjiOV45wKuLmjn7Tx4hvKOPzmgL
vlesYU4guafpx2dlt2Pndo9DwzMDpDRiI4qYq//hUfSGhEVP0Y2jaKWrwxz+nZL8Q5k29bqRcBp+
RHX/wHhGdkuUAen1+ZjCTqGZiFbEt2uXNcgsjZQFe5TTnN8XvU3V5OvafjG0FE3r7Xli75GusQfR
XuVkkbYxNG6ZTIxU6Ld8woKe1nshgKHZfFBduxTB1PnBRgbkbtmeZUus1sCokZgLAHgpA1AnRedg
vVYmtNliojw9//l/pXEVQ5xM/aVKlVQP0rKAVlvT85iCvXiU8qZ1MDDhJSek4b79OVN60scXubei
CvfaAUPZty750FRaooIUfXHX8/hM5Ue4FRj3cCuKqp6W0xwh2g752St1MgVgzA4ysfjrXT4UXBOt
4aoY6ZEZxA5PTCyRBocyiBd6jCzSz+NKsAXPH8iglv2BhMR0XWD0HaLUfk+fuGDgP9gNyvSPqt+n
W/cV/SfgPefm8yXGAz+TKkhX3mxb4OU4tlpqwELxIQ5wbF2CEsl31u4r9dqqNYR0HcljisaEi0ce
FWGa42D23LrofIjuYUtCSAXhI3RBdKxuUAc1aV25aknIIocqQ9t8UonJUAkzZkJP37RT1IZBdMEL
qwDFrQq84eu40YKExZz0LLSlV8ScxmAjuBfGIuNibnH1m1AnKoiEU7HfJqJaH8y8CacLQTS1Kskm
FGdgcEKHud7s0z3m/RzwALDn7XvdACTy3GLksYOEdlNi9EadtDcYitHLlFe6oDxXkXTYdKc5ibOG
WeBpnXr4VowL7L6HXIdYvHIkM1pAsEuF4MnyxS+nadUolivx19FEjI2HWS9IhiRjZBNrZ0ZrQsP/
3ZNRyPZXbNU8eB4bj1wSnWwVMDIttrPg9tVSb5CP+nt0VJtBTQ/DCxyQ0iI0OOPxTg9ZASe7zcIH
ohbLACVaEdNn0dCscDmGrBoyYRdZ/i3zW+vMJwh8AhJu5U/DxmVQu1itwqHzAjirj5nSYBmKJRVW
Xffna/vFoLm8/s0qJFRShUD7d2iKo0u2SjSRD1TpqPlI5YPvI6Jp4kaMt+URrlJR9/YH2JNsRq6x
LPMtCwMe03b8FefsgukYYamxONH9ewjJYSIk/fDOW1yjTChJBC4IMvBznHYe2borCB/YM/aBJxtA
5fOF+9HL/iAwsReAa4w3Tyu2XdXknTo6Qqzz3RsPZPXu4w4PTftx7nF/AS93rW9DSw3Un18TtDxI
8bGPL+kvQ0xw2FPWs78CxUWAeB+MpLMdIMtXKQMi+MwqKBvo1/eGbEatDnyDwiZ1lQLQgFFdRKn7
aWPeo9EasIFB3kwkHFS+YkKeRt9JeNRXlUOyFJACn+EZikzER5dVxPcipf2C+pcKKSvmK7Zg/XJ/
UbQtLHHCU2xSSfqdZ4km2ywAi51Kd8sHMpbJfSGnk2ujS3w3Tker8Lnhwh+FhOSvaqLU6X4dd0Lq
D1Vn4HCueEv1VjGm1cJ7pvVsYxbqretjbhZzlnAbXSld52GZe4caXdhrrlFTUFPkzLxB6VGv9KSr
jvh/OKSIpIx+oqoCIWfYRYtu2B9xs77FZ/S3kuGZQ8Yo/R68HOjrOqvL97dQKgKmd4Yo7FEaMeJw
dA0ErPciY8SfQIZIAGg85AAXaO1HggMa4zhHEmsqhXFULxEOnp8USHtHogBSTljUDVFJ8b6I+EiX
e8drnYXzDUGTAciNiz8Qck1T/qL+2OC77Ici6obBtWTFA7C8QYldDYoR1nx0Zpv9DCbyhlAmY15I
CAC/62zJ7nwJejWU9OF6vEteucOLGhHhmU9IJs039fXOVVyWcvagqMj0mWJd672Eh54nqTY7WuWE
MnR3L6GnCWCv5kb2kkSMW6YHEy67E0ZWKpPXeF8Vx/8X4i3oRv14nVLavLDXgiv58Tt9tVTzRmKo
CXGGppEiF6tB+YVVA+ZoRk2R2PJz0U4PeOrLFGgj3/dYLXELuBVFXgMkTKFhmC4H3fJbOo7n+vtM
9UzBkK+hzaQFRRcbiNiY76iUh8mPV2aZKDEeInn1opKfIt06klvVdnhEMOwhzALcf/sJj7jlZ5CQ
mXnypCYMQDioMtPVL1JvDWncMJ75MqyCiC9/rHTQnnxAkiYSyY5IjCH/x14wP7tK1P9eurjOK6Cb
VDNmn79QELN8bRcW4TOMUW4P2KC1UG5+NJt7pfV9f5+B0uAvlo3X9eOmnOn18k0OuJMULfJctbqj
1NGeXfF6JwRpoG/2J0khOwm8cMyxJqyJaRgGp7z8SugFK1qD3dxIFXqWvtUo+Zgp9gbcSbeXf6r5
o8fftKhddyPfv4q4hIaxfX7Yfaw8IliPgkQCe6gHxAzndNUvs/semrNUycRXRkizoblItAZwsmsm
GuTEWllndkStevGuBC6aMES8vBBMUtKgar1RY5e1izCZmJ4V7NqMx85QSnOsjXMwaFZVDZhV+LHJ
ziwtomCX6CiBOAdNmj7TMPq21OKQaOlvWT1PD7q2PfoNfIEpNUGpJz0lVhtszz3pxXonaXom9Lxs
Aooo/uay3kuYB5g8JEsDuKpvtCgg+kGass5ki8KSsq0bcadLs/xumn3F09TiY7/FwS8rUxQYUwt4
rqvBnmI34Qj5dW/YpmqxBn/tMRTsTRusN36OaWkPoE5VqTMDMbqbsTTv/qwxKsEo4RCasSKX392k
85NfrI6Jn2WaLiJpsNKxdW/C2DiXTsQyK9AwTW8B6lP4TT3FHj1SrI2OLKsq3YaGR/u4AdF7Lfbc
8a/lOzlBQ8DlaCFKQSm3kDTbk6fnwIL1ob5Y/BIhTTEfP+NYq+D13WhQ45a4HJhyiRQEFLT/tkP/
J95rhMHJBftomA/jhKAGoZRMdxekLB1kMj0xAsyF4Ip/K0qZkwoBOVYZJU46dY/XWqYQEbJV0M5T
2FQkd+55ZIQi8njAtawe+e7N3fNi6LxGl/aXvQ3WghucOScLC9YZCS0HflAlOqC+lQsNVf/udm08
yY4emEBLgP1JXIFzVj56kqbCg3MqAavAu/XR4PUWNIXBSgJtGMFFRGWQ1QVwNHV6LsESpTVxAJd/
1uqShQtOKgekP8IzaF8ugYfglzxb803odm8NWadaVZLS6hyYEIC0pa1hWB6ornKPdCHv+q5555H3
+gfyKeoVWH9U/4mGy8xB3YRceNe9nQ5Z2TvJAf57Q3drdrMo9Omv1kXAmJLfb6aiNGqkRoQPeVEv
e3dI7yVKqfFcGr30h2hkAyR3yMT4WXuLpew9y6rCro9+XV+09w0l50K3cPdnloTelI6ukmqNA8Ia
glBrsRL/SN7zwZTxMH0CkC7uQHIJ7a7m68vhBmuApziHFNQIvdnipiDgW7r9atEdgeaHykNFND0o
5D5YDc/JGWQ6fpGf7WH5LbsoAlPmEKJvDHTysivvBZhNV/oR9sPYbyYtpVdfTlFOVuDbJlBx7uz9
NnI3SqQPgsUDHaXcqqykgxNWWrnK8IV5HcFiZAmKAvvoCsHI3OzDVwvhC27vo+xphnljCPUpQYXH
rSuFaSafoaqgTMz7HJIt48+TfUQy+4W36qLOOBMq3peC8HirMBKbqj/Ifs9NhzAr0C6iDslEW9EY
0lpK2I7n6YPuNIS69vjV8mCxfyAt4ZGglNwx81AvUXSxAVZy18nDOhhPMgFCJpLE/vs07kolm31K
jX6RrN+VpKOOCFZFtcJGqGiutY5Ltm3sx7aZ2gYoDpFBlvWBGlxsOGQlZnmLy4qwuK6s5bthtjn3
1TZmv05ujxvZGkUYu0oh//WlJU990FOV2VNfdIEcjfy0TnoxJxw3vjjtMRh0ZkIL7JBkbumdjdah
PHAMsqomhe4dd0Gw8UsnJ17C0RsV3JRVsn6mPvLZQaaHgEl17sR/g1uQAMbVKzZmKeVoT+RoxFAr
DrSoUY2SoaK9k7Zi4FQyHaZwSYf3Eo8yPuaNeNe20z8sEZ3svSfVzf+qa/upTKNZUUdXG973lqqI
k7JAKE8Nm5yn8nKwWHX9zjW9OZylqsHMP8/IYtElvaZRuc9Sg6Ahmj+Tcf3p4KYclk/tMrNfj6kT
+L0sHePK0qCb5J5pVpa7J01jTCTlyHHH6meOHAw3TYnG6bWntsu4qnG1lCJQPzoySjzb4Fsc4y4g
Y2Tqj0wUx8iqYXwfvpBprITmeeRU8pq/zZACXL0Fc7ulMQ9+b2kWDYfC5HgNMyOBHgzat8rZXVDh
jJKsqOB8gq77ljAuMsjVq+yjNmciTPG13INWCx6esI6kCjM7qQaUVcpVRVlvWPky4gkkUSsGiKoc
A1PtGaapKXNtAs6IGFgVaGujcU6S2+Po8DsFotExr45SHI0Gi1k7/7X+jlcoFeXEPzIcHNoALCVB
PeOkGASEPCfHh/S6ChFvRr5Pvo6FOk4RkRNcNe/1T8x2Hs7X/oXzNOJrJx2BIONdozsRpgtHrcVL
9YDOqgNkNZLNE1C6TSoGlaYGhL/imaPVTjIK5eHuvyj9hfbUBvqumj6ALElIO3EOxiokqxCfsAhi
jbDlYyEDzLMfgbJSwDu8oJfbPvsY0YTS8DGQifECMd64QsvyBjOu1SveZFxeUdqj7vt4x396XDLh
OZK89s8095h/fc72SnlI9hQUGsE+rEPtfgktR9xdO65PeyWsWmI/V3jB6lGtGYqsaZPYmiSlBlPK
oZ8x9T9dSD5zdPYtfTZUOe5GGdgMIktMBL8RWVXcS+qFYlP7geEZcURO1xMI/8Ar+YvGIkB1TCDM
eAqAmcw+LIHVAJrm2Iy9Gi6Wu3VVFt962HQcdfZyR+YYWRD9B2w0iISQpyEOmWZvXA2HnlAk2U7s
ZdPltsg6pEbao1jYAfgG4p09bQL8/0eyWAD1oH+3U7sQYSL/U4hv0vflgdUPJClLwqVRJrrDCNRt
QJCVs3YrLKRZnHHwUhvCUSETdTNuqo3u/afur6hg8JfKZHkoJB5vRQQYtBz8OselyIoL+O+3XB33
BVJeW7+XCrdr8nPzQye+rDl/Lfsim+5ElTLf4ylPO4ZqKHQpHHgsFEiIhtYRMv6p8ewRZMPgdOXC
yuP9lEHdkS1BtcAO1HwgaOA4MHiPNdcbQEJnjeQ+dIrDHf2I3tJ94Y6CIBfcy6Vbul7Lo6zulJNp
zvK/40xEn5IsAH67a0V54iLl2sBNZ6X0r4jXagARUZlNnt9abaw/dCkOgM26NMKOvlunF+2vWxCY
9Aq6+Iu1yIbufp/RfewjOiid2iPR3vRvwr5lupo5cs1TE8nj9P1gYIFUbyAwSME2zp+aJefmVJZG
cYuL/EGMGXnf92H1kzCWSXyGQ0CCtq62lgt+yE0OYWh1kLp3/M/2y3Ht65AZPnu8m0+6rKgjmnvz
PhS4LMLI/CVccKPvKgsGpPLIu/5ncto8DEkrcRPZNOlD6mIo8h5I6ItitpkBbb5e2lkIXSig0T5h
WXCT/TjuUfPIKR3wenVXvDthYGclcqLVbYm8aQz/GnJ2UwRGrtdb52BDpnnK8/dieTQlWqddOFSX
myuA6tM1y8Zsm5DfGslm9jDc8/3sREXi+YQZNB6ghF3bR/4kdWMX3eudifhY5eC9wUwi5Tptzk0C
husdwgCVRTmI1p0jdGL96OsOKl1Hk4NhVvE82y3O9+SGAt9BQvjLwc9e5z6f2BanWWxicZw4A7Od
q4/jvNW+loHcEb0C19iqbq7pYh4KahqCiwsJVt+Vpr/ro2KkJVbt5JAkWh8g7hYg5z7MiG3AHrnr
3QDvuRWGNhV1LpnRzG5TfLcAGLb3cxXFqDtbOrbgRVMYCC/qnITaojVvpNHvj06ZU2UXS9qUnsIB
L6M/eByKuy1+Xc/+ldQAIUviimL7zS9Kwy5HEcewcqGOx6lp+cz9qmGFjbxAhRkHbZIZ1MWxB6GI
RywNArtfml14Bck7e/p11ifqcMN3kChQOSAHMpYxpLyyzD5mlqLV4ZftaoOBSIyYmkqoDIJJbEYZ
s5r2ORb6Zt89LSDR4Mao3u7UJpdGucp8fPNvm75DqHASPQph/2lVnHJO/FCTNGoAHPmYsuLURnEu
e8FeloqUuDRbO6hhCC/2r7LTmQgjVRxT29a+sCJxw4TvOtebJUOZCx0txOYZlXanURmoMkEMmWAh
0H8WC10xSnzYOAz2ZthJrnxj9l6jirVZwhev+dSiNvk5TdI25xwsJzqQB532HHOXSDYTN4FvP+nn
pIGndFckkZjvt55I5PP9kZVdRFb+qnK2HuVwxfxazF4YCSbgFccOYlPU3R4GAzbpUQi1pzBZD1t5
lq2BIMB6YhZ3ocDxtMiqfxBQLDoT56nnUvjg1VrabY0m4f0HS5Ev9fglTgEWqTbIJUbDt0bacVFj
k4yA4unaZ0UWsj2Ml5wbCwPkftNQLtmvbM/nUUwznCQBq+n7It0cPzO6wbyCDg+OT0mJNSoeXRmS
VNTFtLEeu5sNoeApi1U89WuYXpKZY4oN/7OSd7FeLdgfHSE4gJXVfMac/EoMk0Mn7tRdRKdZYYnz
TTYgbGH+p4BBAgntezC1c3PhcFGX9t/ubZLWOri52t+48IvfGkUdTxLBo/jGCLznmGgIOlPwCSCz
RBvIHQ+4G1lk/YL/z7vZeem2TSsF/dAAcA6juhEPZhh0qC095N/sFazBoWJYLDZNMaVZQ3CkVHo/
licG2M7TGWaA/v3IaoTuhDjmmLZcwS96G9endECC2Z+TJbiqy8OCi8JkyEmWzdgrKk7TLOtExNVA
m70M8nbeFBWzs0Yd+WbZrSe6gnE0zZFLTaBDQSgw1q1W3PYYsygU9bl7smGjTAV+FKrTaM6ccOrq
nmUczTlJUD8V/tZogNHFU2jgGIPzxYRC+jv0H2kItE2PHDJkHTHmyvzxxshgev9hI8X+khvQkG5G
iMBYyuCMZt5wVs4maT8o/DuXo8Gii9AVSCiCFXPNitOzebFcc29XWUknh+8Z5vfMASecwXmDpyQX
PqRyxqdeuYUGP/I+Crz4IatsrHYoaKO5wOvzCoU6p5fEjzmGr2wASworEDS0hEkogyWF3bJ1U0b9
RGz/c4kBH5PCvR34/5X/fzQZh9ku9pNBnE1siKwoIJSJyYpz9FxMBEY/t7CbWkXr/8InEyxyP9iB
pU++3Cv73ZQ3euBhZMQ0jkS22WGpKDb/kn+SXUYoDS6oeg27ZDswcSarj8zRbHIKqtW9Nn81bUL/
xihiDWyxIStrcnjbK7xT8w9ZyrKAX01WYWCzRIinuJuNm1qJJPSYW14cyZ3uGX3M34HdqGRsCB/d
+fEMHpPjF3nmA1vUJj4yirFEe4SJkQXaGadRtN9pOgtOJ40tTK4tQtEA2ManxeyfHroHSDdxD6IU
7kVJeY7hLs3Sp+RrAB7EK8IcpmTto5U2gU0F84NMWPqlhdkB51W3ysVQhMEOSX7y1VipNQSaW+Uu
1BgiM9kDpczvd5aA0AS7D3zLEQBIk6LR+7DiEKsTJpfCFb6IP0tAxNvkWZY0Nz224Gxnbvb2EmRB
OryZ89OiHyiId3r7Ks2N7lfFGHYBmxuMGjX+f0khroxQXFxW3eGAZmW71OITfso+Drt1+NsEpaIV
V259q/3496tofwFyv94VL3vgPNIzrq+AHMpzGqnwRHy6C8JEO9/iI4IOO/RElDVjwEC6l5iQ1Wud
hY/3G/T+WYE1vyvtiU8hk7jrxntWreXUSEMmL8DghIxcY23q6Jjlz2yXruwogshIFy9VOb+j7pm+
zgnq7Cucm+E4XBxgr9uebugReq5uYKKxMOpeQQqgkCXfpX7y3m2+Si7xZ2WqcPgMDhMb/05g9Pk3
S5H4FWqQRW+nyRpPnXP/oOdD8hYOeJ6bwyvx3DenqtNDFejmDnGRqpa+Z1/hdk+QTrijN2AhiHqw
VG41ZZGvSVVUN9RLcipJTg259pdxjLdmS/uwBCD5yWr/xjeFwWiyziz5y2XLV+ozkxDHpRglJQjN
jOXwkA+CoOrQZrJee4eggVNhQ15sucMJViEPTMs4MGm3EhQju74QV8NbeMpSJrm785qK7EbgKxyY
jeYw1oZxrkMxrtCODe3Q+QXiQ2SQfLm51+xIvtmiCIx/iKLEgjuFoHyBysRuK4YaaqUd3BkIV0PO
hEq6kDP03j8ZmTz92fhEMNUW0SrSXxmAPJFo5o+hh2C4fVTrqJAKqrbgvkT3AKBy6oe+fAmj0jhu
bUVBuvOMgNyssgsxqoPd90eCFgHj+VHuY8Us1SLMzqHPgycQhUj3DUCg4h7bn0Kl8vocOKeWMHIy
Nr3z9MmzJ4iywlq2Qd2cvqnxmx9Hb8iHX+EcdRZnq7hljBXfaJt9EmkGgdTDljOjFwBM5RZP2l9n
F05oJQKVj+wntG+QA1Zre0uho/IKCIAuBOilgYLqVGmD5YYhm7becmjcV/VAC8eqx+KXoDZu9Ldl
wouXplyMeaVqkE3po/G1aATieMo8Gl5LNgdk8T3GQABF0T3HbkMii/zlsnrzCvdFwCAX7BbX0Ghk
CinBhzqEBh0IwucJDDNFL+FZ1OumbzMf7f9cBCqgiZturKOHG4nncJs0MWAoO7gQIc5oAC903IEb
U8Hg+Mxgf50gWKbRnGtSKns/uCmcm5xHQNiTE3Vj9CsxKTl4/sSsIAVoVbRR2da0m8oDas8HrBe1
UpeUoF5L4ksga7FlpubiOziXkAlsg13i61bvRuK1HAWXi9qQmf9fA2vEo+3bMZo9kqoEpIGj6e0b
8DbF15T5DBJReTISOdPKnil5pGkFxECrOQWkpTOOc6v/PyvMNv0RUY+SQVmPXUwOyq7CkaWgaIOk
GQh0Q9QHziQR3vmbsI3pRRpsTXHaqD1sm4on/6sHt1ScfXILzFAjQ6uERGDD9XvzZHBzn/GnTX2e
mFtNAfvVkWZ1oRfwBK8fW7nqcCgFP7NVBLNcc2lCEuJk6+fq070jtEK9KYs9bHWG5P7zxnLUV7mg
btR5OsEqQnD6Um+GA/8ihrZ/STD+f9RthBp9VCMYFATeK9CjoR/Zy1agoN5mwF9Szq56eI8sLn18
Pp/DegyirjY9Xugnptj1Chl6aLEidBQdSqdrAy2/su8/hJ1YHTg/QUiRMLnUZN+G4PwNMq6FlHfX
95J9+j48JbxI+67i7NEPDZTrDywwIUgkC4MriektM0+l9NMDCsemdFA9wBTSiwccbpa4ptZmEn+n
aB4d2uyVjPV2ziwpZ8Foap9R6dv3nPDaplNHdrje0Hpy80/SO6fehGeoGs6buKq8ralzUUBL5TtG
3KHIZamuTsOaOA8gBSknNIlnpVi44X+Fmsj+L9ozJyDDtFpTmRWzZpK58gDpNIbND9W7XtmAUvqz
7WkClPABLD2Rn/KqrIWTvsJXYMTL+V8fVxu/ZlftNoeTekzBS85ofKGOG7bHAki7uOYT9VPIC6KY
UnVNCS+VgL1nB5NsQVpBu9iDTK1+/L9P7pWahkY55CfdB1k2kdHW6ijeOb0fMfXI6jrihBnKafZr
/Oyk0wEmBUwCTzgQ6KIr1hXPOLD9uRxblrB4W4/nhsu7I5vBtjmkCM4xKWYM39a6bbF8nizAHtqF
1CmGZKsKYdUxbzOq5qGx+cVmYWC0f50IITM8718hCPyDuNjn2n6wCw6VdzZKy3R3sZnukyNGjnzD
8XPMirEafDLdR2HKAIbDEVlfX4uXyLjHYnjAkHZtZDwOZk/xQDZqevdtk1PF3YnT17QqSvvoD/83
v6Q3BCjhqXB57UFsE/Ewf9RKhbbbbJSdM2nmEL/5N8Kb9mUWmI2GUbd0n+lpB5dItdo93+eMa1us
2/2YvKBZmQgBWZyASrEKEqwCTQ2HhVqR+cNstucxrvRQmwAJMuou+dRFClIVpL7iGbpZio4BhXFL
yu0+YqD8un5+Zu2mlDIlTPPrGXlxFtpYQQeeBakDe3ojlSjvU2vQ7ZQfSiK5l3pMFdgm/oPK+6AZ
842BzO3wZ9UMoOeNKPeXZ6AnXJ9EEoEjpjsDzIvFNMaz9J8qMji2aMPzzLDUrYOlbj/GfnRb5sON
UjTUMYd2fy8mxnK1Mn02JTxNivCtVNGBa6/lJcC7QX9DoD6BJvRKRCuHyFVKsHD//0ghOOiCU2NA
9dq+w10WVMIBFCjy4SjGe7dTDnrZrsARYX2gGzu61nQcmqDb++sYc211n6QM0POeOwow95aA2dWQ
A/k8BbuSGRRQcVZInSCbS49sXslr1/APRmDRHZYnwyQXJMSV1uh0rHEhldejPw+IMNxCgFrWqIzQ
fT8RPINuPfwIw8RLFpRlpUov6m/u/o5uJdoZgZLNEx+bQXTtMaZPRemUeDv1N6t/LqeAFuq93peD
2Iv7Ng1dCrMmajF+43j6seXcR1NFRHmXFABSKx6G9xz/nQqSbAjgmN5dRwBM81q2YIeSE3953qQm
YLpA+eCRdhYaZTNDZlsLpNmLbx+c5kiHRd76Q5taVycBbIthPkS2wlz7+un67dFIU8VJNH897Fl0
hWayOaCnV14f4AEaHs2YN4jgMmWj52hG6W9p9gHHR6HWF8Hh2Jowu21+VbtWIGkQv87Kbzzb187f
/ns7C/04KNGghe8HFO/7ly7NYPzZI5CFfxIonBqh1xf8NpkSX7zG4+ocA52/F9eT18vGwQTU1YHI
7RwQLWgLtyjK+UUuPvZRcEutwwL3fzbxSibSYtrzyYfrr5xxRaSJSg0PywEbgvQ16N7NK1utmXE4
WdJqPBNMf3TCa73axp2vg1KLyqhHJ1JSRKRp3qG25pkIPP7bDvqqqztdAQKCq2YPjiqLt0SePcdf
1shZiHwkusnVhiiWDQA+hKfx+3BS8LI+4dXYxeQWkaEQ04MfaklsFczDJXJjacuhzBXKDpeDMcXG
276h9mXnWH6XW6Ql5+JMUPaEkCjC7Q3fszlqxR7Uhm6ach120geqz0LZ10EZcTzKAyBUV0CH/wsj
LPtLmTF/J53GPVYkCT9L6+zCm+nw2Uy/Gwl05wU8bGD7F2IM86Ad/sIqsCj+IbConWnz10NqjSHg
DiUOKAOqOKMji7Gz1q+g791hIdsddk/2cM9RchTWR1DfkH+B7FRA44BvIhktWuCPZkvTmpvpbzO2
P5TzpSHOx2XxSqHpW2bwQ7BfY1naRFnZOcqlJr0+yYLmvZps/o368poV1pjZZ6fRjp+0/wuYptFy
Cph+rYdc3IY/BFpXB/i6iu4BviPNhU8PRs90RwXX+nBaDHXY+oRy672bdWay4/vtZOZ76gFtbNU+
/uPHDudbtlWpN9ynlB4SqwKlQxnf3v4K//ttlWaalOaZp8OSvTNw5vJ8/CZ2OaPo0e0ZGWSDw3Md
Sj7a4SmdfthYqINqN1CYGZk2pQDHhO6g0tcWPCw7ERPjB7nDHN3lbHENOndqWLSTea9hH3Fyql1k
TvvliJaiQCTSaqtyPqC9xarNnfYk0uXngPZ8yNZcCadrGlfWt8C0x8ZLBuWcrq2i42cFJLNonu7M
8/UhBgizhz9y5lZqduUQHejGZ3EuHWPEMssiKDUqxoKaEQmJJtYX9Y41h0i15k+TSnv/PnvlVVFs
kePihP360X7S4lR9OCi+4dsVp466ARLfhYQzLyjDm7Ma0CUOlCPPjHog/UqBqML5T4V5Q2UYvDyS
QF9N0FpciJhFSSN7H/vUJP+3XtMRQPAUEu0jVvUmpAixmVz64ppmP0dyPDR2abMGxjgDwuejHvQX
Bw36YXuu4+jLfbpOJpn9ZdsmPXKRDS6f9Dat2jvQ7+DGLvt2kvNYeGieqetDPLniwesTHdkTPEpq
z4a9PZQg2b4xRNeviysB+cdWuGaKNify1rqjoGDGbcoIiExgF7ZayMvZydM5hbF+wEs5fQRHBO7Y
5NhilM17YQFEJp/5du8QydPDwRzqzW3Pt86cXB0yU5+3tsaAgNGFtBpX71zwXVRzXtf1PWIyb0Td
WO56LIx0+XT1mVu2zWHytlybciLOdooq/pD8xUxdhIikOkeLVA9mVc1F/zAihD2AnPEEiyqLYmww
OCov6g+ojPVZheB1STypemgMQIWY612iW7Yw6x5lJ9jFx+oyZwG1EEadIsqj9JCyMr+dyFGQNlou
oSL7q3ukZu5LAYxeTAQHNl1jPv2WKeFqQ8LiONLlUEB4cBiSAmVqbqeJHS3DoxNQ+DaMab17YOBn
5libykss/Gld4Ozb596zaM01UwEc490C5bTJbpzlpknkIC7oGf1fui8Oe56Q3fSufxTrRtzsHv4p
QqYNBRF5g9tx12YCBU/gR0SoDGb8EhC6ix18zBeXo/F3YgisYPLs5v+Qk27icvSArJ9j4ZSt9v37
24eMy9JYjUwiJI8vdGUoa8ryAzzaCPSfQD5utaEXg9R94LaND/ZT6Rnp2OV/+Tx/p6dtsqPIV8wq
F3qxVVc7fnsljDgKAdlDj8ACwZrce6NkW/m1roWILb3XKTozyWo7yvjD1LYLv/xCVp9LwvTXc8nx
PfQJQGr8hCJ+KuTsVOzT7B9Jd8q78OQHVadjUtppmceKQdCV6I4Kovs9KAM8Pq3ZXWV8l+0Q3uO7
HLzQhlL40HP3SFt0EJWkKQVOCREWcIhcDJZ+h+LmDxI4VYXTRGkk5TlWCedtz1jY6ehVG9rdaraP
Gj7N9JzJw1azTivfiq9kgeKs30d6ks0DpSg92XG/Fx5sMlyvu0N/HZFkw6t870+eM2mTNKKJsJp7
ypXpEY42X2HHzbqBRkpah/BQ1QTq1lOYZdBIlv7uyR63fishVRfY4BWTynSL3OMh3+5tCdaduane
5sRWhoM4MOB/l6ztHupi5Sfkf6gl455ggAjkc749vtJN24GSsbOtm32XTECXBRyI82AphEplZeMi
TlE2ZV892fgD96le/tLD3CTexC6PQbo9LL8wqeOHo17gAbh14XvFWRINywuU8EeCFsYGcD1sDkLu
U/JQjI7xLdorv/fAZ0y/kSlJHA5GWh/wY3oKfv0aIA2jNfXwb4iTsaEtybZhFueJcT1CsviOc6pF
BA+Rehn48w1ipN3UqKiaZzaOUhwkfJpu6QfqjXKMB07Gt30YpbGSpgmNaP/VCNuImA5epvsjKM7Z
z74Te6uFHugJ0sHDQKpxL+hGQYscIscW2Qd0YSEQKzcHtPMuEPP2l0A5mhrtmbTKCgVhpGDKtG5X
7inL0eiHHlFYXZmhpHuNkiGaBo/cban9HP9cBn2PWTiA41H7TM4a4atG0ssV7uMaNCv0mtKs/qBB
ZSoqlR+kq2U6SEWxronA1GFeuf1c7Vje874aU80B7g2hJ2k0zyrf1gHUIyaNH7SmZr/wanttFr8E
gRnKQTP7oYAJPPfjEp0p75wZSIGy5SBqmv5wIe2Okr0T6hnR/EtVCWgve2/YPlZVg34OZEGt8nrj
6ptPbegAvWcFh4uHEbgmkfkdkCkY/fdBgkyjl1q9izP2O/GNApKIU+jzSNyxHQt2uC4g80LmOQ06
tc3G8K9Rqk1+2nyvC1xM10a+vX6ZU/LzrG8OPCSRc/yuxUKTgPn8q1EKmdsrq/ZdKCZ1jRNEg9uL
e2NzlQDW7+rKcF5K11QxfkKdKEfRUsH+SS0MHpzdpxhLHk/X/Jo6ANzbTKNK5cb1ZmyQJApKaIjg
6ikzjSTCqPYq1Y52DbCjCAu8+q37pUaGgXb5HIazBirTd2J5bhKrVV/d+s5uAHUXJeK95R3/DeqA
OjIUFvelfrLdJsL9lWlgSZjPKuuFocDhbGrcDs5xmQfbMFCVx1+kvp2ed4ouzwyoHEHsaF7gPxvy
Bs5PHGNktdzz93C4057oGb2qWi4rGRszkJSeACJdyfRFgepGYRYfP7zrmI/MtQqrMzoajkmDzRuP
6UShINcAmLqdPS/HV2jwQIkqOa63ktbKxT4wp+uNTSvpBsTDqVZmgU1bw85gROfe6XkwaSWxFeRY
6MkmZSz7kOpq4r0NrboZSuHypBKPpCrUvnZTNFunPPNzR8ip93/MAsy60X/daJHvWnB2qAUj9sMF
v3jm3Hry1S/ot2vqVYNWoRXlPaJB5cqMasYJMy9nnf6ULs37rJKsC3AwK757uQ4qHX+GhAYJ+6FJ
vgv7qWRpoHqBWy2PSafuSbpCbakhYLxaZNnH+170HL6OEw17hlM9oVSSPVP/EIvQcLgv/PVV1EGJ
9emgfShRoc0OVvcoasuHWq4o1gSQGHzCoskpkF/cJDg+5tP3BO02PS9uuXJa9rJPvoEYxjEZxxg1
qHhM+lsgjsm1I8EAVDzNNp3RNKmaN0iE7htUQJMudr+sC400hc6x6JSU4y6vrrDRc4NNNaB4T8TH
yT3mjZw01sFF+M5fipoOSbN6UMWyJRrYzHJObEdMUuqN9qqx1/UPSR+WJlHhDnfsxVV5Ufmn766l
GxtO2r+VBDTw/N4CoPUncmZg4X7oHlScR8lpvNlzSp5lnYFHGg9/qMLNyOWFoH2S/R4Qga1ODY3C
LKkhorinlgqAhyqu5KS1I4xxiGprQ0oLalYB+dngYqsNafix+qiUsbOELdx4kJvjflvN63A2Y2qe
bckT728OetwgtF0l0L8L/9qhZHIop0QDV6LW+698eZETImGNsWO5H+eywFveiKb/Yt2v2eTz17Tx
C6Ek5ZAxp/YJMKsp1CDL4YAZPQR0DfkckX3KKKy+05vTFTHrQU8+kYGBfQux6XTKEl5Wl0U8YWZo
y0lMMMCKsjyTNcJPiPcNwVbSk0OolTKvSxJ5Uq+/s2DIqJBIVL9Uyc/NIuOPBfYQpxEqONCmJ269
4vkxq5J1lRvHILpKS6g9nUGFrHnCBse3GeDbWlXEapIcizZksN6RKxY1BG2yi995GxCTNDSHVpO0
uat2RRgIp+SSIlHTTPFnj7LSQ98qkCjkxuGnEAUsaGdoVObLm4rXDH7hAv5ZQYHtAD0nhppIzFEv
d/uF2yphdil/A7MlAiFUwET6ZiTyUmMoLr2NwpMLFPQTXg7kap5etN+C0GyClRInERrXltP24vvD
xS8DGrSatMRCon0ySF7OtDj8w625pb/dIN4aqr38r1TKM3mKBNMKPRHm8kintTjct9LKLkt53B7A
BoBkBcQlYeJJxSFvzxSAfsFkMpuJKOOVfnirqitrH/VN2LvkHOWgeKUE8/drXHPUs5/CpHgyg3yr
+yOUfDly4bPVLf7FG7tMb+EwgFSl/CLpQYF8johczZpDJZOjBuIVzJifHKOULdorMTQUs2Xak8Hg
Nuhh3N/2LXm1sXtU/I7nTpBbgcwAHdjBX5oMc6sVMrOVwEplGbtDR7LzO3WIlB59NsVty0o9hROy
YKtmv1aPSs65itUeyCsM682TBRMK0XyreA4A/bFx5LOiQVKTeevCwyvQL/BSbsMHP/mGnIbdN5ID
Jdi1Sah6mI/NZcCrNEyGyJjOI4yH1EvPshxtHLeytgIu3A8G6OXwz5FHY+zNE3vQv8LEzdnnnHix
d23MkX//g0hG37UxSiOchQbXBg2MUyN2xwJigRr9nDyNDhud54Jr8s9ewjy3ifR0X7o1tw0/g6N9
QSNIoOwAwtXITp3/6mNF+jCP4ezhqgxMCXOnM3yLvg/HrpNaAvzxn/hJUwv4P5UamDW2VvftsgFC
vZ929NuGXWdOO+Ogix5JTbBlZtF4lSTEs8T20B/7ztv0nmVh4LBkHUI5Iwhbt+Jnb/UMC8Nff9F8
A/4DuORgma9FqsPzyPTX+3h4n1u5Dc0a066nauafcbTF4iNwFvFkP8xLTHZvCjp2veDY3kimN4iv
7njYBQzCqRuIuigqG44XKFg2EsTYJMYkvLVdLjVrbUigu/EUNI7V9eH35EFNZWaBYy0P6MwOKOLt
1RSklkhciTICYOb4HjWyUL7mrWCXY48BchoKlNNjI+q/0Rspn2BlV1iddg7Hxc+7PrnZumg2ugas
ZKVIVqcvDdaJ3e1F+HWmi688+UHNFBCNdI2wLJUmE/QLOA8UhdyFHGHwGTuWXjUOQ2i+YOsq2yis
NRsAbTVa8MPCeTY0T1njPDLOIB4cgA9yQ3yhaoM//a97bb4u9PZaz6YdwpdvWKUG9Wc0quLPjvnW
L+qkD4lmhrGPbcjrt2mPIK3jY3PTLg2C8zkMFatGeTnWUzNLZ2TAP1vPlsgef0OLblTaEVxu7U0G
cgdtgevwoYfgaSfJDqdI45bef2C/JgrRJquR2osTkfQde4/SxUaxDH+3b6UpXteQMCjgoEV8wpju
+ZpmlKAZklMzYMqkg7xdyiJRoByiSUWLtI58E6zbEhx5v6kOUzcue+UEz2Yd46DPS0B0chVZuKpT
nUEwRdyK8NxJcOXE+yJEG2QrXLYXGDYoddR89HRJYzMM4fmSTVUJffd6ntP8DVfNmvkrOvKiGuYc
E+OlmtCQbum8g7W3s6kGOWGw3WH6Xeu7w2pOhPwNnazZhqZSMAAfuq/J1hvChgix6Ov5+dB7EdV0
kAm4YGLCpM66HEzWAheRkYO7aPqq3gxAkZh29FFRiatggY5j0enCquoVeYZl8MK5uWB0fUvSVFqL
DCCV9D9uxeeDt94r7hYf/7dLXyqrsqRz7Z5BcIIDcdQxveqbuPdO4+JfVrc6zRAgQ8yXyntBebBF
NA6rY0p1ZSKJRbuK0oq/hWdW3tzXheZ682Dh2L7GbwChASXsYKumA/GOWzDttLQsbR0nIbUWddbz
iz5iafuzBfogbhbCqDEFuU4X7E1f6BPGeU7RQfX9o039Czq0th/36G8GU+rEtkwp3sWDQ4VaJTK+
qjAfMl9AoXGbPVaRBEltrXMwY/quBUD8mcgohy4YNy7FEZxdqBlk8dfm17FCzYUxwJMnhQUZeDWG
G6oPoKNBzK1NcQFyIZo1wit0GZE01a7wp2Sy4IROcnRwiRwyO7TduO5mgMzvbaDZICpeBn5cxzqR
OKAd5RxTp/FrJ1Rn8rNlDJ8SvKqL819TWN0Hl15c0yVuWMiO/CmZSgHmVw55YGyffJx0oBcn4p/2
iH976kvXui4/HyKl1CC9OgkbWxAwwXA6CX4h5BP3FT3sn34buB0CNgRtnfKeyLrkTHKOk5kMEpUQ
uPcDlRf+yH2QZBPS17SdhxedJvcZFJD2NLQdXDkL7sENdL6a/55dbmmOm2nfzumM3Xud+mZaEGsJ
rVS77AHJSG3HLF6mP17CWjhdeQBJdtGEOrK5ZCCAoCAHOsaGsd7NmdXgAuoE/WorLJy3yBrTB2iI
+cEfdKPhoYxaj7XFvYfQ+0xGGlucS3S8420Y9nSJnwfYP2CTrluyyGThWDe/RMJxUHF3MPFjDcvj
Qr4rP/TVndVGBkzaU7EZZryXjUT06z6bsqzZaiAr3KW1A0MtVQZKFHwx0qK39reMvqGw/grEZgaX
8zXWyNq4kRb8QZz44hfJZ2R1ArWY4/roK8TkF/NynOpWWBIWeqyz+Uk1vl97+303qdhJ374OAMOx
3xIQW6RHlp72ATOb1za4ozf6mznqh4zA31NIa+aRzyaPT8fZpz/0+oACCJIsoOSaWZ0ZkZNMWqkT
/U/81tTwI0a5g44jbk6/ZiQ7Mpiw0W5o8wLrOscu9hNGjsKZZBj43D8yrMY0manbwyz0e2GMKOoI
vQjovnyWwsezAFbfHOXlew9Gg9aj5AIafjL1VXM2M/gCpbw2LLEeyH4ulV7slgtnRIJgsK0Bq82r
PWaOEROdJvq6nQMZZl56D1en/A2myKD1v+dmfHYrE240JWTQMG1lTo7V1YM+3NPAYxg3xMkri7PK
KVyfG43Zu/KvhaJc/T5DdZINjTeULo4O3VKFq1JKDiAGb0fDTm2Fi4UC+UlpUEJpCXxrud8z1Z/7
U6o6z6u/D8RhgE8ow9LuQ6HpuIyQ4ZLUZAegNoKIF5HilMdbje9gkHwsbDKkblLKFCtPnRNbJX19
9wphpTYq7wl67Nr6t+ZZQAYaH68paNwDVu8GhGfETyiI0kSpemh7xMjaQsJsc9mBVwgF8QXxPp3a
aPzgUS0queFtuJaBUUaFSEY2YHfq9W98wI6qmqrjIH1ybHEr7AEOMAQf6bWQdXf9jdXEr9iXvOuw
A1lZKYpqnbXtc3Yj6b5P/vJCtF1VehU5HyZvSY7ADPtirMhdgHz//JspyrIWB32WnXEUST/O82WP
/FWpqtWjFvqrrmALrvrpS5wfeMSGVfupKglUYimJ0pl5pxmzGyjRbZ7daBGWKuJ8r9C+i6dtlHjZ
rmg0y0JrpiuzCsijYNMnHS3zfhMje8cDoVgrANN3tSGrDiAfths5afAqKTeR8kO5X3pYT1ucUcva
iEkb17UAH7E8Tle0rRSL6jN2D+/TvVdZT14ok066PzzcUKVF53bX59XZO6IWja1JEJOZtRMrgjgq
D1zoBd6qyHYkYD0HuKghUa76/fCw/jXBjY8nGn93pgTKkMm7ZzLTfr5qi+BZ9Cb26yCzDfBf+9a0
Wt1GX2pMGmxph9wImJU4mIe2mnFHR93FngZ4mr7j5i2e/fUAyzPbT/JNzai77Kt+NhcT9TUQW/FV
zi9eb9RqFFRz51/HTOLpBehL8Q1jLgjV9LlYQtO9diad0sqELTnsQS2ViNdLN5rjdhYdbyWKFuqX
Anj2oiongjJF6R8NBcZ9+UvVTNBjUXoSgSWbNc6rjISK+4TfMOgSWIWl2/UQEbQ7/cOTniKsU2wM
JniszONiOMT/6Qj2I+q1hNUgZBJKx16rsnl4KCtnwr/IgvPkGIRFbHmY2YiZRC1VPNf5A8Ys/OUx
6PBAnNt3KybMy39lpus15K6HDP5DF4k5q88nSQR/0DQKUi/4lFLw6q8R+ypwawU6Ui0PmbE7qDm4
oPP6JkeJEjjeRl9yZpRkTMhDcXBQuVbfl1TiKNHPbc328ZWDS7TyqIPEQb6mzC2109tbPoSgUQp9
ZuDTAQUlnlzLWWiWIPr5rl6Ijl43hc4W7CJ1AFFHMPW5RYfYTHg/lG7YTkVDUScyWSxA9xpT9r8m
VCNOaxhPumA/hyrSZlcV83/Wg1GqqJQa2czWgTxJ8zYgiEaZAPbA4RD3X4dGAUmWwtdvo85GYbl1
0w0Ah/l9t2N6IvvSvTPBZ2j1oJwAz8/r0j+vo1b4u+SEV4OtebhLCvAmhgTvTdZMrNv93foTyZm3
DwWE++L9PTkY/5Zaxsvg7G7OU2/1vwIrAPyKWmLHfObV+zAWlJJ6wdvHEAIvwagXxN+d0RVmbPXG
NN3/GiJjX0pRvA6HGGZaLf3FjqrjdQo1mS3SnK772hf1dnbef5mCqVDdQPt5DAj5k+hiYJLnLnbW
uJhWBlndR/xaqFnxuvOK9/fPn8VAJSSUE00dEvwwn7003NC0owSlbiQyEuYgbn5MMaewRSXPqwcA
T2f4CI/G5AUPaFBDq7zEVqrP3rgwl/mRvlyK1AO7h9vvEjG5iU7FXC7/7/9u41I82VyEMjZKYF0u
8CISKZWNS2Jhc76pp1/wW4JVV6vUT/8WH7tWtjcEa1LBLhTtrnFFGibrTmqIA3z7YY+S1vvG0Nnv
6Yak39jtDcszKcPedJZDW/C7SUNNhABqtvdCYZ49px8wxOi2s5LBnObM/nmXI9tBfC8Q2R4ZDJom
AKiCa1GThjk7w7V/0wvkJ6VufKYNFKB5shTpSPs5tCn/VMCQJoswI2+BH1PlDVSpqog6eQhRE+u8
NunGntd2ArnCR2Y1ZbJUk+9It/zmG4VJGDnGQWz02jGfuSKxjAMHLNqvdADrM5wrl3uEhx048d49
njP3hldrrrtqzDb2zh84n7BsmLP+atCplIO5pLnUrB4eZboTkgq4GCfCHmKrbtBbIOf7kJBnFt3F
pTG+pAxTUIOm7INPR94Pf/XpsK36eeYyD7NXChO+WeD+0BTuLvZzxeXW5bY2TUECyJoqOQ3b0zKU
BRVG8Ts0gonfnCOURoCv93HUtQEYz01fM35FnV4AbnPIFIaaI0IEeyko6PQO995zwkS0hSQu/oOl
isXRDVcTeCcR3fupo2Z0u56HpmfGE6lRtg+m8VZF9weIWsg2WipP3cz0INQpFLLg1z8AC3FnCiJ7
zrT43cQZef7g4aqJvC2ahSh07VLCIQ3DsUOA87yXrvgUL7BVB5CJ6bA/TaKS1X9BoRx4LfjUs/ka
+crgB1Jd8UzafXJlaVU+j8TrlS98P0nv5Jm1Umpy601Qzu/fI5VhtBAlwXNXRWEf7aStPjztGg18
pTkVNjcd4XjEGBBn8W3vy+EsixFnFgE1t8uQfK3o4JuUG3Z+lnpj3b9xbbRLZcGC+yYU9EkZI4Mv
NNPpGspQtZKnQoVGT0SrMM/7K/34/IBBJmCFUqbgBduy4kQ8tQodM5hd9VzoqlGvdIcPo88OWR/U
N4f2biLbMhL0V1M0lzhOCxmK9ejl+kWQUYabiktnLC5UPGg169y5J79qOgGvu55WQSLS06M7ySxP
7/WogJ0mKBoB3oeBbfmoM9RUl8h2JOrSpRsUVTNGc++mv8Ify3QEqAoWOhxHyLumR0AXHcwNTjqp
H/S7cABmn0yZ8boMiRuiJ/9Vz2LrN+VAe7aBAKHyrqOHTDlfaJq7a2vUMxsQl+DsC7w9w3OuyUT+
VQfwxXdiQBUWJsjJtHz/ZXexsguKtOjTXe8tjxn4rK7RwWShjE4nQ3Y50yG32TeV5Yj1mIZxLrCw
fFCu49wDebVfMbP5h3rGN350Jp0ctLRC/NdWGuQWJazs5NPQHR8TOo/aMncxHxNfu1KUrtGTZvaw
egcWrCO0/JpJGllcR/5Sph/421JI5lRaBC9dLMJtQQTPsVRpuJv/p08IkW7mkjabUO9UlAChOd4r
2HS6FMkdDKcVJVwI2FlFXToSk4egWRJZ55KWoV3WsFS3+VkGnQKl7uuG6c3Z17g0I/YbM2GuCh+E
m5EjOocZYlL0HkLZf9fx/zd+x2giAVSnSKnuzEm+xd+JYUaclNkgmUif6Ac3+fM0BA9J6GzXgXvM
+EqwWLE8GNDcAuzFgGZ67oM/YKMHgNx9KKltT1DMb4XMv+EYYB81hEvfL9ejyJ20XXwFdXu/FFZ/
I7WCbm0cc6tDQ6YSKvHCFqPFtaRKduT741JgRoD16Cx6J5CZzobQ2zQptsc2MfUElzPupOBFgyZS
py0OIDo3r3Qwx+Y9tyRXnyqUgTkNNOSIUIXHrLVKj/t3kuHa5NS4XTWiYTS6hOskbKu2FJjb+RUT
49lUnmvIGAqX1BBKYPduum2pYd2JMAgVviWbGzsT9XEW2v/jCygIJ2elaBt+Nw87184r3e1fsV5P
l4NPeZAKPmvjQ+iPpCdhZTuW9PiTgEUT1SyO8XGzUcdiiUPNfONgT9Ud0AA8mkmU2gbO8eT+Az5U
esEQpACbk+50bo/HfcJ+bIin323tszbBWd1deqz3QaOhvrkSZ0D/1Lr3B9eawLcXGAfeb+Kf5s6I
8bMiu4l7FCNnuCoCpzCvppSNAP0eDbJ3Gxm+R7YvZ9sMU4sHs+B7/fFnSzRsY/SeV8WluzQNPODd
Y14dGsMjRcn7g2afgv7NIY0zxajElssrtfkFeXgXr+cn5zIwljZr5SJRn+rRgKnXdfxvLHYMFMTG
/UnbH0YtH3PfnTJhCATjOzT5KEj5RhCeRg7+lJ5+gS0nlpDtwa7O+v0+G71b5KwmYYntTYxztId7
pc0zDyr/kDHIaGwa4Cm2GFL9XmT2Ep5y+XFAIkoRcOh2T9HR62cZukloJQ6FLk6aNJ+lyyCBuCx/
NksA+gJUNSuxfd6yWxqsRA4wwCkGOZT1H/tSlGRcZjrtUK64V4jHwOcca/e/a+90Vqr/9E/9ygRc
tsTMbTWz0ATtzDMLdhJBV29GqT+ytFhINeQAGScz0j4zA/CW0rhbDqKzflI3cd015G6V+WekekPV
fAh7cwmrscOhFO5c7zZBQlCKUG6Fs1Czi7sXzntDsWIrwitEbM+f/RhD5tBryu9/jmOY8n6cuD9N
6UkDLi9KmaJfbYFdFg8AbJivLZppc+Wu0Tv0fhRJ0gqHv96t1DufLnCRFt4lKUypVVSe7gW+uBLm
MICDb63kGew5gsKFnGNoyxx1G1J7iycccA3JzMN4FK2ZJ9iyh1HgLSD/PFoqyTGzHKGg5/z6HGTS
w+kMcB0HMNVcccTDiGkd0/IM3Da4WweTGrhcGFQ2D6HhEG5onzG8OpIQVtkSNPpppYJ5oMHGxNjt
JxvAYIbVbmtFgqsDnEo+ws7O5XrccFQUDMztTkqUjolI2Xnj9GO5i//RPXoLt4eN/C6GqFb8gZlK
27Ch1IJTi9SVU85GTZJBkILJ5RhwH7Fz3B1Szqj07zxeXENgogOpr1aDyeSIymnCitGxbNLdgV+1
p+uD3pjc3KyLi5D4r2fH2rSn9sosS0O+88UqiG5rroOhzaC3lC2w6ha6F1IDAN5ao2DRDZz1Fpil
8pTgA6GbBjsDPLEWZPqvqS/XtYwnNGZ2N8A8MV9/EZ6Es+B/rD9JNyfRs/FOI0lVc+3ka1hg91M3
0I0WADIAtMVaEEzG/PYOrIW5kHRQDpcFRBE2rSqWiWYrdovMzvCtW2A5A5iKo86xCFhNTr7WN9EO
vqw9Utb+EKXOpUzEICrlTLRmSQzNEB/wK92kDW5gyypb6yj+RibeAH64o6ibc56+fiXFxJ6CA4bb
xyQFt0fg8WhNiT4s1wPLVtKKcn1WlMaUhnyhQD/klCXoj+3AryZiOYQMhapFqWmyf01O809amOPL
NbnnS+Nlm+fOT/jBd8Nr7pnwfxwc+jhr/ZZoztKsMd9eYThH1n4Br9wG+0fOMdB9DtISBlXaHn7K
yu9FMIdTU1d765ootFo8pDF0/R/a1dLoNMcJRzx2SMIQ6WNFxWxro9gD8tdFVTnsmsWahC/taKsb
ElXlNsXPNAX0KjtP9EEr44dUVEYIOCJvMUD4r87X5BZ8wjmKBuh++pnYwjTfK3+Xz/Bf+fk/v5t2
brLt6mWI2p90MHK4d6cIHrxr6Jp0NL0BeYOXSb+aJhjs1f2Ut9i6bsdlVJYgj7R8fe8r391LPX/X
qQogHq9OD337nCJxC7YXwnb6WOD8V4tzY3Q4c3KCiiDm0H64fw+nAqpzzVDTX/V1dfp/r66gk9qf
RJpIfUveaw4z7lzF640+ZL+MGNAKr7fZs/QlpsdXo2CxnO/t4i/XdMs4PpA1BAMwgSFHmonhfIuC
I1EwRd7oQdrUiNuW5lwVlPblb+jKeH40W5l5myC3mcHWGNYGOy28/D6Ya+08HWySS6cBOcXxYEGb
LagqmEuilo4Os9bFWEQumcWAgi+RNep8wehyadZjYyU4ZfFLuIz5yg37puyMgKEZyczwkmUu50kO
NcKkQmwsJLgDLskrocYpaHAAGy63a8/EDou3OLMTQxcv/z+rbxC9egg6/s6tGYJkO5AcLgCO9kuB
+SLIl7wa6qnySReGnOUL9JD6c65UupPLPm5OgYPyqy9YnS0Paz/WWYjFJ2I9/Nu6D4C6bq1J5GJW
ag1l77c00wk5Fgy7m9EyDe7lXBT1mn04DEktB7vj+qxTOYHiKAZSLeB8PbTY16U9YgGkDNjG3pVX
2oDAJZRtsSXnPniByAm2i1VT1JYdiSmmmkfq3VtEQyuOyQ0jQobE2aYYaJDluXl0niao+g2wAems
qBdq2RXkCzfQrZpAgnqWh/9ee7MFVbWdkIZHcZDMxC1g7nO0e444rv/7kFE/3qjmiF1HdTEWjLPa
i+26eExq34T2/Py1qKN9n1dRVv1rO2EzVCWa5M17dr9BBLQCuqIvfjDjFO5tSzv9GazFTXSznEXg
iQt0mSHug9+prM8SVmg7MBzcoPAcgZgRfCKeBcp7VZYHMjN79Xi+4QTTGKWJEDXwAo8Mawda4gOi
nMJAVO5sY56VkTO1F/48pExzKqVBHsM0dk/II6CRwlZsIl7XWUwnC8wDtkoHZzoRjSpMx3z6qS+7
cWotrwl8epCcoi6+0KbkyNs/QDcqBgCZIUe9Qsw31O4XIoa5+Cao0zvt4AeV4qgIGQ4rX1aK/g6d
v27ZDU1obUM1WR3g4XIcgs9BNoA3QzkL2Mda6wX6jyEhfLiX5M58A1DERey3lQZowBBSePdtwztZ
/UYvZSZpZ2kmtLa+ZVpqRWrnDzxxLaftVH/O59bbsPS0VI+xdNYZY/XafhNXTfbY0Y/y6GxukdEB
PGxLYNn+cnfyKLmBAHOcvU0EbEN4rxrRScvYJow8CFKwNAV6Rtyg+XI8itgwrA/Od0JxbUKYI0MU
biehd7rYAMHmjLjjcHAitLqbOrOKk5vD0IQDFXPRItk1pJeylFTfuTwfMvW7jOnCuQEhMImIdWAp
VMFaj+bAfm3O5KndLEpCTws4bkB15vCrf63nny8k5pS9NeLUdMKQT7I/2/iadWcEy1S8GjUzcPFE
MpkFIk5C9YO9dXxRlc+RKXKmOpoUOYZH17S56W6KithjGKeJxiUqzNmCGj5lfZ3iLSTsRL2B8E2h
rbGuRWf/gY4f8F9QH++6o85di2hbsLdQ+gscz8BETWeSHYrjWosDCUFqvFZtKmFVa+QdNPfq9w5b
45ZlPPbP6HBBvaUQ4jQP8pxoIh6NpPUrqTiZQm6KaScU/WYCht2rhRbWup+B9B77MYoDQS/O2ST8
jlYN/v/zMwPjyevO2rIj3ZzSvl+vioF/J0X8WgAZKhCAG/ZjamEr9TrieZORd4G7NrU/rxDYOs3o
U2/cvHIZ+fhGZGmkFwm6YAmyDA5dujXVhsPyO6OITZ8TDQAFyXbaB3S3qVVgpRlzZPasgRsVPszW
o+q2lN83A4VBGJqU1U4PYsjvgewLPbZL0NZsUe1fhM2DOijiJQRWevreXn1xoS4cncAGbG+vk5eM
8gP2TxnsJ1GXiUENacr7wE7YSW4ttpp3KyLo24vWmxGeNCysPZgTrZrYVFXAwyIDfJIUS2+ooZgB
XGFSKwDhSwkxL2LTzN53AkLoEnY2mA2hMA7uO+Svv7RcJATK0unER6lEWXVHDW9aZ9bgI/qPtq7m
R8CVNpC1bdCvfrgaOhXxPHo2XGVNsYV5S6oMJCILnxZNmJI1ri5WF8vD/TZYKUtN1npdVCnuuwDa
ng4ZPvHVWX/vA+dH9xtdlDdBHCvqT+awgK+ybggpUwnJzojG5qY5Vo33TR8dftMdFaSC9pFmmLYw
HFa80MhaL7tnXMCl92OzoW9RXiZO9OXbjFyn+RsSrz2Vz4zTkM0NJwVXViK40Qrj38H9KRwLDR7E
TNCEB1Ek/bzGgeIgklng48G3YEaZqotJP/Hbc04A/OpVMnbvu1I0xErQbBCR/Tnsqoo0ANznj8E/
iDfVDRplYGv1leY4t+6pqIIhVMdD2gQvefHdjd2vqutZv7QxyES5TjIblscpp1Yw5SZSF+n5ZDZK
Se+m/KrqDUZqcd6KvoE37fa11rP0mP3/OWZsrTESo0pjxRcB7+41su6zwa/KBCrW4gxhehHukajA
7//5g2wJw5B9zOk2AEFPwNvuOdc/2Uzf6VkE70Ajaw+QK5M5KaKgnfk5aoN7ZYIWwPQaqmeYTecY
YSxcR8Jb25vlVPu86BU0PlwnMiP1DI9XJj3PVumV+jPgVx94W56XFHLE6KoVMo7Wfk0ecWaQO0Zx
hdO6Refuyf/DqJmQerbCvbZbnohRw95J0iwchf/iuZEIGYSlnsTdOmx2uJvCH0pvWKgr0krwXWMK
rEh5gCcpw0u/F/M3DElH2DXcQ+Lcihj65XVPD7FrnG57w5FiGuCaMbGyX2Xim0pbgagE9McDYSp9
bYsGed8P4/Uqv204v4kttjg8im9pPK1BTObjMulbFiYm1CCVv/v2eYEM5SdYczGb1dZQ9slx1G0S
y+ZmWFobZ0ON5KkWsd4wfPqtodMkJ8e73tiP3Be3NpG/hsol2OxnUNar4c0d3K6P6ZH1RR5OdX+e
z5X864lPAX7vyzh+xfEeuOTLsM4pErxiLGo+9Z6UhQPfAYr750zMpR/kqyltX8ShL5blK/uaGkfl
tPlswIyeQCDgZo8uLk+smyLQaRewjv0MqYb4RAkIP1aPSj0aLbTDIacgYDmldhi9BMJyV6cHXNJv
E5RT7aU6/auyDPzqkU/ElVN0s22WHV5px5f9WWwbSYuZsmevF5Tja2IVk/y2D+iupcD+0AmuJAXH
LgngZzeOq789P6aeF1ykz4EajY9xhB+8aghHoqvySYB+SDYLG9HofOJnVNRbYzfgwJvH4BO+GbCi
Puu14J2HiGhgx2X1ur48bQ+Ftl+YDRMBS64Dm1a3tAl4wUrmRcyg+7OfNwSwYuWgvOw4qbNuwO6i
dBZ355jQJfOwzlPRKImvaqIrazLuHmfPtY0ayuESjpxi/erK/yieXHs7jr351+UhwbqF6XidcQ3X
aUzd3XnkX9Ev0lKnMoJ6iZdJMjvxM3Ry3BcNN9q2FPSCXp/1yR3JwhlvPNkdX90VpsRjI+MaX62+
/rBEZuKvItkw9R/7eDviWE7ziY/NMb7QF8A1OqR5M4qut/42l2wvpOvU1GjncX/zgJ1Hn3ZsM1Us
UstZgKDqBh70CNhvrHtCKVa9pRIqhgi87Vkiq54TYHjRccXMU6bZK/wAAImIV+mGbm3nJBf7Fxy9
ngrZjkxVeo5eUsnOYbKC6UAOEkqJdJbOKCKNICRriYr2w9UFAGyeUXP31hBNpmydY9x8vH6cUQXD
guNG0MqLKjn71N58puYstecNgp6HbdPrFx/Ubr5nDTrq9xFnIBIjX3IQPkQUN23lUQ1pNoEPbd50
hPpjorLU3qwP6u43A2uZHOzkB07tEKinH9mtRISIYNSxD+d3DGTx69pd9NsMUUisGW1BLnfTZHx5
WHSn5e+UTna0p4OV1G816XHj17M2goOQlIvfklPPTL0OZu0afdlZQRhLHH3VPxS+Ss00Jl2JuJQq
XsIrsDIuIb+3rnYbfGfWk9UHxcdKFvqT7LS2eMvr3iYZJ6u1ccrYzngRA8TOLpMGpUm64GP15kKB
JS7zWck7XyJ0cO2Qh3AET+Q8vCPb226yDiVZ/IjTjrwitrMEhgXetxxDoRZ0TbjvoMvrDYU/D4xB
KjK79hV9TAdxYYQ6w35d2RTRhn3F46LCZTUDFDIng9mnQV/eeLDD3Qtj3+8UmyywNZYVjFyf1OGG
Us1Xfui8dxjD3/uB+QCYDZo48uZ5+2hQ+IDwsVt09zXxBrqIaLLQ97VSxGM4QZgsAdrC760elirG
cQ+PSq9quKH2AP3kFqi4am2zV6cd1xaD5SUswHKB7rqfJsKaXh+F9aNYECq8T4l5mS1RbqNXAvIN
XF1TpsI1Zy+4OYoH7F5KzJ+gQBez2Gt3loDVDj/PGyO8y9hevSYlsbuM0H282qw2v83Cj+G7lZjd
Njpf/anglCUv9zLlKRRyJDd4eiJeSYdJbKjUCxfLuqvoCwiHLleOEPMxAtagnMPlxP1GJetSTol7
Z2jjkmDh0/qFHBNkuZY6vNjBRbguPx9p6LnRsxD5/VI47WakNDIekuz+dxg9IOr4z3I6hNbriFOm
MlKbZQ2q0Q62unerTZD+Ly5hAIT+5en7+gvv23aUbGSX2mQrecI57JRvkVVlTT1PZN49NglEb/hS
6BroFhvu0QlptGlI2tTucXyWwVOQaAwV15J7lCZniTLgCbIK2E76gr/DvkaqS/tJqF4iqc1mMoQt
der3aotSAiCsDxZxR6v9dOsF2mbiS0sCFt2egMyvEJ8SY7h6nozub3Yfkr7sGZ0Hkco4BIjJ+0XV
NRXmgmx8BCVluaTCO5H0dir8i7/gfm1NolniRii8B2FE9DU+cy5aFjb+DRtopwHDdLsZ4tW66LQA
fGurvzlDSKrr3v00+FbZLcqZVtl9yM/blUfWv8AGgN7PrsPJo8sbp5Sxamnmnl+DrvFE4VOQ1dE6
Gy0dcpVFFIuOLv/MEV74kb7dfHHTJ8U9GaIhIsKMn4SCNvh/EA7MBTljDCPn3K6rPOhKHpS5LTff
8a7LvTNVB595tHOAVP8HOgKerwSgpOougne10chgdELGCuC1SuSMvpNYjhHYaqe/df1m2cPh4x1a
EfTv/5mRYmsjqQn9ZQ44F/IDrr5ddviAhR2Qu802/a+59U7Fp9yuXCJWmhl+ggPV8tEdhCZqrcFV
UUd80D9y9vYR/N/4TrDRR1jmGnPjSie7z4pkXltriyZZZwq+JjHRpMc5gJBOvNFqRxEH1UsbGJrj
/gad3AYZMpvQiOJAnBayOP0MYrVSTi7IrW1QmgoqDnQNI5+iKxwjTvht+bwb40z5yMqOCB838S1Y
cHLnfPX2svyDDDF/q/bjiUlf3Son+ExX+9VI+UrWvm0J/5UW/LBG0QFQnGgPvlmx/nATy/tAb3CF
n1Q1facY1LKKuiacngcs7U8j4M6AdLqORMZri3BCBcoT5AJtRZEndr9O0eFLXJrfAooSgwuID3Mm
UJRP6KeSuIySYS0W7YBWC15lbVmI9XpgHDJdpybPPdF49lf6V1BRTP5tRU7xgEiOynWRaMgZLJQb
H+Cfri1W9XtKRlIGg4oyFz2oW5O2l1UyiCIZrSp9NELKVnbg4wVLkT2P2o5yFTiaU/19bd+jRTVa
JIqSYaeT0Hd5w1gtUrezJTqrfNQJ5wuXAthXkYO/y9+K9AvGikZbqk/OmGn6iVPJ/1L+JYIkMdfL
ll1abRVBwcKXBvUKVg3tTjW0Eo+/tzGsX9cMfH7er7r4ay20l18PXAq3+/GWwBnALkkt3D1PfM2j
EiBmnzpuNRU0O19r4nsIAI4Z/eHtryEYHj7h/IFtgFAiwvCQ4I4L41sB8ny/CcrimggCtHrzq9Wk
V3RKgPhOmszsbWDmt9RcEgy58FhHQyyMWUZGinKABmEfOA2iA7RdALz3xfGWuZhAVngq/OCfdf5g
8JDhboFhr8MggRwBFGNSiwuS0Y+x49Hx9DfU7r/rStA+JZi+fYfH3O56qIr6vHQJ+00CtIXX/mEw
a2bw9v6QRFB5ssjsOZFq46MVNwQz7iD8QrxblBNirCN8iQI9ida2z6KEPiiLyMlCtzs85iZIUght
T1Rx9tGDE6x2z3uSTMg1LDgjICWt4EQfOYIf/F3SihiWy2GLHeAxuIHh26me6Oz8MGnpz1FSuRA5
41H/B8BcfOahn9KKq5ufQb1iwPYCE3FDu2GsOPmvvkPQWNy8Kafk45gJYrCY4LmtE7FOIUBBrnPM
MF9qLW5YOmXWEr5V6oHSUhNieyhXzMF8UXBCdTwu+JpINU5vXcBW+dUiCHFYsLM/JMNhQA1vyhAj
ZLFXw9AYm1Ra5cTeZi4Az6tAkD3dML8NsrLarDhi0elccM39Sp9qWrEORNNQKtSyme8y6Nh0/YP3
fBbTzDnUXsuEIDRmoj6uDyY90izLjVC/e+gY0XBOUpJDh3+k9J1gXSu8NcvdbGLHjAAd9qrx1JB1
b0MvpBHs+Zz4lCJYGniSk/qTp3YZM70wFuSHIF0Eiyx4nwzWsauLTJzkZX8Vd/eeuA3QABk2GPtU
RUuGvp8Vhe180fpfKEu3lTpIc9u1QrWfrpq0C5qXqPLpBs/C2odGhRToqp9ba4SorWGwnpWaVZl+
Zs05POe5hKX/taQzSTZFXHg9nf08GQhtURR/d9yLKYYKxA52TqCliUyepBQ+AmykwAh+U1hS6Tbp
f1XeSQkfc/kjtKOEkzombE0gfV5Z+dNki791X8f4wk7a/JOCp7qL7n9BuhtBywWHytMnkGOpo2/8
B8M2HrHcmu48NbeC6yrtUGAMtc1/jaNrIXDwBOL1kZIYaa3ZXb00rd/n5xdmAsXwtkZ70OpiOWIt
YTz0zyzNiE7wBYfY3ZsrytO11mPl6C+kwdkbRdnckm0tk08eRCpPF/B46yxQ6OOrm3nmbF2pGBbv
ceyS1FF7kDDnP1vCO1jvGYTjvhbDugzhfN1GTRaiVHgsTh/PbXPT6zSxaTNuNMezCty52pqrnfAe
irFRDdTMOJ00sSQTizN6IaJHIIPuos5ym56mT9OMKrhmdXqEcGKwY4aicY7pBVpTluqSJnkpzAI4
LVxQPVVpmhOcnf1SKqq1WMHkWQ4dIww/yayQO6W/WfeCwb6lKA0X4wCZNMcWZIvK1ywficzMpLLh
yQ8qfhyrpSI3rnN0IPhDItvDujDbmrw63L3QkY7NhZ/3rbB1UUj5ohqs8buiUB3CeyMog7lXs7YB
3L3w2QWy2Jor8rDQNORHaf885ZqCuB7KxsgE5WBhOflRZXuRwJ9koG20nH10ObJvJX5il+PgTZ5M
P1vXwNyNQOuy9Hmr4kZ63U2euiIprk8I75N7Gs3WmVk8CbE03jVwSbxWzJ/QNaEjGHoJzfxTjNPG
NU0Bu6JAPu6tF9mEoxaCooXEaYbkxA46sVInOWi9gbG83kbTkyt8gq2jIfQpEInh45hP1PjGkZHY
/OzMpbUv35YHW8YnF3/uMzC8qn9seqUAnWxjd9UQP3vLnFK+3WAXJELqCwk3FX6/Zr4qnHXD36ao
U1N1mfuB75Lw4YjZR0P9uQ4UCJtKR0+ZXASI7kkhlDHpWVj6QXnzEIcNKPuY3JkcsJYhiQlHwUoO
jwEaxuzv9+xkrLw5zXKcp/Oie4b5dxAiY6V6jNUk8eC2ZxJcpUO4PBwAQ7J1IpcWjLIlOuZ0IscP
P5BsD08geKTAeXRnrRJ+lXnmDEbQ7xi6rWYkRKrm/nydemJVwaTyBtNZJNLjGOf49IPhE+jDYbfv
HjukiPZhiHWE76da+w0UdK8sJGPDPKYZB/miaQ6jI4Co4ga8pBsy9HFP6PaTvzWKf2nK3tPdg5zL
svF574IXGQ2zZBOSsyxKOc/+uEZYyDyGWwqdwE3oZXpkQFIIkcA6GQhvmSK3iq+VPGyJRyKJFLlC
/pG5b6OoLVS35ux9nKf3djePTDr1VmsnWWe3lgVbVmInjieXK1YtPD6a7YesRXGCcCV3QHiTAXkQ
1kY2U/+A4qJGw6X2bHmslIrN58eu3FH5yEh6dN4uVCOO35Xi1rN7KVgnmdI3LAYjuPEmKeSBizfJ
ow1R0xASxc0U0HuM58yZ/OpQKRGKtYPYGjXZLGkbtiEmSJ8KrezPAIZvABWrPLPtAzJh5pg/3yqs
LwSj0zKW8aXKs+C8RKCGx3BEPIOV9hioPxnNLfP7O1Ud/8FuetrGjupe3tf6c1Mlq/Y/+S4CyW33
SMc1pkThzK6xIZe+U4sFl0L2ChsQOr29y3DbAW6pdpuVLt+nkzd64SOeVrgA50sg+3lh/CtpdDVd
M7jz979e2m4Mepbspw2zm3vrPjT0tvL2ZjxY0z4yqSgSc8HRF8kKHetmP9LUD/FWpoP6Gmzu+KFI
v30jC/JvevnFSWRuvZYo1Ef1ixhI5WcitLoUHnNLnk+vrZu08fuCAS3jWtlxe36G6IB6iWKZu2VM
lcup4FwToZo9beT7hJp2XzXsvyAbGJ6tnGWJ+AcIW/DhJs8JXTwNXUiCybb4JNz1esm0Qj791tQF
XpjUFPLWalCj1QS4fsoFJItpJLN3IWU1Zxok9OrnwyXNnkmC8u3y+kTotm4i99CRpj9WGOJ4WNb0
wx0kSvDWyq/jNXsBffnmPB7Gq6ZNs64Ob2fJtJu1eTzdv/BS96OLdOLc+GDg2jPoUZkbRVJS7SZf
cfs/o0YoM2EQrRfCBMPSrxFWEWEJmkNlcaXXK3x3MqpGCXlnLg+uEG5o06Lhb/m4qksgrSzLvcMc
YJOmgBILMGr6wmfCFAbImKEXaUQIslGoWlrSPsnPxAUdvMR520GoBQvJmwYQZw9jX14XP12+Y0x2
3cHvGGPeEQAls5ntDaFJ5v4VQoO6vLfng+DkeiXaQwm/HBxf94ANPqJ2cuEZOLzduC74NiBGjEZE
XtegkCJ3Z+zwej71SA/orYcTclf5EOg15sShmPBa13BQvW66hmj2dEbEOSeFPj9BK6T8TWpRRoUf
2o3BgWeO6gPy5r3JjhSU6CyLc9J078orwV+o9soh1T5+7v9qasMg08bzMSX6hbGsjgPfgBIxXQht
Xk+C+dBI+bkoe19zKRbtjpMZl5lhsDmwtz0MNM7Z/cgeW4UYlA9VwmKs8oAz2kCiyl7h41Mnhnnf
xEixgUU0GVreF9Sd0d7M6CLq7biZ3tSQroDM32w0v+aRRXIwIQG8Ld/yv+2OyTQVl2A2OwPMrOJy
H6g2fjLkNPk+SE0Xa4QEpo67qZtQqO1cODfdbYHFdGz3PBL/OCDS7fznKJ/XrtfRY7Zww0EWpfEv
QCLdY90/B9xUSzvZuOsLjXdY/f1gGAufEWkxCD4Bsj1r+ro+Fr172NrL7SUhf8qSugNfWIi/AFw/
fVlAlmE+2/m0FsM2lHsMX8kQNBfBiOVr1uKLMJrWRQZLdCtdYfhV1sQzi6rblFVFNgWDPs51UpBm
SsauH9yWmcwd+aayPHHZy1PMo+CvXrv1HD6C6dV7dB8r67pdZ+madV7AHdFBa5qT026ImO1gw5u7
tKKKaxcbPn9dlufilX10W7LS5Iam5ldnD+4gSkt9ptQsRINgTXaA12zt1gDbndnM+qHEK1Rhv4Rt
8RaOcpglfBeb+vsTSQamEy2m0YYgwqfhO+fmGxPx+NJ8OeOmiR8/8mKtffQFDqqevdtQbcqh/e6F
ekWrzujKKyihnfiOZEdLTWVAAnKCzDa8TSREOulE4HVh7BQhN+ZWu3cmhtLt8M3/gkzw/VWq6nMQ
odq9BBdwT84AmN5j2XnshfCMLqQqcQ5xs3u58oZI9sQyYVGXca10EKPnysKUMoZZIH0WoSLIKz2z
W325e9Mb3h0JAuE7ejc4jJzzkQOIeDLmFrZw8wGA5ISpfxvBb/ZRDot7iDztyX+za3Ie1GRyn4EY
2Axa2xPZbvtkPrJzmia6qLYZcCMRrCYGFHPf7iNZXu1A7sf10h4H9mLPrzicyN2Dyzwth5ExDyiO
Io04R0Khc3Y3E3IKKERT0WG364Em1dZolYRJSFr++mselrPcNW1uYdjruYcmEyHB+rH2iEYp+ppo
XoF5KT9r9I3AoeqkuNBnoqorNaid898LCpXq7bwLFf2i9mzkveJYuXN4TN3AlxRNu+c+Q1DGfXYD
EsGtjz4OnlXlg0goVpS2Hu0tSS44pNBzWHmhJIfJkGwaaXG2IDvWot4K2RtnBaIHkCZuFbXWbaP0
P7nXKVPfcvMqb2JUxz/fcNYxw6GMC0Wx/aRq0VdwWY90m+t7qZOXCMASB0V3sUHKLPFJfWLoQ8+9
8IiKz71gCwkGATz5n5mvTsLO3Z6xUH+/X02NjKZd1gSHrsWC1l4og+Yc15Djk42rqanhRYks6YwX
ck9VEKxv+pq17KIcm/iX3vqtwjQnYwU3iOGIRSNo/hJ6Vc/B7fVjvAskO0OWUoogOxhYtl5U6wu8
ami7ukubPWijKtoQZX+r/488WKUWBuTevyLsvjaHeqFq2oszeaoWBSaJMYYAPjc+4ICSIHcZGlmR
Z794Z/r1sXlNdKItLza7gs3CM7BEBcQwF45+KU8ZlqUAO253UsMZ6VMv2vrTIikFbXZjhvbjy5Xy
5iBCrbdNEX8Ib7ZFzRtt0vimXu9ZqTnow5fDAaj1hk0Jj+NsvgqaOO/r+zR8HVxwhiQIqczuKoS1
RajzU8jocqTGExqL2cuw29FgMWENvJei4jyeAIPOZ/M831MD8dmOKqTsUfLgafSgCWJFmSgH38E9
gS2HVOomxFs50+Bn0nnT6eUdVjkk8uvT/5YgjA0Y8Vu050OXy5p1P380DxK7nuBcRH7u6+Rd7jgU
kFPuK+f5JwUiXl5MK5t4eYQh2Fr69vXf74UzYWkxdWoynoZMkNFT+uXgKM2NKjNuoZPRtN1vwlDn
sZThAt8QRmC02lphNJeCihN900jswwmrOKIja6FB9kpmRnjhjvmQtWeOQySc7qaa1BqQgIE/213I
x8J8nFi+enyNMiHa8Ijlb8SWtLFxEFrEx18KrX38v4OjvdxW69ShN4C/0y6EUNmFBUD+aNMSWgyH
ASoAYBQY5dbnO5jQF0aDQI4iVxNHEXKTHKOfbXAvBKYg8l4dMWQpDZ7fDjjGLr1hRzKU9FboOG5q
uds2cpL+f3ghWwEro1jHtPJM5dkltxHgO1kRvCl9U972GnAOcaGY65S4SOKnMyy8Oq1sCO13girB
QwMo3KE40uoZpRFYk2kx1pbX2raHVdRIqp0uhD/S4aDlq2T+oAa1NC2z941gyO4+wHn4+XyURnIa
Q0g337YvcPNEMZXY4DD1v7MiUyDsYyMNr1ziLKcIH5oiU7I/R4gIE6Hfqsz2xSRmxYqvxoiZ3c6G
z7Lie/KWYcb4I6HCgovADkzuCzGHT7HTHFdyMEZW5C7v38ET3WI7nEDyLWf0b4tfat+tUHQ9XNp8
WeTrhZBJRUXg4/BEa+4st3F41O0Yj5Gmjp2J/GZXTYaKi9zGrAzGQMj/hnXPbcFEAq9LoQEDl+u6
BV1BP8Y2smn0fUMXF4QkaCLqR7edm4NAm2d8DWnvASSnLrA3RUgoZSczDot6QZ3pvuo2jbDc9FdA
h2XrR7EBkWMjjMaOw/PVSoOz4Gl7LGRritLkyvbmgC+WrF0rO8kISsSAsPKY4SRzYE2y5DTkh9/V
R+lGbpCc5RQDegQFpj59NmmZsCfJSfa3ORKiKAwq+YvdpvzhW4FR/6YKYDM6I+1LT6+1fLvav3Vw
1ZKUpnIb6CNDzapUMzw6BuPJcrQkTJsnC+1Qql5WVmfe6cY7ScgfsVM12fm0Ay8Hq5FzbmlX37UF
EYOyT9r9HibjBhTFLRXJxDv7JmIqLcBdzGGaxXlTohaM8XH+Z9/6alGlJb6dj64Z1IXaQr1WfENz
cYICZX5vg+vr3YX3CMCx8OFGsOtJIfnnboX59PMjjO4gTDcV3ukJNc6IZMhiC7lsPAXgVoQOAHpq
ckaFz42CZ9VQI3VSxFOqmgfxFn9cr122h6PmLKQcu9LkiFDGS/MbeuQA2vejt1OtIOUEa2yDP3y0
jVqJk1MDg92ej8Ea1kWeHOBDYZcrEC/1KIQwNzED3nL9CxednddMdXmJNjzdXrC7bMQPSkYfavS6
qoLke6kCpPXSXVb2CRwNGRnyjedNJynESy0yHZnc2cGWjKDWj4dQN2y8lizbpAMwJvlK6hd+Yrr1
1+E2en0k216+3reX9NvwZ3NJYzZ5LDMyFVhLDqTqvZUEeZ7xsCb3R2nUCTAdEVL8k0o9mmj5QVVz
UnXoG6ZhSlJvglGxBGX2MIQSkSF5DC3Qcz8L4irECX0rs4OLzVPHYh42XqU/olRU7S5AyU78FuC7
ntRReZ1QtLPNXTEWwlvcRuUeulZ9xFznagKKhQi0QKHuhHfyownLVXvU3I4B3PGeWTQ+bEKP41j9
4G1p2gN/lvccOSF5hVBGlTxa9yFoHktb6BUccLMgRoxvoJT6eODtqiK+kJYW+H6D+t79cZ3HqdtC
WZndHbcMu3fUL7eSt5EOMTE719BlB8W+XgCogV+sXNgvVgJA3QJkExY776H2Fkt0b/HBAlUodCod
xk7sp+ldDTAR9Lx2KB/TgXIFoS3WiuDVArE1yNQ9nleDu4ShzQowavyPYTdo/yaOrk5g2+LSHOly
50ulxJ/8YRRfaCd1NbT+C6CK4KpVEKMGr4ogbwIM6uHxh4S1ldUAhHHp2UfX5HIgkP7Zzcf/ZaBX
ZrmLhIlaE62J84vp4l4bPiTLiuceEedJimmJv8RvDw2wop4PQ8y7KzSaf0qrkoTYHTwAWgMGG+R7
WXTrh96Rr5CwwPeonxLfDHSw9EaB4FBy3/GRPNQabc+ErqZnlI0J9nbJuVXy7zEnYgfQ7B57Ns32
BUT1lp27nw0FBgbAUuiaT7ooAJ1FQAzcNpzFUl2udwMyaKd61ZngUXxp8oL6pv3U1nAvopr+WeEf
7QLYaMIibmco7GA4uuv9Ztfb+xVwm8llcGZPcnJ6vdLcmju8G6IbACZTMcMTmZ3cVW4sTz+BrwkS
mNzn5+DrUyy2c1l4tbQDrqdxg7F76ePumpmVIPp/2mXwZDCvAWwqSoFfBF84adpaiQmghVOyqLZM
rADx1RGB2V5+jmHFO+rxEQm2KpyrNIiN+VTy8dNUwbBt4ZV2p7Y9zbep9vmGD+lRHuWXJucSiSEY
Mgqf39UqXegYVUdmefWOozG7gt4mR8ZtdCcpQLt5U3YXtnfxvsJPKgdP7KcIEC22NiOADGS+ax+3
QwS4WHHL2UF8D7TRMHDmKvmam+grtoMJllFQDY5f2IUa96krNroaPJLpKxGaJ9n6vTmEXSsA30F0
Ue5MTnewLq4grdzL0UU2tXGCA65nuSeqGpX9mPLabDVaM0Z2FY1qf/Z6huB2/eSUtdsv3kQLWMTE
4b7YyxMo6ZVb6Tyfa83e5RX1B/0mfyilAuZdb7IMtonr3hx7k5xrxbK04MAMQHQkT/+80z6ey8x0
YC+JkP8tb1dWQZ+CN9DK2jZHByy8jbAjIqmr71N53TV2OUhTcKUVXxrpl26/vRK27FsGeOk5WypT
yvLj5wKTvdjAogpgZMSAdmheiraDrtLnrh/FO8FT5RMt0F187v4q0Um45oWYIKAjbKLH6E93+DCg
FTPNxFRYfUJqNP2Rs4io8HXQGwh0StpKBMixifKUFmcUPb1JnQ9e6tNZRUACP9uDtQyOdFfft5Ys
rQsWIdPOSf724ugA4iXqjOpjF5JBGRioM7km0f+T6qHXe10542yUgCCdhxJ4vY1dLAWE67K8SoVG
Q7xUi5uXjli7r8hc24BeGJSniYTIfZiPvLe9CG0HlXPTEtUhXMZzPxV2mewkZyfC8IBtTCf3qYQm
+dfYG0i/D2FFrTWsJz4Z+E85JDLPRtzE2oMGs7SR6sfN3r0pV5OgAzATUbQBMXRhuHxkGzuRX6q4
nWMu47iRUY3hJtYkCWdGsdBVSbN5ZZqlYV1C3Htir3nb8SXvBcWUWOG93lEsWH1taCp8lO1AZg6j
X1edG5FxEgz4j3rh6E8xdpRmeiNaJZXj9SV2yIYuBzQcw/4QwiibkcDh9EEbR2W8r8qGCzXiEz6W
Im8v4MlQRNkFm60KBb/9fEzpx8rbLQirwFwQDdkAXJT0cIsZMevnGSKUIaC009YE+3eX1eyjV9EL
4uraY9ktWbpBGhIKyua3U9bB62BgRDBPUSyGyvygCef3JsoHhg8M/PBpJ7COJgoiP1bc2igA//9u
tSprJe1l6biKPiOFiD4l4drAbJ5d5KTgeELdDawa3IKCs98Z8BlU74HHN0Vjcc5Bl87wfZPCjDuJ
/8zAGqB6kk5gCzHz5xM91YSFktQVmg2SKIHHu5Cux+HK1pLRrTfREpWDFMPwnhO0QP+LaMsfxF1/
n9Mk3LXIF4YoJI/prvXu9Bh+YTcaW7bpXDbYRFD/09Hca8MKCQF9z+KTKRBG571YB9Fmw95Adxb5
blfU7MJqt5SjnCDcTik78pZ8fMQXWUwjFwrCyhRdk7C75jS6p0Jn9xwm+8psQJFPerHeJgsKvczR
zsu+PYSPsvJydMGq24irDU/gtveGsGOmnPSWsSpeUuHOL4n374nw51w0f3qR3bPA0FINUwybCs7i
fXgeE1+zlADPc9kkvp2CGirluNQ/MQxYcm3rUnYxTfpLv8jGqzsVvzRXiJaHgtFXzh2evzeHoHzm
WyBvv5s2iVvkwmbpAnbNqm8N0L5dFDEuRI4iL+RKl5BcHKTJFEOC45MFgp43v1A3suQG98zvycNZ
mLcPRHu/mVSDq4/B2Jkzk+xHZdPxzcVF45dh9f+Pdey4T5l7KxmDz6Ak7dCoRli6Oyhs3IaAtkJA
A3+jvoMz1x3cLvRRECrgiFENxupytvaiNXWeyRqqlmj7zdMfYo8Lrlp/Sqy+IZXDZTMCWw0daSSH
AEz+1sKt5d7nrg7QrvySLxuYCyPXWH9zIifkTBqxJh8pUaZ0LWiCu7Vx/FpwOqVH2vXUF7G5qGDl
/4fNBzRFf7f/bMa0eO58pNbvA/LPme2eHW7GuLHMT7fC72AMf44yu71fKztdvAcnOeY5+qqfTqs8
vetY4HW0vMdKuw+4339J97slrMVv6YlkTnI11G6eEAGGj4SWYjqo303OT1FlNK2is/cS6yKeQADb
rtrGeBn0qZV6qiKOYMCgpASrkacWi3btZa1dG0dtvzwEuUH5Oc9ueyG/ajSCrbrnpZ7dJJQJp0Kg
SYx6MCm582wwclQwnlI8Cl+mq2NPyPXiE4a3E2EDx8PA9z5TJUDA2FIwsvKUcrTrPvzmgHBSNdtb
WCC38ieVyegNHvs7hlAGfWfg5jB/lIR6AosKUNFnOHObyJX8CEukYr3N5wj0pZpLfNoKuV1La0xb
on+Oc6XrF5zlMIVb6ZqfUhBFXIoWufQVUx21n+IGl5fLZ46yo9cgS8cJ43vI61290N5qXNMUgi+R
cdDR9xRzxO1r2HZuS5FJhAX5xjHft4N92u+AU1LgG4XsUeyLuThPStZYiDcXoR6faLgHezRcmEs7
nt90J22putepN7WxPfZ0d02WkiCMuaC/YmyoVilTI/xNqhwDkoc/0610fp9fDLixIQ6Gwp2Q2wbO
+4BL1HS+MUKSQRspqHSYhUdlSO3NzM1PqH9EoFVvsdxBdyALt5O+mhy/TX5WziEemyyXOmI81sPA
srdpOhYeK4B5HMOGDoTBjwQZFffM/9JB4PLV+6G/hRcpXcXSu7iUJtmzbNiTcq7Z/V0Oah4cXyna
6Fc6pZ3q7zQx1n+hGVv4ZN+E4egishxBqRvu3w2L7a8aDH0dnAdpbi63GO3O4xMW4M8j9rkUyC+o
pGp0gxrxG64oBKxeMcHy57/qg2kgauN2W1YiTiBbqGzQ+afFR7Yb1VfJryJoHIdIjgxQ1YyUQ6ss
+rCKnTbLa7HIKWjuoqrnM5BbrgZjXlLnOZt8dGz01nTHK4Knv7e6SAtKlIwZjJFzI0UdcwRTybud
ECx13ORDJzr2+SZt4dUPSVSpeUUBcT5lZHQKhOCZX8Pr9p6Yi4CnBF3x1DCx8veyGTzYpFqGTB2T
AzJw8pa6AopKobNuFwGmJV1lojPq6xq5FD7tPykiMpoT6qAo5te7hAlmb2/FH+63YfL5Xmz5swaU
oV3yaU8pdzwmb7BuDNhV8FuZeHoKvoCPEaed3/VHNyhQVoTOS8NowHe/7m/CskXQ0SJytSxRYXWs
SZmKaG6/mGI7kMbIKY+rTUDRMPywxMWBJRt0ichLCgNcluHwXJDGKZH40v6Q9MWKyxXMwYUBJPrw
FwHBbQUTAZ6KcMLyqr64EPTDXfDa9I6J8gwhojgYph/gOtRut6yDZd+scO/wY1w6PjJrfmWcZPds
CWkC3+MIpUsiXnzZBKOPumshpm4o8aQtZ09G+8fs3RGPqf/GgZOXMpkCLuTyzP0Ix0Q+0nEdBhWj
dYx5VMbZ/hrxspZqyoznoTRPY3GZo7iOW4zugUkBbuOXDOH8cWXbtx+Vt14TxAMkJfysS8P8byw8
enAJb4++Vjsb1EFpRN8Bu/OU1NFWCRsX2hnebKQJd0B3isE2E/IxzZtdD/9ZVjLUBNz1DXY9Pn12
Fz5n0Yf2vHtnCmaiEoF31Uz5A225G7fHP6BvARsabAbjyGd2Qulpvk60/fTw99+IY6+Y8D2UZJXX
D0LMcl9AXhOxY+VjCgeNc48Ab9AEjqh6E3kPeLqZp+NP1CypX1hf3XQNej9UfFa/4lQWcaBZA6eK
MdUdsZ26VKGefHT7mEoPgECXQUHHZMxV9+eFJn4MSSx3aFevY97FIDeTeuWT0/Du/+cL0Fwt3ioo
qajuV2EheMQJafro7KjqDJmwdi4RimLQxrOJbm/LOGaAe0TkePewbioC6q0H6lfpyzP05TjfKuqE
AKkXLW1rCkx2bPK50T8e76Pldj167pA/hHEmE/obfM+YVUNfK7YQsmeNy3OyQi9PiaD2mvhkA1Qk
rVhXAUyzDtyT4r3U9JfBHrnM5BBO1tVhIlxf4eTDWZs6SA4/mDZfArTKou6SZKQlOSnWFprd+Lkm
nY2B74MNaMkusclebwBfB9ywErQn9mU7Rxp7F/I7amlZ+3SgQLoFWILmQaNgw060aQWGjpcMc9RY
nsYmPFOSjZMY376CbhpugpsadRiOGS7i8gJrcwCkSwUIjoxdOaMlmZkAtXhxw3iZ2Bp84lfHVpdN
JmdULpHoKLbj6M4/RNfvxEGC8dTZhdUN2IUuc2W8r0irjnz99Rg0ibAKs4BgKShDVo2VYXhHnT2E
IDrhwQ/8WeOokslfQEvvhYcPpYhKDxoNC36xcQCo0GSETShq4+D3txJ1NRe2wR7k9kdAXQfmNCyr
m0fOQ9U51OnfG4TSRnULcPKhM+VMuQydQVk6rfborMHgUyB/oUGACSqLYm2jNX5wPPuzFw93U3Fs
gWlNtgG0dZZj46ELbb9at9wroPGrxUWBiG1Xy7hH0wXIpYIKmi8x9FRVtoAiIHf5HQwo+zR+JhwA
TRrDviKdjyusMolrm1kkLBPc2q37baapVBXoLIbslUHnpp8Kch68fHUBwUSLguPzHN9NHmZqqPJo
jVYeuX/XXahh51qHjra8/wX61wHRsJM4ir0Y266U0fm7fNnj5c0hm7a6U2FDsjjsP3mwxhj4g8wm
OTp0PJvoPvdwi1leVVJUPY2pxXTjMRKMWFFE6poA1t0pqRP7EKED4urNYJpMXLiY4OZItUV3mtIX
kgS34emZuA0zCN53yhRJ0xEsZ19H8R90T/YkK1mnwsftQQddbOyZn1KeLcGfvqhHeSufc7UTrsnM
kIDafSlDPsJMF+e4OGAkNk5YJhchCsHXYxdnEtB2NJnAkJogWjek6lnJYeduZEYiyATDxWQ7UEh2
85RpPWhWRN+UORfDXsjbGuwqxL9FaBugbOpaCNH7jfRU/CKGakW8giHCGHKLRhG+Avm9GekSgN9m
6RQwNW6f7kuDlyrlE67fXPPujz2BRQ0W57Tck1hX1fUksSGQwyBNHAPfSsPGF7LcJyr62Jrcobth
WJNwaqg4b2qgEnsHxHgMhLYYwrJJFU373XB+NBZMSzWG6IcTBuQPBuHzYNbUz7tqQmK+3Yf0AL6p
A05h3ViKQRq7FaZGn2xVmSxJex/AkM42a4OJ/ohm63E9eiTDcBBMcrncdJI/rsqL8P9IjrTnwJpF
lYIp8CkzRqxV4AVFlYS9GaTzfrptJPT4LMnqJqxeNLQmCLM8cC9Oi+r4zmaClWYixZkBNzsqKgOC
k8CtKZTMlc7JUPgecncz3Fw5En2LwH15rPTVjsF8900HjeYcJenIIKzrKl9hr9GBQ2cgcOWBrSfj
NIXydf0RoC/TjmH+xR4DjVjrUbD8S9oiC7+7B3BbXYZOaFSoKJdpqm+dDTwIo7RS2uz/AA150u6c
Mb/zdP9LbBNJRDqrq/zj2fvNZyFUyoK6XHb3arBkVUjaPVZwOpP3eYx3tgzLKKlKzB98FNdmfSnW
ITQI3dhmcPisCBbR9leFoYU7Y67n58brlPdN/cZlzKfOTv3Is6EQ5CI3yVpJgagKxPmD1oKL2aXP
agI6Bgnf8RiVDun/tchxb2ZAUaFhPKRdu93tpKeDiDrSNS7ayPQ0s/ug3HQQylR9yg0FoD3EOAEI
qrVpFizBj8EQ8FMAn8ANTs5dUKAcLUiOS3GNLU/cuTrSwcsTbHGfoeEmvyHQnnDiPDAJeO5mGcQE
D4yISSc9woYwWNv0aHZydbgJ9pSOLEN65kJpeA7NATU53EY37S/5ODr6EEVExkmRL5s0AvxoI8K+
EA9Cu6vCudBx3Wcc0/eIcd8wdExd/xGwmgt4NtyqyiRubrjcGjwvTFQElEBk9YOTfgtTPjWtwtpH
kjJEwJJkt+8HWiNmsu8Owy8+Cj0brlqrkf3DpNjvoHrk6yoBJJTnNbLR1htNFLtYzCdZSPHAEQHB
WqDBl5dM7aLwCn8pw2VMdZUNrIp/PMMbgkefvC2GkRNbuvTS7Txycb9zJ4NlSyT81maGVrMz0T33
k9EkLbg5i5rHbL0Hts8l6Rd2pAre9K9vOJvUEwObqVn6tnuy749K4V2JkBB94Ad0no59K3/UyexY
nzEVVgfwO5V8eXdSB6mXQ/rbTHl9UJeab0gvmH/gKxOtg/KqPNp46cpcpYmlw6eAHc3EG93ioSi7
A+IPd7nrlv7o76YMrN0+m1TACVMNSvXsphbDVEK1HF79dB8LWxyIet4hsL3Wzi4im4nUDF2fzl8T
8g2HvmyIEE6tTC95uaCM+4gHCjz1S5TBtWF5NQkDc21U4J3/RO+1eF/wXkC0cz369g5BYApdwW/o
DUOugQnp/7Yw8UeOk6KGxCSa61pcR2SNjQFbbOFrxh9jqiRXEfV6VM+IuTRfMhpu7wQV4Y69V+p6
vNYFy5uI2QHOkT57BtS5kqNrQvh5KOeSnnC4eUt/DgLAAZALhFxGlY1i5XlimExu4BKnkhZxksGO
3+jNgEnY8TEvkhCtRXQcHypMyT2b2svCF2UIX5GOpaKSIyByv/virFe/0SldYF+7hY/GaliE92R9
LrWsYKBOerGUPjLMEDt3cpeXJREExmXSC+PkOYW3c2XR+/pOQMRp+vhM8WoTSatCUguu4hOK7fHs
/RwHaRaXVJPeCuTfl/6QEl8xEInqtb3MtLX33UcsPkNVHZTkLSFl2aCG+mbVbTnqSL8p8EOtazRp
5cRq1FpRWoBdBxXE7DRokVgnm6gfaMiiKwV6NTB7BRlULCxOnMSN8h+dCRoZb4lMGJxKf5CaQf2C
BUEoveNnllPEu1sAkdRXPWIXtMy980fDvi/qA3gqzg57+kUUropaRKvFCKCmKP011AIkfhcHQNBB
ZvhWmwI1N4U/tOCcoKmAvrSW0JUg1c53lMJzkfiOMz0CBwLjsxahRoLKaGBvi+56DMXY0NuxSapu
E8m8+myAWdp2Rj12j+piYib0jQzKF0MV8fEgtwBjwHtIz8mJ/2NZX4fTexoVaKljEVpqUnzMbvvA
ThV9xi2cEpFJ2OGcpJMGSL6WJBYBlCGxN3dPOpGEirW/sjgq/2oVcIaW6HhSjsMdAnQygc1yL1We
FuPQsy+3TKAsIjnn1TsZOFuhqH1KXmnBSSRs45VxMVpNO2ftLA226EA7PfACAp3i6G7mfw8kkdO/
/IOYtLuONxchI9/qAHrI0IBwLc/TjmHbJ/p3zeTSBGVbeRyKD8g6n5FgaKPKTM17/AnXB4o9VGHN
dfRKifD029GT5qBXW5umQ222huJawT4ivMdEnHFitOkwghC2YyYN+TTVR2FP0YFlHRbHfk50/E0D
1rnahowjmJ48DzOuq4dbWXXwJtFON2GZQwGkPm1tGHWivzyH4ItJ+eOOP6CU3/ZftrlMiIOnDEBE
PxxOnt03tZMDq59bTIFe3cEZvpLo3KDc52+LBrea5vQGdmjf6qzlrRgZml/YNt0ktvA1XRumtAlM
ioQiIy0J58o1MKvlhdctTtSzM9GIdd8qaiIJ/gaTDfNnB44g9Ig09AifvJWolSeQmZdLAiXTM6xs
Kyasr7UzZonP4lhEgNYNrkhWZmorfoOoo2SID1yjI/Q24WJMn3A8SLpKclAUD/Xmw5/bfOqEe/ux
ar7WX5GOpcvaLbjM3RYMrotytLdTP/pr+f29RiIANopXMqqD59yd6QY28A4Nt7uf+MNqY15g75RP
9pZhfQn8FOgzOCtFV7vgCc1sIHN+kuKlRp5GfRViN0wkzamaq3SKVDAQtT0hLIA/3zgqQ9sZtfhD
SuULWm607rp2ZFtV33xkBcLsEwnoDZELYmQ6B/qVzwAzKlc5W9lbI4E8YCGCfJitP5lfJ8UVi4CU
X7/buIywF9w8sS1Z3Xb9HJcj0UgewodxfgzNu+bFpyWdX0hmD7lGXfOwbxZ6nN0FR7i86NpLiIH7
0IO6hCSExiKZEO054GrT/XReIshfWnkV9J8Hli4spK27lt/nDjj2dCy7YgjYGw540IA5wJpDXeLw
ISZ5YEV4NEDCND4Qqc4gZ587EYjpoJsEREqwuTMEGXrzAv08hYKEOL9yokmXCWtOjhrp1O7i1MA+
U/IxhPMFTk3Kmg91wugA9INcKHjBRUUhzkE5gps4wEM1R5PuWLS8PISRHN/xnZm07cK6y3KkcL2O
/HJVIhdwkQ/KLGJCOmTpxQIo8h31EXYj89BYzXtkNpr/updosojPQpByyj41P1rbt8LpGRDRm0QD
VhniSz3bt50K1sC2aUVePBKGpae5P1cxE1TqUZZRwIkMJKoTO6JTkfnsaS0gsnJ2T4sVrpKjSEl/
bOC4aKSeIQmivTeWvWoomi+piNzaG6WPdd0q5aa9Wnv91inDz+cWvbbzygusgbLGo86X/VWdqUeY
lWov/+HU4zWT7duPknVFNfIe4HH4PQ/yEQ5N+eaJ3xJXlQ9hIYkaCms+ps8m+KEHDpcjuJy4BbKS
vH+FgCTjrBR/TVBvXjq0pJvSc6xddB2sYYvNTeb8r1L/AR2vxBar3WxE0EyuXTQLXpEIC569iiKL
XBriffU1b9hBk7qjvjvheZHJTW1sB1NatMw8HH06LMMiHJ7z20zvor6/KAaZZ0ttsIft8Rp+Hk8z
9lVxumVdvg3NR5kLQQLC8RvU2mCWkPPgdK9JREDq41V7kBQIspR+xESRN1Osqzud16TlRxlLRbx8
APmvF7v7J/yd9nxlRgjUtsQ1KjW3jaXrhrLLzg4lu8RSi5iXSmbRFkYrPvlCIQnQJYU/evhLIftU
Q8DTQpL4JYo6qYBXBpcGRtY6WoAYVOWoT7HQ0x43ZWV2G5u368mKWHXdyP0ljIg9uL3bqbE/3l+8
Gdl0CQoBYrRL2AHOPsonYn27gq/mKUJsaHuAc+xXHV+j/6PhWHlG6rR1sPrVmrE/TRjZqeQtRdQX
gf3jXi9U50TjQTK/uyqvaNHoTcyiWI6UK3rYDi4WQMvdxQnAvHAYZ3bJYQA4fDjrA7c79bEX9LQz
TtrY0HI4di2FCIZrH7k/juq7LHxVYyEJblIsp0jrp+ykpC4jrIOrPQGHtmpBJZ28MLpNeVxv8MDJ
cVGSV6IlGqvhJizBBWXt7M1guEPpiqFltXvZtEYcJrsTWftY5j+GkpT5bz3katIiLhsFi/N9vZMv
tlu3D08km8IXYJOMS/L2dB2uabv9oqklOQyRbrjU3LhhEEAaCRnktRdL8os3pAzoyyfLuKXsy/RX
NiuZWlXV6AhSOZfuqGzkSK1jvKMLdDv0ru+A6zq6zFBRMbvZ3dS2ZKhPrA9s+WoZmHXEt5eNtXtn
zrupg9qmljxBtjV8mfd4C7842eIjFwmQXIe/RVABwP01CDiRYNnYtojFfHeTcGEGY3EcUumgIDN0
7QvRAvWI83dHpcoO0RE0ki+TpCNMNVsZ9lOq3NLDmiYNQMYICxZPuX0EQxmN93wl8dCFoGEak46S
qQp8wzhfpmnv21/5R4wlqLd/AqN+oHky6cH4zt3VSYFetXZfrWUD3YWB3WWdEk47Y1/eHFB+Zw8E
DCqpsfxzXibFn/OdXzWfVAD96LsW+6EGYPVtYS/HFc8ljtvWGmd1nBZktK5OjVyXD+Scs02CKRal
baH0xDTTr9nHz+Tk4LPhOiiOIiIutHThG5nm7k0HaWvdbvjD1li6H6X0TQmOsi8mnu5vfYlIF/6Y
hJGDdofu49WN9NhQ7jJ8N7K9WiHxz8lQTYaS9n9k4nFRlSHB9e/u74ZxdF1brIX8wE4iQSjRE196
7/N3LviAN6MUynAL/xPDabO0RPQWs9M2L/etIsut7n3mu+Amu6WPvOmKz96Ek6FlDWyaluJJAXko
C9JQpTmIXwGcdh1TMg2exlL0yQf2mKmcbSBOPKF7uujr6UlRJ1ySgKSzWj8abNqLZsVvI/xNsOdo
c3Yclp/BtylcKkORlqaXGDdO83VfisrB7/0QyjWjD4Zb7TuEL58tjrzSQSUdTUQWEq9LYfGwYs9m
41yC3a+T+qUlg7p8CWSpqKLwZA+QUVlvvb24/mSMnH+1q0xaFylGylMb2KC726lN2IfgIWPgbaPO
hip8i268o6Jne8N/46RaLHm0EypwZzROhVySBBcNmZAVhmyeH4K1jSpSvhxdifgsWVvbX3zTSo/J
k1rXKF4hkqCombmsBvnRyNuB4baD5zUo9XeTn+U9kLiiLb8qo35MXnru/QK1Cyk3G/dcwOuNUl2B
CZVabV5KLax6C3JL0cHmY4bGkQuI2r7y2EtLorj5yFzKYy1tBgggSuAnuAQYeMLDGowM3K8HqCwu
UMxGMHoZnE/CDXb0oyFLCXk4STEbsCzTYREjffwjfFICJiIjbI2njiXsmGQX4Kxlgl2rjqE9Mmid
KiefKUeThpDx8qCibh0+CHQT+qNYe8O3QkA1dHav9sOICRW9XCcHuC3VdjGM6oXQXIVq+q2M7gfg
tE4Sz3QYsAUhIpH21NIZB2N3mYbElmyV4AVI1BJG2ze9s189aquw3J8LfIoqHTipL1yEeJAigAUy
wVw8aOlBPxcwEOMJEQnxZEN4DYPZaEQe1s/kNfuN7XmrzLz9/N6NcWSw0BRuqWMYEqIygZC4y3G6
hAowAqs0EGoIPUnJbBp0+o2qElDLb0V7cyaHljEiR1QI/UrkAGeyjMgjUArcPF6yLveUzjO3T4Qv
XIiE0jSt+Hqyp39bo/ySi4sMHDHU/64p2XQW9yQ/YrWQaL+sq0nGrIWGlczEnDvRLAMCLS3ikzCX
oislXashkI9/S0RM1NA/35eChCn8LocyL+X3gZ1ezOmGnzefiJ8m5CwP9Vj/6QkaD2ix077WdQ7C
mGUmL2mapH2XkJtlTfoRxZZyLFhOa4qwa/hkqmzTke1Iw9fujAfZJ+IYTWJUnbIBDn68/5wMmNLC
CTBmzCGMtpE9k1gVBBMj/sdMOT1ZluckL8av3Jf16qXCN3PxhM4MZPkMKRQ0lERjjKAhRuHEVrJC
gS2FWxF/aeIxk+UOyJQ4uspdki06oVbAd8STeFwVetWKXBMJ52/rZ4FwFrL7cn8CXjobw1qJnTO5
e3t8mSGM6MHU5+ay6cBptXdihHVjCT2j3eJUr7Aq7sm/Ebl3tsfGPR0CErqHbM1LzjWkUXKNd4bH
FpgjIuRhX9DKyaqQ43MJjpYL2W5r2nrgovghx5gifBlgkHkkaGjhc0jUikyFBlPmTDMAfI+66Coe
njtlgSBPL9kvGseBvCiYsUfYIM43aJRYy5lawY1nKmH9EZSRmpnV2XJLyDsgcJRdscaBds08F+pi
F/As+Qnn6dbk+bWNXKQKg7itIY/msP7TaL+kN1HsJGoaXYPLHDzvEFRCQWWaxFGqdsgWdMTYtfEE
GJXm0pCRaGVyQ4wni/XtkPK81zSmLKUY/+dMPmGfl2JY0/3OJaOzq42BNHDqZaVfGtKP6F99GNi8
pvb9eeX3HZcgIgyxxR/BOdyabs9J2vUbGjR0qUCEzFO76ksKPJrCwiRALcYbnfDO9OrqDlnHFV2y
rxjI0j5DAgx+ONAmPdJ2ftCDEhb1gmsYWLcySdGbFuDXiIj0zd+9tnm/WFnV5YygR6gEF9xsAMoz
3IXMlQPTE84t3V9UKZO+VjOyGSsa5F1zPdSpTO3xRWH3MtZPCppX6RHRpL9KZyknYUgGb4VBauqx
0vzn/iqnyt37oARLsMSJNyLgCOL0BfmbJeRX0qfjsaJj87O0RGQ9O2ta0WgrowJzgrj6isRFjZzb
DOBT3fhevKW2koJOWVXKufGakGZnV5UYK9Zm9H/ibDeSf+K+7583/bkKHZIQPUd8ExS5o0mXUOeA
+D5nqsotku20GO+RLs3NBOGqXUF/74qbKBwv79N5u9yiU5bEIDCWbU5rpsJAzoFd4IkACl4dYcx+
9non4sAwWF6np00M0gjOzB07hwnVDhimUmt5ND4NfoJCEK928PFFzR8ZA+QVcyS9Ku1XyfVIjDOz
WfjJkqpCaX5MquLX3x0Pa0MmcJy3TYGSBIeXcs1X6Ml7AUWto44S/o+2eKYknzwWD5SaJnC8Q8Ew
9wSiSlzR711vtdYmyppr6jTkPYmLbqxUxkeIwKmPyxVqrnw2gNUa7Dbe6K+0OqCfIV6bnt+Aj8Yp
ecJKpGBMWq6bP5u6aZODgrHuQJRx7HpsqinHbYQ3LJiGrBPknI+q0aMMRjgD6e5JQYD8IZDanhTp
bOGAHr1ubcTSUkJzsZqHQEMnI4LpDGff96le/Zkp4ySjAEp42wNcteHqkDKWrjzrtw2Oq6cHqezM
efkISE5fUJXWwphX5jPehyU3C/hWErcBA/9sMraX+eGcMz5y4F87+L/SKNzHDygOg8qC1WkHRxoz
z3eN1hoY+7NYp3OxA3bLCQBxkjm91NZ+34Yie7GlECnOvkwJzLEsmQI2dpX+uHF1s9tJ80hWdNmc
LtGpHUiG4wvMz9cYyAOb+RVFfodGdqBKx4Lgnf1phxAr6Ba88Y1OIeBH/PQFqDVABBOPVmaaSSK0
xSziDrkar0JQlxXXeWfmomlhQ7Xhwpi64gHulCwieFbtirHG5ycL4sqQVvsTvYnziKIsRJS+5ewY
v7Wru2jsdfiyUgGJBfiV4XSBLhtpOqOrJomAFGXmuXxhFn0n0hsBL/yU4clOmSZiEFzQiWaa72bD
PSV0T2pxXSHtQ4TqvQceI8FBLxQtXM24ew0Ecqns+eM0w1uJElh8BqLQ05rG2CMHKpuX6XaFtDxk
Pn4umJluRFVMKT3ejRsvVmCd09z25mRNIoHzesPwMvvIzgvfi6dxja971UBQwGiWSNvWAlioAjKA
+K9fiSx/bLUOOR1Q+RGTjXNz45QD6Tl7Y9BnHhNzrXN1bWkfnGJy4X8i2dY1Mmj7j9+Nz+aSvblB
RkNwqe30j2nGlLNoP2sEwi1xrmApa6WIZlSOQXiKYvoBA2G+rID99KTS4pFkqjao+g4fUUSfcoX2
MotZa9UXrTHtL0sNxXl7YN6C+Gg3zSEeCRkb5h5+vk+WZSUpeyRZ36sN07rDVI2iQTIm67x123Nk
rVuSHLRwSi3ot6ZCOJK/HgaGH/2DUTnrxHctUmnp4CzAx4JuawBwbH1lBYLZ/BPXIGMw4YPnJ4FJ
vr6hVhnQ8G5jkSL3F0jUGt+ZvUSWUFqG/Rn/qshwkTCtG/5SMNjTyNNBuu0Y95v1G81MJ89csmY6
ix9VlsqPVZzQe6Hp+hBETVyXxUBJltfepz6LghFfDfeaBNJ9kTgtUZ+ovOWWbVOL176vCG98mVdG
fst9dUH32WTmWAvAsOL6U5HchAS5Qzc18cMsbjv8hd/8HiaL+QxG9TWsiKmw2esthSZDYMpUWiy9
lDcQGrxQKlUvLY2w+XUTybRJ2DyuQB4PX7CsFbnobcq7//8rx/L+yKHLvBYDtl65IjLnL2aYrovI
A98wd6Y3yZva7ORs93XL4LgxE7helWOZLaF5kLpb0dnSxL4l56JAj9p+YvdPi/c4420ZIy3VNEWv
a9qX1QfSk4PBVdZnkD19tLQwvZ9airaoe8rXps8MSFE+2Ssd+efwfG84UMD+1Zc4/qIT2ceyXbRT
H7ij0xCHwmHYO7POvGli67Pda51WSQ2GYEtIlyj9/il4JbwMw8YvmkOkxh7ai9VRMjC5I8hoZpab
ZvgvFDDuu1hEiQ0MSlZ7wAV9Msvkvptc6yZBJQkKQEna7hwtljxgBZbjZfNWnov1Q2m3+gl53WrE
11Lr1wNXY6YeYt4QPXcFDleU7CBgCh+9dMAqhboXBzvMDRY77i3OpopreLlwIqRCoftSfjPUeCiO
KGpfDPfEa2WYtG2dk0fbStBFACtF6R/hiR98/ejrXE2lp3xyUeQpZoThdCbpxkjFJ7EiV28HlwFc
lCWCisRYdD0QjX1ih6m7fnxF2isrBU9JlT1/xd5xHb7L456buxWmzSupx3ttUWjpx0TXLSlvLe4t
kTVYKtinX+A0vBiBqg5YVmXkM5pC1juzUia6CVaX22L7bfe+KQFtm35De0wU4L24j6UbbUuMPbzX
f3R36a+yn96v/QrsSBxApy8YsVjtUnHfwxrrK7Ob02VEJchoWAEMi3QTo85e+P9NeYfeiQg3HEar
719OrnyYkT+rdhwHS+DVVoFNK/ZgcbjMCvdkBJNuaH3gHyVxF+eSURsQovI2Zt7TmEwicGkLETk0
d+OytkdUEt7oyG1wd5xP24mm/S/97u5JQN3msYaJLccdK4M+O1YIo0gLpk04K0kZtbb2DBfsUnoq
mFPQ+XRRSwBh5mJU+YtD7/Ve/XxuIGaQgNe6sQTPCZBb7Goz9Rvj5RtPrRG2osoYbIHAXVjwgfkn
PgmJFb1e6tOH1/ZUataPXoL8IrqUWZCv02sy4tYYxw64nIrQU+I7DYbE2O7FTVyoFXgnBD9oj2J+
bZss4mqMel/1//rGX7zacVIo9p9JaNK0cQ2sh6pItoR73ssqEayI6L3Q3XfZjwMxfuBQ6vhbUmbm
KGxNLXizwPMTV60Wk63kbud+6uMO1hxw6wnR2y0xUDxBNYwTnIUpZJcIqcf8NJBM7C8uJU7uPDEv
W28ieBqRVtnN/7ozqJ7RjzhIwhhZTMknDqgK0oCnz1h5Zr1bLUmD7zxR7wxBYYnF2LOAqm3XXifi
oEz/se6ry2q1FZ5gsYsFhpc8mc3n9DFkCpto3K9jHcU+fezybV061GPpoBVpD+DJaGCZXmA5HmbO
ZWN8D3UETtogQk0FUy3+Ltrn4bkLaSLmxPllGaQlSaaK0C+4FrIU2sM9Sta7N3s5+SMPEBxoS+rc
Bdh3w/vSYx+Vr2MM2QgUCrKvkjx8cUifXfcepmsK3bB/O7MwRmvvHvyZWV2Km4aWbKBwCZq+xPnc
hH9TMNP3HBq8GyhAbBJO1Zw3vIxxZmOAZZZ787E1TOqwJbBkEa4uJid/+jzCMRTJUuEtRZ58fSU9
1bBbjZd7w8bgaPQ9sflHLGFhLA9HuiQDYB5OY6zm0KIQoNn3uG2YHd9iRYgUdfT+sgYcp1j73boO
2boO23t0y0hoxM3SFeMpcq5dQYyJZRXdgv9CY6J7X6QzzLBhPtYZ+mAMb+6jKD+rmaa43L+O1ae1
H1J3nh3C8dJaEadkpgVHfydNYEJmwLLEzERXJrLy6V7vzngiObBjC60wqZqo5IJG4b9DLn4jflHB
bL19OtL4pWG8ZytuehxfAYFUg/QhnWgO8pMQkQkmysOLm1lKd69fTEKx+yOzPQ3EgxgUFazG9Xj3
Ezgf/qs2zoJVfECqw+Vy0xv/0KrNYBxCcn6InfxkFj1iooHEkB7Pfe7vd6+97Pm8eVWvtvCoAzcV
qVEA6/u8t5LgkWiFgXaxOswDLs4fmHd7wQ5Mmc1/XRDNVjFZs62/Ll3cjTcu3iTcGQywZgpRgT1P
2vMAFPm2rGLet7aaognw2IT2s20YZG40vxsy6aZhC0IchegAZZ0bF0n9t+H83+N5+0fQSrMXBeKB
lQWvSvXlUXBua1a7FW3ti0o+C3y2qptyO1F/W2wOKETFujaeb8FqrRa204/LpiYHs5ybu3qEzqPC
8QNFCMHHuzCnnnFhcfhWHcfcjjtzp4sz42oygIlGoe3KjCzGgwXBqTMbB8TLMpUhiwfp25JqIk8a
k7T2d5+acaDvN7P3nDLVXfeaycuvWKUGDja03G74Dbf/xXOfkIrADDNUf/14CCZ+jEmAT0HN4au6
nHt/YsWPjIYkkgY26VJpkdIPvy2i60F/e8kpzouvXhZbe9xezn5hiX9Tnej0NfjYUldHKwVQNc2Z
J2pzaxEIZsBqe05idbT8EIV/qE2aQwWLRYCoLSCqpE2bP55L+Frun42bdpCrFipNy8fYJxHOePxO
V5L3NVDkjEj0plr4mQGvQL2t9qvws8pyNlJ1Hzctz23u0OF6PJQH0Sr8nLJ+rJzbHcZkqhXVyYQF
HVWzyuJNw/HO0tEkpSM2e4GCEE5ZVLUvb324StuQSA1WEF6/AfVoouQ1NonZbQIoeeDo6kMl7k7V
UhgrOM66ZGdcIJPeOaADccrjC41s14y8AYIbk9KUm7FhRyIWXjLAqY40xND8DMi5H41bGJN6S9+8
l4fK97UcK3nOsb3scrxIif6XRPg2OPWGcCAxyI4NIuVmXD0T+4wQNxRo80u9gLCEwNk2w6wrInNt
wMnK6denIYxh9YTsaICG6hDnt6LO0xrTpzJeYtfehw7qQcQGaphccfSSal1wVoqvCYLp2NgpaAn/
M62vjvtoV5F1uYxDPLcpxX/d6CRBL8pIEWViyPSrXdWfT+tj7pCzk7eic/U0NnsYTH0e3e0UjpoN
3YQdfELrRWcLQlMFvQVC4qZRsx7JNbvNylp40LDcLylJ4IJ931O0dYTUhmHwItl4gHX+Chm160TQ
M/KhW3FGay4zKVC9Tgk0ItbrdfNQppS0mLC2PG5pDZRmhpX77V0iXHBuEZA6KE8xhpBAXnuGm36o
bgpqlkydwihUpxvIzA6GrfgyNyiBsX2vJR6w62T4GLP8bsVGy/1z/qsPhZONFq/SUZy5PdJdLIAG
kYdgzfE5o6nYVRfSKFJ9fWePyuVYkkboVMTc/3uFyhhd3+9ZYLUoUtZt/PZ5t5HI9n84GW7vnp79
JTQXegq9q4WDWXIMf9lEQxQZ5SRuUXlJiw2/7eLpkm3uN4rrhja2mF36IWT2fRKv3LxiBpaVRVp9
4XyjuJdbeAix3ZnN5gaPhFxOqlrAn/5VTBADk1jixdJqjDP31X8RVOzr3NsOT2B6/RcecdZGv+Rf
kcJpa/I7AmnLGueHzqQ9XbDCItFLTuf2cUevWnHGWvCZz5YmSnrsecc1EUj3MKDhpFOvuGhoNNar
JZimuKkurzQykl6FoDcub939GkQ0amOv7WxF2WuypRXpV+nGsrdGv9jNvY9uqoLsRQSkqZtYMpUM
IjrkpDr4V+pbT1ARqUnZ3rCZPiP4kMq5G/r4WVs5fGN6BBkf8bVo8mDwSnq6OVFujTe+u/KmYtXW
6Z/ml9y5Wpg1H0pAWZ1p3UojkDaSnJ1prZY9kwW9Qv9nvbf3lEHsTlQ86I9i47D2RDv3m4n4u+Fv
Oz0vSExZd7x/mj1/lrJOoDiXsDnHheFA9Y2vmsuZzsgnxgSlocRQhCpsLXb+sYqNAcaAHq6tjd7I
rtVidxPxkQFD06Yx3DHpQLgA0bQT2C6+Z9478pyKEMKYfP4hpp7G55pIHPnfZA23wmkCvjS3LixS
D7KuuqKWDW+8+NlJPrU8UzvxDgkNQX+M3y1bAxSTbj/0Ch0HqS1dvaZL/YvGg5MTypT275Ptnyaq
pFSHlZGmKwWhf/DT04egQPwDx3Pi+dYbtTi+5TEFWWKUc75FJYdQyewVyd21XnXvX8nk9EjU9a7r
xcahZJXDx87vVJ1re0V57O7cEz9JidXPr5picZvY6gOPh7wf8JSHtBBKSEfpMFgBpMuqHuv0gnDp
WIlfATILvjjwyihZnnLUceOt9FLr2DeF5Q7TyPbeYLTJatC/34ebA5iUdZLs6gPUbdks5NOoR/5W
oncYuPq92Y2Xk+OEda4iqKMu14UEEgXyaczviU89Qia199S54AxCieEskzVmstBocsZ4e7elAoCT
lCUFHr76dieSww6nS1+EmIsgeMjFEqxm88Wiafpb1x3c7R8KytUxeVdHg7W7n5Oj0LsDFNxeVGOl
PbmjgfOAi0LASl7IzpsG5Bb7pm2NgQWVrkzYcCyDlQ2wkBiljNSGtlDImNr3S1pjDPvuk1KAz0GH
W6BnoY3ww7QDyZIHPxmLqgzJFrDxDi/tGEpyJFcjnw/r9G5YE/D4RHMg9X3aZG+V4sWqvpkuRUDe
J9DONKT1A58mTG3Acgut85cPdRa1+bdczHwyI7raHAsGlzuJ7gHqcxdpFESPYP8xPpP/SO87cyiN
xXmTAzQOq0XA3eKMKEd1O7ZoB4tHSwbCBpN/dHDioe0pv5B1GWCtGBKgUvncTojFDQMJDCm4WLb0
05pbDxVW0Z3nvVjq1QxBLxNfibxD4YlOi/xGTzzbAlbRBRud+zcXtyjyGq8kCsYZJuCr0KLX8jFc
EQ8nndWv0BuaYnN+t1vYpV8+783wMXZGovHIaEMc81Au6AwY98xQ6UToLMCL1/Bw2bbySxy3BKPx
pO4IGs2NVGRsa8+X6w7E0LHWMfd5+JqQDNBlpYydYhuq0oTKi1wh8B04W6S+y3Fc6el+G+yRPy6I
lrpwlFO3lQCYJ44v1h02mCBcgUUI9hmqmN8YMpfdDKq7En3jRXQxCOiUWHzoREaFkA+5XGXnRMnY
IsDSsMKDP9JLflBl2IDL25OjfnhZWgoBvt5mXMCmS7gUBgaeeoQcLPs7uuh6NH+S7POW3TJVuF19
pZCqP/uiyVEfGPgwYFSLrpZlovlGmhnq+Xb9e8VSONpm8gdMIz9sC/OZ2mcWJz765tC6CaDStWXP
Ax0Vizk9EZUVC0HnfFGDmKVmdCVfzFz0pR624vXMf194O5kh7tpdPhOZXR7QVAPTGq+JeL6Vqdiw
3X8YoSxStKa91TAOdUXiDmjxj/i6FewlS3KeNCQc3ZNGMELBc2b42K5nnB19/u5bSmp5KLpL46yw
r6Ksb4FflTMPV3/WjLaikjA/q2ZBk3aX8HaZXi4RICeytiBCoGKNnOqoFSq9re0zMqRQGxI5uitf
+V1+d9R6klBwuU8m9WGa2aH76ffZSNPzUxwnwcj2WUkE4Vi4VAgD2zlIp4Rb+eE0KKIq0OU75bk0
iFFLeWn9HfP4oGpK0fqQhhck6NZA2GU/ilXm15OVzHA6Th6gULdkanIquBMF7fK1qd5QtQ3J3pj8
35DnSMv5971xqYQfTcy+QLZb7D8e9xgR5NM4vmylR8tXteGhTR6C4Qs1UcEq2688/kK4ZJ2VeA/R
uKFLVniZKKtd+rz4GbwozBLsRDuQSCZiY4cGfP7N2Fym6fWugK2An2AeU8wJw3zz6d99iennc35h
Q9sAuPKy7AIz8GHhDhWdy8grV2EUxUVT5pY/OBndsRAnD0I73ZjSImqi+WIlQ4uC+aYSXbSvoIXk
1Zn+1eI6kdMOXf3Mn7n0OMKB059HU6fuEv6sVVp8dwbOyKVRCFYHnhlb+xHeajvPpciIGzdtGk0U
TCKtzrFWkVkG3+U1XJpkN5dSJbE3qyyiUqfw+KbgSbe913dJOHB5pUNo/H1sLm+XBetaUy2Gm2+l
X9d7Fo4rNycKAJqysBfamGRGLnozqh7SAD6fGRZw3ZyDsabExs87oXuC8tk6ZW5DHuu+m5tug5qn
9JApOMQWMSpkK1xMHx7w6NzwVQwtpD4yqIf+vDUTRptLopGVJY9eUXlS69VcegI76PAZYnYP2DZf
Wk+2eliSjAy4BJA/GwB4kz0J+fEdcD6FdwOydhlFUQJFD63BJVUrbdV3SylqigEqqMFuunRRt2mb
s0ETIIxF3OaLspHJTI7vuQcHNsVpCRCb5Dlx7FLkIGmLrMGegoYNuwZ8FF3wUkNJ3Erht8IqTvXd
kyT7AC1N4ueVf6vEFMQppx6J1/uKm9kc6YsFC9wAaUdXsd8ZFmDlVXNPJLM2iuwL/pnzl8S5B2f8
wjVwFkYYrywrn2JktLfjSs5cARKRLDN1vddiIwi4TyDRTWTv9HgCqubN10dApHNJoPZVzG9IcWSN
8Ov1acPRxtfoEG0vQ9IpzfEGPXOXQ051UwLo7C1p/Il7lcdOPqZghc7e1vbm0/oHR3zMVoAGVlNg
HkYp7Dl11AajwFU3JJMDAQCfzfgsaPyg5/EEs2lk1L4z8l6SQ2b4breEb35/nGN6Dt4VoyKTitq7
RX9kd8Kcn4Rfw/Igiz1jbLpveAXFMkyEHExnzcaCqwNvVoazse5gfGzJg168gaUqJr9/odHUZSUJ
7ql37YeUbcdJOUQaj3rCTGm6NzilqL2bBY2a/6V/Z6ViI7YvyWbJjzk0JUtUuHjvdurQybJHI+jn
zT7oCyNkDJB5/RyGO6MVbZcNI4ia+vY1wd4+AVOnKeL5rSNoOIpMcNb4NXmQ0y6LFzkR3EzGGD81
y5+HFWfS4GNQUoTXchGqVPNw2AeaS0qjdX5wE8LeuA8Btaot2OnCHrO7fd2EMAloPIe3rrcYDXOg
EiwbFrCXHcLjL4v6cD1ON88GbX28pyV3LqKSDqK8zckEDbOnDIc78gwg2rLoeAke4P7SP7ajijiA
YIsw6TJNdR564uXq/oo8KTD0KhIvna5OjJ0utWle/o5tm5dpv4sf9AdMGoqwiW4agpAH3C/FPgF8
XOC8/egKfc6BGeyoNKOZv/QHGVsXswEl4sZP7xgM4cvTFRNTB4mUGUt70QDaA1ddoH3DqRoDE4Hw
wtgSGh2i2bcMllYSg6SWzMXYSfSVxFw4yThynfFDZsx5l/ee2fMDGaoc4NlwTMQEEDcitCtKSW6k
voQFkLoOkP/kIMFYNZQlmPkgOCf2+QvMDpDD0tlQdfMQ8L4KLMQ7TbY5Elzvc1W8kuWogzRZeCv6
B+U3Ul4BNtBC0nx1EshBihzzo/+Qnr616zyOnB7FzJO8E6rK3O9lPynePb5TaW7VU+9W7OQ5q7/X
mwSCSieBR7De+kARsXh+yHCL8i/BK86rEyBxtJ9+j2kz78clIIdDrthnK86AgdQMfOM754IHqQ4k
QPPvEEQvjrLwp+1YSPVpnCbI9xzVKz++EL0O/IsQN2dLdz1A0OsS7ButImfnNrkYUnkzJtSeF5sP
ZIwvPh/HxuMsV+alV3I8WjomGRS19gHkpAlcQl1kU803Mpe3uqNyVhcjYHewkZ81+HlOSok9zOyc
DPQznpogEsbjBK68paSBIES6UBo+sJ9qllvw1TELofn72BpyRtLhRoPSZtdG1k5bj1+FKmnaDHCX
SDE46JddYzDupPvSQD7Ks+yhzh2x1FncfGbr8PJcdZ68xBPM5Vo7Iu/cb4OdWBR1LEz0mB3urMmZ
qoG//slCOdjnmZPCecjoE31vcOd5I43uQkkI4oJMn5ePObhbjUCYYbsikoHawZ2XZRBj5l3IcBjJ
U8BKLVtp8t3i9KY/SHIs7IkqQ2A1zWNYuTg52sRrUV+T6Te7B/QA+CRh3nAC6NU2ImbqXJlB1B6d
AyCSfk2uoeXNBtVLqNNvu8I4E/+fd13Azg7vA8slGVpRjqblRyVzfaCZnaqJg+XH13113lDcFq/W
uuBraTV3BqLUH5EW5bM6qDyEojqNMwGo8/yeXFW97DAhIJWU1MQeEB3n1yyPLBANnzCgo6WFz2Qc
WXhwjtRhZyKgvRbRLziDHtZvSoV6iZzRl07hoTW1jiNTxl7tUxU4/j/5GOVCTLIG59AH1ESAvxVj
nlXlwc3P28hN9yyQxIb+G9GcgnUnQ78ACSvIRswVjGEMnTDW41eAXwqAqW/dHYcYG4EpoXivbU2j
SBy67o1FgdFpVK6PURsckKHGzPnXni9Fvb2I2CTutW0U44/PVFauo97Nv+XeaIGa/HiT3hbja0Wd
iMvdDJWLON4X4ugUk4+VtBfHpvLgq4pRQ+Np2Zzk2VbjqKYshN7e69mF+OJ7Nx7WsXCGoBjf3fw+
1CsnSK/BSiGqXU/zlj6fSXc5R485sRgLWncswBr57l41grFlQwEL6n+pUIrxtKPzSags7ZRoy8eD
PkhZbrhaga8MBrXUguYqK0HgVow6VYDD8gYM1TalXKN5wKXMUtUBex4XZN4SAef9KyJ+EbuEMVZH
D3adz8ieiQ3WnaDrqTksG/yBubyStUeM1X9e+ye8gbZiwD/eS2BES2US8rKIUnOep0eNb+He6iCM
7SHOOW+1cu9QI8lTMO3hkYE5UJ2w0UCRyIyiCDU5nNZGH286i7dgm1gT+DZ3OoE/qF41HOlxowIZ
U7Xxk6YotBaoPO9asQhHyzi85yIJP9Xmf605s0agmqR405xIZ0vc3Q5DFt/0BfC4/uDnFfAKWvKn
MkiifP9mwy/GUbk3Z72XJsJM7YCbE5lpbtNQzZFwbjXK4CnR9dNYSj2RLfqr2FO9B8hLhJcLZhZa
XusfEahAh8tnD53KnM2xJ4ExkDt2z9hoObdVvhodKvoxIxCkaHsrPJpkZtSMCF21QXo5GDsi5LU7
IdNXcNdK7g4sLM9mOmLCSt5NVMtYFJtM0Gy5xRqSIvFxEnrzm6B3YOjeKujBzr7nmgaLAXozKUFJ
y8kyyEJBkcNdLkaG0xukL6Hi0oN+jjcj4fajwD5KAs7DIF2lP7t0ve8Zf3jp1x9BXtQwjyCJJ2nl
gHUYGCsoK5J7hYyuSsTlq7Env6udJa+oOYvaAnhZ33ZI93DHZ7T/vc4RCP9vMcLtvR6BV79gwq9B
RmJQmSg+YSgLurku3en8oXBFpoi34CpmczxylGAqEvKCSoY5ZaO+lH2sXgphy1R3QC7iqWKcFTi2
0RiIdbArVKRztBguS4s3gdzWq8f8dQL4XKnukh8V9jcOAtRT7HkQAMf/oBS26sX6oCFsHvz4K4q+
08zBUE0i5jVZS50rt3N73JSWNRzQHfPHykFOrQuRERWogXnvz3WTvJ6haeTdMV1VBICcxSXUcPUu
dAmKf0m7fgCNnbG+dZl/Jp9+cOo8Eh9Ts3fOwnPRCVza57srrlkBtwKR0VJTO2k5N4JJkEnGoQnv
ub5jxFHqAGkmTj5eu2FeXGvbP2h1tHdyBEC+0bXx/fM/XWEYve+iUtWKpstHmCjrzw1Xus8bx7zd
6a5IWz4I93JZtdGWh3LkXP8j3hDiyDIcyrRyERuJq5TokkgNTjZxgQXPlaTI/qFSBrqJ79HaH2sc
wqnd9cvncWXVZaNJ6Lo4+z2nplz4gjHcgWS7hmSYC47a6OgTPYYAVc0Bcn+YKT/KWGPKC8lTm8A2
1Mj8iGQrUvnhCGOftsmR4Y3lgq/Z8kIkF/aiJ5dP37lhts739o301jNs99V5WxkuyCH8FxjFnevk
ZhACYC1yD0FdLRuw2WLCQ1OlIW8XxukcGjyfr8Jrej4Zm+NjPC7LQC2WLlj+Nk0D2qezfKjvOEAI
boWCJsf8r9rY2x9rb2HXx2RwmofYC0xzQkeB91fDn3p/AU47EDANKWsVDxiuKueM9p61kQr+4CTT
gKEV4Ib5Bwdb++LhVyd77W/j+3Gs3yL7o5QrsUtlKszEK+KKumWLyHBm62WJq8CDiULrj0DxQL0b
L5RPeT3gO9xDBCWiw+4bCgBcIGrHQKt2ZTDZEEhGyDrV4Bj9Npp/WFrjuhPJ4q48rN5DlsnK3eD5
dxALGcqnLypY8ODvPjD+Vm6cak8mMoMq/VaJC7gp8BZdWsOim98uCdnCPg0a4NcEHpDpTUG9Hxbf
eWIGeSQs/aALQNFxmdykHbOdT5naKG8eBJqEQk7U1Xiego74tOWS5xo9fbtJ8SPPcG4Yz5SxPryo
Szf8Ss7JDp56aTqhVr57DPvUPgl580eZUKnY3iggTlIyzPh0SlCfCUOFQ8SfVIkYhQRmWsYbUl2w
Ali3eTh7e359eiLB/xuprjvd5ObYxamZjyLx32Q+nzrm/mlBAtvAnU3B7Gnr5Euy9oPpQhAkDK/3
dG5phO+BFD3qa4Mkf49d6/ipkaxiUH/7viCNOcADiAdkDyJIVTslRDfIHQU4ZkIWm4NWaY6gktAP
JI8Q5UksqYEhs3VVl0VBZrROjfIva32bHX8s0bmZOkS3LfCn1LqtGWEHVPbDtE7Qfd7E4AR3Z9VX
o1WRREIea+P51lUSfsEK++40RXfHZ025yfYa4YauFp6H9/IvY7lMOkKa7e47JPUXmtIdL/3m5zPg
l5i9Vq83CKbig9nT+ozM+5lYc473c0r14O5wPtkLHHIOdBzzkD+g337gu5o8kEodN7woFGxfq3v7
Em5aocX84z0eXdLZBxuv/okL+1C50OzMDLnXm+R0ym//ILgdFCNgGuFWmAvgvMyZvLQxGXFVaRU4
Zh2TmONFsqzWIV+YsAhYLubR/VQM8oqO6W7iOCKGev4BJtfPKSR23ITZj9l1E8lTAHiTh8XiDM+0
zczr57pn09KKiFe/lWEewCL3XWwYHmE6dm0Baosp9dY3mVMXo4GZZxnHa2x3gFIsnEQqLrPSIosX
nJmsZXon1douSGf05j5AT9ZPPXmXejN/ev2eg4FB2mK4UQY43vJiiIAwLNcSIf8WDKtRyjT8FwkV
qTLXy/Qsw0/DQR3A71SEzDasBdyo7+BHdA20lYqncskaGeSKpfJgPyDZyUBNXJ57YS21+Vqli55k
lgDbLO2nFaCzupqkfEE4DM+86N7fsI3le8yxUowuBoWp9867e4eMeprmZvcY42CXB3tQqbfkA9ok
B+d98jGX042YWAcYiaTaT2eiZYnje/VbXmiwABKTElahh31fqW2dcQ9JE28k561t2jetmMNbdobf
VBmfNhnyUaStE6OCQBW1wJYQHtlSm8KPgZvZi0muuzSIi324oZ4p02+KDwJmO4BEpqGgWKijMFt5
l8SdK+b7+jud49VTQoz36QjMjrV4NyiEtMiouHiZQjdHU2Bhak1vUETRB5ERNhWJnRXcJy89lwOc
AihdCdAer/CrkAfWgPnDf8KKhd5MqTM3rFDgrS98euJBAgN14lTaCEw1oKkq+JoiECRW5sVQkjQC
kAQHuqEuSzovhuioG+d000ZuOwIP6rM2EUGpEXv/MTJQM7HK7yuT3GWg/SZZmq8qwt2K7VrhzXPq
dElNCN8yrWNy04xRgpM3pCOBMRBdf0+dnlEMEDIjpYdnF+tLgiEZ8RNRrVwFCuS9YxFbd71fIkg4
6OR5C9f1jXzkNZicRCF/p6NUd0e0oLQbEZzSUKAP7yAJKQNsYhsJuCiwyWWXsRrHchIik/8hioGl
4zysvvoE3jng9iwe3zlMNQc8VT3JkKw8l2D2lTwnOjO3CKHKr0tthEMb5FgKoQnfCEdt+dFTOdIY
dcyyWFzTxGjL3zNtvArWSmUCUB49seVmNwU68ygR2XwiVNKBJyl2EViP40je+OwA8PZ+Ux1/gm32
sl9wiEODJxuj+8PuvPRM3mC0DTJKYu4/7dtsCYtGQO4pYjbl2pb2I2WPSpeYKhrAFVWoSUqlsbWN
Xa8iSlF/l1+P2rU6NorIKpyc2s9F6j/TjThP8O0OjG2jo7OlYmgFv3O2S0KIMRDVm+m8UMNA9OO+
XG65l8c0SYRpECR02Xlh0PDkzjexLoYC9RI9SQ0HN0qYhIt3r2rF/TSwXzLGL4bAsj11CdsM7RWI
Oo+1Q6WoiPusA/otrD9FjLomg98hJ4CpelWbtWUl+finHvMSpUntB6UvLC/fJokfbOQshVV5Pepy
LFDdh46xI89ssSeGzQhC8MLnpR01JPltIqTqcyzXllXgRafOOVo+WLJz677jFpDgxJKtjdO7VWhX
lYaloVUsqwDW13JFpX3bEfexQZW6AbrA9lIjpmRU+vl+9IeVvjioWmjSEkYJbRR/KYOprEFmeZDd
j+uVTpdkFD6Fv8Y9T2elLtTt3A7IX52yxpuUkeeT/FGL8l0DTqMpZn3lhKu38U8JloyDs3DMi6nb
5NaDNZNd8JiUbFkc+QAW3Cv7zkgEBOLQME7dGnzrVVhidvUVwH+i8p/5EjbMPt2v0TMF3F1z7Ahx
adByAcHFmMh6MdolFgJEX4dfx7yhar4Ge6Vh+t0MgzM7Z6IG4bJrmSTgRrnmsLy3n0ZtVaPO2C5G
Ff7P9GPZQpeP9u+cPAXWAzJAzqGb6dK5hreqncStgx/gSUL+/ygxquVTp9AkkuPssWuc5T01nSil
6yn89PFjd2NUgmfJjTTjislpA2zR5WzG3c06dZ0GbPGHc6YPUMHc/Opy8UJqXufH6PZ9dHxggLkT
OulDhElM+BLd+AP/t8d+56vNZTd+v6EBovp1nvu7dNsk4gd8DFHZhFSHa5o9yAdCTUP20Gsg1jR4
Bi+3m/krV9EOWK5/6KB9pxyM81A4va57mSLHxHe4XiF8wXuIXTmMT6YTHqtP4hmnMXS6C7mgy30P
u8wNglJZh/8CQkzqmY/hOilyWDZsN7PhAYdto/G0Jo2SoNLhA5q35k9WSVZRpyphsfpOzTRm1s5I
rh3yGRTAIgSOffIgzTFkZl+8MsG23cKKjj9s08DWL3T8uDNvQhZuv8VA0HtmYD66dVYOkMEzW8JC
qHKG4IyzsHkz2KT58lSKAxm/7Uhb+ZCfggaxh+DjeFlPs1RX2puLN3t4eoGXuu9t96m6pynnPuRt
ZtgS5e2OSW3Agh40DOtigvts9q0dp3G7e6GSNyPZ3gxsPQlep1CpRKtu9UWVPiRJDNSh5s6zAAc2
qihs5sk7xpNFvw4vHufVi/xQ1eSlxUMiB+Rpc+b2xv2zSa2h0Gsx14tFNFIbxpHIqDbl+SrP9UEd
hxQ8MW/wMCyGeRP74Y+3LcpFqDiNdVjf9JqhLuWe5iSwTuKaeQQ3oJBnijLPkwXJLrMyYT9EOxTP
PuHD1U++oa8spniEHuXqarFWWAnfqbCc569KzhJQROk9AEsssS6bqgdo5Jqp2XP/JBn22LX7QR2G
WBXUDvYODjSS9mOQ6k/ERVcw+E4MOKpYfcIwHhtHJNmtCArZlLK84BlqREaDRdN+0NEANoVN/en/
JDYfPQ17knoUbMVeHwGEj8EZ/6QxvL0/pNVjNR6lvlR5/Tz6bonxlWEXBsQtSt5c2pRRqPprr+gC
3MSigftNHyS9F6wfNb2wVyleLH9vSEIje25/uNO0/F7QYAGqjkPgZ9/+QSz0aYBsYc945TQqGpIc
4+VdW/JXrcJbKB6mklxZcdithsqPHDwIXnu1UItCOyeifmQeRyUNu0dXD55NBEwOsIRFpOmRwP9S
lbBmr+CcHdzYJ7UvNxJNcQ1g4WproeJu2KVJw0wsGaHLKCKqlVpyLCkIgXodQkHaQHBKaWJ2npbN
c+gZ73TKFT0PfhWsFqwixqnMdNNpH8oC7m6qjNi3zlIlAEdfolQrUJPF55LjuD7Ln1/lLfVd4H75
+sD3ASYpkUXxfvBlCZeBGLbWPh/Cupo0qmLKctZ1j8BocrsfBsL5GeEdmb3cy3bNhqx/J0/Xqi9z
oL35NoQsJ+s4gVkvg6b04XSCQ1T6aV0IcHO+9or1c1kCnnxqZFW3MavHW4D5EXuGNCesqLY4PQqI
CAxX221wzHB4Tmqr/LQNTQOSryCUCMvlkXwqzzb8A7qGVp+Jl3vCRAUl8mil1THJN17GtCd2Z/52
krAFTyI+f7B7Nnyd7ooLwpwcozVkHZ9/AJBG2iHX5VoQ1xWDomcWC+71alUZjHk3TAiEfEPgCBOW
09XjpECd0VTicHAu45H/8qrIQmDDEek5KdWoyuXwVCy2VPmRJyJ/XDdguTQK/UPjet/1WgrOn+Gw
KiYjQBwRqLRzyrxirLIRWa4Kf6uyrCB2LQy+br70uowgChQbzFL5pGOgV1zJk9uWrXD09Dki1KAx
kApEvvmqdn5p6NUc5sWeyNpU7hemcgmdfcxokZP06FYSph/kR+gSWSAW3eNl4dvgj2QbVIMSGlig
zxTgkSV1cxfEMvqhWPK7RRy7xctArUUaSJfy5Vo1dLJ6oCEe8Au7FYAT9Xbo0JFy9iYHdbOIElb0
PDKDJaC6p4x5kMqyTPMk5ltVNEekhmX3Cx2F2oK4JcFI5YFtpd34GCnKoWZR4buzjnRgbug0K3b1
VmLTCHraUhwtS+/M8z0gMaugok5gh5EVmYVjQjURyA8r4XDELDM7IMBe+5lvs06vNnqgy0vRK9hp
WNPJv+C2ULNJXFFFh3UfKmWfxu3qtHKPglrs+JuSZulx5drPFzVaoaqRrsz4QMGjv3vyOqLzHxWJ
YkNlVZv7L+34RVk7WytqBBZRWtzMEco8LVKU1w3S3BiojChZdZZS+Oupn58V/BEVHXda34B2L3J8
muhLyK6m+KoAftQshJP95XoXTnBvD2k+e3ob0WbGV7vpHLX6/pjKPDoLz3oCVwIkG4neJlVtHJxl
ViWPnbN3MH7qDW8WnlVISea5mLYHv23K2mlZZcUq/FNNSmy03U87G+9neWgmPhO01Di4zIlqjNSE
45yRByowWWezQCpL126XhVdaue0DLgl5UhvjLsShqbvb9RxMrY0RrW5+Bv+IWU2As4UhNi5MQVrX
IjR9CPZ04j8xB64lKiiwgkEwRQzzjT5QqKXKchur2bMa+WQClUkPkQqCXF5LTS2m5v5CqPw2EHpZ
TMpH855k4/veC86xvi9Fl+LCx0LZmqQKFUoBggzE4lll5Wkx8lqZrlEiNbkUFSbdb9j4j0tNRdlV
ty4iuawMt/lvEUCn7oyvkJMvV749SE0zkr5mGA+ArDQp4EDtCKcAwkWF4F/1x87c8cCrNI3MViYl
G0gPaQQQkJsOx7npLrJhLs5P41EMJb/84rvTye1pi+gGud8+3/Eiv2BMYTAdeF3ASudQCc5jztV/
4AjEzitzzI5ggutrrar3FeHgTpJyNczG73ZqJcHZHLa0goCpKzaFQ7WzKLgYa5a7RPrgKe4yZS33
uawEOo4zK4gqJaJfxb3CuEmx/eIbdd3onJJXyuwIx5PJeNx5ftVEt5Bf2SqNCae1VkO/JmyX7svZ
PzfXpVmqEtipAJk9GQRHgEDCNNy50NLdSRXUujZDaTvO4gnGPtoWR41YnzEx9ERrG4E5jtauEPSZ
IESihgDZI3+qK3Fqe9StO0YG6J+3HkVUotVn2+CSA1GzJTmDBFAsyewSVEde1fKc9dhhGUrVEqul
Qq16LrfnyGklS5zE5AtRYq49qZzH9evh4P9TEYjPlSuk73ezYkZb8PQx/mZbDANYsVHKeaXz+aYn
7NaWD6gTM5lcksDebIeLtmYPfchiYqYcMr6n6e7icCikRtXY7BxO/WKyzdo89+W0BcoDZ0JnogmN
sRpJ3raC/HchpiT+/tyxmm6MDuTljki0vqQrfta/OsW72FhBsQvaZFdlFzB03RX8od1N5k5wnMUq
2aEE27UXLIKtRodQ6a6sjUN9UY2lUyAJtp0PBEc7k0arYok6F2pcZClmoH7OzU+UmJ9OeMf6j6aV
42vHZn3BLsdSSWNzYQgWY9rf6I4o3BOFEW6ZQdZjCe0XJ+BXLO4Uxp3+FFqMgFrOA2DX0jNhFgEC
FhxeIy+cGS0x9wIOATinI//TbJ2R6eNHCKDa+I5nTycN4pFRMZHaJxmlkU8ePYq53Y2R2+wcpeHT
Lc0AB1WAMmCXPu/Ep4hinsT6ABxcrKb0eUQQ3vncMX2tpv0jGzrDCsJWwBWWTptTA6WxT9CAxoTj
EB/PmJG9qc4UppsOEvuZGbqUKarHfjtiqV6Bd0KTyXJ1GrX0em5VdZKRTGPQoC89JisuE4q4//xr
Gdl9nBEUjlwjHFRQtfyDXZXZ5tkCPoN94dZ5Ghi7royNPga7FAEMJVGUcEZuVbnqa9xlS7AYn8/v
rr5wK4h68reUf0dFjJzkYSrw0v7o+NKXhjl4onHzFo4t71hxa0wWmPOhU00jssOFR5s95aO+NOQU
zEYiqPmBcS+FcmZutyeBkZGm86XqzwaalpO0oLn7rf0LH8/E3wJZIa9f3aLRJ4Yvk2V2xSwnaX/H
3Adf9z8WArVAnVNdaNcmv21jvtXjLEcEhOb42BnXI1DyZeLfbRpw0UVV2zZoE9kf1t+6t/rAGnv2
wevdLQOcNKnrT/lhQdUr5bg0j6DnUsFlHst7aMnEjDdKzKvOo/pt+FPcs6sEJQZ5lGS4Qgbz4B8I
abbjDFD1w/5mCf3K9mFsQeGKh3Edo6DUl2UQrF3FRQNi4F6xNfkFSRez3xvX2d8c65t3JL+uq14p
LNR4/SF8INkCvSU1ZwXJeFfjZY50V68CO9Ks6h3I81yX5nlGFPt+tqCZxp+oFcg46w7p+CkL71u2
ldxl040hAOiXWuopGFZJ8RpFfSMxiWTNOi6k+dlpgOUebmcaB5ng5ksPbtmB4ibCJXjOLuwisHCl
LvERyVHeTAs5G5dqPmoa1dKTSVJsOtVmX2Hl6aubLenhCbTI7zQ0dhKkrIRlmFPmGMJ5EZ9lJCx/
CqWUiVMwx/fSgzyzxAyB4LGrA0PpZVhjPjpTuHMvWQt5VUvZSiiYryQs/cs5OicQ3QWvCQtm2cXd
o7d/rGHh8+zpH5gFjnqeftvDXD7zVoPLJxEuop3Jhjz7Z0HfqGhmAyHcjViWpOzoihc2KCT3WgQE
MNSUbWqd/1YXGz2QhRlsQqRAoqeR25Yu5VVf61o8UlLnpDEJpnKRzQHOPmatDWkc9lIpS4I3KJCq
sgaSgoAWvOeHdR025BWj9Hs7n7qDhqiivaiObZSiCYaCWVWx9QNd6YBnNctxsPTceBOdDUkevuPc
fDNRLPMUk+JI06nB3WTdMnzfajhYcAygVBruK32qCJSj194R/XaxJ6FMQeKs7ZJdJxvuaFbHhzI6
XMhBVm07nQ6v8/2IhPMNUOnS7BLSrgfJDcvref1vpNh8Km1d3z47Ic9pFnhidfCl3D4qIbEq/JjS
w52MdbWTQn7zOwCMxpZyQ74V06h5BVi7g5p9UWl5m2l7RoMGfqjznRGst2l9psp86ldbl+pQlKFZ
5i4ZG4/Yee5Skxmm7GZx5XsMpio5hGLE48e/5htTskHviLZe6kaWOHISOET/nYFFozLT/Cyl8RU4
gaVnn8s8hynRJcAMcEkfoJu1daoFMzR49K1LyTDH2nK1VkAhmeQR35odq9ngS8a5zdf7RNBSs2jj
AIvHItpWV1FSQbrUuyv0yLqZnybsVN3BkQc5BkbVZuN7/LbyKQudE5W8bXsOHow7EeS/dElPA9Si
wFfA19hNzl5fkeKo5emPqKjzCOA4oz4NqbNjp1682XYrJZ8WogfqSbjk5CdDbwGBpF5b+iBr62EC
Os5EVieQkRUlQQPnP703yEwSdYziNX7MBjEboatF2tnI0Mca9ygxxxd4k59fPtzmDxnE3sHs6H+Z
1TnvRa+SmTQVe70WJG7PMLNidsR8VWR9CfYl1OC/I2aj25hm+awW3Qki95R90iCKZHJXD95JEP0t
s6enuYItQUCMFI+z66kGSvcx9BD1BR9fO4tBtYDudyYhMqHbxvNtBPip++WEglwiw0RMdbig8frG
0WciTi5u+n6LEN919bGDLTBOUDil8jEiJ3zuO0yT5QHyjcaZRCKut6DOg0idcvBy5XMfbIhNIaq/
B77HCvxV99bqIwS6oxv7f6UAk4AZWP+ijIL3qkEdLTz5FYPCC2joGG0djqkjjjORXDdZvkV62YAF
5TQwM3GoIMs/bK3G9zlGa4jO3AGslozJJsYknngtDIiKDMnSoQz8xbZsC63CErvVf+SuFE/uKPL9
p9dhtRemK2H+Pt1ZxbEoGoUvJW91MINCFWDqemE/vNb1eyFZaGl8H27XrbQ+bK6JFat2iVxxFQ4V
OCkMezOx/1FQtQeOPWzivIO2qi/LKGVrmdDeGbjN9Ww1kmMzi/cMOUWSxGTk1ZgziLi8Idmano0F
D9V6S31G4oZVfbFtfeQUaNn1aKhODm8m9c5/sBPzssSTreMJqTXvqC3E/jXaHljLRfrwhtMti/kN
KxLbCndZX6ss8eMw+a/uHY9xzAhikhUQ+0gkOYZWzsARHbZsci11j5EA0+QscB+Gu+pjCO1VG4ds
chLIR9rII4/tX6pMXkbRtM+Ii5tJnMSLCZmA8EhbtHzeHZRl776i/x1bvQ991ezDeeqqVqtQPTT9
TgyS3nWcOl9fOUItNf9uftAZ2djCLqprDv1hadSJWq+Evy+ScRrs9yGrHOPld7BWaleq88EjchrQ
s0KwO7ZOfBzLfd/Q+Vf65a97+nK/xZDqtRuhg8/3pFPEycxIOCpmBlAFjFi80oUGuwh7kbgESaA1
EX+8rujWM3PniSv9540e8xftKC8ze6XIFbxYFDgWuxDVrvJQrCWr1xT+B37/P4MQcSIBA58aeVDt
Gkfcb/JxTFW3hA7tNWtgfggN0j2Jw0f+hndpwq+ZSczowrYgFbQ/NaHTcxW3eY6mUgljy9HXbfxQ
DwqEHtRYfGnCnjDFoFpvX7BOirnu0NdpyNNhKK1mzVi+/t7zWCwMd1NTA8WJgIJzXJcjSe/b3bP2
GIvD6iYAwTgac8vSLP86uOUk+cdzju6cQiBK3N1c9T+uXhifYo+hGaAkyT2CzyN7bUmUIa0qU872
0DVRnqgmpVo+BF6lb7LWWNmFOV5sVqRHbb/zgDXliocWNThnW86Q0u6VBh3o2tTGkbgy+peZoSDA
QsS91p9nac0QBiyd62VPJ7e8IUA1fUllpIE8TvHr/NaWRTGWnk048neAppQ/rJWflcdgVA8KVg0A
tMIN3cv/GKP5yh50jikUfM8EJRttGezP3P51wnSxXnZHkb5D1NTtQQYJyjAZRFPc9b6zCdT/vSCN
VrIf1t8/LSGRGoVGcYAgpBEzgezWwXpMr/jQvoP5EqlXQl7jlSpIOac3HG9kyitv0Vbp9QyaaE7l
BG1SLowGaq8QzUveYeMmvnnYQRtNLPBH9bUFm5VGdye8I85cJN52FL61m34mCuEToSRjUapN6BTJ
fZ5Cim4WSEA2kSMXk8tpE3xHbvCf1HcK711h4itAEUwJ42z2YCA5DcVs+MOC3agbC5PRISnbL+k9
9+kAVC0RYaBaBqs0ZSKE1CJ8dyaFGnPEcbATktGqU/PlXTFj2oaZQrXC/1XFP77vc/V9I2kpSZbH
BUaFFroOTRxXGeHB6kYipMZpvTjlVJQsHU3iHsjn9y0mCtjmUpyxamkz/8eDDEmDFq0Cd0y3vaa+
O93EXx7aFML346uoOP6PT6n3QXk713oPQgkY3uu3NU7Pa72ncPCSGD13UTevbDB4XvwjVHt9UAyI
xgGB3M3NzkE2WGTFghQW9431tYjcZELAybqmA5277SjmsqKVt6++kt9n5uzbXmgS+ps1668CDFmG
GXdaWFnW30j2pjJjkFrhbPi71xe/+kSrVXFpe+xEALFWvyRBUnEMIklTXN9IqQ7KzjbRHMTnZH9m
M/Ove0L1kizwRibcum+xtbRbGYHlJetCGriL1GIDqCr/XU6GGpRlzZALpqdzISkj95eQM2Ct0ljA
FBgXt8BqSBUf6QDCQwpM/FR8tZ4/GwWCQ8LXPDuiKGi+durUqRp/7DeM4F9D4QMS9GoimRj6SM9A
jQ7laUtiS/b8HNn/0F02MX2ib8sYLftxOzVpmlv9/BKRuxdyYKPnvNu/x1c6wC+zUJmRcq/kxi2e
PW/oE5vXrJX0BmcjBtnkGobSLQ9DN7ioU2HNaj4Cb2Qk0/PIdZo++skROEjojmL1Awzb9WxSH9BR
bBmsHNQh+YiryFtbanBhn9r0Fq9JfDbsD+mYfZb008VrnnpdoiG/ITpfDe2lD1Z7JK/WV3ahwD3y
hh93ZH2vqRJKnXM/ZZEN/BqJjRfO/ppenpyeMml9Z3MXETW689FAYGO5BwH4GAljjF0G62TM5fC0
253ItHNxvzGoj31F7ix71pcGrFHvmPvaPhZzAV6rktrd17ZgWMS357p3nU6wtYlAj7wb3h8xufDV
JktqiUWM8bsv5wciYh3RZjqXBgfWyWQfbwkCg5+RTMBs95EOTvCMVGyHiTh4QhM8JD7U2TRTcFqB
NZN+M+ekk6CuCPoWzwyCunv8BeXpW9cdUkWvJ6srG8Qgiw9fRV7m712H4uAy8owz9+LhJ5Kz5TCs
5+xm7X0byXx5r6W09mqhnHyRNMEDuzY52nBXga77oRy1XUAALYt+5GZR25A7YHhXtqrWu+Uvddva
PKwcekTuAfqK4fVatXEQrjTD3NVimK4lu/TsW+QhDIzYYmLY3e+TSbsTtjujAq+BNoizv+Uc5JdT
aIAGv0XQ1oqjPzALEtskIVlD4gmi2LiEfbAZ26wRx6oDj76z0wzGnDXFj8kWjgaS8bbFcCwbd4RB
7C2jCFBW8am1CIzj/yeJFa51HxUD/3HSLmEissLtVwpssETKLxKCPl1OOaGGWqN5If5Gq+A1LikY
zkezrWPfTugfwQfEhF79JSSefoL3N0dx7rZYuzDhjHYoEUaHMEkSYYNqpBH+DSlkSDunr7v+YefH
UBGoGe0ocMv/UzUu70QvSe3V01kMSFwfEBf48fjq9dqI1rFo8O2tt9f1WRrf0uu2lvEv2imOlbHp
ujHQ1U6wTeSFQcWrojgRKgoURS/mPnDBoDXxamoFZRtfiDZ28p1WGDTIkgNydLJVk9T1fwbCtwL+
u26RdBnzy3QwgEYiDRx2hnf5YG+kRIeVcpbH2GI0fy4FzPLlQBTuN4vIs7xecnlwhkpHCAhZOyfx
TTGnpXCscs+n9dpwWT0Xu8O27Q9OFEmjQWXJmPZa2mwYNfAtuorT043spMrJjUqoFJTO/ARyFcCj
eqgq8tG2k7BdL/tH2MzT2bYVnIie+EIZwbs9K6eAFXYlLlpyIKRfBu/X4DLlolKaB/jnkQmWoV5A
XxbyYKI40yQhKtbwvT3W7bvKlzAAFZH6BgAHpdL3xtmkibi6Owv/k/b3gVVUubNldIJu+fTJ9mXC
JeYky/H2vom14JSG+eiMwbk5oMXU4ZnIjRV6Ws799X7W6oWz0HcmdsvrUZrW6D/RmDHb6npgfET4
tE4UsNvYCZSEGkVhQ5xDw2WsOFqpmElbGxMddRYR/orE1JHZv6JvBvS09Yy3t88aFxIL16zHMIOh
oKua7KnFJy35j88xDmhY1cwq9n/Bt9tQMkYcf3dH/25viKZnD59k860X77UQxX53UET/q8ZFVUCE
yrpW2bwLvlsNax7WxVO7HjEzj4lTATy0Vrdczx7FFLdq+1mPeGk83tphSSljFBMrYVOQy7KIYtjz
N+zsSfFXqrx7qeCYDeruLtGJCj7IinP6Ns9DMYNyDAJyF1ADb0xlXTSRis58i6ZzK7uzBobNFuau
xkx4/LRwsX6qVHKKmiElTQfvK1Z7fKQXqU5G31z0sZMivq1HlZP2SON4CN93nBP7VoiVAL7WhP2q
fD4ZpYQOGGu1IWCBgmocQDmSM4vnVWJ4qo6FyzLDOIFmje5wylJxdV5CkMpbbBfIDYWjCfeWCnMG
4PJy9R1mHaTdAkLXzMw6VehpF52mBXtwb/YoBBIz09TerYg2ebUZ8tVN8Bpjhg30Bbp+JPgYzOGt
mF4vb0oMclJKWPCvNOGpFRGHmCIubyN3v5aDwoo8q4+PtspQmpx+OEIuOhFWqkp8VZNPJ2N96CZd
gBDy42dF9QAz5DUmr+9VLiI26E4vPCRUViAMpeWq0lM4LmuSFNf6GuL+ZJG9G7W2KAOSe7h12y2J
0nXeo7X0yrWb0agGGvbrOteE0r9p5zlmyW5uyWoY1+qGvtynOTOmxfZPLMSl7peJWhUQ45yGIWB+
gWpaVB8sym08BOl4Oq3LjKKAawLMrsjr38O+0661k744uHiYX/pqMWhUtpsQwyjYqPKJOfO36wbp
llqmvre2QIKvxQEuMswTev4oGdg2GvEgI+atSRBXdeGzBnOP27HiwyvX43+lQKnyMrqZECq21Sdt
nI20VdRIeJOIwe4xtvQPZE9rwQFG2FqTMxcL+e5fhg3c+w7NdQHyFfUdb7yPSeagn9UwthHhQBsC
XwsEwmHr8gqrbE1MhwFoeDuRl5ACmK0tjMFAm2ZfKqbt0O4k5EkzXVraSBkLq4L4wi8xmC++LTKO
0be1UMu06+7Nt5iAZMTo1JiLRwLnovvQ6rm3x4FE07UvcaunTnfSDCp1Ue7MlqZ1E037RVUyry8i
Nb8FZt+LVXhTIPhg94eRYXl204IyCHk8aXcMPIZi30Auj2gh6kccPSfm/tdp7JBqnmeqIAxm2pys
9ZFRc3Z2UiGiAAnMDmv+CY2qPeawywjiIvSUHKrv4Kc8aeS59h3EHrGsa4WyCNZThLSU6+gBmalU
TvEoq/CAy/vk4vHlmUd//HjMwOghEniT1uA3OWTZS+WX+o6nVJ5opzlACdX/eDJcEQDpL5PAteLn
cYGEMVMbkpc8ycxEuU1//8ZUh4aLm8ZnM9x008AaPL7pHP13PL1em4OwIGJa21jO6ju8cI6L/7mB
ctmyDfFCl8ggcgZ7bqG34+oF8C5DOfhwVZvkOagkL7SVyDxz7+buLrsTCgtnjxaeu6V+3u/UlLPP
pG9VrcNOyvFSSNOJZMHrtVNtpu3p0Pm07k9gqalI0hdkAYdLvX9rquh17Eck1ria3IyyPMjiZjrQ
bjpTT44MMUbEAJiRoMRh0VObVJt4o9Ej9OtABVfY74uFmL8mCd5Joe+0k3mo/lRzMb3JpckKB1ha
hl+SrP4x61yLc9wk9Oc96PTuk0ZgmYljdi+aYIpY6BFuTJYS1FtbuI6tzW18XG6VdRh34+1PwlTN
qVmRdUfbmv2ClU4MH2sq0P5nvwb0bnCG5BHk3yFPVZUHdnhbjyr2DmqDZuV6qd2V64qd0nzvVYZi
zYseTQLxz0Kn/7rK+FfI4aoDyXrr6MWnBsULcaEKkitXPDkVQa6NgYtKt9n4k1ikWGwoqkeqdKtE
MSEdSOVlgekx0X7globIdhlIBj4uvxL8sbVtGpgRsakjI/TOal2t5IoLJ5wNb4Q1zOHbS8oynQom
zC2gMwwAXrH+gCwroa+5QcaMSdA0aCtxGDmA9boeGcUmnctKyKn4lk5kYxGZCA5jp3K8mj8oKtc6
37B0Y1+B1knbBzwkfkZd78nMXZj5frSWg206lBg9mEPuMTVybhL1NFDrF+sPOCjQHi0oXbKJYee4
IQSVau22ampPYxlWe4mxJoHGRrCsDEviAfVHhdxXdzyGvwfINxTGFiiNlsKVVJg77tqFSLSfJNEO
FMQyjWuxLLk0QfyqzI9fRqt+HWaVNIAwZthF49Y4zrVW7qldkKAb020HCfR4WSbu5IUaZhJ9N5PV
+ZXDtxknjLJcGFxk+bCr3n2hGdKCfqIl2Voquz4ijCMYIdGDTYKAYxa3W6vChtPJ1yixozIfcEzL
8XHwvkw43+7NLTGjVQoeyTUoFHsQwh1in5MkNmOqLCCtrz9qEhn4zhKkY+FHuByaitV54lWWGZJm
0QXzp420bNrOMRkrGpqjGNfGC3NgwLL8ZwSekm9QLvuBfAm9GTnh0wlvv3sTu9bLe6tSpnvmwred
VD7qtCrcmg04hfQjDWEbKrCr/0w//QThrp7/4o1qgmxeh5H250j4VHkYUaPVgFlZqkbWWsjbvlD1
eC/oHnGGhDB4ramVy1QEYlz3NB1KGtkMWX/mcrtfZbppC+9nwEQzScSLieTgaYRAQ2nZrtOFt46Q
9pOOwnA/Bs3ONOFUrAlKtql6vNtDmwXWah5diaknU3hZNly1HkGpVdI/NbiA4CxhTMs0PngrzKpW
ZKfZlEnR+d4x4hbz4lA990nzOSN97TOsYFTDGIJKWTU87un8VQEuTpOO9xkOJGNs15ZCnc0aFUc8
ZWY6mPgs4XP+kT3oqPvORjjjvyhbxR3FGpy85CrW06eYDywLbJhOW1NDVxRIYtrYJRENReBxpSp1
HiAOt9lAEKBffnM6ew8iQtpwksjDRXAs+pgtIsXyJugzntpgxUo4xXNixScwiwWPIjhdlsZXpUse
eRpRiUy9Zy3oGT8lSaImcMXhW0epd6mYnLlLJiPaxMKeCg2mxxSe+ErEEJbyn/ySQ3dortWJOzWd
xW4a2xX/AA4K1ecNkZVVdKThYEB8wTGxiX1bzghsvND+Oat5SewLJ6heFouq9MRm86iCTUDUHcwt
mmS0p3tq4m94JmdxG2P2fxmJ42WTHlcLGd8So49ePYpqfP+lpB1+A2Wg/1junW+VZr+knrBfkxxq
U9NNSdE0puaXws9mC4K0RjR+YniEIjyLO5V2SVst7zHtwjBfmbwK8DUJe16ywxYMqQH+npklIfuJ
oykxvFMYTFtuvSRt2jV/akoeOlw+i5U0qytmdI/M8r5ED6V/TYLmb67tbPrMGzx2yLbzLo0bmnMB
VJVs/XvGWzMt+wHoi/3SoKFz50/+Nt/ISYMAR9R7qAotzPzBFgKcGmn3rhKyxGVhwZeY9AWMuhSw
yF23UDC8MU1CfqiPkF1eMjl6sCzXHU2vkH2ZC4iEPY4LoLgG5IDfQz63bLrJY+/stdcsItMk2f6Q
1jEJJ1vDCOGc7U2CWCnuylcwGu4JKg1676/30iXPvPC30CR70irXGvLsZek48SbeBO3TdKqOXB7O
KTiM2sM6SlKA9Y5iM/NcWGhkHPUCLhxPe+er1lW3GXQe8MakV0X5TYvijaSja6mTaOLpVw+mgyS5
fn59xlFm88Sb0QSAiqb8++xnCRWwlwBPAba7tALDrptTs8S4hyX00FwuiBvSD7NaLMuWL7ZvD8t3
JUrEUloMXSc0HJNrCBT4KbJ58ci0FbEcr/1LjM43WbPaHNKV6JAnR5RS5lbYjnOzdV66fUbQ37V8
IWV5T6wcWDTU2oP8LcaKLXw3i9JzFB1e4Phsq19xby5zy20PHW5x3c2jyV+35vys27qCzmKwsWA4
1JiO+6U8IGEQIXv8j+uO3MB8xe5JF+W81sCdcSEJigqhK/h6sJGy+NZ4jv+3IWmdkuZbUQtd0pLM
8EywZCWkQXDCBwToRXNP6kmF2fB9SVGRduBmfV6PQE0hjAoDqOKXa+5/mB0HQuRysult3pkqQ77x
T27h0s1d9cM1ssqLLDYK7tg3XM107d4KQOWsJN2P5rfSe88UdMHeZByw/aT++BQC7s0EUjdfu8MR
Ww6KAYKGlW6dI/szzLjbrEt6pCHjBmtiSt8nkIrFDTGAriDCGvPIAhzeBKJZwrPzmJ6vi6i925/Z
MZ7TBfAfgpk/CDj3Q3xr4ZAvOf2wHbwYz13pRYH/M28NDxQGoYMHJQerX6icZ5etbxEKMN3hKPGc
5FdOJlhVsFJ8YIlblKSZwTWiH/T5sU8nzN8uZcGEw+KEiHb1Gv7CdUw2Gi/Ly4C8ny3PtGGpQqDk
bvrVYAg6w7fgmj7XmSriQbipC77cSJJXo5b/TaNE6OymkppRqbc0JCJ33WwlRm8qqWwoz4dm+Hwk
r0AmQn443JINIYcnDpZSXpug2M6f0N2jB8GbtUQjNgOWAXtEjhwJyPrE3DraT6wY0IF53wTezUgA
nxSRsn5gUaYKYyVVi5SM2U/cUv237382QvUVA+RQPe1Uy32FHcNa0F6najpHon6UOaWr18JLWlF0
UplGylPNGAdrMOgeG/hKdGQDyGU2GM6J6rnBcgfze7eo68tUdmkaYQxERBZ3f51qS4IPF0l48Gig
v+1hbZgiLxr0LII7yzfYDSZ6M9UvhuFI0PsZLU2buEz58P5fz0pRQOl62rRIxFYTY+4nccB1tqte
/txrQL6UY9lOxkB5En+LgKc+9eENMgwy4kmSI7bSc2RrE8FfWYyE8UdU/XhNvI5S8leWGSaqSdCO
g9uIYuwUFWyKL9wizebZFKmlXoqsqumdOska564k3ia+NGQyYps8TE4okPpQreGpe6F6OTxM+FYj
Ka25szg2hJd+TxLVSMaNmw2x/e7z0sw7FAWhHlT0w5QxjMfM8jCdwNUR3XRNQ/fU8k8V+Gp43Oom
pqECR7kvVVK4eTUXhNtedxLL3QJNufohmqdsM+pdIUOju6lpNzDc6Kc/xn52HTjijN2C8t4cEvop
xhTfCfntii+/Ld8NsAiZrOHv3LzK9JiFW0za4+2SD9FL+9+Dea//0LW8F4Nnmc4YwPJcghqed47H
XqiK+ayTEyxihYZpHWnUwXSUbeK+vT61nrhVKAhm/5vJxC9Sg7TuDqpph9bFFSaHG9EgNaw1G8pi
C4YYfgVCIWgNwvoxmwakdN4n7NiCQ3vdfVw70fWX33yMONFwLzPUdHiUPeEAA+qPTooNEVKa76vS
jC2qd03bcUNixX8ADUfyVNf1E8FaEZhz6rpBCGhayVCiDCireTIPPOKCrKt8EODMEHE96OmroIbI
CmxV0J5u2ySiA6efed3K7wb7uJCgewqx7ZdlXfNHg51hg3jzxFTQeeUw5AWo88ccVtvovzn8Cjpb
8FAWDFYprEcAhxa3jrn8kyoqv9lShuEXMVhH1o5T2HHkbHOoaVgGXSHK4vrGLWP6WIz0pGGPfAof
eQuJ0q1dvMU1sQrlA3po3NTGO0cAnRTeEmu6iGS2yfZRLLZ3VXqMNrjJa6vA9la8N3Jw9S/pUBrt
OoID1p7WF1FMdphjHxq9c6C0XO+rDZ8cVRiihFnBhi4viFGqpwV4qDomh2qiI9LNIJ0bfszYvDHf
//PiEZuEeRigNcz54K9oOvizKBe3WJqiwGLYzkOElU3A7pyvO4PKnZzyiYs1D8I6fo7wnyls+yLi
MZ3i71L7yTXXH2W2tvEKq7MHyxPHSoakraVVX7nBRLENjXIDuk9fNu1uoNEGMlNlW1doHqX+m8Qa
KOuvyU5qvpXhie9aitCC/zuD6FW30jP8lajE61fWehKrndBdKuKTeaYGDQCtWSzPcyRCbHHTZxS1
7FmQRxVvOzFTRPlrtamzvsZEHHZB5frtBwcf8AezkMfUNesINaun7JYg9Z683R+FATpVELJmSu9s
ICjVAhitXYwiyQ92zOhvY+TBLJS9oBfTtzmY+Nu1pn+O5DCLL/hQDwHaUft1DAsgRd8UwG5N8yxl
NWak4B0hBZ4djg58hJqxIwNRkub2IMfzBx/nJMpo4qoZd3+WQueRry+gUYglv016OAX4aQzI2dqZ
Am30j6dvF6QJznMXlHrKTj+bG3QEb/k0Mdwdue7IavaUmkYU5ttp8MXWqLYmO2KZQTEX0eUPW0cA
frzpZg2yPOBFhTOWXGHusgkwG+iXn643ylJ0K+ioiUExhukxrNaxyH5qs2cJgO7V7b5u6ITy3CII
ExK8eecJC6d8/L7UEBPrFggLPEBw2DchZB0/BB2DscSfhLJ/H9q0w6T8vRMXldK1g+JEC6M1RPaj
kkxeNbU5+XPDsbx2Y3+yhzkB9Ye54pqshRXTNeZBFDzhJq6lMLG1tI2hLX1dVpRNfznPCevyr5fE
8MD0jleQUcPO+YasqcZOaT5zZzk5ZimrNtyxFhbwmX256zXowa3/mlhlyLHGB9QvoPlKHhWTM9Bj
APJvc0ncE3ck1QBHF98xfvVyJNFRNVowCT8NiMvCOfjOHWaHaL2B+sRTduWwOKts23Ggvibbx8oP
2AzGiIX7pGl+8ERopOO+q3xY8xaKTX3OAU8Zu2ASESvv1CQPvE0DMABfr1nstgshrXlBUOGHjzxf
CnhLy59WR8Pvu2leHBLLYGCONRE/zuLHyKkLKHGBk1wPKMIF5TwYaLwK1pTgjc+pNLysHAnRt3x1
ZqgifvmKTUOh4XciqApdW4VLXHKI3zE5ct5LJKixldntm5v8ozeO8Sp6euiASA1GqSAO1kGhD7BR
tNApNgqkE3duFwB5rCflLzWAC1QbYnRuUHSkwxj5+DA8IikE+vh8z+VzSQBl7rYKH/TgCfIUpUW1
ZqdkVIv8HDY6F9piNpE4SqWPh81Z/RyYqtN/qy9TQMfNyRQvsthhvWpRm+aOQu2HAZ24wFtY/6Yh
Qw5zlASjkN035RHxHFpxP0200w/GOHpIFRRAIIMBQUje0vk8RwwvDOHTU9TgU9PDf2HxUbHCHsgy
3la8PnLANNq4bMujodde48LMSBNdmyF/+U9TqaXayVd3uakREil93RDH3OoNxa5WNsF6muhz/oDq
OJeQaqoM9aEE+Cv2/kNlj7HLEO0vUhgMLrf9GAJecwTT09yC6r4nMlkFWI0FgKewCV26P9ytvn3G
/37OTJot4orqT+3Y8RCyv0g1kMs3Jhisf9YoDXaSqEq4+GNPRBWWU2YW3c9vdK2lVYQWiPm5twsq
O/dhdBnm5UhkGRHS2ie7Z3D2WCi/b2aZ6oA106wlVLg44Psb/dfuy8HMA+it3eD/Xmyr6RpLkAb9
D0/vpiUnn4DY+jD5TDHfYzzFCRJxCIRlsEZBNFLv32tSKgdIfJ9QNSXXRrOh7/pdZzOAS4fxy/xA
ioOYBIoXJYnS/ygvRIdEJ74f3O705u93jNENzJq7dvJfzu93pQgbFvAksxAanuo/bEoPP5MI2Cmy
txkWK2MnY6zsTg1jARROSrVgCM9oES1zJ7F6FKZGIJ/o08IFe9z4aDmcYSxjAeeh4vAlAz6YTWdW
WTWh+K/kC0XkcfgfLBjXNWqTwbQiggvjGgGY61pHHDa1+PlucM+K9hR1mHlfzSXgqJ70hqpQKmjX
xz194YoNRE+Zso9FN0jDDHxQpfGkvcitpX0WLEOqaTPpoMrcShF8OCrMN71sqk6raOC3ipHvThsR
r8SXsdagfcr0OkNhWHk1eoNXJ2LNQtpSlITCtYwxwCUJmzm5OtQUnT+1g1QSEaJyYT5TAEA24JC8
16sfqAaEGR0xBOul7p9eAMUJUh23ClTb4ulXR9oCYg7pwelLcmMnac+/9iXmsuHdZOp1OkI3k1BG
ZqhhbEnlOnZYKyZBPw2R2m7yr3oALWniD+NxKfT3vMzcQ8ffb+XRLBwuzSUuBSwyD2uMXugRs2QF
Au3Qs50BoULJfXeOWGCmiGo2KoJVwLDvJ423YSr7sYHkTVa6RTWZDfIU4sdcT0xnbfVmQJk+oZ/w
Ai+JoZiVsLnujgbZ5fs+nra7/zOxy1lpZL2FL18NERvVSy0qV3IS/c6TUMwnwoO3kOUPCzx0qSjH
kd4/21uUEtkH0Kc6PsY2EGqiq2iHT4LjriGuW1Bwlqs4Nh9l/3ejPaWN3ox2J6UvgjB5JHf44ddQ
JR7jHDeYGLYonRc3GtHoTas0nrGrM2PfPkwjr+f9lWuvowFEg0+ZSA4dy9IpoaNrS+zWJ8vYuCQY
5lW7UHeOxxnlMoZVUher1EP5PB810KL7xfBsHJy8oDjD1Ooo3mFam9VXCsZT48uwXC/aKLZYVkWz
eKNXdRddDbMAjOcw7z7yWpXzV9F0RL6+WSJMzXnusDIDvyrs1/Sv+lrCPR7Ax0ibtMj590DWkP3C
ou3I3bXCQ1Z58WQP9I1n8ds/+fqWTkzyedCJUMxcc5TSZm5cGgoGlxYPEtFgAO2UY90zR6Xh3MLx
COZ+BkwJDLRC3zxjjsHZg4P/mnN/V4SGsWpGIhd7N0vV4qighlh9nd/lg2OJ+RSjK/ASGvReFg+Z
6Ti8XTZf/LX0od3SV0y9rgnff4mu/4kJIypYQEk9QH7h740dKLQI987l+Yp2Pk5+JzF6IhueGoh4
HCYJoBdyd4P+xxN/saz+smL0rSR2jL1/HWmvudC/fc8gTiIOIDUIzSYoD4paQjICy33BD/tZC2l3
BJhX4z12oFw5Am7YNirA05fywDqBD5iwr/LYoEOIcYwDxGrTysVLHAEX4BcHh9VxkYqFLSh7Ofln
++5edoi8ln/W6hXoSvTE5BLaN8kLvpvgaS0iSoMPSLLeTG9v9PLWJSyqsqgVUy3R1WZpyiErzjTp
avUMNH4GerKZ7GQBB2QvNgQpQWIuSRBzUUIgzolR6LfEgyF29bNlyMZs/UspGzVVKF9W/hfXkH2U
npo5neZzNnf31icab8BWcuvYo+8i9QTPi5SioUAXRun82OR6ZLJ4GuDtF6uP/tCjsBRK4eCQMmPP
eEzzILttdLGucc2NlajrjlpL3KwGdA/UCsJyZZMF6Xvr7vDWJLARL/ke2l1L4pgCAA6QpxEHinO7
poAnsntJttn7w+20G641TrF+D2q8dhOM8XDGEjGNv1BTPTjk9D3yex0gHEOy7IN9J4HCwT9CZFEE
mn/aVaKclAsug4WE89YBIxUdsJICvjantA9iOtvGuLSDtCsYqA3SfGWAAuTyL8ZyJKchHQFcmszc
G55Vb01Gzmd6imZ835zUXohgUYa4iDB8b3L87s5rbvEcn3k7x6mXxcPyW/g19afxAukSBnWrL+Ay
KKVOisvgt7ewcravWfjsBRIahqYn9wCcHB69vGO1y1lpyPNM3G+pWit+jj1Te6JZ7Es47YUzLNhn
Y90jaEG0ewNRA3WI6yVXzPJljjEkc/kOrMZYa/b1xkzRIrY5jPw2hhg0eiN5lAZYW4TilX5jNGNJ
XilLP00M2zMT+eqe37kgZV5ckCEwQFbSkRVd4XThh+wd37J2hR8BDrxALMnx0h0DIZ1XLQuEjY3n
l6dRb4Mud8Bt1Y5ogGepYaPPn6/Jn2EMv2rJ/UUoLgBL2O4elAh4G0tVG1SXvs1bmhhE/xJE5JAf
x9CFLqTXzLkQ0JIrwRYO024zPXvta5T2ZJvW0bto7Qroslh3TMC8m0OrpfiwSjFQXUx6q4NSK/Gd
AkpnYoQvQpNo4MHG+OC6iFY7ysME/eyYjDEOUSTdiVXCTbqBz7gnw7eT1sQs3VFs0REPkT/OeZyj
SFOuo298pYXmPBru8WMidcSUGK1kg7+tI03vN5p1WuH4nC8UceiCW+KS5tjAEop+Ayueil/XOp18
Z2E0rgoWtD+9H3Olqpr1ih3YulenFiHHuLeVqQlF1bf9NxQs/7oNNVNdRa/veovcPVZvNZj2XENO
zcZ2tb/oj6dfFdwF/3Kt3btRVMg9BJm4zSqbfYkWoDr8XP7J3dycK37UgvKL16a5G7H0fiiVrT8U
gy2gIdiOAezDNEZPu2J1b6KayoM9G1e/huahIP5VFKBFX9o99nq+9OguHi+IBt8CQ9ilz7N7yDcf
OySyqpqdEllCOqNLrcVPdr0V5jja2itdsvF9i7kRSHb6Rue1QrQhiUSs5JkBYEmxEDY8x28wnh3x
BXZTAurcKR3GPaJ7o86CgdXtCevYGF4sgkrNITmulLwz1YPmOsEgwn2vZdp8/e+nb57vQuosVMlg
mrik28o+drn6LgOEjCBjC/fEFFJUOAi+oMsCEjDUL7C8MAkT6yE4LTti8T16QsKzrX1SqiEuH+ud
HOJGa4IokzZ05cJzR6BfwJ4TIZpKR9R9hDiN08AEe1euCn1dz4sRSKqLGhXZm4dxpVK0ROzNm2a0
k1epCbAjEjxhcF065/eFbhIwryBkjXOYyyzJDI7N5oL/YVzXjYLLZSl5u3N2pBbJ4x3HhkrJAEtn
ltytSJ0HkWSEMXesHic2UYKt4p6Ee7eHOVb3cyVCWddWlW/H85F9Sc0uxiUsxVaZt1uKCirBbIH+
/v6AtGqlWdhNPvEsHwVhqelkn3k8NEQEYs/Yb0t2Qlgd+a/hhOHUV4HtdRFUbB1P7XsYDTOZ4tui
NORbERskw+FNyG0UEuwELL6s79qdfh1cy06BJyM5U3UOwHSnjXE+LnzF9CO8UpOaW8z2nikWtNPL
razMZCaw1Eq8umdjWd3UVm78nj91i454xYdlQ9e4ysGSjQr+viv5loxnTN/0T1C81rFVNXrOgUEM
1aNbsgZ4pVrDNh5EZlweZ9pQC18KMeXBTo0aS/P7OUtjC4lQ3x3eLij0YfGvuGzvcX1jwEE2pJTk
1INF2KR04KShuW9X9NiVBflzxlAZSbxQE65T2g0OM+yFRixVs6naF/s5lW60IY+gj90sNN17bQQM
87cX1ULfsZXUsm3g2yDK7QgXatHhpmBJ4VAVq6BWsiXxabIzlCA6M2CZktm+1JcscvGrsNMy8Usw
6jupPaOIHkHAdpK6vYWiYhBm6BQhqNVa5JxuULNiN6ekzeL2TC6rycmAPhU1b2InbMgQvW48jW19
ZST4mUxEKtfNyf1N+jdVmI3LL79gVivLNKs5JLQcSSAp+G9v6kxyiFCISu7E4ezqBsWxH+6INoF1
CbOuUiwi+Vt8c3eBR3o+eaMR+e/yohMF9UizZjNk8L5LQeyUeQJx6HWDoI1goC2eAxgLzURKZ72i
686pBNTxKIcNRhBsqPyCVGPRYG60bPjg3fm3K54+a2wrOxDgnxPuGy1dsvs9u1mchsbgz+kfH3zC
kSpKlsLoBtRmAbgivDCstDM0wecxPfXhHME53mUsVwZSnHOqrcOsCpQc+Pl1v10qxryCgozEpC9k
HXFn/WYWB64Z5HFd/t2nPKLPHpTOGNDxIE4Nanj6nThvcjiF/ZxsOx4QAXWopr2KSSLyPd5OegDL
8ZZDNle1WLx54uTK2tZ+p0niRTrDrgGMR0sOtYLCX2oAoTkR2y3wgNQIHluoteLzaNz1voMX9xwS
Oimfm1wSw5i4VarUn8xF1G+cmlo14EdXVW+r2DkOnFelA9j/dv9Fmffj526d9HDMZDWAJqdU45qn
t/mgnwhrZoYFsdKqByhtZY+9A4B4FHWcG8x6mRpW9Ao3Leoix6mNmJ9g1YvqYL2Fd7Pzzay02XKQ
YQ0hZOKdpoLmVF9Mkd72InVFyYv56s1vide71sFECTshBen3f2Lc+m4DwNqPfv87d+/No63W0xRF
vKIz2YAEB5ru8zzeKn9ooovfh0nP3Kl/OP6E61pgLQNd84zAN8Xvcv2Nd+wvKV3Yk1yFjgMulim0
MGi36zx6emDz0pPtheurZghJgbVKM5JFrwSsfT8uHn2eNYJAOdft55XWu+dkIxKtGP02U622ZQos
F+8mG6amKPXW+OByiUVVjh/iDm+5w3QP4tj9mnU1sVt+/kl3rXT/PTy1N8pJyP8m2tkqKJyYjGr4
SKur7XNZDwLLF6Shq9DuGjGakKrRAxxKKIYLpPFpiWuChWVZhcqYjN8jaRuHi9updR+OJfoMva76
WMW+XKplTVh1/+uF91glbUc5hazuqvsRRAwJGSqVKzsCYB1FNkHfA50ri8v+5Dak6ikZdgrlEW44
Mpg12tE91vj6BizsYzDu7lAH2LKNnNLOEhyh5sWJeKxxamSRr8T1JFT8BID+6dz/KYskNYIbugvb
btRtAjSioWzKjYIdqfqkyWuqa578LIImMg9V+vK6g+k+/uHAoZqrNDucdJCZPI91rgLrt2r/dTvf
jjr+sQn0L9s8dPwgR4tYvLn1Ywxzqog7M/hQ+8GSjqiwp4PbNwbpEVpEjPlvLP8HnhCPM5+QHYlC
L2T9zgce2bHlr2mEirgs2nK8Jl0Sndn7Z7bsJjgpSfmT2Vy5tq8NUPAroq03YzpmxXaM3KN/L+z8
7zcPMNn6pFqgyobpF1e1RaXgNoKHwWUNfqJ/sRipVljvLN+gZkIQuEHBticZi8VVjn4WSwGG9Zo9
0N2eFoRfGV78xdYxJU8ugxffBwwJwS4qhsk3m+ZYWPQ4FiAZ1uxB5MmEY6C8NHp4z8int9lpqkBF
ckz3zU+ItKvew3ECXT60yVZ6DYx9RiPnmK4c3Jm1APpv8GJyJ+5DZvKt/dHLz/gxnIfejV8kZ69U
3oPdoKCaaNy6DKF9kjxCLHttwTFMIsBNvgrAuH82Rorm1cdINo5XeSRIZtan2TTm/Stp5Yf4r6gB
KWbYOhGPfT456OyTBwrTvI9ddtwAb2PYEIBnvAdLJL5gKWo5iJEsmv/MlOLvwA1LWzKZPB7vH1aE
C50LhIzHfXOybAMPFYLU7r0H5LI3BWAHAqsFSY3ikV0JMKckTLEuvpnM91Csbbz+le7mpPlqlsAs
HN1fAuLEPaw000Dwxf44uH7GXaTbIr2b5w1zQFbagfaw1rMbbrHfQ8tXNbj69gEJGLdwIxGf/vEK
ijbCb07jqgmgX29nxffBNz1wPy7Hnv11PU+csLV71GggKcZiybRhAM4MN6r0oBkG/IShcXxzwLB2
9TSXtQqWqCKXpZOl2VyfWn7gmevdHaXPAwvhFR2lzxquoC7T9uDtFQVfWL8ihloDSHffhEP+0JMw
N1gZaLyifCia+nxFkyaum5q+RWMu02ie9m85+roiL6zenUx/Zm+rZmRik9xZyy1HCrquOKk7HsiM
W8p6fJKYbifFnXgeAJumfvl2wZP8peUajTua9di2GV0F7avEwS/BS/WwrgijYv4Y55Y6jia9Qk+V
u1GUfxirdm8M+OpKxbSi+5piNtGRD1iLMWgZil4suHNPBy4IEm7u6JAOy0qN4i0llRCI/G2a9GJq
wL9iWDni15782vovW1fUBNftEsuFMFaiiryzNlwdH2NiLmxcv1bNX+3axrrFIl+Xsic2cUCRFLWe
Qlk4ZQpsc6sQS6O2JvVoKUZL2mTwGpvTlbaA/7hUrvkO8LN9L317CYqJpFBnrcHoOtnVphLzoJg4
lXqFojUzFrUk2uU8GcwWoN+5/B+G3niTc5+cnPKWXYOdg5c571MTJAXlz9lGKoZK1/UBVdyBeVY/
3DSeIuIpnZQXSJXIhGdGjhVvcu8bbW0epn5VQFYnUnLC+qWWqw9IzCYYcRL+80q9M4npEIiJlbLa
1jL9uKdKbaFItTs7BM+anrdrNx5T8vf1+CEQnbUd71sH5npxzSVSnqythlUYHx1OfGo2182xrBPM
v2Ok78XquyYhk5alHnjQoFv54rkSgxL+ynpS/G+2NlE0Sb9nkjMI5LkWo5PE9R/KvWqQPX45IZPn
CxRBcduMCbwBsBsS4y7/KsxArcYjf7WP/X5KTwQYWOKWJbivmn8agvKBeQQOBe8+d5JPqhbEb+R3
s82cerHqu3wjlWikMiNnXraj6B3cEvlWmvsF6fBa+dojKRVIkHGd8o9auIMaqyH5Rua3sx3IrAsX
D6eCFM5ifznCjGK4erHeD/N5SqMFcoTZTMKVrvuvA42+txe0vwSimN0omTGvZwdmqkGSEehEoytG
MAqqrm5Rfovh4rHw+1jYRwObPIp5XOuzCVjK8r0XBa1f/nofVgoFOPdUE/0/vYe396U4ky35Wy59
n1/DNkPz57GqLm9hF0q1RByxIrL6Cb204AWOSxIk5XLX98i1Uv0Mlg8BjgRMnpSvMNR4sgVg5wIi
UddWzPMvPgbglSw1lpAARzWMsPwj7VIVospXXavUfYDFx6gS0DqDLA+vjB/kHwZlKR/7Qsbo6/jC
MLh3pgVELPLSy49XB9rI7hAU0ExDGv4VoAWSncX/IBfK2/9LvbSN0XwSj8XyGPdNkqkSXF47ZzSx
9cmlQ1pSgMhoxnvnuxtfqOi1KQ1yk479yDVGlmC40/kMdrYPL9CKfk3tHIJNKEt/fInPVEEeOHIf
yZ7J4sGEHvQhyY0PAD5opEer1BTN6JgIkETP2NxDr0michgqV5aiy2EG+sY6iHs169QRmyY+QsEJ
o4WoCyN5EMvSYi39isAx5+TiWNb1pR5RqcglSg8NYtVcVfkBrqpCfCCjGwWcomqXkecvLP0xPVMe
CqyIRHihb5lyu2270ziVL9tSs3A756P1rvjWM/uoxbVu0RW1+agBE+Ezhl8I72+7Ni+C5cjo1SWz
yIkJ4xrrb24gC7Ff9+DYenS+jVsr6vQn4fPVs1bwtnMH1+GRwg2Z9gBQleTU7nHD13ZAnMlWRdl+
6QKItJXdL4gp5wOF1nk5tyJAO28IlAnI9kx5PzlX5W+zecrxDhN1ILI6c9zpFhIKTY82jrEPVEW3
mmHJsMcyh9kkMdpqP81fBIf6FrLAIvTvjS453HMIGBz0hmR5MA6/0RMWPmS94ouNUIxJvwKj44f2
kzWsaM5TtfHK6FF2CfBbvKmZyBmiAMKB/iL5kW23NDGLUA70mwWiQNMSGxkCWp11h7CkQPz4WnWs
X45FJPZLErIcHMyuByXvAninMDWhDCZoTjc/ppD6kEOPsu3scWOLlhqESLpoRzU7ZTRC520sY+ja
nvzEUcoKEKYc5Ml6GArhjUYGKV+Q7PWqaJdQIrJEaI5WXu7tw901DcKm/HG3bZpWLIMVWukPKCQ0
nmFCbf0MOdMqx0xnRu5nxpkQOqQ8/9RPvCVr+3t5ysbUXlv2kgKtslACJbg5z/yonbDTVHbc1gDW
YvxK3UmbzAtGP1+YFqitSqMlAqooYiC09FoZmHWcnbF5EWCL5c4MLStF/ZigyPXY2YUIrkzmuDq0
9SX90IRc0U9LI4YmcsWZh6pOWV0KDKMvWwn0lMacRh5PdWOdSQQeMXE7OiPbl7689gqpr02/0SSR
xDfRBm8URigHrSgH6Xmc/vBzXc8cvS5LZoO5nv6uf7uBf+WBnTI8H+hKjHCbgc5zDv06q04Du2KN
kVtmLnK/qXRZmQuxedMcLh87/9g2QMQOo0cWoMyGH3+xYKj7C6SUNnv5Wid49q7O3ixgGdWRqUeh
5i/mKMtNIierj5CiQd4rh+2kfyzElCyQ/fYhdzZg1iLG1WFeGi3TUxeweGsu0NWGetV/5X1zEg34
PA7jtqJvkjWl20qfgVsbOckHFHMpcJrCi0Hs3aOHDI/p5oQ0gAJBgZSDEVPEaG/x3w+isXygMi3L
4OOhnQe46ksDnnEtNwVVFCk2MyXUVCRsdz7b1tU7EbBgpftZ3n/p0DeXeyovS8RJ+rrfaYAtd1GC
Fqh2+Hp6YRHZV4/80WQgHFkyDcj9aVkxYecJ4g6iSIoK1QOoJgT0QOpcnMf60wbNgippFyodliMT
QH2X5g3exs3uR0k2udEtPXUj1cfyVmzoJVVjIhHrGSFne5ce76JuXQVkdfnWub9l04UIMcd1TVg3
8tyPzCbmpfMdjMXhlNF0lb3QlgdOBwLiWPU4hl0/JZWZPqaj9VtsHWJdwncBXeZrQxy7myH/FLic
uVF/E/e2N71lue7rWE7WEjgF5ib1A6buoR9he38u1P68H445vZAkeGDxgevn5tKbsnmYgbdfZr/w
Ci2iLARWxcQBnAZfRg3ESMifsPe24HkWuvrd/85a3wfpWld3Voc7CYxrOmheRhUWBl4+W+uyIDTo
I6XaqGmHLAgfmWafsKduzIseIrWQ4CQJQHMcpMc/TFCnrhOJNsaMFEwMZPfM1RefJqtqSftNxzBl
0C8YJCLtcZeANdwey5K0ls7cBIiGMT2tpGVctAvdqjgvncr3bg8REqlu6+yHXsFryQ6LMxA9u6Qv
eDkTAc69EeSVxyjW55XMAKsfdez+sDnnmNAWzkZ6RGjG7e7ACJvGfslkNwkvTm5djcyemYN/oAKD
FHnJ4uukKMueC/KrZOqcIOd4scAbD3uLW+A80niiY4VtoU4k7x4+PjaVUCnt4CEq/U+p8lehTt4l
nCrQP5J4poEP3ChNeJ+azOCx6erEqESfVgSKSpGtLfpUwrmWpU2x5si2MQz1o/Hc4ipc9AxvLFyo
pZWcseNEOvw6OS6sg3nlzgXJKgtXRPuggYBgel6nFRTOmXsywD/gVs8S8FdTtELimxkjpmJEltLj
0R5r1kfKypYX5srcV7yFWFh2xLhvFOouePD5Th7b3WPOrkhH3M2oSKstq7f6BwpykWlgMhrKPdM6
Zdh/TqxuUGqrXgy3P0ay+br92B7MX5WQRJzGCjSuR05fiOXXji26nuz0/+tzZci0DsTgItgjX9By
F6nUnNB450OHgsyNx0g3CqNmy4hLROoSDFbEVRClQJdtlz2uSZIxQBsp7UgxUz27x74WFweSiNaF
PNsChQyUaaolX3MHXxNbfeq1uID4nEGKHG+6abY5VyPVSq9Ykf4FngigyLcfZy0XHuv9CXdT/zNo
GadIIUcOqku2NFSMjhQrM2QhiFPLxESnlcuM2kMbB1NVHYajainzi9ugMzo7YIXmayciH+Pvp7qr
YVye7wI0eWr9iUB+WABxY4Ka80cBP9VID/YHsbr+a5CYW7jDYpp8yXRwflVN1BvOgLwweR+GBHCR
Jzn0ItvgXl2DJEpcR5Mpj5waWDQqUTIadVbEFXLcZg91tvupjvs3Dpt7YUkf4yVpveyEUNQWYv5E
/BwHipuyYibWP+N7HMhVUYtbdu3U14x1eNancUXwgFoCY4aKNPEejBBXNEmG26VT06u0I7x6uf7s
M7NSsEub8mktEa83wQJxQyIE2O/69MDm995fqT+1o4kohGPp9lGII9BzypuHN4QcjX8ErSHTbJJR
dm7SvTU702waHVBTj7f6OWjLlhNalwCKPXrC1a6FxeXy/q0U+lRFOxHGDIHg/dHRfuZz5oMB6G/X
nKkoljFqE1ahHZ4xBnXbf9Ue5sviPxvgRtPUQlVWvldcFGqRgPTi1RBpohZ6UU/HjIpQOmo9gjwW
9Ft1MOM+DaXfImT0zys/TU7c5yPL1odi4wdoZJF0LCAPJiVPg2kayRKLfxJ/g5oQICUCoE11TjKi
udfXONvWMEm7z4t+wmQqX+HPopMgXn8ZaJtqf0E4Cz3Mjf89f3+UF4yncK61ET/5D1Lsm1n4j9yC
wqw8C9wjeOWWX/hPuiOhzTT0ZwuvivCOIHotTpdGg72ybLIyKG725EaZeLXnoZGRxQS82qyO9HP+
H053dxSVoaZn1Lg2xNZY8krDsxNvfid3f3NL0J7nRGXRwXbR8/J2SNYvFRc6TpB+gXF1UlI+Pe1n
aSv+H6Bg0HdRRhVCZC/Iwz0mg6l9y1lBh3GvH+KANV83OmmJJemA3BBLohUG1pTlHqZZ0iVudgxk
KsvP1QxnggP9E/fjxGphVU5KnrqoOrtNTLkJL07YRQ7HkhP7pG7wXL3hlm8EacLr4d6Qo3L0YNxl
D+04HPE+IgemEsJwaRmBFCT+00XX9H7QBG4IPNAVX6vAf+GOhvqMLd7x+bCg0OPzOK9a/wUixRB1
gZKjJEl/IN9Wh/OgrmWgFyDKNWnLXh1iwGa8fppMnHW3TQs/CkIgjgOQSINm/ZgTDnp21E60wADV
N+bTX9mAHrYAzi/ZO8QXHbhIFwjADKB8sS5Wg9AtP+TZDLPob8QmiD1WGKyuTaxKg92L0eTGKG0d
ajXRUW+ZGsLF0QnxAgM3cUPwXy+Q9Ne8LzxLyc7aWG45xlGC3Li+bhVRtq1q6Lji4/StAjPmQKlc
Scii8++Vf0l9R8hQZZrPv9mSsLHjyrwZv9gkT3Tg+rMoaDultqU1OclrTIwr4b21yeZpDZa9MUGR
iRf9PFqcUqxPZuCuTIn10NaXbxcn+mKjg9VkQ2LCYP5ZALeY6eosLEaSOAGXE0dx8OS9fhoBeXPq
FjNfE+/558DBi7Hj2FjIo2duKcAHrpFFktezcv2pn9eQKdzP4DB2E6ggtkgJGDaaw2j7cNRZePGh
J9im8TazgNOz9KzcNVENFrqdi8f/awLZNIMk/Q4xQngLE75qbwwy0AJaW7tX6VIQyQ1Ow5+g51DB
jY7ytXwwHH5SjwMCwDUp1pyhDD1xod8loz3QtnCBwwUM5xfm/t6wlN5476q/g61HnBjuKeyJsslN
U1n3eVkIzpyi7uJRPbNlEgVUk8vqGwuY2OTy0YKFQ9VdCCqPtwFgktbfu962dK+J2CBqzK6vAJBZ
IyHDZVhBlNbhgrG0fESdVOrA7F1Djn5bTkym1tvOBpWLmLPHAJ2ztFhz3p5Ch0KvG4+GxL8KtzIY
KEnwFbhPTlZuSk8/ofnbPIEbXkptUIzvDB4zjaysuwiYCmIQ3FOsigWNQxHybthobAJQKUG/XByf
fkqM6H9pq9gYc8ry+2WkmHp01fLKJEJsYoIBZjMMutURPoPD9+H+WL9wtJmNdp4FHP/LlkWJF+m/
N+Yu7fYO966OH73r7uYO1+u10R6rvEqqLA9A5qS0y/vkEoChXFmC2HhAtQmnBIYRfhMgXQwQyX6f
UvnXwzMGZKyInOjOzyyWqDPBcFMtVx+kKKFc7qfM2cEwcaCs/VsuTLYNgdlBeC9cxlvXjo+mb6aA
zePgi62H2t/4+i6uXTFAGo1m4voKtna9WntQ6sBXA0IbJbbQykrWPt3RQLCsnizh56mEGODxBwIH
QO8rUqf+rBGRdrHUOIvhYumjJt4RTIGpgPr6kAXf04gyRz5J1UGQovJXbdMNW2UiEidA6nU8ZLYF
VXjkxpCJQk8ORGfExHP/v0LAOgLBouYZx7avimtSPHz5dCm+BaV7b4QoDYdSKuORS33HFIm12Q+A
jtgP76Fv0uN1YEHdsRBjZNPAfDdGNaS3vFVy0qSmFX+i/DAW6bSxgpWKRJX9MhYWAcF1LmRGIcAG
zd0ThUDtaBTXwzNTk2qlE4Gpch7/8r94ph7lQVVsmneaUtybyzra9OXSURpccriY8FicVL4GaEW/
uUnYaW5ABEeXzQGNgwbTwtmycL6TkxOcGDyUDMLzMHj2Ahb7HYGPuW31StlRQb+htxTN0o1iVSuy
TdGo1tuKRfO10RWwlv/jE5jY34nwXcnis+88UqLTLnV8b13t1zd+cWKzyBvgfbc5yog0XXpGAr9W
bCDeOo+SDebfhvLFb/10Fg0/rcfr7/hEcowzS0a63gi5RrHEmk7+k9Q2zamnpVpfZ/0Qyusk/IR+
XGjNGcOLTvkmFFlHaNDYFstF01UMYhCd3UC8eEnDsuFz1LIr8su2QCYo/Nhjwrlk5wy1LgM4m8KF
oJrdJ7PMT1guyIHJDSHsg9sO4PhXa9l+l1+lXHsXBSBxSvhBurzWSyXQuv4JoIhwmlwBCFZaUnPr
T2OAWwAd0TulZDnqd2zoSzcvL+zcdIt8fJfyRhMdGbbmEGplIkOgt1WQXjRHQanPgp6PLQSZN8OF
2xYn2biEOtCEydwz5NZZPMC3PCs2ie7i20mg6wPl2rCJuh/f1y4SUHs/BfTw4wjUnUA2qBTvoj2S
6oXMsBD/OK4Eh1gWZBElhFo1IQz169vRAROopergmJ4LkBllShDVBf1NSSfQQhaaIE+FoiPXwoJF
TP8bK18OiZwYFdTx1XlMKoSeolXYGqehcTIcY2rLeEqY2EllN8pfUZQCLQncTKhkqEE/cPSes+l5
5sSGiZxwHO5rfxQmwFD8pcHoCLD7kHB8/fY5FywGBI/DhN+GpzLJX3fZFHV1K4SYjXYwhAusXepO
3JYhgdVN8BLxsRmAf+kt4TQx1BCn2mVJ3CEvK6oKkJb7aSt5bXCH2FKPy3EXDNI9bOSECSSIdhl9
8UloODnQp8TvQFf+SpXaCP9ZVHS1Hpc9LnowaLzPhjEkkyQUk2NSBPjeNmRgnMz12/ES2d9VrN0u
ElxIOtNVjFaZusrogpP4J64eTOwbDCmf+nLie2Z3WtN/0pRwStcc7+7Jv0M9gMtbtIX6VDjEu/RV
uzLXmSBh+hx7hV+fNzkJpD3/vhN3WvI/qsL8HxwA0Uix54ujqOVm5t76DWenBFt0LZVWIB2k2EZh
exhTP+S+Jr2erVnxBp6ribKuF5QUFK1uIE6Z3HE8ceWavLwHCiFrgdOLv14Ucy8XbJqJ0/sdt4XG
ANC5pi+AwuKbex1WYeuR6qrlp/9SKjbqrzDgdW3JvSuS6gAy/s9AUxuSR8p4k/S5Cvmbk9t0N2UN
DusqNdLtQn8nLoMbGrfsqz0y3Eqx5xTyFErunddbKfJheeXouI4JMeaZTDvcxsaqoelYmxtrTP9b
3apIBlG5q8JsJIbM7QVPgui74BADBbT8UFpGY87djNgNCI65OLNbPZo/WQgRKBl4ehFjLRLfDcBD
XGs3MfV569mraU5eFQFx4j5nTXCLLGnpz3An4L5du07soJnJwoZqw4fjA/KRuXPkv9v0Xn9sfXDr
evW1NIbj1NgHYv2kceaEHDKMwTIp0q2TQVw9ULsWLVO6JPld6x9DiAzBiv0J0uYhIuYdewAjRLCk
wNyO7ifhG+Q/P1Xnf564LPM0GiCyC7tFYjyuTTeqhLQ6zKbYYYyj2aWsb4sHqhENSMUX+JV5Xkqt
tzUOuVb9+M4+U52a1LavSg8Leu3vzj6F+hU6E8lOdmLHLnld3efLn3uV5+SErXBsO1Fa8cNAUkY8
K38EAGLXFwjvRjWJD9dgVFoHsdxMfUamginZ2lhYMnp5JlcPaiQi9tNYM0HlcZjw260QXm+iMVDB
iEHfbGpyPsIkx+vdbMYW5QgTzIfr7ExMT3m+msX3XN+8ZI8Dj+KuwGBhUX5a8gTMzW3t+TD3FcWU
A1LBoTHDPvOhUHkTKhyVjtrIs8iGSoO7AZvKgBpc6CHuddL9hyyt7rCr5pTAn+u83+x4D+SPkKcw
3VyQUtMRTlzympC+MZTO7YFAWyxmDu8AZFneQa3nwgSP5jnwC8sjJyuIEdGMQwmto/GvhU+Ib7gI
ohyGPoGudBn/DesZkIGV/GUgWPxpz+xqAFDMvGM3Rj/ZNsBBb66ZK4fEESkV97bLqgE1PHN8998o
7HSRigyCQ03il4oWyd6ufkWvCxJL/5N9nl+dTloAQOJTPBLTs+VvYB+nPV3Q6op80m8PKrzHHDQc
BM+RWurk4f7O45C0E2awmUluLt1LxS3jMwdIoLlWGf12EDh9np42MMHi500sppBbxmy4d2/3Zbxa
vi0VZ5mPjf376PP1AduhYSe8z4BzFHaFQkBgq10QkQOdNuv/mb7ttVerGIwlW3bwfqZMySdG9qPj
ICjtI6yPtBnZCwUv986+dbEY/gcI+gpRoV5BQR77q8mJ6Y+UdRg9cK7AJ38HsrkDFqr2kPGcIbtm
KXVf27Hlpa+hBpiw7jXffP3qI+QLXU1iDHbp0yeoTLQd11iH240XZN4gf9OT2DXSYaCiiQFhDDQq
H4jqD3TeDAo1U0h22LiH6pviRoGjjvcGxaGeZbLiipIJPC4JUQX7Ib0OQre5x4HdvklEazYeIY3v
g2W8fn7j3Pu9FMQwgbIs58D7vZVKJ2XtGISITxltXRSHJgvNKQ3pAeUNnGp8Q8G/yFPqIT1wG4Kh
O5rXllYqhDlYDoqIpCIw9V4xL/v2U1GsWOaQkrPo8QCWJMdhUwGbTmUtcJ5cXiGYFTcFNCGJd/sv
WZ59vfsfzMnDYGyei3sRwUDcfmAXMkPQK23BKOSu6kee7Nm+vSPPiVbrRXSQNnOhdB0CqqQOVTFr
uhbEu4lbNlByOIUNiZphwuMBBMUTxvvsPaNNkhV/x9QxGI4r0/QgoPMCh/nSleYJYTWatJuHppbd
ZLzt3hffx9iQxgInqLTVfQ1g5MZ5VNgvD3wAcp9IIMMHOoYt5njrqBhJt1X6DsDO5qmu6ucPPvmD
Bn+PyQIi7lZJXeykRj/OTATFGdmYmmdtju10cd8bartPLiThYdPCj0QIqlQ+EGkKA4yJ3ZFZqudn
G0hbrwIncmDft/SBefQzPW6y9Ls+A9D+O5QUM54MV2ST5dJPa8VbBlm3B5EWo3GLyiWnub6oRDlt
UmMDmX4KhuFpB93p2ue1LpwGB3xigesycfyK9oGVWkPyhiR+6b3ZEua3qg/RxRODqUcoo53hh6CB
XgXNr78l+XF++uRoyfE1VveiRb1kZVmBd6R4IhYEldXSH30V58yM0BS0aaa0NxNC+YiSbEX/50+1
RsypA3EFM2/a251nCO0BxnproVP6KnBGRSpQaJJBzfo3DbBjvRV+vdIV9eRm0iFcu9p0+hynOqej
u7lsFolblpF1xEkrzslc80QN/Rt2qh1GfnvQZ9v7nWjgOlR3W/lXXIcPf/r6nBrT9dGFe1b8hE6K
dy3JCSbaKVAL3ulX2qxS2EIAq+8fLoD5HHEs4RuOCnE5PGcfQEsMpH/KojeWUqT1t1QUeD5CRZy+
N0DeYLuZEo+LLgGfnrADVvuUdHadqesW5IWR8pAb+3Z8a9puzrGaLlkDDFSq9gKKJvJ5NfX5dWkn
CumMScnfuwz5R4VNAwuWS11FsZsMCip66d6bwU4b4xhCjKN0KI2kFhYEcb2kQ1T9Gt72ImgeWtnF
jp7R2rQQz7SyAPBCq2oDgUOebsOgdG8bnOm+6QvFlSw5u0PpCFbQ08eleNwakzUriDrMEA+vev5b
AV16HAUS0Mtg2oXPVJcCeelHXYSqBCPSRnj0llirjRpkyeVo+ntHtitabcWbWG2wKCFGzzbHG4ec
h7pf2eL5BAClLc6t7vkwWVjxBD+okHHq/nF3E1nVYgaRLPMN2d9BV1QpkVIFI9ZQSSh48duyV3Z/
8/GmEOygl8Q21UaHyo2Byd4RkDH2Enpjxkfh//6C+/3SEtANNEJtQbBIZvrRm4J0ZnM1Ez6iWoyz
pRPMXwMLdpz5MKbUdR9si4PST09iZpi15VCGL6kejTuCmeEMqYjGk92ve31aLubZnDOdEwtakliB
Oe0Jz0J/sDWRoGwL3lq9gOKU1sD4n1X/zgiFlAoGPnUH3xqojQeaATGkbsweP0exB9wGhu5l0CtU
phq98KqNCO2oUdCfnd9eUsrcmLjUxJA7SwTjBupLywX9md0sBqS3Dgg0Wk+W9QqugRn6KNOS32nU
dgo0XPBZeY+SRgqJK01oDv1o8Rg=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EJqZdQq8nVnK5ypj58RK31/jiaVj44lXjMypHi70GZDkUwvdatIx32BwVlbE9cKUjJ40VFcWQyOE
NAQtkW9DHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
a2BNmJ0P/KDDphubQfjJh65LQONNGS+nPDI+FEBqVqVh3llYcPm9TEnuAyovIirerrM92px3IQSh
cFSpAPp4u/cd2TJsfsLOrPD9ZnxO7qy+e2JY5FpUi/XAqggR3eAOzMXj3D5VHeXdh19yOQmdTRxs
7IQJAFlwq6g8IYGzFxI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HJfCQzlhZ8q7ejhQ5EFzp0sqg3HtFae77IOdJeWcto54U3E78SpeEDF6pEhwACgUqjZfs9yzpiY1
EUUgScwgIN7Wbwe/7apXbfFWsLRTz8x5L+Yl5SnoyXFwvLOYWAMsORan8OWr23dd+9kfG7yc62pW
BjXmSWx7Wi0O9XlFgED4nL6YYV/M8k6xPyx0GNKFeG1doQNF6Utkl/sAjy9+NglHdDzTmALPsQRU
/DJUOlU3QqBR6nCUQMBlE1kkx7TEFVvhuOJDy0wsNIcbrlyf+PZm0ruu6wGyKsynW4HQx0weUNsK
ODzfMWLQQZMUTvWbLVYZberOAXQxSc+pXIpW9Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
22ja5ZdxCeErOR7hMWKMcmpZ+VKfeNCMU6DxuiFXT/HUT+7i9bqIzlJcz/hQC0EjyB23hZXTNzfm
c92ta8uxwh6+uP8+SBSMnH8ZueZAmLNf/5UV+aaOZAkmdYvLw6D4n5sDpBVVjloTF6tV/N+f8w/S
eAJYzTeQTy5nodOpg38=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bw67Aw1Vod4+yEV0TbTFZJaFDqK8HUTiXKh6QYc64hlfM5XHhrfCdy6yOxSysow3bXzUJqJGp6aw
tAeU/hA19lI2p12pRkyc7GhOjslb1ulgnqKjCqtr9jZL69HHOpRw/lg4xsvirSgCPOrQgZ5ou1ig
NA4Hat4XuLKzqjPgqzY3V1qTaS5VxOOfbavUc9WEeh/84FKAfghw7h1KPrezdYYv7QxJHnIo3IPm
sWfq56b9MNVhEvGehHmES9J4qHGzwAtzm6NNmj9TFZrDAEPLJ3yKCvXPBT441pK5ZYogHF4H18rU
kbxd7ZO/JjAzrLks2cKgQuhcXRvNBt+Vg6W2pQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74576)
`protect data_block
BDJkwKT7+i0ggT/c5enO4549jBinzkMmeYCLn8JCaIUC+BFLiKutNf75P/gZqJHJjylbcwi29Ppf
BoRPwwR6yCFQHaK7RK/tyJSqhrHrQPI0NPsTbFt718YfWa+7TeqaOGSUpzDj8X4fUIaZ0AZ3B/IV
7/TR9OZQoniDDxlFbD6m8VatDqxjUfIWhGeXwM5tCd7dS5U0gh/3yEPB1dtwryFS1mwpql1qkH1e
9LdwcEmdvg+BmV0DlJbPCILrqad9xhwl0RHqTAjf8Qrd/aJhjcCTz5H0kqrMesUAl6OOwWlSLqjI
nhAmzslqVQvJ5AJmHWE90wM/f2d17Mj0RAq7XhphqB3qM8xczw7JWNeeKGN2rN7KU1YqsPsbZ5sl
koEwaB0LX1kBvaxzCKWALvF1GMBq/mGZhmk0fmXBSU6Y//jBVYnwjB972EVPDOF+M04ERX1DIy41
WB9te1mX3OKtL/CRKvr46PJ1Egh+OnEHfg1U5ztlfhIL72c4cLrloBo++b6tOLTQy1uDPlkRVExP
n4jcamVdET2O9E1oPB3WHwLowos81mn/faGzKwSLfM1mQ8eKeMaZHInuavtF7TXhUki9R3bdK1Je
WycfLP0oj+a5HmmTi8NL1mZxnhX/FWtNr3MJyskLhtUA3g+z+toDjuS2fLQ2oyYlwtM2h0dPdRPn
imYSmVFxuZT5ZbFl6ZNg7cBPzbm57eOO6xGLkc20xn1Bus8uRoPQAhs0ib+krovRqaFlqM1mI7Ey
ymqjBI1Cmxe8CSww5RS9Nju/j03eFrGRC3tF5FmWzzUQsUTr9L9LMXwiIvR1VE+hD9/XR7YepGtN
QisrXFrMBTR3y0xnOJBUWqGWLZNTwMRcwcdE7eUnlF9m05Ho153OPr7IqeyeRC5yic5AXLpxNABn
FyfXQl68QyviGhOL7pDocNiXZeO9tD6fabEs2NdEO8P783KXZmgnpmtq5SSn1MfQW32C9yqrru23
CnqAVuoltD3sPjZaTdJxJN/Ay4St/uU07YcxmBOL3nxmiASx0waEjt/ms8Bz5/mWfRYlW+OClrEZ
+JyMy7sec6i531n6dPa4mUd9F/4Sl8lyo+UAfyFOD1fXMuw90RH1NO790kLrDa88IQh9r6uw4hHv
s3EWdMqQUPqFyqIhsE4Iv2HfAHjrcmXDu5f0hZ+WhAmN825ah2HfswcpIFZOsv0gflehS0jh7Vp/
r6JiKY4CPlB/db6KBbOiRbZQ9pDjG7K5Uc9q2W43xA00kzQ+QGIliU6qmwpCYLpfTWHEVJtlDjXI
pP9/TqGm3aXDmjnjzCqO3rcDa+y/koppwAtDQDJLo9Nwdv4WBjmJ3C0kDbrqJUgNgmYKfKOP3PTZ
CMm3s+bxeyyum7XVw7Zw1McZ0UrzKWoJDEGIwniKrvn+P122xAsxhQ64Bpdw8DISCXm06wq53KsI
MAMScBE+LBNzOLHWXaEhcgGC9LeRnmfxEg8RMUoJ/uZIx+AOrLxe6J1WzPTOF3KaXuPCQ4brhWuQ
kXb+bZk7Sy/+05LJwgxPXJd+nAAEkZrYLUvR6TCODUitqL835EIWzC/2fed6oTe3M8yP4WSU3POr
YpZ6sAlbKBEFJEFhxCH2nm/lzQNI14pw3iwzqbtAbSRj/QsrLYFs5u1vHk7Yh1m+NlyvFz+23Vd7
84sCHgKpQ8chs7N01inDLp+0OZ7hlWclTBf6sYTcLR1j76Fi5aaCTof1NUGqYt7tT0jKbHzdlP+5
ZBteEEDMur4YcXSK3PXyJr7ljZ7iifWIRTNy0r4KSsfCkC1kOofkffLYpHiF5qJTkqECwGtRcqv/
eiWMwwIdp6FXkMPDiy5CwHEWCyjZbNmM4qh5MWnWIt4QY3uw8rJAqkPXV3JZmKSMdhpSOnbgm+Vb
RYzooF4cSoCB7TJNz0cbffBP1CycaAt/TQ7cj35zgGFPvc7cqhZ6Rc+rTJro+UI9tH4TYJp3ix+1
Iz1XF4auMIe1+vh4Poo3Iuy72S15Cc3aA2NJHgV0LybXbNAq8TqbJ7FfNCVpCdnfe8PZlFvpLrZC
2M74hFtlop82Lb+MQfeMFzO+e6rS59J5OhduNXcFH8xqY3h2qad83o93MUsn+vmj9rKxSans9nwx
R7JRuaAbxDJOQyV3C9tu86ITxnrvJhxRFntI58oF2pR55AHA5XKYOlLyHW+mPOWAzFDCJui1b2kw
xK8d305fxRm3ZQBYz8AMebSC3K/EGYo59MmxnBTCZDa/NkvPhcC/lgeYmRoRQN1ohLjGtxEdtToh
sFXi6Lc1l4QF2OEmvLa8VCHkXnl2RD3gJoFapKfWTq8jtxbGIGKkrDE2LbiF0AlZtaAyBWxiQKPt
Yk91MKZCDWn28pIjkiJImRn1iWL/p1GYRTPy7m8Y0FF9LO0yHOe8qFekPpVZvViytES+jv2jTO6h
ZO2c0lCIc1QJm9u4tyxJNGPQjwDZd6EpgnEMMc4bmjGaZKlTNSQlM7/iLpp4bURGlW4YNUsxBA6g
Ce+ddLLVcERCgKNA+L3bYY53SMvL9XZzmdMJkWfoTKeJPqjhd821G6ijhF7TKj17Ln/0z2Dge5j6
opcEUlZ3XOpYKaELVR5haYD/c+qDZTlv8KcOf7AOwMKTqjaXP2hoP+zu20MKE+zgIckhZykvtbfI
QskhD/T+SCCJA/whaEr8xsYb/09kQ9sz345lvwHyFN2r6V2JXC7NPVnX9JFY4K0/1SmGfdnzaYDI
mm5+PsVxuS+D3e/uwr5t/lalzqTlFO8/dr2bgBq/I3jKJAAc0P8TOgdUPoIzc02TUrMeqXde+4l3
9Lh8navQepOYWnNh87rJXt4hnoqDmmb9UEsAe82XnpzBvwiUIPNB2NlMqprz6P8F+zGslvtnfe/u
La8UpsYuxWXqKtmnB8wmKm3+4wS2AMzFwEs8utnfDBF9i0v8lvDB8Xj/l+v2ogAlyVxm/9yI6KCz
KS6JKk2H8WbZaU56u8et6G8rJCaNEN2CVtmVf9J5/XDF4iikT/lbEq3+36e2GNQSi4FfP44MVUeJ
XisDkiXOoiPZahsU3xS/jOf/K4kSIYKr1yJxw3Hs8GcdvnVuvyIGLLPh3eUTmDOa5qUvzeKw8gik
4e5NpaqOz0uCP+ti11WrabFInBU5HAeiSRQEVnJKBGe9BiTCZVCN7S8uBuKGBah32I4KHWvW6+vt
ZahsYtjYqlB7a8st2XZ8VNGQjdTuOB8UdU6+nG1g8+dgMHwD9SCza8L0358iOR+AJN8aLPKJX4Bz
2entAXscX9KBYP1+AwhYRAhlOiEZYZfX0RaUYvwVnEFCUYGFZUaBXmNjNAAhg/mYCZiqkYwk20ah
cxfcHw4QKNdma/naxb406ZY3s/iIu6QOR8zlDzQIZTS/Zv301165UgJwjt2h6bV0uHE1YZQJ/+9u
xxUSNOLqcBChM3X4MOagSvEtbrsx4Lqor9ivh3absBFXgZtOB6yVLHU8l+Iy+t561GVk6qUHVo2t
R6DW8atkR01kd/prQTP+64eBtxiAmaInIcxpV0I0qmG1YXVAwmjKC7jHyusjhFLwywYlvNHObziY
Fwns7rZ6F8mQylAgeqNC7xAOZaY2mDvk0c0RExOCVh7VY54DFg+agvvD7TeoHUSBylu2oqK/iLQE
ay1YaeuZ3tNlRonLkMAskml7RTPikGdWefGUztPhsI+jZ5cNklxwhMJTpxXTimnGUr1RO6QNSgol
a9LfJYDyq17MgFtopiMGGY8od78VQoM7MC7Lzg0tl4hFurWP+3Mjjoy3Gr+rXqWnb+6CJM+V5zmQ
ZzrFjuvZIBVQ7IqTbLdgk4rs0+YjR1AK1HuF4nhjc5ZBWCB2X9dWajXxUZhlB66zgwTz/uUbsPFe
FxhNJPDMNdvBkL6PhKRmxCjAuTgBqkY1ONhrmYz35nrOv1S/D4NU+AU1wmIC+NP4r87GTgvCZFp2
U471LZ7Pd3Xve83LoDDVtizPxmbS6AA0rVFwmoozDwZlg6RA717qeqco3YQ8Y2dRcP0FpIC+5Ra9
6xm0cnB8qEfQt78L6eA8bmS7afFV0JswwQLY6rdyEwzgAMuKVD9+5k96Vb3ShR6fudoZk28eMknd
mcTuWoyNvbCvuGww7EHoTXrIFa8wHuVExDlImhXAXZciv+/Ty8A0w5lwwXuiDS/rvX+6sb1HkQcr
QzxDJKBBE5WCNXrX5YUnxpiPol9Z9Xzr2lTXCBQf8yU6vcxA1PRQgG2OdnbXftAXO2OUP801x/Ir
Pp5UOuIqnu/Cdwh8i+OtYG0PFAuWvaDgOF0DX/EDTkkcifXsGPyHI4MlsOOxitkdPzzYRj80Pb0J
BiI47ZC8F33DMVbGZ81ghqq3wsvx9gtp9pcecDYFglPGTEJjV1xIaoWastSpXNMedwBrOnRxdJIi
HOrIRk/M+0bqOpfNWMlXqhRlrFfiwZFIG3vNgBaspJ0jDLLeN9alCqyPJKWhKsupXV3/OnoVFfYJ
SMDyjn864nvaGiM8HIh29P1eOlIs/01W2Gkoh1833d0j4UllwKnA0+e8WhKRGf8gwWhPju+cZ13T
H1LW/NFLl3esSBAV5nquT/G7YZnCSfsH/icUsPK3pH4rZP122iiOb7tW5NjolYMELIMMJYEJ+x5n
QHJZm/YgfJP5DuFc71Ve4EoUdssU9sYJTLYxPc7yjmJquM/DBVR/GgaMfe8OD7B+u7QGYBBXmHcL
g1UEwGx795wc3sdN/jn5C41+0bWjKxbAI2vQQDeJFFY2sWDPX2AW5TpLS1VK3zi6GkrRwujVKDMq
yKDyAEZ9SQ2KXbpqc3jmohsQ1YuEPTh5XNYhOKtGn5BVAgfnCwdLecU2M4Er3BERP2AvQzWMGkCk
xcvv1FgPHfYgZwKh9/MIwc/vgD0CLrcTr0V5bOWHl+3RFy26/gsCfcugtTOlW1cZRspbiPldDC2f
DIbhcTcYNyZa6m8WzvjBTVJV/AHSgL1ESCZJpvYbxQTP1NOWoLvu4AabHkIqcwFONA1q2i4gVs9U
/w3Oz5KlllEbKUQYNcmaln0T+JNTZRa8FK8LL5k3M1T1ngQecEiGCUghRY1iNeG+502FKYPqB/dB
/PKDeCvsbQKlO51UjZlz8cgSMhLxzv3VK1SfbzExxYcriP37SqzBIMqPdpLgkFmxFWAWQQO164XT
wzWsY4zfmqAzj4MZjTdbh64PySoIhnXwfhsoJSRLGNty+sGJ4bbJMefaNE1PC0hG3w94pfztrRXi
Y7h8EkFFqaClJ5VsLsRmPZveo/F5QJjBd78/JlxSsAOr0mKQLJgJ3Nta7tyvXdOrtYF0s1Uf5hPm
xFX7orRGht9/LzNAjiBSH0yQVSPw1Cke3iCvYi7kiDolg5ty4Y+Yj6v0PYSbdwxcCDXzk43gNOym
8mgs0UdeUFa3KDeNY+P4+8xTctD/4EQ9oXiiyaNM7Lx23bMS7ACxX+4x4PRJoQpto4T6OS0jHKDC
s4n5bFoLD79Fa3DpCFE+skLXCSwThUiwIKPAN65aJET1cl95liga8/2rdgokVtLtYiM2+n3kAfQe
g0N9E6hzTiW5zygOtbhHGcoIRn+2RMPE34v9BxdotbuXu+i+13C5FSzzXDoAp8RsWDX1OsFMLycQ
Kz00OSfH5rLY0V4IKGsjnIv2E5/vb3chew/oRdh7a2Q+dy+RpJjiOV45wKuLmjn7Tx4hvKOPzmgL
vlesYU4guafpx2dlt2Pndo9DwzMDpDRiI4qYq//hUfSGhEVP0Y2jaKWrwxz+nZL8Q5k29bqRcBp+
RHX/wHhGdkuUAen1+ZjCTqGZiFbEt2uXNcgsjZQFe5TTnN8XvU3V5OvafjG0FE3r7Xli75GusQfR
XuVkkbYxNG6ZTIxU6Ld8woKe1nshgKHZfFBduxTB1PnBRgbkbtmeZUus1sCokZgLAHgpA1AnRedg
vVYmtNliojw9//l/pXEVQ5xM/aVKlVQP0rKAVlvT85iCvXiU8qZ1MDDhJSek4b79OVN60scXubei
CvfaAUPZty750FRaooIUfXHX8/hM5Ue4FRj3cCuKqp6W0xwh2g752St1MgVgzA4ysfjrXT4UXBOt
4aoY6ZEZxA5PTCyRBocyiBd6jCzSz+NKsAXPH8iglv2BhMR0XWD0HaLUfk+fuGDgP9gNyvSPqt+n
W/cV/SfgPefm8yXGAz+TKkhX3mxb4OU4tlpqwELxIQ5wbF2CEsl31u4r9dqqNYR0HcljisaEi0ce
FWGa42D23LrofIjuYUtCSAXhI3RBdKxuUAc1aV25aknIIocqQ9t8UonJUAkzZkJP37RT1IZBdMEL
qwDFrQq84eu40YKExZz0LLSlV8ScxmAjuBfGIuNibnH1m1AnKoiEU7HfJqJaH8y8CacLQTS1Kskm
FGdgcEKHud7s0z3m/RzwALDn7XvdACTy3GLksYOEdlNi9EadtDcYitHLlFe6oDxXkXTYdKc5ibOG
WeBpnXr4VowL7L6HXIdYvHIkM1pAsEuF4MnyxS+nadUolivx19FEjI2HWS9IhiRjZBNrZ0ZrQsP/
3ZNRyPZXbNU8eB4bj1wSnWwVMDIttrPg9tVSb5CP+nt0VJtBTQ/DCxyQ0iI0OOPxTg9ZASe7zcIH
ohbLACVaEdNn0dCscDmGrBoyYRdZ/i3zW+vMJwh8AhJu5U/DxmVQu1itwqHzAjirj5nSYBmKJRVW
Xffna/vFoLm8/s0qJFRShUD7d2iKo0u2SjSRD1TpqPlI5YPvI6Jp4kaMt+URrlJR9/YH2JNsRq6x
LPMtCwMe03b8FefsgukYYamxONH9ewjJYSIk/fDOW1yjTChJBC4IMvBznHYe2borCB/YM/aBJxtA
5fOF+9HL/iAwsReAa4w3Tyu2XdXknTo6Qqzz3RsPZPXu4w4PTftx7nF/AS93rW9DSw3Un18TtDxI
8bGPL+kvQ0xw2FPWs78CxUWAeB+MpLMdIMtXKQMi+MwqKBvo1/eGbEatDnyDwiZ1lQLQgFFdRKn7
aWPeo9EasIFB3kwkHFS+YkKeRt9JeNRXlUOyFJACn+EZikzER5dVxPcipf2C+pcKKSvmK7Zg/XJ/
UbQtLHHCU2xSSfqdZ4km2ywAi51Kd8sHMpbJfSGnk2ujS3w3Tker8Lnhwh+FhOSvaqLU6X4dd0Lq
D1Vn4HCueEv1VjGm1cJ7pvVsYxbqretjbhZzlnAbXSld52GZe4caXdhrrlFTUFPkzLxB6VGv9KSr
jvh/OKSIpIx+oqoCIWfYRYtu2B9xs77FZ/S3kuGZQ8Yo/R68HOjrOqvL97dQKgKmd4Yo7FEaMeJw
dA0ErPciY8SfQIZIAGg85AAXaO1HggMa4zhHEmsqhXFULxEOnp8USHtHogBSTljUDVFJ8b6I+EiX
e8drnYXzDUGTAciNiz8Qck1T/qL+2OC77Ici6obBtWTFA7C8QYldDYoR1nx0Zpv9DCbyhlAmY15I
CAC/62zJ7nwJejWU9OF6vEteucOLGhHhmU9IJs039fXOVVyWcvagqMj0mWJd672Eh54nqTY7WuWE
MnR3L6GnCWCv5kb2kkSMW6YHEy67E0ZWKpPXeF8Vx/8X4i3oRv14nVLavLDXgiv58Tt9tVTzRmKo
CXGGppEiF6tB+YVVA+ZoRk2R2PJz0U4PeOrLFGgj3/dYLXELuBVFXgMkTKFhmC4H3fJbOo7n+vtM
9UzBkK+hzaQFRRcbiNiY76iUh8mPV2aZKDEeInn1opKfIt06klvVdnhEMOwhzALcf/sJj7jlZ5CQ
mXnypCYMQDioMtPVL1JvDWncMJ75MqyCiC9/rHTQnnxAkiYSyY5IjCH/x14wP7tK1P9eurjOK6Cb
VDNmn79QELN8bRcW4TOMUW4P2KC1UG5+NJt7pfV9f5+B0uAvlo3X9eOmnOn18k0OuJMULfJctbqj
1NGeXfF6JwRpoG/2J0khOwm8cMyxJqyJaRgGp7z8SugFK1qD3dxIFXqWvtUo+Zgp9gbcSbeXf6r5
o8fftKhddyPfv4q4hIaxfX7Yfaw8IliPgkQCe6gHxAzndNUvs/semrNUycRXRkizoblItAZwsmsm
GuTEWllndkStevGuBC6aMES8vBBMUtKgar1RY5e1izCZmJ4V7NqMx85QSnOsjXMwaFZVDZhV+LHJ
ziwtomCX6CiBOAdNmj7TMPq21OKQaOlvWT1PD7q2PfoNfIEpNUGpJz0lVhtszz3pxXonaXom9Lxs
Aooo/uay3kuYB5g8JEsDuKpvtCgg+kGass5ki8KSsq0bcadLs/xumn3F09TiY7/FwS8rUxQYUwt4
rqvBnmI34Qj5dW/YpmqxBn/tMRTsTRusN36OaWkPoE5VqTMDMbqbsTTv/qwxKsEo4RCasSKX392k
85NfrI6Jn2WaLiJpsNKxdW/C2DiXTsQyK9AwTW8B6lP4TT3FHj1SrI2OLKsq3YaGR/u4AdF7Lfbc
8a/lOzlBQ8DlaCFKQSm3kDTbk6fnwIL1ob5Y/BIhTTEfP+NYq+D13WhQ45a4HJhyiRQEFLT/tkP/
J95rhMHJBftomA/jhKAGoZRMdxekLB1kMj0xAsyF4Ip/K0qZkwoBOVYZJU46dY/XWqYQEbJV0M5T
2FQkd+55ZIQi8njAtawe+e7N3fNi6LxGl/aXvQ3WghucOScLC9YZCS0HflAlOqC+lQsNVf/udm08
yY4emEBLgP1JXIFzVj56kqbCg3MqAavAu/XR4PUWNIXBSgJtGMFFRGWQ1QVwNHV6LsESpTVxAJd/
1uqShQtOKgekP8IzaF8ugYfglzxb803odm8NWadaVZLS6hyYEIC0pa1hWB6ornKPdCHv+q5555H3
+gfyKeoVWH9U/4mGy8xB3YRceNe9nQ5Z2TvJAf57Q3drdrMo9Omv1kXAmJLfb6aiNGqkRoQPeVEv
e3dI7yVKqfFcGr30h2hkAyR3yMT4WXuLpew9y6rCro9+XV+09w0l50K3cPdnloTelI6ukmqNA8Ia
glBrsRL/SN7zwZTxMH0CkC7uQHIJ7a7m68vhBmuApziHFNQIvdnipiDgW7r9atEdgeaHykNFND0o
5D5YDc/JGWQ6fpGf7WH5LbsoAlPmEKJvDHTysivvBZhNV/oR9sPYbyYtpVdfTlFOVuDbJlBx7uz9
NnI3SqQPgsUDHaXcqqykgxNWWrnK8IV5HcFiZAmKAvvoCsHI3OzDVwvhC27vo+xphnljCPUpQYXH
rSuFaSafoaqgTMz7HJIt48+TfUQy+4W36qLOOBMq3peC8HirMBKbqj/Ifs9NhzAr0C6iDslEW9EY
0lpK2I7n6YPuNIS69vjV8mCxfyAt4ZGglNwx81AvUXSxAVZy18nDOhhPMgFCJpLE/vs07kolm31K
jX6RrN+VpKOOCFZFtcJGqGiutY5Ltm3sx7aZ2gYoDpFBlvWBGlxsOGQlZnmLy4qwuK6s5bthtjn3
1TZmv05ujxvZGkUYu0oh//WlJU990FOV2VNfdIEcjfy0TnoxJxw3vjjtMRh0ZkIL7JBkbumdjdah
PHAMsqomhe4dd0Gw8UsnJ17C0RsV3JRVsn6mPvLZQaaHgEl17sR/g1uQAMbVKzZmKeVoT+RoxFAr
DrSoUY2SoaK9k7Zi4FQyHaZwSYf3Eo8yPuaNeNe20z8sEZ3svSfVzf+qa/upTKNZUUdXG973lqqI
k7JAKE8Nm5yn8nKwWHX9zjW9OZylqsHMP8/IYtElvaZRuc9Sg6Ahmj+Tcf3p4KYclk/tMrNfj6kT
+L0sHePK0qCb5J5pVpa7J01jTCTlyHHH6meOHAw3TYnG6bWntsu4qnG1lCJQPzoySjzb4Fsc4y4g
Y2Tqj0wUx8iqYXwfvpBprITmeeRU8pq/zZACXL0Fc7ulMQ9+b2kWDYfC5HgNMyOBHgzat8rZXVDh
jJKsqOB8gq77ljAuMsjVq+yjNmciTPG13INWCx6esI6kCjM7qQaUVcpVRVlvWPky4gkkUSsGiKoc
A1PtGaapKXNtAs6IGFgVaGujcU6S2+Po8DsFotExr45SHI0Gi1k7/7X+jlcoFeXEPzIcHNoALCVB
PeOkGASEPCfHh/S6ChFvRr5Pvo6FOk4RkRNcNe/1T8x2Hs7X/oXzNOJrJx2BIONdozsRpgtHrcVL
9YDOqgNkNZLNE1C6TSoGlaYGhL/imaPVTjIK5eHuvyj9hfbUBvqumj6ALElIO3EOxiokqxCfsAhi
jbDlYyEDzLMfgbJSwDu8oJfbPvsY0YTS8DGQifECMd64QsvyBjOu1SveZFxeUdqj7vt4x396XDLh
OZK89s8095h/fc72SnlI9hQUGsE+rEPtfgktR9xdO65PeyWsWmI/V3jB6lGtGYqsaZPYmiSlBlPK
oZ8x9T9dSD5zdPYtfTZUOe5GGdgMIktMBL8RWVXcS+qFYlP7geEZcURO1xMI/8Ar+YvGIkB1TCDM
eAqAmcw+LIHVAJrm2Iy9Gi6Wu3VVFt962HQcdfZyR+YYWRD9B2w0iISQpyEOmWZvXA2HnlAk2U7s
ZdPltsg6pEbao1jYAfgG4p09bQL8/0eyWAD1oH+3U7sQYSL/U4hv0vflgdUPJClLwqVRJrrDCNRt
QJCVs3YrLKRZnHHwUhvCUSETdTNuqo3u/afur6hg8JfKZHkoJB5vRQQYtBz8OselyIoL+O+3XB33
BVJeW7+XCrdr8nPzQye+rDl/Lfsim+5ElTLf4ylPO4ZqKHQpHHgsFEiIhtYRMv6p8ewRZMPgdOXC
yuP9lEHdkS1BtcAO1HwgaOA4MHiPNdcbQEJnjeQ+dIrDHf2I3tJ94Y6CIBfcy6Vbul7Lo6zulJNp
zvK/40xEn5IsAH67a0V54iLl2sBNZ6X0r4jXagARUZlNnt9abaw/dCkOgM26NMKOvlunF+2vWxCY
9Aq6+Iu1yIbufp/RfewjOiid2iPR3vRvwr5lupo5cs1TE8nj9P1gYIFUbyAwSME2zp+aJefmVJZG
cYuL/EGMGXnf92H1kzCWSXyGQ0CCtq62lgt+yE0OYWh1kLp3/M/2y3Ht65AZPnu8m0+6rKgjmnvz
PhS4LMLI/CVccKPvKgsGpPLIu/5ncto8DEkrcRPZNOlD6mIo8h5I6ItitpkBbb5e2lkIXSig0T5h
WXCT/TjuUfPIKR3wenVXvDthYGclcqLVbYm8aQz/GnJ2UwRGrtdb52BDpnnK8/dieTQlWqddOFSX
myuA6tM1y8Zsm5DfGslm9jDc8/3sREXi+YQZNB6ghF3bR/4kdWMX3eudifhY5eC9wUwi5Tptzk0C
husdwgCVRTmI1p0jdGL96OsOKl1Hk4NhVvE82y3O9+SGAt9BQvjLwc9e5z6f2BanWWxicZw4A7Od
q4/jvNW+loHcEb0C19iqbq7pYh4KahqCiwsJVt+Vpr/ro2KkJVbt5JAkWh8g7hYg5z7MiG3AHrnr
3QDvuRWGNhV1LpnRzG5TfLcAGLb3cxXFqDtbOrbgRVMYCC/qnITaojVvpNHvj06ZU2UXS9qUnsIB
L6M/eByKuy1+Xc/+ldQAIUviimL7zS9Kwy5HEcewcqGOx6lp+cz9qmGFjbxAhRkHbZIZ1MWxB6GI
RywNArtfml14Bck7e/p11ifqcMN3kChQOSAHMpYxpLyyzD5mlqLV4ZftaoOBSIyYmkqoDIJJbEYZ
s5r2ORb6Zt89LSDR4Mao3u7UJpdGucp8fPNvm75DqHASPQph/2lVnHJO/FCTNGoAHPmYsuLURnEu
e8FeloqUuDRbO6hhCC/2r7LTmQgjVRxT29a+sCJxw4TvOtebJUOZCx0txOYZlXanURmoMkEMmWAh
0H8WC10xSnzYOAz2ZthJrnxj9l6jirVZwhev+dSiNvk5TdI25xwsJzqQB532HHOXSDYTN4FvP+nn
pIGndFckkZjvt55I5PP9kZVdRFb+qnK2HuVwxfxazF4YCSbgFccOYlPU3R4GAzbpUQi1pzBZD1t5
lq2BIMB6YhZ3ocDxtMiqfxBQLDoT56nnUvjg1VrabY0m4f0HS5Ev9fglTgEWqTbIJUbDt0bacVFj
k4yA4unaZ0UWsj2Ml5wbCwPkftNQLtmvbM/nUUwznCQBq+n7It0cPzO6wbyCDg+OT0mJNSoeXRmS
VNTFtLEeu5sNoeApi1U89WuYXpKZY4oN/7OSd7FeLdgfHSE4gJXVfMac/EoMk0Mn7tRdRKdZYYnz
TTYgbGH+p4BBAgntezC1c3PhcFGX9t/ubZLWOri52t+48IvfGkUdTxLBo/jGCLznmGgIOlPwCSCz
RBvIHQ+4G1lk/YL/z7vZeem2TSsF/dAAcA6juhEPZhh0qC095N/sFazBoWJYLDZNMaVZQ3CkVHo/
licG2M7TGWaA/v3IaoTuhDjmmLZcwS96G9endECC2Z+TJbiqy8OCi8JkyEmWzdgrKk7TLOtExNVA
m70M8nbeFBWzs0Yd+WbZrSe6gnE0zZFLTaBDQSgw1q1W3PYYsygU9bl7smGjTAV+FKrTaM6ccOrq
nmUczTlJUD8V/tZogNHFU2jgGIPzxYRC+jv0H2kItE2PHDJkHTHmyvzxxshgev9hI8X+khvQkG5G
iMBYyuCMZt5wVs4maT8o/DuXo8Gii9AVSCiCFXPNitOzebFcc29XWUknh+8Z5vfMASecwXmDpyQX
PqRyxqdeuYUGP/I+Crz4IatsrHYoaKO5wOvzCoU6p5fEjzmGr2wASworEDS0hEkogyWF3bJ1U0b9
RGz/c4kBH5PCvR34/5X/fzQZh9ku9pNBnE1siKwoIJSJyYpz9FxMBEY/t7CbWkXr/8InEyxyP9iB
pU++3Cv73ZQ3euBhZMQ0jkS22WGpKDb/kn+SXUYoDS6oeg27ZDswcSarj8zRbHIKqtW9Nn81bUL/
xihiDWyxIStrcnjbK7xT8w9ZyrKAX01WYWCzRIinuJuNm1qJJPSYW14cyZ3uGX3M34HdqGRsCB/d
+fEMHpPjF3nmA1vUJj4yirFEe4SJkQXaGadRtN9pOgtOJ40tTK4tQtEA2ManxeyfHroHSDdxD6IU
7kVJeY7hLs3Sp+RrAB7EK8IcpmTto5U2gU0F84NMWPqlhdkB51W3ysVQhMEOSX7y1VipNQSaW+Uu
1BgiM9kDpczvd5aA0AS7D3zLEQBIk6LR+7DiEKsTJpfCFb6IP0tAxNvkWZY0Nz224Gxnbvb2EmRB
OryZ89OiHyiId3r7Ks2N7lfFGHYBmxuMGjX+f0khroxQXFxW3eGAZmW71OITfso+Drt1+NsEpaIV
V259q/3496tofwFyv94VL3vgPNIzrq+AHMpzGqnwRHy6C8JEO9/iI4IOO/RElDVjwEC6l5iQ1Wud
hY/3G/T+WYE1vyvtiU8hk7jrxntWreXUSEMmL8DghIxcY23q6Jjlz2yXruwogshIFy9VOb+j7pm+
zgnq7Cucm+E4XBxgr9uebugReq5uYKKxMOpeQQqgkCXfpX7y3m2+Si7xZ2WqcPgMDhMb/05g9Pk3
S5H4FWqQRW+nyRpPnXP/oOdD8hYOeJ6bwyvx3DenqtNDFejmDnGRqpa+Z1/hdk+QTrijN2AhiHqw
VG41ZZGvSVVUN9RLcipJTg259pdxjLdmS/uwBCD5yWr/xjeFwWiyziz5y2XLV+ozkxDHpRglJQjN
jOXwkA+CoOrQZrJee4eggVNhQ15sucMJViEPTMs4MGm3EhQju74QV8NbeMpSJrm785qK7EbgKxyY
jeYw1oZxrkMxrtCODe3Q+QXiQ2SQfLm51+xIvtmiCIx/iKLEgjuFoHyBysRuK4YaaqUd3BkIV0PO
hEq6kDP03j8ZmTz92fhEMNUW0SrSXxmAPJFo5o+hh2C4fVTrqJAKqrbgvkT3AKBy6oe+fAmj0jhu
bUVBuvOMgNyssgsxqoPd90eCFgHj+VHuY8Us1SLMzqHPgycQhUj3DUCg4h7bn0Kl8vocOKeWMHIy
Nr3z9MmzJ4iywlq2Qd2cvqnxmx9Hb8iHX+EcdRZnq7hljBXfaJt9EmkGgdTDljOjFwBM5RZP2l9n
F05oJQKVj+wntG+QA1Zre0uho/IKCIAuBOilgYLqVGmD5YYhm7becmjcV/VAC8eqx+KXoDZu9Ldl
wouXplyMeaVqkE3po/G1aATieMo8Gl5LNgdk8T3GQABF0T3HbkMii/zlsnrzCvdFwCAX7BbX0Ghk
CinBhzqEBh0IwucJDDNFL+FZ1OumbzMf7f9cBCqgiZturKOHG4nncJs0MWAoO7gQIc5oAC903IEb
U8Hg+Mxgf50gWKbRnGtSKns/uCmcm5xHQNiTE3Vj9CsxKTl4/sSsIAVoVbRR2da0m8oDas8HrBe1
UpeUoF5L4ksga7FlpubiOziXkAlsg13i61bvRuK1HAWXi9qQmf9fA2vEo+3bMZo9kqoEpIGj6e0b
8DbF15T5DBJReTISOdPKnil5pGkFxECrOQWkpTOOc6v/PyvMNv0RUY+SQVmPXUwOyq7CkaWgaIOk
GQh0Q9QHziQR3vmbsI3pRRpsTXHaqD1sm4on/6sHt1ScfXILzFAjQ6uERGDD9XvzZHBzn/GnTX2e
mFtNAfvVkWZ1oRfwBK8fW7nqcCgFP7NVBLNcc2lCEuJk6+fq070jtEK9KYs9bHWG5P7zxnLUV7mg
btR5OsEqQnD6Um+GA/8ihrZ/STD+f9RthBp9VCMYFATeK9CjoR/Zy1agoN5mwF9Szq56eI8sLn18
Pp/DegyirjY9Xugnptj1Chl6aLEidBQdSqdrAy2/su8/hJ1YHTg/QUiRMLnUZN+G4PwNMq6FlHfX
95J9+j48JbxI+67i7NEPDZTrDywwIUgkC4MriektM0+l9NMDCsemdFA9wBTSiwccbpa4ptZmEn+n
aB4d2uyVjPV2ziwpZ8Foap9R6dv3nPDaplNHdrje0Hpy80/SO6fehGeoGs6buKq8ralzUUBL5TtG
3KHIZamuTsOaOA8gBSknNIlnpVi44X+Fmsj+L9ozJyDDtFpTmRWzZpK58gDpNIbND9W7XtmAUvqz
7WkClPABLD2Rn/KqrIWTvsJXYMTL+V8fVxu/ZlftNoeTekzBS85ofKGOG7bHAki7uOYT9VPIC6KY
UnVNCS+VgL1nB5NsQVpBu9iDTK1+/L9P7pWahkY55CfdB1k2kdHW6ijeOb0fMfXI6jrihBnKafZr
/Oyk0wEmBUwCTzgQ6KIr1hXPOLD9uRxblrB4W4/nhsu7I5vBtjmkCM4xKWYM39a6bbF8nizAHtqF
1CmGZKsKYdUxbzOq5qGx+cVmYWC0f50IITM8718hCPyDuNjn2n6wCw6VdzZKy3R3sZnukyNGjnzD
8XPMirEafDLdR2HKAIbDEVlfX4uXyLjHYnjAkHZtZDwOZk/xQDZqevdtk1PF3YnT17QqSvvoD/83
v6Q3BCjhqXB57UFsE/Ewf9RKhbbbbJSdM2nmEL/5N8Kb9mUWmI2GUbd0n+lpB5dItdo93+eMa1us
2/2YvKBZmQgBWZyASrEKEqwCTQ2HhVqR+cNstucxrvRQmwAJMuou+dRFClIVpL7iGbpZio4BhXFL
yu0+YqD8un5+Zu2mlDIlTPPrGXlxFtpYQQeeBakDe3ojlSjvU2vQ7ZQfSiK5l3pMFdgm/oPK+6AZ
842BzO3wZ9UMoOeNKPeXZ6AnXJ9EEoEjpjsDzIvFNMaz9J8qMji2aMPzzLDUrYOlbj/GfnRb5sON
UjTUMYd2fy8mxnK1Mn02JTxNivCtVNGBa6/lJcC7QX9DoD6BJvRKRCuHyFVKsHD//0ghOOiCU2NA
9dq+w10WVMIBFCjy4SjGe7dTDnrZrsARYX2gGzu61nQcmqDb++sYc211n6QM0POeOwow95aA2dWQ
A/k8BbuSGRRQcVZInSCbS49sXslr1/APRmDRHZYnwyQXJMSV1uh0rHEhldejPw+IMNxCgFrWqIzQ
fT8RPINuPfwIw8RLFpRlpUov6m/u/o5uJdoZgZLNEx+bQXTtMaZPRemUeDv1N6t/LqeAFuq93peD
2Iv7Ng1dCrMmajF+43j6seXcR1NFRHmXFABSKx6G9xz/nQqSbAjgmN5dRwBM81q2YIeSE3953qQm
YLpA+eCRdhYaZTNDZlsLpNmLbx+c5kiHRd76Q5taVycBbIthPkS2wlz7+un67dFIU8VJNH897Fl0
hWayOaCnV14f4AEaHs2YN4jgMmWj52hG6W9p9gHHR6HWF8Hh2Jowu21+VbtWIGkQv87Kbzzb187f
/ns7C/04KNGghe8HFO/7ly7NYPzZI5CFfxIonBqh1xf8NpkSX7zG4+ocA52/F9eT18vGwQTU1YHI
7RwQLWgLtyjK+UUuPvZRcEutwwL3fzbxSibSYtrzyYfrr5xxRaSJSg0PywEbgvQ16N7NK1utmXE4
WdJqPBNMf3TCa73axp2vg1KLyqhHJ1JSRKRp3qG25pkIPP7bDvqqqztdAQKCq2YPjiqLt0SePcdf
1shZiHwkusnVhiiWDQA+hKfx+3BS8LI+4dXYxeQWkaEQ04MfaklsFczDJXJjacuhzBXKDpeDMcXG
276h9mXnWH6XW6Ql5+JMUPaEkCjC7Q3fszlqxR7Uhm6ach120geqz0LZ10EZcTzKAyBUV0CH/wsj
LPtLmTF/J53GPVYkCT9L6+zCm+nw2Uy/Gwl05wU8bGD7F2IM86Ad/sIqsCj+IbConWnz10NqjSHg
DiUOKAOqOKMji7Gz1q+g791hIdsddk/2cM9RchTWR1DfkH+B7FRA44BvIhktWuCPZkvTmpvpbzO2
P5TzpSHOx2XxSqHpW2bwQ7BfY1naRFnZOcqlJr0+yYLmvZps/o368poV1pjZZ6fRjp+0/wuYptFy
Cph+rYdc3IY/BFpXB/i6iu4BviPNhU8PRs90RwXX+nBaDHXY+oRy672bdWay4/vtZOZ76gFtbNU+
/uPHDudbtlWpN9ynlB4SqwKlQxnf3v4K//ttlWaalOaZp8OSvTNw5vJ8/CZ2OaPo0e0ZGWSDw3Md
Sj7a4SmdfthYqINqN1CYGZk2pQDHhO6g0tcWPCw7ERPjB7nDHN3lbHENOndqWLSTea9hH3Fyql1k
TvvliJaiQCTSaqtyPqC9xarNnfYk0uXngPZ8yNZcCadrGlfWt8C0x8ZLBuWcrq2i42cFJLNonu7M
8/UhBgizhz9y5lZqduUQHejGZ3EuHWPEMssiKDUqxoKaEQmJJtYX9Y41h0i15k+TSnv/PnvlVVFs
kePihP360X7S4lR9OCi+4dsVp466ARLfhYQzLyjDm7Ma0CUOlCPPjHog/UqBqML5T4V5Q2UYvDyS
QF9N0FpciJhFSSN7H/vUJP+3XtMRQPAUEu0jVvUmpAixmVz64ppmP0dyPDR2abMGxjgDwuejHvQX
Bw36YXuu4+jLfbpOJpn9ZdsmPXKRDS6f9Dat2jvQ7+DGLvt2kvNYeGieqetDPLniwesTHdkTPEpq
z4a9PZQg2b4xRNeviysB+cdWuGaKNify1rqjoGDGbcoIiExgF7ZayMvZydM5hbF+wEs5fQRHBO7Y
5NhilM17YQFEJp/5du8QydPDwRzqzW3Pt86cXB0yU5+3tsaAgNGFtBpX71zwXVRzXtf1PWIyb0Td
WO56LIx0+XT1mVu2zWHytlybciLOdooq/pD8xUxdhIikOkeLVA9mVc1F/zAihD2AnPEEiyqLYmww
OCov6g+ojPVZheB1STypemgMQIWY612iW7Yw6x5lJ9jFx+oyZwG1EEadIsqj9JCyMr+dyFGQNlou
oSL7q3ukZu5LAYxeTAQHNl1jPv2WKeFqQ8LiONLlUEB4cBiSAmVqbqeJHS3DoxNQ+DaMab17YOBn
5libykss/Gld4Ozb596zaM01UwEc490C5bTJbpzlpknkIC7oGf1fui8Oe56Q3fSufxTrRtzsHv4p
QqYNBRF5g9tx12YCBU/gR0SoDGb8EhC6ix18zBeXo/F3YgisYPLs5v+Qk27icvSArJ9j4ZSt9v37
24eMy9JYjUwiJI8vdGUoa8ryAzzaCPSfQD5utaEXg9R94LaND/ZT6Rnp2OV/+Tx/p6dtsqPIV8wq
F3qxVVc7fnsljDgKAdlDj8ACwZrce6NkW/m1roWILb3XKTozyWo7yvjD1LYLv/xCVp9LwvTXc8nx
PfQJQGr8hCJ+KuTsVOzT7B9Jd8q78OQHVadjUtppmceKQdCV6I4Kovs9KAM8Pq3ZXWV8l+0Q3uO7
HLzQhlL40HP3SFt0EJWkKQVOCREWcIhcDJZ+h+LmDxI4VYXTRGkk5TlWCedtz1jY6ehVG9rdaraP
Gj7N9JzJw1azTivfiq9kgeKs30d6ks0DpSg92XG/Fx5sMlyvu0N/HZFkw6t870+eM2mTNKKJsJp7
ypXpEY42X2HHzbqBRkpah/BQ1QTq1lOYZdBIlv7uyR63fishVRfY4BWTynSL3OMh3+5tCdaduane
5sRWhoM4MOB/l6ztHupi5Sfkf6gl455ggAjkc749vtJN24GSsbOtm32XTECXBRyI82AphEplZeMi
TlE2ZV892fgD96le/tLD3CTexC6PQbo9LL8wqeOHo17gAbh14XvFWRINywuU8EeCFsYGcD1sDkLu
U/JQjI7xLdorv/fAZ0y/kSlJHA5GWh/wY3oKfv0aIA2jNfXwb4iTsaEtybZhFueJcT1CsviOc6pF
BA+Rehn48w1ipN3UqKiaZzaOUhwkfJpu6QfqjXKMB07Gt30YpbGSpgmNaP/VCNuImA5epvsjKM7Z
z74Te6uFHugJ0sHDQKpxL+hGQYscIscW2Qd0YSEQKzcHtPMuEPP2l0A5mhrtmbTKCgVhpGDKtG5X
7inL0eiHHlFYXZmhpHuNkiGaBo/cban9HP9cBn2PWTiA41H7TM4a4atG0ssV7uMaNCv0mtKs/qBB
ZSoqlR+kq2U6SEWxronA1GFeuf1c7Vje874aU80B7g2hJ2k0zyrf1gHUIyaNH7SmZr/wanttFr8E
gRnKQTP7oYAJPPfjEp0p75wZSIGy5SBqmv5wIe2Okr0T6hnR/EtVCWgve2/YPlZVg34OZEGt8nrj
6ptPbegAvWcFh4uHEbgmkfkdkCkY/fdBgkyjl1q9izP2O/GNApKIU+jzSNyxHQt2uC4g80LmOQ06
tc3G8K9Rqk1+2nyvC1xM10a+vX6ZU/LzrG8OPCSRc/yuxUKTgPn8q1EKmdsrq/ZdKCZ1jRNEg9uL
e2NzlQDW7+rKcF5K11QxfkKdKEfRUsH+SS0MHpzdpxhLHk/X/Jo6ANzbTKNK5cb1ZmyQJApKaIjg
6ikzjSTCqPYq1Y52DbCjCAu8+q37pUaGgXb5HIazBirTd2J5bhKrVV/d+s5uAHUXJeK95R3/DeqA
OjIUFvelfrLdJsL9lWlgSZjPKuuFocDhbGrcDs5xmQfbMFCVx1+kvp2ed4ouzwyoHEHsaF7gPxvy
Bs5PHGNktdzz93C4057oGb2qWi4rGRszkJSeACJdyfRFgepGYRYfP7zrmI/MtQqrMzoajkmDzRuP
6UShINcAmLqdPS/HV2jwQIkqOa63ktbKxT4wp+uNTSvpBsTDqVZmgU1bw85gROfe6XkwaSWxFeRY
6MkmZSz7kOpq4r0NrboZSuHypBKPpCrUvnZTNFunPPNzR8ip93/MAsy60X/daJHvWnB2qAUj9sMF
v3jm3Hry1S/ot2vqVYNWoRXlPaJB5cqMasYJMy9nnf6ULs37rJKsC3AwK757uQ4qHX+GhAYJ+6FJ
vgv7qWRpoHqBWy2PSafuSbpCbakhYLxaZNnH+170HL6OEw17hlM9oVSSPVP/EIvQcLgv/PVV1EGJ
9emgfShRoc0OVvcoasuHWq4o1gSQGHzCoskpkF/cJDg+5tP3BO02PS9uuXJa9rJPvoEYxjEZxxg1
qHhM+lsgjsm1I8EAVDzNNp3RNKmaN0iE7htUQJMudr+sC400hc6x6JSU4y6vrrDRc4NNNaB4T8TH
yT3mjZw01sFF+M5fipoOSbN6UMWyJRrYzHJObEdMUuqN9qqx1/UPSR+WJlHhDnfsxVV5Ufmn766l
GxtO2r+VBDTw/N4CoPUncmZg4X7oHlScR8lpvNlzSp5lnYFHGg9/qMLNyOWFoH2S/R4Qga1ODY3C
LKkhorinlgqAhyqu5KS1I4xxiGprQ0oLalYB+dngYqsNafix+qiUsbOELdx4kJvjflvN63A2Y2qe
bckT728OetwgtF0l0L8L/9qhZHIop0QDV6LW+698eZETImGNsWO5H+eywFveiKb/Yt2v2eTz17Tx
C6Ek5ZAxp/YJMKsp1CDL4YAZPQR0DfkckX3KKKy+05vTFTHrQU8+kYGBfQux6XTKEl5Wl0U8YWZo
y0lMMMCKsjyTNcJPiPcNwVbSk0OolTKvSxJ5Uq+/s2DIqJBIVL9Uyc/NIuOPBfYQpxEqONCmJ269
4vkxq5J1lRvHILpKS6g9nUGFrHnCBse3GeDbWlXEapIcizZksN6RKxY1BG2yi995GxCTNDSHVpO0
uat2RRgIp+SSIlHTTPFnj7LSQ98qkCjkxuGnEAUsaGdoVObLm4rXDH7hAv5ZQYHtAD0nhppIzFEv
d/uF2yphdil/A7MlAiFUwET6ZiTyUmMoLr2NwpMLFPQTXg7kap5etN+C0GyClRInERrXltP24vvD
xS8DGrSatMRCon0ySF7OtDj8w625pb/dIN4aqr38r1TKM3mKBNMKPRHm8kintTjct9LKLkt53B7A
BoBkBcQlYeJJxSFvzxSAfsFkMpuJKOOVfnirqitrH/VN2LvkHOWgeKUE8/drXHPUs5/CpHgyg3yr
+yOUfDly4bPVLf7FG7tMb+EwgFSl/CLpQYF8johczZpDJZOjBuIVzJifHKOULdorMTQUs2Xak8Hg
Nuhh3N/2LXm1sXtU/I7nTpBbgcwAHdjBX5oMc6sVMrOVwEplGbtDR7LzO3WIlB59NsVty0o9hROy
YKtmv1aPSs65itUeyCsM682TBRMK0XyreA4A/bFx5LOiQVKTeevCwyvQL/BSbsMHP/mGnIbdN5ID
Jdi1Sah6mI/NZcCrNEyGyJjOI4yH1EvPshxtHLeytgIu3A8G6OXwz5FHY+zNE3vQv8LEzdnnnHix
d23MkX//g0hG37UxSiOchQbXBg2MUyN2xwJigRr9nDyNDhud54Jr8s9ewjy3ifR0X7o1tw0/g6N9
QSNIoOwAwtXITp3/6mNF+jCP4ezhqgxMCXOnM3yLvg/HrpNaAvzxn/hJUwv4P5UamDW2VvftsgFC
vZ929NuGXWdOO+Ogix5JTbBlZtF4lSTEs8T20B/7ztv0nmVh4LBkHUI5Iwhbt+Jnb/UMC8Nff9F8
A/4DuORgma9FqsPzyPTX+3h4n1u5Dc0a066nauafcbTF4iNwFvFkP8xLTHZvCjp2veDY3kimN4iv
7njYBQzCqRuIuigqG44XKFg2EsTYJMYkvLVdLjVrbUigu/EUNI7V9eH35EFNZWaBYy0P6MwOKOLt
1RSklkhciTICYOb4HjWyUL7mrWCXY48BchoKlNNjI+q/0Rspn2BlV1iddg7Hxc+7PrnZumg2ugas
ZKVIVqcvDdaJ3e1F+HWmi688+UHNFBCNdI2wLJUmE/QLOA8UhdyFHGHwGTuWXjUOQ2i+YOsq2yis
NRsAbTVa8MPCeTY0T1njPDLOIB4cgA9yQ3yhaoM//a97bb4u9PZaz6YdwpdvWKUG9Wc0quLPjvnW
L+qkD4lmhrGPbcjrt2mPIK3jY3PTLg2C8zkMFatGeTnWUzNLZ2TAP1vPlsgef0OLblTaEVxu7U0G
cgdtgevwoYfgaSfJDqdI45bef2C/JgrRJquR2osTkfQde4/SxUaxDH+3b6UpXteQMCjgoEV8wpju
+ZpmlKAZklMzYMqkg7xdyiJRoByiSUWLtI58E6zbEhx5v6kOUzcue+UEz2Yd46DPS0B0chVZuKpT
nUEwRdyK8NxJcOXE+yJEG2QrXLYXGDYoddR89HRJYzMM4fmSTVUJffd6ntP8DVfNmvkrOvKiGuYc
E+OlmtCQbum8g7W3s6kGOWGw3WH6Xeu7w2pOhPwNnazZhqZSMAAfuq/J1hvChgix6Ov5+dB7EdV0
kAm4YGLCpM66HEzWAheRkYO7aPqq3gxAkZh29FFRiatggY5j0enCquoVeYZl8MK5uWB0fUvSVFqL
DCCV9D9uxeeDt94r7hYf/7dLXyqrsqRz7Z5BcIIDcdQxveqbuPdO4+JfVrc6zRAgQ8yXyntBebBF
NA6rY0p1ZSKJRbuK0oq/hWdW3tzXheZ682Dh2L7GbwChASXsYKumA/GOWzDttLQsbR0nIbUWddbz
iz5iafuzBfogbhbCqDEFuU4X7E1f6BPGeU7RQfX9o039Czq0th/36G8GU+rEtkwp3sWDQ4VaJTK+
qjAfMl9AoXGbPVaRBEltrXMwY/quBUD8mcgohy4YNy7FEZxdqBlk8dfm17FCzYUxwJMnhQUZeDWG
G6oPoKNBzK1NcQFyIZo1wit0GZE01a7wp2Sy4IROcnRwiRwyO7TduO5mgMzvbaDZICpeBn5cxzqR
OKAd5RxTp/FrJ1Rn8rNlDJ8SvKqL819TWN0Hl15c0yVuWMiO/CmZSgHmVw55YGyffJx0oBcn4p/2
iH976kvXui4/HyKl1CC9OgkbWxAwwXA6CX4h5BP3FT3sn34buB0CNgRtnfKeyLrkTHKOk5kMEpUQ
uPcDlRf+yH2QZBPS17SdhxedJvcZFJD2NLQdXDkL7sENdL6a/55dbmmOm2nfzumM3Xud+mZaEGsJ
rVS77AHJSG3HLF6mP17CWjhdeQBJdtGEOrK5ZCCAoCAHOsaGsd7NmdXgAuoE/WorLJy3yBrTB2iI
+cEfdKPhoYxaj7XFvYfQ+0xGGlucS3S8420Y9nSJnwfYP2CTrluyyGThWDe/RMJxUHF3MPFjDcvj
Qr4rP/TVndVGBkzaU7EZZryXjUT06z6bsqzZaiAr3KW1A0MtVQZKFHwx0qK39reMvqGw/grEZgaX
8zXWyNq4kRb8QZz44hfJZ2R1ArWY4/roK8TkF/NynOpWWBIWeqyz+Uk1vl97+303qdhJ374OAMOx
3xIQW6RHlp72ATOb1za4ozf6mznqh4zA31NIa+aRzyaPT8fZpz/0+oACCJIsoOSaWZ0ZkZNMWqkT
/U/81tTwI0a5g44jbk6/ZiQ7Mpiw0W5o8wLrOscu9hNGjsKZZBj43D8yrMY0manbwyz0e2GMKOoI
vQjovnyWwsezAFbfHOXlew9Gg9aj5AIafjL1VXM2M/gCpbw2LLEeyH4ulV7slgtnRIJgsK0Bq82r
PWaOEROdJvq6nQMZZl56D1en/A2myKD1v+dmfHYrE240JWTQMG1lTo7V1YM+3NPAYxg3xMkri7PK
KVyfG43Zu/KvhaJc/T5DdZINjTeULo4O3VKFq1JKDiAGb0fDTm2Fi4UC+UlpUEJpCXxrud8z1Z/7
U6o6z6u/D8RhgE8ow9LuQ6HpuIyQ4ZLUZAegNoKIF5HilMdbje9gkHwsbDKkblLKFCtPnRNbJX19
9wphpTYq7wl67Nr6t+ZZQAYaH68paNwDVu8GhGfETyiI0kSpemh7xMjaQsJsc9mBVwgF8QXxPp3a
aPzgUS0queFtuJaBUUaFSEY2YHfq9W98wI6qmqrjIH1ybHEr7AEOMAQf6bWQdXf9jdXEr9iXvOuw
A1lZKYpqnbXtc3Yj6b5P/vJCtF1VehU5HyZvSY7ADPtirMhdgHz//JspyrIWB32WnXEUST/O82WP
/FWpqtWjFvqrrmALrvrpS5wfeMSGVfupKglUYimJ0pl5pxmzGyjRbZ7daBGWKuJ8r9C+i6dtlHjZ
rmg0y0JrpiuzCsijYNMnHS3zfhMje8cDoVgrANN3tSGrDiAfths5afAqKTeR8kO5X3pYT1ucUcva
iEkb17UAH7E8Tle0rRSL6jN2D+/TvVdZT14ok066PzzcUKVF53bX59XZO6IWja1JEJOZtRMrgjgq
D1zoBd6qyHYkYD0HuKghUa76/fCw/jXBjY8nGn93pgTKkMm7ZzLTfr5qi+BZ9Cb26yCzDfBf+9a0
Wt1GX2pMGmxph9wImJU4mIe2mnFHR93FngZ4mr7j5i2e/fUAyzPbT/JNzai77Kt+NhcT9TUQW/FV
zi9eb9RqFFRz51/HTOLpBehL8Q1jLgjV9LlYQtO9diad0sqELTnsQS2ViNdLN5rjdhYdbyWKFuqX
Anj2oiongjJF6R8NBcZ9+UvVTNBjUXoSgSWbNc6rjISK+4TfMOgSWIWl2/UQEbQ7/cOTniKsU2wM
JniszONiOMT/6Qj2I+q1hNUgZBJKx16rsnl4KCtnwr/IgvPkGIRFbHmY2YiZRC1VPNf5A8Ys/OUx
6PBAnNt3KybMy39lpus15K6HDP5DF4k5q88nSQR/0DQKUi/4lFLw6q8R+ypwawU6Ui0PmbE7qDm4
oPP6JkeJEjjeRl9yZpRkTMhDcXBQuVbfl1TiKNHPbc328ZWDS7TyqIPEQb6mzC2109tbPoSgUQp9
ZuDTAQUlnlzLWWiWIPr5rl6Ijl43hc4W7CJ1AFFHMPW5RYfYTHg/lG7YTkVDUScyWSxA9xpT9r8m
VCNOaxhPumA/hyrSZlcV83/Wg1GqqJQa2czWgTxJ8zYgiEaZAPbA4RD3X4dGAUmWwtdvo85GYbl1
0w0Ah/l9t2N6IvvSvTPBZ2j1oJwAz8/r0j+vo1b4u+SEV4OtebhLCvAmhgTvTdZMrNv93foTyZm3
DwWE++L9PTkY/5Zaxsvg7G7OU2/1vwIrAPyKWmLHfObV+zAWlJJ6wdvHEAIvwagXxN+d0RVmbPXG
NN3/GiJjX0pRvA6HGGZaLf3FjqrjdQo1mS3SnK772hf1dnbef5mCqVDdQPt5DAj5k+hiYJLnLnbW
uJhWBlndR/xaqFnxuvOK9/fPn8VAJSSUE00dEvwwn7003NC0owSlbiQyEuYgbn5MMaewRSXPqwcA
T2f4CI/G5AUPaFBDq7zEVqrP3rgwl/mRvlyK1AO7h9vvEjG5iU7FXC7/7/9u41I82VyEMjZKYF0u
8CISKZWNS2Jhc76pp1/wW4JVV6vUT/8WH7tWtjcEa1LBLhTtrnFFGibrTmqIA3z7YY+S1vvG0Nnv
6Yak39jtDcszKcPedJZDW/C7SUNNhABqtvdCYZ49px8wxOi2s5LBnObM/nmXI9tBfC8Q2R4ZDJom
AKiCa1GThjk7w7V/0wvkJ6VufKYNFKB5shTpSPs5tCn/VMCQJoswI2+BH1PlDVSpqog6eQhRE+u8
NunGntd2ArnCR2Y1ZbJUk+9It/zmG4VJGDnGQWz02jGfuSKxjAMHLNqvdADrM5wrl3uEhx048d49
njP3hldrrrtqzDb2zh84n7BsmLP+atCplIO5pLnUrB4eZboTkgq4GCfCHmKrbtBbIOf7kJBnFt3F
pTG+pAxTUIOm7INPR94Pf/XpsK36eeYyD7NXChO+WeD+0BTuLvZzxeXW5bY2TUECyJoqOQ3b0zKU
BRVG8Ts0gonfnCOURoCv93HUtQEYz01fM35FnV4AbnPIFIaaI0IEeyko6PQO995zwkS0hSQu/oOl
isXRDVcTeCcR3fupo2Z0u56HpmfGE6lRtg+m8VZF9weIWsg2WipP3cz0INQpFLLg1z8AC3FnCiJ7
zrT43cQZef7g4aqJvC2ahSh07VLCIQ3DsUOA87yXrvgUL7BVB5CJ6bA/TaKS1X9BoRx4LfjUs/ka
+crgB1Jd8UzafXJlaVU+j8TrlS98P0nv5Jm1Umpy601Qzu/fI5VhtBAlwXNXRWEf7aStPjztGg18
pTkVNjcd4XjEGBBn8W3vy+EsixFnFgE1t8uQfK3o4JuUG3Z+lnpj3b9xbbRLZcGC+yYU9EkZI4Mv
NNPpGspQtZKnQoVGT0SrMM/7K/34/IBBJmCFUqbgBduy4kQ8tQodM5hd9VzoqlGvdIcPo88OWR/U
N4f2biLbMhL0V1M0lzhOCxmK9ejl+kWQUYabiktnLC5UPGg169y5J79qOgGvu55WQSLS06M7ySxP
7/WogJ0mKBoB3oeBbfmoM9RUl8h2JOrSpRsUVTNGc++mv8Ify3QEqAoWOhxHyLumR0AXHcwNTjqp
H/S7cABmn0yZ8boMiRuiJ/9Vz2LrN+VAe7aBAKHyrqOHTDlfaJq7a2vUMxsQl+DsC7w9w3OuyUT+
VQfwxXdiQBUWJsjJtHz/ZXexsguKtOjTXe8tjxn4rK7RwWShjE4nQ3Y50yG32TeV5Yj1mIZxLrCw
fFCu49wDebVfMbP5h3rGN350Jp0ctLRC/NdWGuQWJazs5NPQHR8TOo/aMncxHxNfu1KUrtGTZvaw
egcWrCO0/JpJGllcR/5Sph/421JI5lRaBC9dLMJtQQTPsVRpuJv/p08IkW7mkjabUO9UlAChOd4r
2HS6FMkdDKcVJVwI2FlFXToSk4egWRJZ55KWoV3WsFS3+VkGnQKl7uuG6c3Z17g0I/YbM2GuCh+E
m5EjOocZYlL0HkLZf9fx/zd+x2giAVSnSKnuzEm+xd+JYUaclNkgmUif6Ac3+fM0BA9J6GzXgXvM
+EqwWLE8GNDcAuzFgGZ67oM/YKMHgNx9KKltT1DMb4XMv+EYYB81hEvfL9ejyJ20XXwFdXu/FFZ/
I7WCbm0cc6tDQ6YSKvHCFqPFtaRKduT741JgRoD16Cx6J5CZzobQ2zQptsc2MfUElzPupOBFgyZS
py0OIDo3r3Qwx+Y9tyRXnyqUgTkNNOSIUIXHrLVKj/t3kuHa5NS4XTWiYTS6hOskbKu2FJjb+RUT
49lUnmvIGAqX1BBKYPduum2pYd2JMAgVviWbGzsT9XEW2v/jCygIJ2elaBt+Nw87184r3e1fsV5P
l4NPeZAKPmvjQ+iPpCdhZTuW9PiTgEUT1SyO8XGzUcdiiUPNfONgT9Ud0AA8mkmU2gbO8eT+Az5U
esEQpACbk+50bo/HfcJ+bIin323tszbBWd1deqz3QaOhvrkSZ0D/1Lr3B9eawLcXGAfeb+Kf5s6I
8bMiu4l7FCNnuCoCpzCvppSNAP0eDbJ3Gxm+R7YvZ9sMU4sHs+B7/fFnSzRsY/SeV8WluzQNPODd
Y14dGsMjRcn7g2afgv7NIY0zxajElssrtfkFeXgXr+cn5zIwljZr5SJRn+rRgKnXdfxvLHYMFMTG
/UnbH0YtH3PfnTJhCATjOzT5KEj5RhCeRg7+lJ5+gS0nlpDtwa7O+v0+G71b5KwmYYntTYxztId7
pc0zDyr/kDHIaGwa4Cm2GFL9XmT2Ep5y+XFAIkoRcOh2T9HR62cZukloJQ6FLk6aNJ+lyyCBuCx/
NksA+gJUNSuxfd6yWxqsRA4wwCkGOZT1H/tSlGRcZjrtUK64V4jHwOcca/e/a+90Vqr/9E/9ygRc
tsTMbTWz0ATtzDMLdhJBV29GqT+ytFhINeQAGScz0j4zA/CW0rhbDqKzflI3cd015G6V+WekekPV
fAh7cwmrscOhFO5c7zZBQlCKUG6Fs1Czi7sXzntDsWIrwitEbM+f/RhD5tBryu9/jmOY8n6cuD9N
6UkDLi9KmaJfbYFdFg8AbJivLZppc+Wu0Tv0fhRJ0gqHv96t1DufLnCRFt4lKUypVVSe7gW+uBLm
MICDb63kGew5gsKFnGNoyxx1G1J7iycccA3JzMN4FK2ZJ9iyh1HgLSD/PFoqyTGzHKGg5/z6HGTS
w+kMcB0HMNVcccTDiGkd0/IM3Da4WweTGrhcGFQ2D6HhEG5onzG8OpIQVtkSNPpppYJ5oMHGxNjt
JxvAYIbVbmtFgqsDnEo+ws7O5XrccFQUDMztTkqUjolI2Xnj9GO5i//RPXoLt4eN/C6GqFb8gZlK
27Ch1IJTi9SVU85GTZJBkILJ5RhwH7Fz3B1Szqj07zxeXENgogOpr1aDyeSIymnCitGxbNLdgV+1
p+uD3pjc3KyLi5D4r2fH2rSn9sosS0O+88UqiG5rroOhzaC3lC2w6ha6F1IDAN5ao2DRDZz1Fpil
8pTgA6GbBjsDPLEWZPqvqS/XtYwnNGZ2N8A8MV9/EZ6Es+B/rD9JNyfRs/FOI0lVc+3ka1hg91M3
0I0WADIAtMVaEEzG/PYOrIW5kHRQDpcFRBE2rSqWiWYrdovMzvCtW2A5A5iKo86xCFhNTr7WN9EO
vqw9Utb+EKXOpUzEICrlTLRmSQzNEB/wK92kDW5gyypb6yj+RibeAH64o6ibc56+fiXFxJ6CA4bb
xyQFt0fg8WhNiT4s1wPLVtKKcn1WlMaUhnyhQD/klCXoj+3AryZiOYQMhapFqWmyf01O809amOPL
NbnnS+Nlm+fOT/jBd8Nr7pnwfxwc+jhr/ZZoztKsMd9eYThH1n4Br9wG+0fOMdB9DtISBlXaHn7K
yu9FMIdTU1d765ootFo8pDF0/R/a1dLoNMcJRzx2SMIQ6WNFxWxro9gD8tdFVTnsmsWahC/taKsb
ElXlNsXPNAX0KjtP9EEr44dUVEYIOCJvMUD4r87X5BZ8wjmKBuh++pnYwjTfK3+Xz/Bf+fk/v5t2
brLt6mWI2p90MHK4d6cIHrxr6Jp0NL0BeYOXSb+aJhjs1f2Ut9i6bsdlVJYgj7R8fe8r391LPX/X
qQogHq9OD337nCJxC7YXwnb6WOD8V4tzY3Q4c3KCiiDm0H64fw+nAqpzzVDTX/V1dfp/r66gk9qf
RJpIfUveaw4z7lzF640+ZL+MGNAKr7fZs/QlpsdXo2CxnO/t4i/XdMs4PpA1BAMwgSFHmonhfIuC
I1EwRd7oQdrUiNuW5lwVlPblb+jKeH40W5l5myC3mcHWGNYGOy28/D6Ya+08HWySS6cBOcXxYEGb
LagqmEuilo4Os9bFWEQumcWAgi+RNep8wehyadZjYyU4ZfFLuIz5yg37puyMgKEZyczwkmUu50kO
NcKkQmwsJLgDLskrocYpaHAAGy63a8/EDou3OLMTQxcv/z+rbxC9egg6/s6tGYJkO5AcLgCO9kuB
+SLIl7wa6qnySReGnOUL9JD6c65UupPLPm5OgYPyqy9YnS0Paz/WWYjFJ2I9/Nu6D4C6bq1J5GJW
ag1l77c00wk5Fgy7m9EyDe7lXBT1mn04DEktB7vj+qxTOYHiKAZSLeB8PbTY16U9YgGkDNjG3pVX
2oDAJZRtsSXnPniByAm2i1VT1JYdiSmmmkfq3VtEQyuOyQ0jQobE2aYYaJDluXl0niao+g2wAems
qBdq2RXkCzfQrZpAgnqWh/9ee7MFVbWdkIZHcZDMxC1g7nO0e444rv/7kFE/3qjmiF1HdTEWjLPa
i+26eExq34T2/Py1qKN9n1dRVv1rO2EzVCWa5M17dr9BBLQCuqIvfjDjFO5tSzv9GazFTXSznEXg
iQt0mSHug9+prM8SVmg7MBzcoPAcgZgRfCKeBcp7VZYHMjN79Xi+4QTTGKWJEDXwAo8Mawda4gOi
nMJAVO5sY56VkTO1F/48pExzKqVBHsM0dk/II6CRwlZsIl7XWUwnC8wDtkoHZzoRjSpMx3z6qS+7
cWotrwl8epCcoi6+0KbkyNs/QDcqBgCZIUe9Qsw31O4XIoa5+Cao0zvt4AeV4qgIGQ4rX1aK/g6d
v27ZDU1obUM1WR3g4XIcgs9BNoA3QzkL2Mda6wX6jyEhfLiX5M58A1DERey3lQZowBBSePdtwztZ
/UYvZSZpZ2kmtLa+ZVpqRWrnDzxxLaftVH/O59bbsPS0VI+xdNYZY/XafhNXTfbY0Y/y6GxukdEB
PGxLYNn+cnfyKLmBAHOcvU0EbEN4rxrRScvYJow8CFKwNAV6Rtyg+XI8itgwrA/Od0JxbUKYI0MU
biehd7rYAMHmjLjjcHAitLqbOrOKk5vD0IQDFXPRItk1pJeylFTfuTwfMvW7jOnCuQEhMImIdWAp
VMFaj+bAfm3O5KndLEpCTws4bkB15vCrf63nny8k5pS9NeLUdMKQT7I/2/iadWcEy1S8GjUzcPFE
MpkFIk5C9YO9dXxRlc+RKXKmOpoUOYZH17S56W6KithjGKeJxiUqzNmCGj5lfZ3iLSTsRL2B8E2h
rbGuRWf/gY4f8F9QH++6o85di2hbsLdQ+gscz8BETWeSHYrjWosDCUFqvFZtKmFVa+QdNPfq9w5b
45ZlPPbP6HBBvaUQ4jQP8pxoIh6NpPUrqTiZQm6KaScU/WYCht2rhRbWup+B9B77MYoDQS/O2ST8
jlYN/v/zMwPjyevO2rIj3ZzSvl+vioF/J0X8WgAZKhCAG/ZjamEr9TrieZORd4G7NrU/rxDYOs3o
U2/cvHIZ+fhGZGmkFwm6YAmyDA5dujXVhsPyO6OITZ8TDQAFyXbaB3S3qVVgpRlzZPasgRsVPszW
o+q2lN83A4VBGJqU1U4PYsjvgewLPbZL0NZsUe1fhM2DOijiJQRWevreXn1xoS4cncAGbG+vk5eM
8gP2TxnsJ1GXiUENacr7wE7YSW4ttpp3KyLo24vWmxGeNCysPZgTrZrYVFXAwyIDfJIUS2+ooZgB
XGFSKwDhSwkxL2LTzN53AkLoEnY2mA2hMA7uO+Svv7RcJATK0unER6lEWXVHDW9aZ9bgI/qPtq7m
R8CVNpC1bdCvfrgaOhXxPHo2XGVNsYV5S6oMJCILnxZNmJI1ri5WF8vD/TZYKUtN1npdVCnuuwDa
ng4ZPvHVWX/vA+dH9xtdlDdBHCvqT+awgK+ybggpUwnJzojG5qY5Vo33TR8dftMdFaSC9pFmmLYw
HFa80MhaL7tnXMCl92OzoW9RXiZO9OXbjFyn+RsSrz2Vz4zTkM0NJwVXViK40Qrj38H9KRwLDR7E
TNCEB1Ek/bzGgeIgklng48G3YEaZqotJP/Hbc04A/OpVMnbvu1I0xErQbBCR/Tnsqoo0ANznj8E/
iDfVDRplYGv1leY4t+6pqIIhVMdD2gQvefHdjd2vqutZv7QxyES5TjIblscpp1Yw5SZSF+n5ZDZK
Se+m/KrqDUZqcd6KvoE37fa11rP0mP3/OWZsrTESo0pjxRcB7+41su6zwa/KBCrW4gxhehHukajA
7//5g2wJw5B9zOk2AEFPwNvuOdc/2Uzf6VkE70Ajaw+QK5M5KaKgnfk5aoN7ZYIWwPQaqmeYTecY
YSxcR8Jb25vlVPu86BU0PlwnMiP1DI9XJj3PVumV+jPgVx94W56XFHLE6KoVMo7Wfk0ecWaQO0Zx
hdO6Refuyf/DqJmQerbCvbZbnohRw95J0iwchf/iuZEIGYSlnsTdOmx2uJvCH0pvWKgr0krwXWMK
rEh5gCcpw0u/F/M3DElH2DXcQ+Lcihj65XVPD7FrnG57w5FiGuCaMbGyX2Xim0pbgagE9McDYSp9
bYsGed8P4/Uqv204v4kttjg8im9pPK1BTObjMulbFiYm1CCVv/v2eYEM5SdYczGb1dZQ9slx1G0S
y+ZmWFobZ0ON5KkWsd4wfPqtodMkJ8e73tiP3Be3NpG/hsol2OxnUNar4c0d3K6P6ZH1RR5OdX+e
z5X864lPAX7vyzh+xfEeuOTLsM4pErxiLGo+9Z6UhQPfAYr750zMpR/kqyltX8ShL5blK/uaGkfl
tPlswIyeQCDgZo8uLk+smyLQaRewjv0MqYb4RAkIP1aPSj0aLbTDIacgYDmldhi9BMJyV6cHXNJv
E5RT7aU6/auyDPzqkU/ElVN0s22WHV5px5f9WWwbSYuZsmevF5Tja2IVk/y2D+iupcD+0AmuJAXH
LgngZzeOq789P6aeF1ykz4EajY9xhB+8aghHoqvySYB+SDYLG9HofOJnVNRbYzfgwJvH4BO+GbCi
Puu14J2HiGhgx2X1ur48bQ+Ftl+YDRMBS64Dm1a3tAl4wUrmRcyg+7OfNwSwYuWgvOw4qbNuwO6i
dBZ355jQJfOwzlPRKImvaqIrazLuHmfPtY0ayuESjpxi/erK/yieXHs7jr351+UhwbqF6XidcQ3X
aUzd3XnkX9Ev0lKnMoJ6iZdJMjvxM3Ry3BcNN9q2FPSCXp/1yR3JwhlvPNkdX90VpsRjI+MaX62+
/rBEZuKvItkw9R/7eDviWE7ziY/NMb7QF8A1OqR5M4qut/42l2wvpOvU1GjncX/zgJ1Hn3ZsM1Us
UstZgKDqBh70CNhvrHtCKVa9pRIqhgi87Vkiq54TYHjRccXMU6bZK/wAAImIV+mGbm3nJBf7Fxy9
ngrZjkxVeo5eUsnOYbKC6UAOEkqJdJbOKCKNICRriYr2w9UFAGyeUXP31hBNpmydY9x8vH6cUQXD
guNG0MqLKjn71N58puYstecNgp6HbdPrFx/Ubr5nDTrq9xFnIBIjX3IQPkQUN23lUQ1pNoEPbd50
hPpjorLU3qwP6u43A2uZHOzkB07tEKinH9mtRISIYNSxD+d3DGTx69pd9NsMUUisGW1BLnfTZHx5
WHSn5e+UTna0p4OV1G816XHj17M2goOQlIvfklPPTL0OZu0afdlZQRhLHH3VPxS+Ss00Jl2JuJQq
XsIrsDIuIb+3rnYbfGfWk9UHxcdKFvqT7LS2eMvr3iYZJ6u1ccrYzngRA8TOLpMGpUm64GP15kKB
JS7zWck7XyJ0cO2Qh3AET+Q8vCPb226yDiVZ/IjTjrwitrMEhgXetxxDoRZ0TbjvoMvrDYU/D4xB
KjK79hV9TAdxYYQ6w35d2RTRhn3F46LCZTUDFDIng9mnQV/eeLDD3Qtj3+8UmyywNZYVjFyf1OGG
Us1Xfui8dxjD3/uB+QCYDZo48uZ5+2hQ+IDwsVt09zXxBrqIaLLQ97VSxGM4QZgsAdrC760elirG
cQ+PSq9quKH2AP3kFqi4am2zV6cd1xaD5SUswHKB7rqfJsKaXh+F9aNYECq8T4l5mS1RbqNXAvIN
XF1TpsI1Zy+4OYoH7F5KzJ+gQBez2Gt3loDVDj/PGyO8y9hevSYlsbuM0H282qw2v83Cj+G7lZjd
Njpf/anglCUv9zLlKRRyJDd4eiJeSYdJbKjUCxfLuqvoCwiHLleOEPMxAtagnMPlxP1GJetSTol7
Z2jjkmDh0/qFHBNkuZY6vNjBRbguPx9p6LnRsxD5/VI47WakNDIekuz+dxg9IOr4z3I6hNbriFOm
MlKbZQ2q0Q62unerTZD+Ly5hAIT+5en7+gvv23aUbGSX2mQrecI57JRvkVVlTT1PZN49NglEb/hS
6BroFhvu0QlptGlI2tTucXyWwVOQaAwV15J7lCZniTLgCbIK2E76gr/DvkaqS/tJqF4iqc1mMoQt
der3aotSAiCsDxZxR6v9dOsF2mbiS0sCFt2egMyvEJ8SY7h6nozub3Yfkr7sGZ0Hkco4BIjJ+0XV
NRXmgmx8BCVluaTCO5H0dir8i7/gfm1NolniRii8B2FE9DU+cy5aFjb+DRtopwHDdLsZ4tW66LQA
fGurvzlDSKrr3v00+FbZLcqZVtl9yM/blUfWv8AGgN7PrsPJo8sbp5Sxamnmnl+DrvFE4VOQ1dE6
Gy0dcpVFFIuOLv/MEV74kb7dfHHTJ8U9GaIhIsKMn4SCNvh/EA7MBTljDCPn3K6rPOhKHpS5LTff
8a7LvTNVB595tHOAVP8HOgKerwSgpOougne10chgdELGCuC1SuSMvpNYjhHYaqe/df1m2cPh4x1a
EfTv/5mRYmsjqQn9ZQ44F/IDrr5ddviAhR2Qu802/a+59U7Fp9yuXCJWmhl+ggPV8tEdhCZqrcFV
UUd80D9y9vYR/N/4TrDRR1jmGnPjSie7z4pkXltriyZZZwq+JjHRpMc5gJBOvNFqRxEH1UsbGJrj
/gad3AYZMpvQiOJAnBayOP0MYrVSTi7IrW1QmgoqDnQNI5+iKxwjTvht+bwb40z5yMqOCB838S1Y
cHLnfPX2svyDDDF/q/bjiUlf3Son+ExX+9VI+UrWvm0J/5UW/LBG0QFQnGgPvlmx/nATy/tAb3CF
n1Q1facY1LKKuiacngcs7U8j4M6AdLqORMZri3BCBcoT5AJtRZEndr9O0eFLXJrfAooSgwuID3Mm
UJRP6KeSuIySYS0W7YBWC15lbVmI9XpgHDJdpybPPdF49lf6V1BRTP5tRU7xgEiOynWRaMgZLJQb
H+Cfri1W9XtKRlIGg4oyFz2oW5O2l1UyiCIZrSp9NELKVnbg4wVLkT2P2o5yFTiaU/19bd+jRTVa
JIqSYaeT0Hd5w1gtUrezJTqrfNQJ5wuXAthXkYO/y9+K9AvGikZbqk/OmGn6iVPJ/1L+JYIkMdfL
ll1abRVBwcKXBvUKVg3tTjW0Eo+/tzGsX9cMfH7er7r4ay20l18PXAq3+/GWwBnALkkt3D1PfM2j
EiBmnzpuNRU0O19r4nsIAI4Z/eHtryEYHj7h/IFtgFAiwvCQ4I4L41sB8ny/CcrimggCtHrzq9Wk
V3RKgPhOmszsbWDmt9RcEgy58FhHQyyMWUZGinKABmEfOA2iA7RdALz3xfGWuZhAVngq/OCfdf5g
8JDhboFhr8MggRwBFGNSiwuS0Y+x49Hx9DfU7r/rStA+JZi+fYfH3O56qIr6vHQJ+00CtIXX/mEw
a2bw9v6QRFB5ssjsOZFq46MVNwQz7iD8QrxblBNirCN8iQI9ida2z6KEPiiLyMlCtzs85iZIUght
T1Rx9tGDE6x2z3uSTMg1LDgjICWt4EQfOYIf/F3SihiWy2GLHeAxuIHh26me6Oz8MGnpz1FSuRA5
41H/B8BcfOahn9KKq5ufQb1iwPYCE3FDu2GsOPmvvkPQWNy8Kafk45gJYrCY4LmtE7FOIUBBrnPM
MF9qLW5YOmXWEr5V6oHSUhNieyhXzMF8UXBCdTwu+JpINU5vXcBW+dUiCHFYsLM/JMNhQA1vyhAj
ZLFXw9AYm1Ra5cTeZi4Az6tAkD3dML8NsrLarDhi0elccM39Sp9qWrEORNNQKtSyme8y6Nh0/YP3
fBbTzDnUXsuEIDRmoj6uDyY90izLjVC/e+gY0XBOUpJDh3+k9J1gXSu8NcvdbGLHjAAd9qrx1JB1
b0MvpBHs+Zz4lCJYGniSk/qTp3YZM70wFuSHIF0Eiyx4nwzWsauLTJzkZX8Vd/eeuA3QABk2GPtU
RUuGvp8Vhe180fpfKEu3lTpIc9u1QrWfrpq0C5qXqPLpBs/C2odGhRToqp9ba4SorWGwnpWaVZl+
Zs05POe5hKX/taQzSTZFXHg9nf08GQhtURR/d9yLKYYKxA52TqCliUyepBQ+AmykwAh+U1hS6Tbp
f1XeSQkfc/kjtKOEkzombE0gfV5Z+dNki791X8f4wk7a/JOCp7qL7n9BuhtBywWHytMnkGOpo2/8
B8M2HrHcmu48NbeC6yrtUGAMtc1/jaNrIXDwBOL1kZIYaa3ZXb00rd/n5xdmAsXwtkZ70OpiOWIt
YTz0zyzNiE7wBYfY3ZsrytO11mPl6C+kwdkbRdnckm0tk08eRCpPF/B46yxQ6OOrm3nmbF2pGBbv
ceyS1FF7kDDnP1vCO1jvGYTjvhbDugzhfN1GTRaiVHgsTh/PbXPT6zSxaTNuNMezCty52pqrnfAe
irFRDdTMOJ00sSQTizN6IaJHIIPuos5ym56mT9OMKrhmdXqEcGKwY4aicY7pBVpTluqSJnkpzAI4
LVxQPVVpmhOcnf1SKqq1WMHkWQ4dIww/yayQO6W/WfeCwb6lKA0X4wCZNMcWZIvK1ywficzMpLLh
yQ8qfhyrpSI3rnN0IPhDItvDujDbmrw63L3QkY7NhZ/3rbB1UUj5ohqs8buiUB3CeyMog7lXs7YB
3L3w2QWy2Jor8rDQNORHaf885ZqCuB7KxsgE5WBhOflRZXuRwJ9koG20nH10ObJvJX5il+PgTZ5M
P1vXwNyNQOuy9Hmr4kZ63U2euiIprk8I75N7Gs3WmVk8CbE03jVwSbxWzJ/QNaEjGHoJzfxTjNPG
NU0Bu6JAPu6tF9mEoxaCooXEaYbkxA46sVInOWi9gbG83kbTkyt8gq2jIfQpEInh45hP1PjGkZHY
/OzMpbUv35YHW8YnF3/uMzC8qn9seqUAnWxjd9UQP3vLnFK+3WAXJELqCwk3FX6/Zr4qnHXD36ao
U1N1mfuB75Lw4YjZR0P9uQ4UCJtKR0+ZXASI7kkhlDHpWVj6QXnzEIcNKPuY3JkcsJYhiQlHwUoO
jwEaxuzv9+xkrLw5zXKcp/Oie4b5dxAiY6V6jNUk8eC2ZxJcpUO4PBwAQ7J1IpcWjLIlOuZ0IscP
P5BsD08geKTAeXRnrRJ+lXnmDEbQ7xi6rWYkRKrm/nydemJVwaTyBtNZJNLjGOf49IPhE+jDYbfv
HjukiPZhiHWE76da+w0UdK8sJGPDPKYZB/miaQ6jI4Co4ga8pBsy9HFP6PaTvzWKf2nK3tPdg5zL
svF574IXGQ2zZBOSsyxKOc/+uEZYyDyGWwqdwE3oZXpkQFIIkcA6GQhvmSK3iq+VPGyJRyKJFLlC
/pG5b6OoLVS35ux9nKf3djePTDr1VmsnWWe3lgVbVmInjieXK1YtPD6a7YesRXGCcCV3QHiTAXkQ
1kY2U/+A4qJGw6X2bHmslIrN58eu3FH5yEh6dN4uVCOO35Xi1rN7KVgnmdI3LAYjuPEmKeSBizfJ
ow1R0xASxc0U0HuM58yZ/OpQKRGKtYPYGjXZLGkbtiEmSJ8KrezPAIZvABWrPLPtAzJh5pg/3yqs
LwSj0zKW8aXKs+C8RKCGx3BEPIOV9hioPxnNLfP7O1Ud/8FuetrGjupe3tf6c1Mlq/Y/+S4CyW33
SMc1pkThzK6xIZe+U4sFl0L2ChsQOr29y3DbAW6pdpuVLt+nkzd64SOeVrgA50sg+3lh/CtpdDVd
M7jz979e2m4Mepbspw2zm3vrPjT0tvL2ZjxY0z4yqSgSc8HRF8kKHetmP9LUD/FWpoP6Gmzu+KFI
v30jC/JvevnFSWRuvZYo1Ef1ixhI5WcitLoUHnNLnk+vrZu08fuCAS3jWtlxe36G6IB6iWKZu2VM
lcup4FwToZo9beT7hJp2XzXsvyAbGJ6tnGWJ+AcIW/DhJs8JXTwNXUiCybb4JNz1esm0Qj791tQF
XpjUFPLWalCj1QS4fsoFJItpJLN3IWU1Zxok9OrnwyXNnkmC8u3y+kTotm4i99CRpj9WGOJ4WNb0
wx0kSvDWyq/jNXsBffnmPB7Gq6ZNs64Ob2fJtJu1eTzdv/BS96OLdOLc+GDg2jPoUZkbRVJS7SZf
cfs/o0YoM2EQrRfCBMPSrxFWEWEJmkNlcaXXK3x3MqpGCXlnLg+uEG5o06Lhb/m4qksgrSzLvcMc
YJOmgBILMGr6wmfCFAbImKEXaUQIslGoWlrSPsnPxAUdvMR520GoBQvJmwYQZw9jX14XP12+Y0x2
3cHvGGPeEQAls5ntDaFJ5v4VQoO6vLfng+DkeiXaQwm/HBxf94ANPqJ2cuEZOLzduC74NiBGjEZE
XtegkCJ3Z+zwej71SA/orYcTclf5EOg15sShmPBa13BQvW66hmj2dEbEOSeFPj9BK6T8TWpRRoUf
2o3BgWeO6gPy5r3JjhSU6CyLc9J078orwV+o9soh1T5+7v9qasMg08bzMSX6hbGsjgPfgBIxXQht
Xk+C+dBI+bkoe19zKRbtjpMZl5lhsDmwtz0MNM7Z/cgeW4UYlA9VwmKs8oAz2kCiyl7h41Mnhnnf
xEixgUU0GVreF9Sd0d7M6CLq7biZ3tSQroDM32w0v+aRRXIwIQG8Ld/yv+2OyTQVl2A2OwPMrOJy
H6g2fjLkNPk+SE0Xa4QEpo67qZtQqO1cODfdbYHFdGz3PBL/OCDS7fznKJ/XrtfRY7Zww0EWpfEv
QCLdY90/B9xUSzvZuOsLjXdY/f1gGAufEWkxCD4Bsj1r+ro+Fr172NrL7SUhf8qSugNfWIi/AFw/
fVlAlmE+2/m0FsM2lHsMX8kQNBfBiOVr1uKLMJrWRQZLdCtdYfhV1sQzi6rblFVFNgWDPs51UpBm
SsauH9yWmcwd+aayPHHZy1PMo+CvXrv1HD6C6dV7dB8r67pdZ+madV7AHdFBa5qT026ImO1gw5u7
tKKKaxcbPn9dlufilX10W7LS5Iam5ldnD+4gSkt9ptQsRINgTXaA12zt1gDbndnM+qHEK1Rhv4Rt
8RaOcpglfBeb+vsTSQamEy2m0YYgwqfhO+fmGxPx+NJ8OeOmiR8/8mKtffQFDqqevdtQbcqh/e6F
ekWrzujKKyihnfiOZEdLTWVAAnKCzDa8TSREOulE4HVh7BQhN+ZWu3cmhtLt8M3/gkzw/VWq6nMQ
odq9BBdwT84AmN5j2XnshfCMLqQqcQ5xs3u58oZI9sQyYVGXca10EKPnysKUMoZZIH0WoSLIKz2z
W325e9Mb3h0JAuE7ejc4jJzzkQOIeDLmFrZw8wGA5ISpfxvBb/ZRDot7iDztyX+za3Ie1GRyn4EY
2Axa2xPZbvtkPrJzmia6qLYZcCMRrCYGFHPf7iNZXu1A7sf10h4H9mLPrzicyN2Dyzwth5ExDyiO
Io04R0Khc3Y3E3IKKERT0WG364Em1dZolYRJSFr++mselrPcNW1uYdjruYcmEyHB+rH2iEYp+ppo
XoF5KT9r9I3AoeqkuNBnoqorNaid898LCpXq7bwLFf2i9mzkveJYuXN4TN3AlxRNu+c+Q1DGfXYD
EsGtjz4OnlXlg0goVpS2Hu0tSS44pNBzWHmhJIfJkGwaaXG2IDvWot4K2RtnBaIHkCZuFbXWbaP0
P7nXKVPfcvMqb2JUxz/fcNYxw6GMC0Wx/aRq0VdwWY90m+t7qZOXCMASB0V3sUHKLPFJfWLoQ8+9
8IiKz71gCwkGATz5n5mvTsLO3Z6xUH+/X02NjKZd1gSHrsWC1l4og+Yc15Djk42rqanhRYks6YwX
ck9VEKxv+pq17KIcm/iX3vqtwjQnYwU3iOGIRSNo/hJ6Vc/B7fVjvAskO0OWUoogOxhYtl5U6wu8
ami7ukubPWijKtoQZX+r/488WKUWBuTevyLsvjaHeqFq2oszeaoWBSaJMYYAPjc+4ICSIHcZGlmR
Z794Z/r1sXlNdKItLza7gs3CM7BEBcQwF45+KU8ZlqUAO253UsMZ6VMv2vrTIikFbXZjhvbjy5Xy
5iBCrbdNEX8Ib7ZFzRtt0vimXu9ZqTnow5fDAaj1hk0Jj+NsvgqaOO/r+zR8HVxwhiQIqczuKoS1
RajzU8jocqTGExqL2cuw29FgMWENvJei4jyeAIPOZ/M831MD8dmOKqTsUfLgafSgCWJFmSgH38E9
gS2HVOomxFs50+Bn0nnT6eUdVjkk8uvT/5YgjA0Y8Vu050OXy5p1P380DxK7nuBcRH7u6+Rd7jgU
kFPuK+f5JwUiXl5MK5t4eYQh2Fr69vXf74UzYWkxdWoynoZMkNFT+uXgKM2NKjNuoZPRtN1vwlDn
sZThAt8QRmC02lphNJeCihN900jswwmrOKIja6FB9kpmRnjhjvmQtWeOQySc7qaa1BqQgIE/213I
x8J8nFi+enyNMiHa8Ijlb8SWtLFxEFrEx18KrX38v4OjvdxW69ShN4C/0y6EUNmFBUD+aNMSWgyH
ASoAYBQY5dbnO5jQF0aDQI4iVxNHEXKTHKOfbXAvBKYg8l4dMWQpDZ7fDjjGLr1hRzKU9FboOG5q
uds2cpL+f3ghWwEro1jHtPJM5dkltxHgO1kRvCl9U972GnAOcaGY65S4SOKnMyy8Oq1sCO13girB
QwMo3KE40uoZpRFYk2kx1pbX2raHVdRIqp0uhD/S4aDlq2T+oAa1NC2z941gyO4+wHn4+XyURnIa
Q0g337YvcPNEMZXY4DD1v7MiUyDsYyMNr1ziLKcIH5oiU7I/R4gIE6Hfqsz2xSRmxYqvxoiZ3c6G
z7Lie/KWYcb4I6HCgovADkzuCzGHT7HTHFdyMEZW5C7v38ET3WI7nEDyLWf0b4tfat+tUHQ9XNp8
WeTrhZBJRUXg4/BEa+4st3F41O0Yj5Gmjp2J/GZXTYaKi9zGrAzGQMj/hnXPbcFEAq9LoQEDl+u6
BV1BP8Y2smn0fUMXF4QkaCLqR7edm4NAm2d8DWnvASSnLrA3RUgoZSczDot6QZ3pvuo2jbDc9FdA
h2XrR7EBkWMjjMaOw/PVSoOz4Gl7LGRritLkyvbmgC+WrF0rO8kISsSAsPKY4SRzYE2y5DTkh9/V
R+lGbpCc5RQDegQFpj59NmmZsCfJSfa3ORKiKAwq+YvdpvzhW4FR/6YKYDM6I+1LT6+1fLvav3Vw
1ZKUpnIb6CNDzapUMzw6BuPJcrQkTJsnC+1Qql5WVmfe6cY7ScgfsVM12fm0Ay8Hq5FzbmlX37UF
EYOyT9r9HibjBhTFLRXJxDv7JmIqLcBdzGGaxXlTohaM8XH+Z9/6alGlJb6dj64Z1IXaQr1WfENz
cYICZX5vg+vr3YX3CMCx8OFGsOtJIfnnboX59PMjjO4gTDcV3ukJNc6IZMhiC7lsPAXgVoQOAHpq
ckaFz42CZ9VQI3VSxFOqmgfxFn9cr122h6PmLKQcu9LkiFDGS/MbeuQA2vejt1OtIOUEa2yDP3y0
jVqJk1MDg92ej8Ea1kWeHOBDYZcrEC/1KIQwNzED3nL9CxednddMdXmJNjzdXrC7bMQPSkYfavS6
qoLke6kCpPXSXVb2CRwNGRnyjedNJynESy0yHZnc2cGWjKDWj4dQN2y8lizbpAMwJvlK6hd+Yrr1
1+E2en0k216+3reX9NvwZ3NJYzZ5LDMyFVhLDqTqvZUEeZ7xsCb3R2nUCTAdEVL8k0o9mmj5QVVz
UnXoG6ZhSlJvglGxBGX2MIQSkSF5DC3Qcz8L4irECX0rs4OLzVPHYh42XqU/olRU7S5AyU78FuC7
ntRReZ1QtLPNXTEWwlvcRuUeulZ9xFznagKKhQi0QKHuhHfyownLVXvU3I4B3PGeWTQ+bEKP41j9
4G1p2gN/lvccOSF5hVBGlTxa9yFoHktb6BUccLMgRoxvoJT6eODtqiK+kJYW+H6D+t79cZ3HqdtC
WZndHbcMu3fUL7eSt5EOMTE719BlB8W+XgCogV+sXNgvVgJA3QJkExY776H2Fkt0b/HBAlUodCod
xk7sp+ldDTAR9Lx2KB/TgXIFoS3WiuDVArE1yNQ9nleDu4ShzQowavyPYTdo/yaOrk5g2+LSHOly
50ulxJ/8YRRfaCd1NbT+C6CK4KpVEKMGr4ogbwIM6uHxh4S1ldUAhHHp2UfX5HIgkP7Zzcf/ZaBX
ZrmLhIlaE62J84vp4l4bPiTLiuceEedJimmJv8RvDw2wop4PQ8y7KzSaf0qrkoTYHTwAWgMGG+R7
WXTrh96Rr5CwwPeonxLfDHSw9EaB4FBy3/GRPNQabc+ErqZnlI0J9nbJuVXy7zEnYgfQ7B57Ns32
BUT1lp27nw0FBgbAUuiaT7ooAJ1FQAzcNpzFUl2udwMyaKd61ZngUXxp8oL6pv3U1nAvopr+WeEf
7QLYaMIibmco7GA4uuv9Ztfb+xVwm8llcGZPcnJ6vdLcmju8G6IbACZTMcMTmZ3cVW4sTz+BrwkS
mNzn5+DrUyy2c1l4tbQDrqdxg7F76ePumpmVIPp/2mXwZDCvAWwqSoFfBF84adpaiQmghVOyqLZM
rADx1RGB2V5+jmHFO+rxEQm2KpyrNIiN+VTy8dNUwbBt4ZV2p7Y9zbep9vmGD+lRHuWXJucSiSEY
Mgqf39UqXegYVUdmefWOozG7gt4mR8ZtdCcpQLt5U3YXtnfxvsJPKgdP7KcIEC22NiOADGS+ax+3
QwS4WHHL2UF8D7TRMHDmKvmam+grtoMJllFQDY5f2IUa96krNroaPJLpKxGaJ9n6vTmEXSsA30F0
Ue5MTnewLq4grdzL0UU2tXGCA65nuSeqGpX9mPLabDVaM0Z2FY1qf/Z6huB2/eSUtdsv3kQLWMTE
4b7YyxMo6ZVb6Tyfa83e5RX1B/0mfyilAuZdb7IMtonr3hx7k5xrxbK04MAMQHQkT/+80z6ey8x0
YC+JkP8tb1dWQZ+CN9DK2jZHByy8jbAjIqmr71N53TV2OUhTcKUVXxrpl26/vRK27FsGeOk5WypT
yvLj5wKTvdjAogpgZMSAdmheiraDrtLnrh/FO8FT5RMt0F187v4q0Um45oWYIKAjbKLH6E93+DCg
FTPNxFRYfUJqNP2Rs4io8HXQGwh0StpKBMixifKUFmcUPb1JnQ9e6tNZRUACP9uDtQyOdFfft5Ys
rQsWIdPOSf724ugA4iXqjOpjF5JBGRioM7km0f+T6qHXe10542yUgCCdhxJ4vY1dLAWE67K8SoVG
Q7xUi5uXjli7r8hc24BeGJSniYTIfZiPvLe9CG0HlXPTEtUhXMZzPxV2mewkZyfC8IBtTCf3qYQm
+dfYG0i/D2FFrTWsJz4Z+E85JDLPRtzE2oMGs7SR6sfN3r0pV5OgAzATUbQBMXRhuHxkGzuRX6q4
nWMu47iRUY3hJtYkCWdGsdBVSbN5ZZqlYV1C3Htir3nb8SXvBcWUWOG93lEsWH1taCp8lO1AZg6j
X1edG5FxEgz4j3rh6E8xdpRmeiNaJZXj9SV2yIYuBzQcw/4QwiibkcDh9EEbR2W8r8qGCzXiEz6W
Im8v4MlQRNkFm60KBb/9fEzpx8rbLQirwFwQDdkAXJT0cIsZMevnGSKUIaC009YE+3eX1eyjV9EL
4uraY9ktWbpBGhIKyua3U9bB62BgRDBPUSyGyvygCef3JsoHhg8M/PBpJ7COJgoiP1bc2igA//9u
tSprJe1l6biKPiOFiD4l4drAbJ5d5KTgeELdDawa3IKCs98Z8BlU74HHN0Vjcc5Bl87wfZPCjDuJ
/8zAGqB6kk5gCzHz5xM91YSFktQVmg2SKIHHu5Cux+HK1pLRrTfREpWDFMPwnhO0QP+LaMsfxF1/
n9Mk3LXIF4YoJI/prvXu9Bh+YTcaW7bpXDbYRFD/09Hca8MKCQF9z+KTKRBG571YB9Fmw95Adxb5
blfU7MJqt5SjnCDcTik78pZ8fMQXWUwjFwrCyhRdk7C75jS6p0Jn9xwm+8psQJFPerHeJgsKvczR
zsu+PYSPsvJydMGq24irDU/gtveGsGOmnPSWsSpeUuHOL4n374nw51w0f3qR3bPA0FINUwybCs7i
fXgeE1+zlADPc9kkvp2CGirluNQ/MQxYcm3rUnYxTfpLv8jGqzsVvzRXiJaHgtFXzh2evzeHoHzm
WyBvv5s2iVvkwmbpAnbNqm8N0L5dFDEuRI4iL+RKl5BcHKTJFEOC45MFgp43v1A3suQG98zvycNZ
mLcPRHu/mVSDq4/B2Jkzk+xHZdPxzcVF45dh9f+Pdey4T5l7KxmDz6Ak7dCoRli6Oyhs3IaAtkJA
A3+jvoMz1x3cLvRRECrgiFENxupytvaiNXWeyRqqlmj7zdMfYo8Lrlp/Sqy+IZXDZTMCWw0daSSH
AEz+1sKt5d7nrg7QrvySLxuYCyPXWH9zIifkTBqxJh8pUaZ0LWiCu7Vx/FpwOqVH2vXUF7G5qGDl
/4fNBzRFf7f/bMa0eO58pNbvA/LPme2eHW7GuLHMT7fC72AMf44yu71fKztdvAcnOeY5+qqfTqs8
vetY4HW0vMdKuw+4339J97slrMVv6YlkTnI11G6eEAGGj4SWYjqo303OT1FlNK2is/cS6yKeQADb
rtrGeBn0qZV6qiKOYMCgpASrkacWi3btZa1dG0dtvzwEuUH5Oc9ueyG/ajSCrbrnpZ7dJJQJp0Kg
SYx6MCm582wwclQwnlI8Cl+mq2NPyPXiE4a3E2EDx8PA9z5TJUDA2FIwsvKUcrTrPvzmgHBSNdtb
WCC38ieVyegNHvs7hlAGfWfg5jB/lIR6AosKUNFnOHObyJX8CEukYr3N5wj0pZpLfNoKuV1La0xb
on+Oc6XrF5zlMIVb6ZqfUhBFXIoWufQVUx21n+IGl5fLZ46yo9cgS8cJ43vI61290N5qXNMUgi+R
cdDR9xRzxO1r2HZuS5FJhAX5xjHft4N92u+AU1LgG4XsUeyLuThPStZYiDcXoR6faLgHezRcmEs7
nt90J22putepN7WxPfZ0d02WkiCMuaC/YmyoVilTI/xNqhwDkoc/0610fp9fDLixIQ6Gwp2Q2wbO
+4BL1HS+MUKSQRspqHSYhUdlSO3NzM1PqH9EoFVvsdxBdyALt5O+mhy/TX5WziEemyyXOmI81sPA
srdpOhYeK4B5HMOGDoTBjwQZFffM/9JB4PLV+6G/hRcpXcXSu7iUJtmzbNiTcq7Z/V0Oah4cXyna
6Fc6pZ3q7zQx1n+hGVv4ZN+E4egishxBqRvu3w2L7a8aDH0dnAdpbi63GO3O4xMW4M8j9rkUyC+o
pGp0gxrxG64oBKxeMcHy57/qg2kgauN2W1YiTiBbqGzQ+afFR7Yb1VfJryJoHIdIjgxQ1YyUQ6ss
+rCKnTbLa7HIKWjuoqrnM5BbrgZjXlLnOZt8dGz01nTHK4Knv7e6SAtKlIwZjJFzI0UdcwRTybud
ECx13ORDJzr2+SZt4dUPSVSpeUUBcT5lZHQKhOCZX8Pr9p6Yi4CnBF3x1DCx8veyGTzYpFqGTB2T
AzJw8pa6AopKobNuFwGmJV1lojPq6xq5FD7tPykiMpoT6qAo5te7hAlmb2/FH+63YfL5Xmz5swaU
oV3yaU8pdzwmb7BuDNhV8FuZeHoKvoCPEaed3/VHNyhQVoTOS8NowHe/7m/CskXQ0SJytSxRYXWs
SZmKaG6/mGI7kMbIKY+rTUDRMPywxMWBJRt0ichLCgNcluHwXJDGKZH40v6Q9MWKyxXMwYUBJPrw
FwHBbQUTAZ6KcMLyqr64EPTDXfDa9I6J8gwhojgYph/gOtRut6yDZd+scO/wY1w6PjJrfmWcZPds
CWkC3+MIpUsiXnzZBKOPumshpm4o8aQtZ09G+8fs3RGPqf/GgZOXMpkCLuTyzP0Ix0Q+0nEdBhWj
dYx5VMbZ/hrxspZqyoznoTRPY3GZo7iOW4zugUkBbuOXDOH8cWXbtx+Vt14TxAMkJfysS8P8byw8
enAJb4++Vjsb1EFpRN8Bu/OU1NFWCRsX2hnebKQJd0B3isE2E/IxzZtdD/9ZVjLUBNz1DXY9Pn12
Fz5n0Yf2vHtnCmaiEoF31Uz5A225G7fHP6BvARsabAbjyGd2Qulpvk60/fTw99+IY6+Y8D2UZJXX
D0LMcl9AXhOxY+VjCgeNc48Ab9AEjqh6E3kPeLqZp+NP1CypX1hf3XQNej9UfFa/4lQWcaBZA6eK
MdUdsZ26VKGefHT7mEoPgECXQUHHZMxV9+eFJn4MSSx3aFevY97FIDeTeuWT0/Du/+cL0Fwt3ioo
qajuV2EheMQJafro7KjqDJmwdi4RimLQxrOJbm/LOGaAe0TkePewbioC6q0H6lfpyzP05TjfKuqE
AKkXLW1rCkx2bPK50T8e76Pldj167pA/hHEmE/obfM+YVUNfK7YQsmeNy3OyQi9PiaD2mvhkA1Qk
rVhXAUyzDtyT4r3U9JfBHrnM5BBO1tVhIlxf4eTDWZs6SA4/mDZfArTKou6SZKQlOSnWFprd+Lkm
nY2B74MNaMkusclebwBfB9ywErQn9mU7Rxp7F/I7amlZ+3SgQLoFWILmQaNgw060aQWGjpcMc9RY
nsYmPFOSjZMY376CbhpugpsadRiOGS7i8gJrcwCkSwUIjoxdOaMlmZkAtXhxw3iZ2Bp84lfHVpdN
JmdULpHoKLbj6M4/RNfvxEGC8dTZhdUN2IUuc2W8r0irjnz99Rg0ibAKs4BgKShDVo2VYXhHnT2E
IDrhwQ/8WeOokslfQEvvhYcPpYhKDxoNC36xcQCo0GSETShq4+D3txJ1NRe2wR7k9kdAXQfmNCyr
m0fOQ9U51OnfG4TSRnULcPKhM+VMuQydQVk6rfborMHgUyB/oUGACSqLYm2jNX5wPPuzFw93U3Fs
gWlNtgG0dZZj46ELbb9at9wroPGrxUWBiG1Xy7hH0wXIpYIKmi8x9FRVtoAiIHf5HQwo+zR+JhwA
TRrDviKdjyusMolrm1kkLBPc2q37baapVBXoLIbslUHnpp8Kch68fHUBwUSLguPzHN9NHmZqqPJo
jVYeuX/XXahh51qHjra8/wX61wHRsJM4ir0Y266U0fm7fNnj5c0hm7a6U2FDsjjsP3mwxhj4g8wm
OTp0PJvoPvdwi1leVVJUPY2pxXTjMRKMWFFE6poA1t0pqRP7EKED4urNYJpMXLiY4OZItUV3mtIX
kgS34emZuA0zCN53yhRJ0xEsZ19H8R90T/YkK1mnwsftQQddbOyZn1KeLcGfvqhHeSufc7UTrsnM
kIDafSlDPsJMF+e4OGAkNk5YJhchCsHXYxdnEtB2NJnAkJogWjek6lnJYeduZEYiyATDxWQ7UEh2
85RpPWhWRN+UORfDXsjbGuwqxL9FaBugbOpaCNH7jfRU/CKGakW8giHCGHKLRhG+Avm9GekSgN9m
6RQwNW6f7kuDlyrlE67fXPPujz2BRQ0W57Tck1hX1fUksSGQwyBNHAPfSsPGF7LcJyr62Jrcobth
WJNwaqg4b2qgEnsHxHgMhLYYwrJJFU373XB+NBZMSzWG6IcTBuQPBuHzYNbUz7tqQmK+3Yf0AL6p
A05h3ViKQRq7FaZGn2xVmSxJex/AkM42a4OJ/ohm63E9eiTDcBBMcrncdJI/rsqL8P9IjrTnwJpF
lYIp8CkzRqxV4AVFlYS9GaTzfrptJPT4LMnqJqxeNLQmCLM8cC9Oi+r4zmaClWYixZkBNzsqKgOC
k8CtKZTMlc7JUPgecncz3Fw5En2LwH15rPTVjsF8900HjeYcJenIIKzrKl9hr9GBQ2cgcOWBrSfj
NIXydf0RoC/TjmH+xR4DjVjrUbD8S9oiC7+7B3BbXYZOaFSoKJdpqm+dDTwIo7RS2uz/AA150u6c
Mb/zdP9LbBNJRDqrq/zj2fvNZyFUyoK6XHb3arBkVUjaPVZwOpP3eYx3tgzLKKlKzB98FNdmfSnW
ITQI3dhmcPisCBbR9leFoYU7Y67n58brlPdN/cZlzKfOTv3Is6EQ5CI3yVpJgagKxPmD1oKL2aXP
agI6Bgnf8RiVDun/tchxb2ZAUaFhPKRdu93tpKeDiDrSNS7ayPQ0s/ug3HQQylR9yg0FoD3EOAEI
qrVpFizBj8EQ8FMAn8ANTs5dUKAcLUiOS3GNLU/cuTrSwcsTbHGfoeEmvyHQnnDiPDAJeO5mGcQE
D4yISSc9woYwWNv0aHZydbgJ9pSOLEN65kJpeA7NATU53EY37S/5ODr6EEVExkmRL5s0AvxoI8K+
EA9Cu6vCudBx3Wcc0/eIcd8wdExd/xGwmgt4NtyqyiRubrjcGjwvTFQElEBk9YOTfgtTPjWtwtpH
kjJEwJJkt+8HWiNmsu8Owy8+Cj0brlqrkf3DpNjvoHrk6yoBJJTnNbLR1htNFLtYzCdZSPHAEQHB
WqDBl5dM7aLwCn8pw2VMdZUNrIp/PMMbgkefvC2GkRNbuvTS7Txycb9zJ4NlSyT81maGVrMz0T33
k9EkLbg5i5rHbL0Hts8l6Rd2pAre9K9vOJvUEwObqVn6tnuy749K4V2JkBB94Ad0no59K3/UyexY
nzEVVgfwO5V8eXdSB6mXQ/rbTHl9UJeab0gvmH/gKxOtg/KqPNp46cpcpYmlw6eAHc3EG93ioSi7
A+IPd7nrlv7o76YMrN0+m1TACVMNSvXsphbDVEK1HF79dB8LWxyIet4hsL3Wzi4im4nUDF2fzl8T
8g2HvmyIEE6tTC95uaCM+4gHCjz1S5TBtWF5NQkDc21U4J3/RO+1eF/wXkC0cz369g5BYApdwW/o
DUOugQnp/7Yw8UeOk6KGxCSa61pcR2SNjQFbbOFrxh9jqiRXEfV6VM+IuTRfMhpu7wQV4Y69V+p6
vNYFy5uI2QHOkT57BtS5kqNrQvh5KOeSnnC4eUt/DgLAAZALhFxGlY1i5XlimExu4BKnkhZxksGO
3+jNgEnY8TEvkhCtRXQcHypMyT2b2svCF2UIX5GOpaKSIyByv/virFe/0SldYF+7hY/GaliE92R9
LrWsYKBOerGUPjLMEDt3cpeXJREExmXSC+PkOYW3c2XR+/pOQMRp+vhM8WoTSatCUguu4hOK7fHs
/RwHaRaXVJPeCuTfl/6QEl8xEInqtb3MtLX33UcsPkNVHZTkLSFl2aCG+mbVbTnqSL8p8EOtazRp
5cRq1FpRWoBdBxXE7DRokVgnm6gfaMiiKwV6NTB7BRlULCxOnMSN8h+dCRoZb4lMGJxKf5CaQf2C
BUEoveNnllPEu1sAkdRXPWIXtMy980fDvi/qA3gqzg57+kUUropaRKvFCKCmKP011AIkfhcHQNBB
ZvhWmwI1N4U/tOCcoKmAvrSW0JUg1c53lMJzkfiOMz0CBwLjsxahRoLKaGBvi+56DMXY0NuxSapu
E8m8+myAWdp2Rj12j+piYib0jQzKF0MV8fEgtwBjwHtIz8mJ/2NZX4fTexoVaKljEVpqUnzMbvvA
ThV9xi2cEpFJ2OGcpJMGSL6WJBYBlCGxN3dPOpGEirW/sjgq/2oVcIaW6HhSjsMdAnQygc1yL1We
FuPQsy+3TKAsIjnn1TsZOFuhqH1KXmnBSSRs45VxMVpNO2ftLA226EA7PfACAp3i6G7mfw8kkdO/
/IOYtLuONxchI9/qAHrI0IBwLc/TjmHbJ/p3zeTSBGVbeRyKD8g6n5FgaKPKTM17/AnXB4o9VGHN
dfRKifD029GT5qBXW5umQ222huJawT4ivMdEnHFitOkwghC2YyYN+TTVR2FP0YFlHRbHfk50/E0D
1rnahowjmJ48DzOuq4dbWXXwJtFON2GZQwGkPm1tGHWivzyH4ItJ+eOOP6CU3/ZftrlMiIOnDEBE
PxxOnt03tZMDq59bTIFe3cEZvpLo3KDc52+LBrea5vQGdmjf6qzlrRgZml/YNt0ktvA1XRumtAlM
ioQiIy0J58o1MKvlhdctTtSzM9GIdd8qaiIJ/gaTDfNnB44g9Ig09AifvJWolSeQmZdLAiXTM6xs
Kyasr7UzZonP4lhEgNYNrkhWZmorfoOoo2SID1yjI/Q24WJMn3A8SLpKclAUD/Xmw5/bfOqEe/ux
ar7WX5GOpcvaLbjM3RYMrotytLdTP/pr+f29RiIANopXMqqD59yd6QY28A4Nt7uf+MNqY15g75RP
9pZhfQn8FOgzOCtFV7vgCc1sIHN+kuKlRp5GfRViN0wkzamaq3SKVDAQtT0hLIA/3zgqQ9sZtfhD
SuULWm607rp2ZFtV33xkBcLsEwnoDZELYmQ6B/qVzwAzKlc5W9lbI4E8YCGCfJitP5lfJ8UVi4CU
X7/buIywF9w8sS1Z3Xb9HJcj0UgewodxfgzNu+bFpyWdX0hmD7lGXfOwbxZ6nN0FR7i86NpLiIH7
0IO6hCSExiKZEO054GrT/XReIshfWnkV9J8Hli4spK27lt/nDjj2dCy7YgjYGw540IA5wJpDXeLw
ISZ5YEV4NEDCND4Qqc4gZ587EYjpoJsEREqwuTMEGXrzAv08hYKEOL9yokmXCWtOjhrp1O7i1MA+
U/IxhPMFTk3Kmg91wugA9INcKHjBRUUhzkE5gps4wEM1R5PuWLS8PISRHN/xnZm07cK6y3KkcL2O
/HJVIhdwkQ/KLGJCOmTpxQIo8h31EXYj89BYzXtkNpr/updosojPQpByyj41P1rbt8LpGRDRm0QD
VhniSz3bt50K1sC2aUVePBKGpae5P1cxE1TqUZZRwIkMJKoTO6JTkfnsaS0gsnJ2T4sVrpKjSEl/
bOC4aKSeIQmivTeWvWoomi+piNzaG6WPdd0q5aa9Wnv91inDz+cWvbbzygusgbLGo86X/VWdqUeY
lWov/+HU4zWT7duPknVFNfIe4HH4PQ/yEQ5N+eaJ3xJXlQ9hIYkaCms+ps8m+KEHDpcjuJy4BbKS
vH+FgCTjrBR/TVBvXjq0pJvSc6xddB2sYYvNTeb8r1L/AR2vxBar3WxE0EyuXTQLXpEIC569iiKL
XBriffU1b9hBk7qjvjvheZHJTW1sB1NatMw8HH06LMMiHJ7z20zvor6/KAaZZ0ttsIft8Rp+Hk8z
9lVxumVdvg3NR5kLQQLC8RvU2mCWkPPgdK9JREDq41V7kBQIspR+xESRN1Osqzud16TlRxlLRbx8
APmvF7v7J/yd9nxlRgjUtsQ1KjW3jaXrhrLLzg4lu8RSi5iXSmbRFkYrPvlCIQnQJYU/evhLIftU
Q8DTQpL4JYo6qYBXBpcGRtY6WoAYVOWoT7HQ0x43ZWV2G5u368mKWHXdyP0ljIg9uL3bqbE/3l+8
Gdl0CQoBYrRL2AHOPsonYn27gq/mKUJsaHuAc+xXHV+j/6PhWHlG6rR1sPrVmrE/TRjZqeQtRdQX
gf3jXi9U50TjQTK/uyqvaNHoTcyiWI6UK3rYDi4WQMvdxQnAvHAYZ3bJYQA4fDjrA7c79bEX9LQz
TtrY0HI4di2FCIZrH7k/juq7LHxVYyEJblIsp0jrp+ykpC4jrIOrPQGHtmpBJZ28MLpNeVxv8MDJ
cVGSV6IlGqvhJizBBWXt7M1guEPpiqFltXvZtEYcJrsTWftY5j+GkpT5bz3katIiLhsFi/N9vZMv
tlu3D08km8IXYJOMS/L2dB2uabv9oqklOQyRbrjU3LhhEEAaCRnktRdL8os3pAzoyyfLuKXsy/RX
NiuZWlXV6AhSOZfuqGzkSK1jvKMLdDv0ru+A6zq6zFBRMbvZ3dS2ZKhPrA9s+WoZmHXEt5eNtXtn
zrupg9qmljxBtjV8mfd4C7842eIjFwmQXIe/RVABwP01CDiRYNnYtojFfHeTcGEGY3EcUumgIDN0
7QvRAvWI83dHpcoO0RE0ki+TpCNMNVsZ9lOq3NLDmiYNQMYICxZPuX0EQxmN93wl8dCFoGEak46S
qQp8wzhfpmnv21/5R4wlqLd/AqN+oHky6cH4zt3VSYFetXZfrWUD3YWB3WWdEk47Y1/eHFB+Zw8E
DCqpsfxzXibFn/OdXzWfVAD96LsW+6EGYPVtYS/HFc8ljtvWGmd1nBZktK5OjVyXD+Scs02CKRal
baH0xDTTr9nHz+Tk4LPhOiiOIiIutHThG5nm7k0HaWvdbvjD1li6H6X0TQmOsi8mnu5vfYlIF/6Y
hJGDdofu49WN9NhQ7jJ8N7K9WiHxz8lQTYaS9n9k4nFRlSHB9e/u74ZxdF1brIX8wE4iQSjRE196
7/N3LviAN6MUynAL/xPDabO0RPQWs9M2L/etIsut7n3mu+Amu6WPvOmKz96Ek6FlDWyaluJJAXko
C9JQpTmIXwGcdh1TMg2exlL0yQf2mKmcbSBOPKF7uujr6UlRJ1ySgKSzWj8abNqLZsVvI/xNsOdo
c3Yclp/BtylcKkORlqaXGDdO83VfisrB7/0QyjWjD4Zb7TuEL58tjrzSQSUdTUQWEq9LYfGwYs9m
41yC3a+T+qUlg7p8CWSpqKLwZA+QUVlvvb24/mSMnH+1q0xaFylGylMb2KC726lN2IfgIWPgbaPO
hip8i268o6Jne8N/46RaLHm0EypwZzROhVySBBcNmZAVhmyeH4K1jSpSvhxdifgsWVvbX3zTSo/J
k1rXKF4hkqCombmsBvnRyNuB4baD5zUo9XeTn+U9kLiiLb8qo35MXnru/QK1Cyk3G/dcwOuNUl2B
CZVabV5KLax6C3JL0cHmY4bGkQuI2r7y2EtLorj5yFzKYy1tBgggSuAnuAQYeMLDGowM3K8HqCwu
UMxGMHoZnE/CDXb0oyFLCXk4STEbsCzTYREjffwjfFICJiIjbI2njiXsmGQX4Kxlgl2rjqE9Mmid
KiefKUeThpDx8qCibh0+CHQT+qNYe8O3QkA1dHav9sOICRW9XCcHuC3VdjGM6oXQXIVq+q2M7gfg
tE4Sz3QYsAUhIpH21NIZB2N3mYbElmyV4AVI1BJG2ze9s189aquw3J8LfIoqHTipL1yEeJAigAUy
wVw8aOlBPxcwEOMJEQnxZEN4DYPZaEQe1s/kNfuN7XmrzLz9/N6NcWSw0BRuqWMYEqIygZC4y3G6
hAowAqs0EGoIPUnJbBp0+o2qElDLb0V7cyaHljEiR1QI/UrkAGeyjMgjUArcPF6yLveUzjO3T4Qv
XIiE0jSt+Hqyp39bo/ySi4sMHDHU/64p2XQW9yQ/YrWQaL+sq0nGrIWGlczEnDvRLAMCLS3ikzCX
oislXashkI9/S0RM1NA/35eChCn8LocyL+X3gZ1ezOmGnzefiJ8m5CwP9Vj/6QkaD2ix077WdQ7C
mGUmL2mapH2XkJtlTfoRxZZyLFhOa4qwa/hkqmzTke1Iw9fujAfZJ+IYTWJUnbIBDn68/5wMmNLC
CTBmzCGMtpE9k1gVBBMj/sdMOT1ZluckL8av3Jf16qXCN3PxhM4MZPkMKRQ0lERjjKAhRuHEVrJC
gS2FWxF/aeIxk+UOyJQ4uspdki06oVbAd8STeFwVetWKXBMJ52/rZ4FwFrL7cn8CXjobw1qJnTO5
e3t8mSGM6MHU5+ay6cBptXdihHVjCT2j3eJUr7Aq7sm/Ebl3tsfGPR0CErqHbM1LzjWkUXKNd4bH
FpgjIuRhX9DKyaqQ43MJjpYL2W5r2nrgovghx5gifBlgkHkkaGjhc0jUikyFBlPmTDMAfI+66Coe
njtlgSBPL9kvGseBvCiYsUfYIM43aJRYy5lawY1nKmH9EZSRmpnV2XJLyDsgcJRdscaBds08F+pi
F/As+Qnn6dbk+bWNXKQKg7itIY/msP7TaL+kN1HsJGoaXYPLHDzvEFRCQWWaxFGqdsgWdMTYtfEE
GJXm0pCRaGVyQ4wni/XtkPK81zSmLKUY/+dMPmGfl2JY0/3OJaOzq42BNHDqZaVfGtKP6F99GNi8
pvb9eeX3HZcgIgyxxR/BOdyabs9J2vUbGjR0qUCEzFO76ksKPJrCwiRALcYbnfDO9OrqDlnHFV2y
rxjI0j5DAgx+ONAmPdJ2ftCDEhb1gmsYWLcySdGbFuDXiIj0zd+9tnm/WFnV5YygR6gEF9xsAMoz
3IXMlQPTE84t3V9UKZO+VjOyGSsa5F1zPdSpTO3xRWH3MtZPCppX6RHRpL9KZyknYUgGb4VBauqx
0vzn/iqnyt37oARLsMSJNyLgCOL0BfmbJeRX0qfjsaJj87O0RGQ9O2ta0WgrowJzgrj6isRFjZzb
DOBT3fhevKW2koJOWVXKufGakGZnV5UYK9Zm9H/ibDeSf+K+7583/bkKHZIQPUd8ExS5o0mXUOeA
+D5nqsotku20GO+RLs3NBOGqXUF/74qbKBwv79N5u9yiU5bEIDCWbU5rpsJAzoFd4IkACl4dYcx+
9non4sAwWF6np00M0gjOzB07hwnVDhimUmt5ND4NfoJCEK928PFFzR8ZA+QVcyS9Ku1XyfVIjDOz
WfjJkqpCaX5MquLX3x0Pa0MmcJy3TYGSBIeXcs1X6Ml7AUWto44S/o+2eKYknzwWD5SaJnC8Q8Ew
9wSiSlzR711vtdYmyppr6jTkPYmLbqxUxkeIwKmPyxVqrnw2gNUa7Dbe6K+0OqCfIV6bnt+Aj8Yp
ecJKpGBMWq6bP5u6aZODgrHuQJRx7HpsqinHbYQ3LJiGrBPknI+q0aMMRjgD6e5JQYD8IZDanhTp
bOGAHr1ubcTSUkJzsZqHQEMnI4LpDGff96le/Zkp4ySjAEp42wNcteHqkDKWrjzrtw2Oq6cHqezM
efkISE5fUJXWwphX5jPehyU3C/hWErcBA/9sMraX+eGcMz5y4F87+L/SKNzHDygOg8qC1WkHRxoz
z3eN1hoY+7NYp3OxA3bLCQBxkjm91NZ+34Yie7GlECnOvkwJzLEsmQI2dpX+uHF1s9tJ80hWdNmc
LtGpHUiG4wvMz9cYyAOb+RVFfodGdqBKx4Lgnf1phxAr6Ba88Y1OIeBH/PQFqDVABBOPVmaaSSK0
xSziDrkar0JQlxXXeWfmomlhQ7Xhwpi64gHulCwieFbtirHG5ycL4sqQVvsTvYnziKIsRJS+5ewY
v7Wru2jsdfiyUgGJBfiV4XSBLhtpOqOrJomAFGXmuXxhFn0n0hsBL/yU4clOmSZiEFzQiWaa72bD
PSV0T2pxXSHtQ4TqvQceI8FBLxQtXM24ew0Ecqns+eM0w1uJElh8BqLQ05rG2CMHKpuX6XaFtDxk
Pn4umJluRFVMKT3ejRsvVmCd09z25mRNIoHzesPwMvvIzgvfi6dxja971UBQwGiWSNvWAlioAjKA
+K9fiSx/bLUOOR1Q+RGTjXNz45QD6Tl7Y9BnHhNzrXN1bWkfnGJy4X8i2dY1Mmj7j9+Nz+aSvblB
RkNwqe30j2nGlLNoP2sEwi1xrmApa6WIZlSOQXiKYvoBA2G+rID99KTS4pFkqjao+g4fUUSfcoX2
MotZa9UXrTHtL0sNxXl7YN6C+Gg3zSEeCRkb5h5+vk+WZSUpeyRZ36sN07rDVI2iQTIm67x123Nk
rVuSHLRwSi3ot6ZCOJK/HgaGH/2DUTnrxHctUmnp4CzAx4JuawBwbH1lBYLZ/BPXIGMw4YPnJ4FJ
vr6hVhnQ8G5jkSL3F0jUGt+ZvUSWUFqG/Rn/qshwkTCtG/5SMNjTyNNBuu0Y95v1G81MJ89csmY6
ix9VlsqPVZzQe6Hp+hBETVyXxUBJltfepz6LghFfDfeaBNJ9kTgtUZ+ovOWWbVOL176vCG98mVdG
fst9dUH32WTmWAvAsOL6U5HchAS5Qzc18cMsbjv8hd/8HiaL+QxG9TWsiKmw2esthSZDYMpUWiy9
lDcQGrxQKlUvLY2w+XUTybRJ2DyuQB4PX7CsFbnobcq7//8rx/L+yKHLvBYDtl65IjLnL2aYrovI
A98wd6Y3yZva7ORs93XL4LgxE7helWOZLaF5kLpb0dnSxL4l56JAj9p+YvdPi/c4420ZIy3VNEWv
a9qX1QfSk4PBVdZnkD19tLQwvZ9airaoe8rXps8MSFE+2Ssd+efwfG84UMD+1Zc4/qIT2ceyXbRT
H7ij0xCHwmHYO7POvGli67Pda51WSQ2GYEtIlyj9/il4JbwMw8YvmkOkxh7ai9VRMjC5I8hoZpab
ZvgvFDDuu1hEiQ0MSlZ7wAV9Msvkvptc6yZBJQkKQEna7hwtljxgBZbjZfNWnov1Q2m3+gl53WrE
11Lr1wNXY6YeYt4QPXcFDleU7CBgCh+9dMAqhboXBzvMDRY77i3OpopreLlwIqRCoftSfjPUeCiO
KGpfDPfEa2WYtG2dk0fbStBFACtF6R/hiR98/ejrXE2lp3xyUeQpZoThdCbpxkjFJ7EiV28HlwFc
lCWCisRYdD0QjX1ih6m7fnxF2isrBU9JlT1/xd5xHb7L456buxWmzSupx3ttUWjpx0TXLSlvLe4t
kTVYKtinX+A0vBiBqg5YVmXkM5pC1juzUia6CVaX22L7bfe+KQFtm35De0wU4L24j6UbbUuMPbzX
f3R36a+yn96v/QrsSBxApy8YsVjtUnHfwxrrK7Ob02VEJchoWAEMi3QTo85e+P9NeYfeiQg3HEar
719OrnyYkT+rdhwHS+DVVoFNK/ZgcbjMCvdkBJNuaH3gHyVxF+eSURsQovI2Zt7TmEwicGkLETk0
d+OytkdUEt7oyG1wd5xP24mm/S/97u5JQN3msYaJLccdK4M+O1YIo0gLpk04K0kZtbb2DBfsUnoq
mFPQ+XRRSwBh5mJU+YtD7/Ve/XxuIGaQgNe6sQTPCZBb7Goz9Rvj5RtPrRG2osoYbIHAXVjwgfkn
PgmJFb1e6tOH1/ZUataPXoL8IrqUWZCv02sy4tYYxw64nIrQU+I7DYbE2O7FTVyoFXgnBD9oj2J+
bZss4mqMel/1//rGX7zacVIo9p9JaNK0cQ2sh6pItoR73ssqEayI6L3Q3XfZjwMxfuBQ6vhbUmbm
KGxNLXizwPMTV60Wk63kbud+6uMO1hxw6wnR2y0xUDxBNYwTnIUpZJcIqcf8NJBM7C8uJU7uPDEv
W28ieBqRVtnN/7ozqJ7RjzhIwhhZTMknDqgK0oCnz1h5Zr1bLUmD7zxR7wxBYYnF2LOAqm3XXifi
oEz/se6ry2q1FZ5gsYsFhpc8mc3n9DFkCpto3K9jHcU+fezybV061GPpoBVpD+DJaGCZXmA5HmbO
ZWN8D3UETtogQk0FUy3+Ltrn4bkLaSLmxPllGaQlSaaK0C+4FrIU2sM9Sta7N3s5+SMPEBxoS+rc
Bdh3w/vSYx+Vr2MM2QgUCrKvkjx8cUifXfcepmsK3bB/O7MwRmvvHvyZWV2Km4aWbKBwCZq+xPnc
hH9TMNP3HBq8GyhAbBJO1Zw3vIxxZmOAZZZ787E1TOqwJbBkEa4uJid/+jzCMRTJUuEtRZ58fSU9
1bBbjZd7w8bgaPQ9sflHLGFhLA9HuiQDYB5OY6zm0KIQoNn3uG2YHd9iRYgUdfT+sgYcp1j73boO
2boO23t0y0hoxM3SFeMpcq5dQYyJZRXdgv9CY6J7X6QzzLBhPtYZ+mAMb+6jKD+rmaa43L+O1ae1
H1J3nh3C8dJaEadkpgVHfydNYEJmwLLEzERXJrLy6V7vzngiObBjC60wqZqo5IJG4b9DLn4jflHB
bL19OtL4pWG8ZytuehxfAYFUg/QhnWgO8pMQkQkmysOLm1lKd69fTEKx+yOzPQ3EgxgUFazG9Xj3
Ezgf/qs2zoJVfECqw+Vy0xv/0KrNYBxCcn6InfxkFj1iooHEkB7Pfe7vd6+97Pm8eVWvtvCoAzcV
qVEA6/u8t5LgkWiFgXaxOswDLs4fmHd7wQ5Mmc1/XRDNVjFZs62/Ll3cjTcu3iTcGQywZgpRgT1P
2vMAFPm2rGLet7aaognw2IT2s20YZG40vxsy6aZhC0IchegAZZ0bF0n9t+H83+N5+0fQSrMXBeKB
lQWvSvXlUXBua1a7FW3ti0o+C3y2qptyO1F/W2wOKETFujaeb8FqrRa204/LpiYHs5ybu3qEzqPC
8QNFCMHHuzCnnnFhcfhWHcfcjjtzp4sz42oygIlGoe3KjCzGgwXBqTMbB8TLMpUhiwfp25JqIk8a
k7T2d5+acaDvN7P3nDLVXfeaycuvWKUGDja03G74Dbf/xXOfkIrADDNUf/14CCZ+jEmAT0HN4au6
nHt/YsWPjIYkkgY26VJpkdIPvy2i60F/e8kpzouvXhZbe9xezn5hiX9Tnej0NfjYUldHKwVQNc2Z
J2pzaxEIZsBqe05idbT8EIV/qE2aQwWLRYCoLSCqpE2bP55L+Frun42bdpCrFipNy8fYJxHOePxO
V5L3NVDkjEj0plr4mQGvQL2t9qvws8pyNlJ1Hzctz23u0OF6PJQH0Sr8nLJ+rJzbHcZkqhXVyYQF
HVWzyuJNw/HO0tEkpSM2e4GCEE5ZVLUvb324StuQSA1WEF6/AfVoouQ1NonZbQIoeeDo6kMl7k7V
UhgrOM66ZGdcIJPeOaADccrjC41s14y8AYIbk9KUm7FhRyIWXjLAqY40xND8DMi5H41bGJN6S9+8
l4fK97UcK3nOsb3scrxIif6XRPg2OPWGcCAxyI4NIuVmXD0T+4wQNxRo80u9gLCEwNk2w6wrInNt
wMnK6denIYxh9YTsaICG6hDnt6LO0xrTpzJeYtfehw7qQcQGaphccfSSal1wVoqvCYLp2NgpaAn/
M62vjvtoV5F1uYxDPLcpxX/d6CRBL8pIEWViyPSrXdWfT+tj7pCzk7eic/U0NnsYTH0e3e0UjpoN
3YQdfELrRWcLQlMFvQVC4qZRsx7JNbvNylp40LDcLylJ4IJ931O0dYTUhmHwItl4gHX+Chm160TQ
M/KhW3FGay4zKVC9Tgk0ItbrdfNQppS0mLC2PG5pDZRmhpX77V0iXHBuEZA6KE8xhpBAXnuGm36o
bgpqlkydwihUpxvIzA6GrfgyNyiBsX2vJR6w62T4GLP8bsVGy/1z/qsPhZONFq/SUZy5PdJdLIAG
kYdgzfE5o6nYVRfSKFJ9fWePyuVYkkboVMTc/3uFyhhd3+9ZYLUoUtZt/PZ5t5HI9n84GW7vnp79
JTQXegq9q4WDWXIMf9lEQxQZ5SRuUXlJiw2/7eLpkm3uN4rrhja2mF36IWT2fRKv3LxiBpaVRVp9
4XyjuJdbeAix3ZnN5gaPhFxOqlrAn/5VTBADk1jixdJqjDP31X8RVOzr3NsOT2B6/RcecdZGv+Rf
kcJpa/I7AmnLGueHzqQ9XbDCItFLTuf2cUevWnHGWvCZz5YmSnrsecc1EUj3MKDhpFOvuGhoNNar
JZimuKkurzQykl6FoDcub939GkQ0amOv7WxF2WuypRXpV+nGsrdGv9jNvY9uqoLsRQSkqZtYMpUM
IjrkpDr4V+pbT1ARqUnZ3rCZPiP4kMq5G/r4WVs5fGN6BBkf8bVo8mDwSnq6OVFujTe+u/KmYtXW
6Z/ml9y5Wpg1H0pAWZ1p3UojkDaSnJ1prZY9kwW9Qv9nvbf3lEHsTlQ86I9i47D2RDv3m4n4u+Fv
Oz0vSExZd7x/mj1/lrJOoDiXsDnHheFA9Y2vmsuZzsgnxgSlocRQhCpsLXb+sYqNAcaAHq6tjd7I
rtVidxPxkQFD06Yx3DHpQLgA0bQT2C6+Z9478pyKEMKYfP4hpp7G55pIHPnfZA23wmkCvjS3LixS
D7KuuqKWDW+8+NlJPrU8UzvxDgkNQX+M3y1bAxSTbj/0Ch0HqS1dvaZL/YvGg5MTypT275Ptnyaq
pFSHlZGmKwWhf/DT04egQPwDx3Pi+dYbtTi+5TEFWWKUc75FJYdQyewVyd21XnXvX8nk9EjU9a7r
xcahZJXDx87vVJ1re0V57O7cEz9JidXPr5picZvY6gOPh7wf8JSHtBBKSEfpMFgBpMuqHuv0gnDp
WIlfATILvjjwyihZnnLUceOt9FLr2DeF5Q7TyPbeYLTJatC/34ebA5iUdZLs6gPUbdks5NOoR/5W
oncYuPq92Y2Xk+OEda4iqKMu14UEEgXyaczviU89Qia199S54AxCieEskzVmstBocsZ4e7elAoCT
lCUFHr76dieSww6nS1+EmIsgeMjFEqxm88Wiafpb1x3c7R8KytUxeVdHg7W7n5Oj0LsDFNxeVGOl
PbmjgfOAi0LASl7IzpsG5Bb7pm2NgQWVrkzYcCyDlQ2wkBiljNSGtlDImNr3S1pjDPvuk1KAz0GH
W6BnoY3ww7QDyZIHPxmLqgzJFrDxDi/tGEpyJFcjnw/r9G5YE/D4RHMg9X3aZG+V4sWqvpkuRUDe
J9DONKT1A58mTG3Acgut85cPdRa1+bdczHwyI7raHAsGlzuJ7gHqcxdpFESPYP8xPpP/SO87cyiN
xXmTAzQOq0XA3eKMKEd1O7ZoB4tHSwbCBpN/dHDioe0pv5B1GWCtGBKgUvncTojFDQMJDCm4WLb0
05pbDxVW0Z3nvVjq1QxBLxNfibxD4YlOi/xGTzzbAlbRBRud+zcXtyjyGq8kCsYZJuCr0KLX8jFc
EQ8nndWv0BuaYnN+t1vYpV8+783wMXZGovHIaEMc81Au6AwY98xQ6UToLMCL1/Bw2bbySxy3BKPx
pO4IGs2NVGRsa8+X6w7E0LHWMfd5+JqQDNBlpYydYhuq0oTKi1wh8B04W6S+y3Fc6el+G+yRPy6I
lrpwlFO3lQCYJ44v1h02mCBcgUUI9hmqmN8YMpfdDKq7En3jRXQxCOiUWHzoREaFkA+5XGXnRMnY
IsDSsMKDP9JLflBl2IDL25OjfnhZWgoBvt5mXMCmS7gUBgaeeoQcLPs7uuh6NH+S7POW3TJVuF19
pZCqP/uiyVEfGPgwYFSLrpZlovlGmhnq+Xb9e8VSONpm8gdMIz9sC/OZ2mcWJz765tC6CaDStWXP
Ax0Vizk9EZUVC0HnfFGDmKVmdCVfzFz0pR624vXMf194O5kh7tpdPhOZXR7QVAPTGq+JeL6Vqdiw
3X8YoSxStKa91TAOdUXiDmjxj/i6FewlS3KeNCQc3ZNGMELBc2b42K5nnB19/u5bSmp5KLpL46yw
r6Ksb4FflTMPV3/WjLaikjA/q2ZBk3aX8HaZXi4RICeytiBCoGKNnOqoFSq9re0zMqRQGxI5uitf
+V1+d9R6klBwuU8m9WGa2aH76ffZSNPzUxwnwcj2WUkE4Vi4VAgD2zlIp4Rb+eE0KKIq0OU75bk0
iFFLeWn9HfP4oGpK0fqQhhck6NZA2GU/ilXm15OVzHA6Th6gULdkanIquBMF7fK1qd5QtQ3J3pj8
35DnSMv5971xqYQfTcy+QLZb7D8e9xgR5NM4vmylR8tXteGhTR6C4Qs1UcEq2688/kK4ZJ2VeA/R
uKFLVniZKKtd+rz4GbwozBLsRDuQSCZiY4cGfP7N2Fym6fWugK2An2AeU8wJw3zz6d99iennc35h
Q9sAuPKy7AIz8GHhDhWdy8grV2EUxUVT5pY/OBndsRAnD0I73ZjSImqi+WIlQ4uC+aYSXbSvoIXk
1Zn+1eI6kdMOXf3Mn7n0OMKB059HU6fuEv6sVVp8dwbOyKVRCFYHnhlb+xHeajvPpciIGzdtGk0U
TCKtzrFWkVkG3+U1XJpkN5dSJbE3qyyiUqfw+KbgSbe913dJOHB5pUNo/H1sLm+XBetaUy2Gm2+l
X9d7Fo4rNycKAJqysBfamGRGLnozqh7SAD6fGRZw3ZyDsabExs87oXuC8tk6ZW5DHuu+m5tug5qn
9JApOMQWMSpkK1xMHx7w6NzwVQwtpD4yqIf+vDUTRptLopGVJY9eUXlS69VcegI76PAZYnYP2DZf
Wk+2eliSjAy4BJA/GwB4kz0J+fEdcD6FdwOydhlFUQJFD63BJVUrbdV3SylqigEqqMFuunRRt2mb
s0ETIIxF3OaLspHJTI7vuQcHNsVpCRCb5Dlx7FLkIGmLrMGegoYNuwZ8FF3wUkNJ3Erht8IqTvXd
kyT7AC1N4ueVf6vEFMQppx6J1/uKm9kc6YsFC9wAaUdXsd8ZFmDlVXNPJLM2iuwL/pnzl8S5B2f8
wjVwFkYYrywrn2JktLfjSs5cARKRLDN1vddiIwi4TyDRTWTv9HgCqubN10dApHNJoPZVzG9IcWSN
8Ov1acPRxtfoEG0vQ9IpzfEGPXOXQ051UwLo7C1p/Il7lcdOPqZghc7e1vbm0/oHR3zMVoAGVlNg
HkYp7Dl11AajwFU3JJMDAQCfzfgsaPyg5/EEs2lk1L4z8l6SQ2b4breEb35/nGN6Dt4VoyKTitq7
RX9kd8Kcn4Rfw/Igiz1jbLpveAXFMkyEHExnzcaCqwNvVoazse5gfGzJg168gaUqJr9/odHUZSUJ
7ql37YeUbcdJOUQaj3rCTGm6NzilqL2bBY2a/6V/Z6ViI7YvyWbJjzk0JUtUuHjvdurQybJHI+jn
zT7oCyNkDJB5/RyGO6MVbZcNI4ia+vY1wd4+AVOnKeL5rSNoOIpMcNb4NXmQ0y6LFzkR3EzGGD81
y5+HFWfS4GNQUoTXchGqVPNw2AeaS0qjdX5wE8LeuA8Btaot2OnCHrO7fd2EMAloPIe3rrcYDXOg
EiwbFrCXHcLjL4v6cD1ON88GbX28pyV3LqKSDqK8zckEDbOnDIc78gwg2rLoeAke4P7SP7ajijiA
YIsw6TJNdR564uXq/oo8KTD0KhIvna5OjJ0utWle/o5tm5dpv4sf9AdMGoqwiW4agpAH3C/FPgF8
XOC8/egKfc6BGeyoNKOZv/QHGVsXswEl4sZP7xgM4cvTFRNTB4mUGUt70QDaA1ddoH3DqRoDE4Hw
wtgSGh2i2bcMllYSg6SWzMXYSfSVxFw4yThynfFDZsx5l/ee2fMDGaoc4NlwTMQEEDcitCtKSW6k
voQFkLoOkP/kIMFYNZQlmPkgOCf2+QvMDpDD0tlQdfMQ8L4KLMQ7TbY5Elzvc1W8kuWogzRZeCv6
B+U3Ul4BNtBC0nx1EshBihzzo/+Qnr616zyOnB7FzJO8E6rK3O9lPynePb5TaW7VU+9W7OQ5q7/X
mwSCSieBR7De+kARsXh+yHCL8i/BK86rEyBxtJ9+j2kz78clIIdDrthnK86AgdQMfOM754IHqQ4k
QPPvEEQvjrLwp+1YSPVpnCbI9xzVKz++EL0O/IsQN2dLdz1A0OsS7ButImfnNrkYUnkzJtSeF5sP
ZIwvPh/HxuMsV+alV3I8WjomGRS19gHkpAlcQl1kU803Mpe3uqNyVhcjYHewkZ81+HlOSok9zOyc
DPQznpogEsbjBK68paSBIES6UBo+sJ9qllvw1TELofn72BpyRtLhRoPSZtdG1k5bj1+FKmnaDHCX
SDE46JddYzDupPvSQD7Ks+yhzh2x1FncfGbr8PJcdZ68xBPM5Vo7Iu/cb4OdWBR1LEz0mB3urMmZ
qoG//slCOdjnmZPCecjoE31vcOd5I43uQkkI4oJMn5ePObhbjUCYYbsikoHawZ2XZRBj5l3IcBjJ
U8BKLVtp8t3i9KY/SHIs7IkqQ2A1zWNYuTg52sRrUV+T6Te7B/QA+CRh3nAC6NU2ImbqXJlB1B6d
AyCSfk2uoeXNBtVLqNNvu8I4E/+fd13Azg7vA8slGVpRjqblRyVzfaCZnaqJg+XH13113lDcFq/W
uuBraTV3BqLUH5EW5bM6qDyEojqNMwGo8/yeXFW97DAhIJWU1MQeEB3n1yyPLBANnzCgo6WFz2Qc
WXhwjtRhZyKgvRbRLziDHtZvSoV6iZzRl07hoTW1jiNTxl7tUxU4/j/5GOVCTLIG59AH1ESAvxVj
nlXlwc3P28hN9yyQxIb+G9GcgnUnQ78ACSvIRswVjGEMnTDW41eAXwqAqW/dHYcYG4EpoXivbU2j
SBy67o1FgdFpVK6PURsckKHGzPnXni9Fvb2I2CTutW0U44/PVFauo97Nv+XeaIGa/HiT3hbja0Wd
iMvdDJWLON4X4ugUk4+VtBfHpvLgq4pRQ+Np2Zzk2VbjqKYshN7e69mF+OJ7Nx7WsXCGoBjf3fw+
1CsnSK/BSiGqXU/zlj6fSXc5R485sRgLWncswBr57l41grFlQwEL6n+pUIrxtKPzSags7ZRoy8eD
PkhZbrhaga8MBrXUguYqK0HgVow6VYDD8gYM1TalXKN5wKXMUtUBex4XZN4SAef9KyJ+EbuEMVZH
D3adz8ieiQ3WnaDrqTksG/yBubyStUeM1X9e+ye8gbZiwD/eS2BES2US8rKIUnOep0eNb+He6iCM
7SHOOW+1cu9QI8lTMO3hkYE5UJ2w0UCRyIyiCDU5nNZGH286i7dgm1gT+DZ3OoE/qF41HOlxowIZ
U7Xxk6YotBaoPO9asQhHyzi85yIJP9Xmf605s0agmqR405xIZ0vc3Q5DFt/0BfC4/uDnFfAKWvKn
MkiifP9mwy/GUbk3Z72XJsJM7YCbE5lpbtNQzZFwbjXK4CnR9dNYSj2RLfqr2FO9B8hLhJcLZhZa
XusfEahAh8tnD53KnM2xJ4ExkDt2z9hoObdVvhodKvoxIxCkaHsrPJpkZtSMCF21QXo5GDsi5LU7
IdNXcNdK7g4sLM9mOmLCSt5NVMtYFJtM0Gy5xRqSIvFxEnrzm6B3YOjeKujBzr7nmgaLAXozKUFJ
y8kyyEJBkcNdLkaG0xukL6Hi0oN+jjcj4fajwD5KAs7DIF2lP7t0ve8Zf3jp1x9BXtQwjyCJJ2nl
gHUYGCsoK5J7hYyuSsTlq7Env6udJa+oOYvaAnhZ33ZI93DHZ7T/vc4RCP9vMcLtvR6BV79gwq9B
RmJQmSg+YSgLurku3en8oXBFpoi34CpmczxylGAqEvKCSoY5ZaO+lH2sXgphy1R3QC7iqWKcFTi2
0RiIdbArVKRztBguS4s3gdzWq8f8dQL4XKnukh8V9jcOAtRT7HkQAMf/oBS26sX6oCFsHvz4K4q+
08zBUE0i5jVZS50rt3N73JSWNRzQHfPHykFOrQuRERWogXnvz3WTvJ6haeTdMV1VBICcxSXUcPUu
dAmKf0m7fgCNnbG+dZl/Jp9+cOo8Eh9Ts3fOwnPRCVza57srrlkBtwKR0VJTO2k5N4JJkEnGoQnv
ub5jxFHqAGkmTj5eu2FeXGvbP2h1tHdyBEC+0bXx/fM/XWEYve+iUtWKpstHmCjrzw1Xus8bx7zd
6a5IWz4I93JZtdGWh3LkXP8j3hDiyDIcyrRyERuJq5TokkgNTjZxgQXPlaTI/qFSBrqJ79HaH2sc
wqnd9cvncWXVZaNJ6Lo4+z2nplz4gjHcgWS7hmSYC47a6OgTPYYAVc0Bcn+YKT/KWGPKC8lTm8A2
1Mj8iGQrUvnhCGOftsmR4Y3lgq/Z8kIkF/aiJ5dP37lhts739o301jNs99V5WxkuyCH8FxjFnevk
ZhACYC1yD0FdLRuw2WLCQ1OlIW8XxukcGjyfr8Jrej4Zm+NjPC7LQC2WLlj+Nk0D2qezfKjvOEAI
boWCJsf8r9rY2x9rb2HXx2RwmofYC0xzQkeB91fDn3p/AU47EDANKWsVDxiuKueM9p61kQr+4CTT
gKEV4Ib5Bwdb++LhVyd77W/j+3Gs3yL7o5QrsUtlKszEK+KKumWLyHBm62WJq8CDiULrj0DxQL0b
L5RPeT3gO9xDBCWiw+4bCgBcIGrHQKt2ZTDZEEhGyDrV4Bj9Npp/WFrjuhPJ4q48rN5DlsnK3eD5
dxALGcqnLypY8ODvPjD+Vm6cak8mMoMq/VaJC7gp8BZdWsOim98uCdnCPg0a4NcEHpDpTUG9Hxbf
eWIGeSQs/aALQNFxmdykHbOdT5naKG8eBJqEQk7U1Xiego74tOWS5xo9fbtJ8SPPcG4Yz5SxPryo
Szf8Ss7JDp56aTqhVr57DPvUPgl580eZUKnY3iggTlIyzPh0SlCfCUOFQ8SfVIkYhQRmWsYbUl2w
Ali3eTh7e359eiLB/xuprjvd5ObYxamZjyLx32Q+nzrm/mlBAtvAnU3B7Gnr5Euy9oPpQhAkDK/3
dG5phO+BFD3qa4Mkf49d6/ipkaxiUH/7viCNOcADiAdkDyJIVTslRDfIHQU4ZkIWm4NWaY6gktAP
JI8Q5UksqYEhs3VVl0VBZrROjfIva32bHX8s0bmZOkS3LfCn1LqtGWEHVPbDtE7Qfd7E4AR3Z9VX
o1WRREIea+P51lUSfsEK++40RXfHZ025yfYa4YauFp6H9/IvY7lMOkKa7e47JPUXmtIdL/3m5zPg
l5i9Vq83CKbig9nT+ozM+5lYc473c0r14O5wPtkLHHIOdBzzkD+g337gu5o8kEodN7woFGxfq3v7
Em5aocX84z0eXdLZBxuv/okL+1C50OzMDLnXm+R0ym//ILgdFCNgGuFWmAvgvMyZvLQxGXFVaRU4
Zh2TmONFsqzWIV+YsAhYLubR/VQM8oqO6W7iOCKGev4BJtfPKSR23ITZj9l1E8lTAHiTh8XiDM+0
zczr57pn09KKiFe/lWEewCL3XWwYHmE6dm0Baosp9dY3mVMXo4GZZxnHa2x3gFIsnEQqLrPSIosX
nJmsZXon1douSGf05j5AT9ZPPXmXejN/ev2eg4FB2mK4UQY43vJiiIAwLNcSIf8WDKtRyjT8FwkV
qTLXy/Qsw0/DQR3A71SEzDasBdyo7+BHdA20lYqncskaGeSKpfJgPyDZyUBNXJ57YS21+Vqli55k
lgDbLO2nFaCzupqkfEE4DM+86N7fsI3le8yxUowuBoWp9867e4eMeprmZvcY42CXB3tQqbfkA9ok
B+d98jGX042YWAcYiaTaT2eiZYnje/VbXmiwABKTElahh31fqW2dcQ9JE28k561t2jetmMNbdobf
VBmfNhnyUaStE6OCQBW1wJYQHtlSm8KPgZvZi0muuzSIi324oZ4p02+KDwJmO4BEpqGgWKijMFt5
l8SdK+b7+jud49VTQoz36QjMjrV4NyiEtMiouHiZQjdHU2Bhak1vUETRB5ERNhWJnRXcJy89lwOc
AihdCdAer/CrkAfWgPnDf8KKhd5MqTM3rFDgrS98euJBAgN14lTaCEw1oKkq+JoiECRW5sVQkjQC
kAQHuqEuSzovhuioG+d000ZuOwIP6rM2EUGpEXv/MTJQM7HK7yuT3GWg/SZZmq8qwt2K7VrhzXPq
dElNCN8yrWNy04xRgpM3pCOBMRBdf0+dnlEMEDIjpYdnF+tLgiEZ8RNRrVwFCuS9YxFbd71fIkg4
6OR5C9f1jXzkNZicRCF/p6NUd0e0oLQbEZzSUKAP7yAJKQNsYhsJuCiwyWWXsRrHchIik/8hioGl
4zysvvoE3jng9iwe3zlMNQc8VT3JkKw8l2D2lTwnOjO3CKHKr0tthEMb5FgKoQnfCEdt+dFTOdIY
dcyyWFzTxGjL3zNtvArWSmUCUB49seVmNwU68ygR2XwiVNKBJyl2EViP40je+OwA8PZ+Ux1/gm32
sl9wiEODJxuj+8PuvPRM3mC0DTJKYu4/7dtsCYtGQO4pYjbl2pb2I2WPSpeYKhrAFVWoSUqlsbWN
Xa8iSlF/l1+P2rU6NorIKpyc2s9F6j/TjThP8O0OjG2jo7OlYmgFv3O2S0KIMRDVm+m8UMNA9OO+
XG65l8c0SYRpECR02Xlh0PDkzjexLoYC9RI9SQ0HN0qYhIt3r2rF/TSwXzLGL4bAsj11CdsM7RWI
Oo+1Q6WoiPusA/otrD9FjLomg98hJ4CpelWbtWUl+finHvMSpUntB6UvLC/fJokfbOQshVV5Pepy
LFDdh46xI89ssSeGzQhC8MLnpR01JPltIqTqcyzXllXgRafOOVo+WLJz677jFpDgxJKtjdO7VWhX
lYaloVUsqwDW13JFpX3bEfexQZW6AbrA9lIjpmRU+vl+9IeVvjioWmjSEkYJbRR/KYOprEFmeZDd
j+uVTpdkFD6Fv8Y9T2elLtTt3A7IX52yxpuUkeeT/FGL8l0DTqMpZn3lhKu38U8JloyDs3DMi6nb
5NaDNZNd8JiUbFkc+QAW3Cv7zkgEBOLQME7dGnzrVVhidvUVwH+i8p/5EjbMPt2v0TMF3F1z7Ahx
adByAcHFmMh6MdolFgJEX4dfx7yhar4Ge6Vh+t0MgzM7Z6IG4bJrmSTgRrnmsLy3n0ZtVaPO2C5G
Ff7P9GPZQpeP9u+cPAXWAzJAzqGb6dK5hreqncStgx/gSUL+/ygxquVTp9AkkuPssWuc5T01nSil
6yn89PFjd2NUgmfJjTTjislpA2zR5WzG3c06dZ0GbPGHc6YPUMHc/Opy8UJqXufH6PZ9dHxggLkT
OulDhElM+BLd+AP/t8d+56vNZTd+v6EBovp1nvu7dNsk4gd8DFHZhFSHa5o9yAdCTUP20Gsg1jR4
Bi+3m/krV9EOWK5/6KB9pxyM81A4va57mSLHxHe4XiF8wXuIXTmMT6YTHqtP4hmnMXS6C7mgy30P
u8wNglJZh/8CQkzqmY/hOilyWDZsN7PhAYdto/G0Jo2SoNLhA5q35k9WSVZRpyphsfpOzTRm1s5I
rh3yGRTAIgSOffIgzTFkZl+8MsG23cKKjj9s08DWL3T8uDNvQhZuv8VA0HtmYD66dVYOkMEzW8JC
qHKG4IyzsHkz2KT58lSKAxm/7Uhb+ZCfggaxh+DjeFlPs1RX2puLN3t4eoGXuu9t96m6pynnPuRt
ZtgS5e2OSW3Agh40DOtigvts9q0dp3G7e6GSNyPZ3gxsPQlep1CpRKtu9UWVPiRJDNSh5s6zAAc2
qihs5sk7xpNFvw4vHufVi/xQ1eSlxUMiB+Rpc+b2xv2zSa2h0Gsx14tFNFIbxpHIqDbl+SrP9UEd
hxQ8MW/wMCyGeRP74Y+3LcpFqDiNdVjf9JqhLuWe5iSwTuKaeQQ3oJBnijLPkwXJLrMyYT9EOxTP
PuHD1U++oa8spniEHuXqarFWWAnfqbCc569KzhJQROk9AEsssS6bqgdo5Jqp2XP/JBn22LX7QR2G
WBXUDvYODjSS9mOQ6k/ERVcw+E4MOKpYfcIwHhtHJNmtCArZlLK84BlqREaDRdN+0NEANoVN/en/
JDYfPQ17knoUbMVeHwGEj8EZ/6QxvL0/pNVjNR6lvlR5/Tz6bonxlWEXBsQtSt5c2pRRqPprr+gC
3MSigftNHyS9F6wfNb2wVyleLH9vSEIje25/uNO0/F7QYAGqjkPgZ9/+QSz0aYBsYc945TQqGpIc
4+VdW/JXrcJbKB6mklxZcdithsqPHDwIXnu1UItCOyeifmQeRyUNu0dXD55NBEwOsIRFpOmRwP9S
lbBmr+CcHdzYJ7UvNxJNcQ1g4WproeJu2KVJw0wsGaHLKCKqlVpyLCkIgXodQkHaQHBKaWJ2npbN
c+gZ73TKFT0PfhWsFqwixqnMdNNpH8oC7m6qjNi3zlIlAEdfolQrUJPF55LjuD7Ln1/lLfVd4H75
+sD3ASYpkUXxfvBlCZeBGLbWPh/Cupo0qmLKctZ1j8BocrsfBsL5GeEdmb3cy3bNhqx/J0/Xqi9z
oL35NoQsJ+s4gVkvg6b04XSCQ1T6aV0IcHO+9or1c1kCnnxqZFW3MavHW4D5EXuGNCesqLY4PQqI
CAxX221wzHB4Tmqr/LQNTQOSryCUCMvlkXwqzzb8A7qGVp+Jl3vCRAUl8mil1THJN17GtCd2Z/52
krAFTyI+f7B7Nnyd7ooLwpwcozVkHZ9/AJBG2iHX5VoQ1xWDomcWC+71alUZjHk3TAiEfEPgCBOW
09XjpECd0VTicHAu45H/8qrIQmDDEek5KdWoyuXwVCy2VPmRJyJ/XDdguTQK/UPjet/1WgrOn+Gw
KiYjQBwRqLRzyrxirLIRWa4Kf6uyrCB2LQy+br70uowgChQbzFL5pGOgV1zJk9uWrXD09Dki1KAx
kApEvvmqdn5p6NUc5sWeyNpU7hemcgmdfcxokZP06FYSph/kR+gSWSAW3eNl4dvgj2QbVIMSGlig
zxTgkSV1cxfEMvqhWPK7RRy7xctArUUaSJfy5Vo1dLJ6oCEe8Au7FYAT9Xbo0JFy9iYHdbOIElb0
PDKDJaC6p4x5kMqyTPMk5ltVNEekhmX3Cx2F2oK4JcFI5YFtpd34GCnKoWZR4buzjnRgbug0K3b1
VmLTCHraUhwtS+/M8z0gMaugok5gh5EVmYVjQjURyA8r4XDELDM7IMBe+5lvs06vNnqgy0vRK9hp
WNPJv+C2ULNJXFFFh3UfKmWfxu3qtHKPglrs+JuSZulx5drPFzVaoaqRrsz4QMGjv3vyOqLzHxWJ
YkNlVZv7L+34RVk7WytqBBZRWtzMEco8LVKU1w3S3BiojChZdZZS+Oupn58V/BEVHXda34B2L3J8
muhLyK6m+KoAftQshJP95XoXTnBvD2k+e3ob0WbGV7vpHLX6/pjKPDoLz3oCVwIkG4neJlVtHJxl
ViWPnbN3MH7qDW8WnlVISea5mLYHv23K2mlZZcUq/FNNSmy03U87G+9neWgmPhO01Di4zIlqjNSE
45yRByowWWezQCpL126XhVdaue0DLgl5UhvjLsShqbvb9RxMrY0RrW5+Bv+IWU2As4UhNi5MQVrX
IjR9CPZ04j8xB64lKiiwgkEwRQzzjT5QqKXKchur2bMa+WQClUkPkQqCXF5LTS2m5v5CqPw2EHpZ
TMpH855k4/veC86xvi9Fl+LCx0LZmqQKFUoBggzE4lll5Wkx8lqZrlEiNbkUFSbdb9j4j0tNRdlV
ty4iuawMt/lvEUCn7oyvkJMvV749SE0zkr5mGA+ArDQp4EDtCKcAwkWF4F/1x87c8cCrNI3MViYl
G0gPaQQQkJsOx7npLrJhLs5P41EMJb/84rvTye1pi+gGud8+3/Eiv2BMYTAdeF3ASudQCc5jztV/
4AjEzitzzI5ggutrrar3FeHgTpJyNczG73ZqJcHZHLa0goCpKzaFQ7WzKLgYa5a7RPrgKe4yZS33
uawEOo4zK4gqJaJfxb3CuEmx/eIbdd3onJJXyuwIx5PJeNx5ftVEt5Bf2SqNCae1VkO/JmyX7svZ
PzfXpVmqEtipAJk9GQRHgEDCNNy50NLdSRXUujZDaTvO4gnGPtoWR41YnzEx9ERrG4E5jtauEPSZ
IESihgDZI3+qK3Fqe9StO0YG6J+3HkVUotVn2+CSA1GzJTmDBFAsyewSVEde1fKc9dhhGUrVEqul
Qq16LrfnyGklS5zE5AtRYq49qZzH9evh4P9TEYjPlSuk73ezYkZb8PQx/mZbDANYsVHKeaXz+aYn
7NaWD6gTM5lcksDebIeLtmYPfchiYqYcMr6n6e7icCikRtXY7BxO/WKyzdo89+W0BcoDZ0JnogmN
sRpJ3raC/HchpiT+/tyxmm6MDuTljki0vqQrfta/OsW72FhBsQvaZFdlFzB03RX8od1N5k5wnMUq
2aEE27UXLIKtRodQ6a6sjUN9UY2lUyAJtp0PBEc7k0arYok6F2pcZClmoH7OzU+UmJ9OeMf6j6aV
42vHZn3BLsdSSWNzYQgWY9rf6I4o3BOFEW6ZQdZjCe0XJ+BXLO4Uxp3+FFqMgFrOA2DX0jNhFgEC
FhxeIy+cGS0x9wIOATinI//TbJ2R6eNHCKDa+I5nTycN4pFRMZHaJxmlkU8ePYq53Y2R2+wcpeHT
Lc0AB1WAMmCXPu/Ep4hinsT6ABxcrKb0eUQQ3vncMX2tpv0jGzrDCsJWwBWWTptTA6WxT9CAxoTj
EB/PmJG9qc4UppsOEvuZGbqUKarHfjtiqV6Bd0KTyXJ1GrX0em5VdZKRTGPQoC89JisuE4q4//xr
Gdl9nBEUjlwjHFRQtfyDXZXZ5tkCPoN94dZ5Ghi7royNPga7FAEMJVGUcEZuVbnqa9xlS7AYn8/v
rr5wK4h68reUf0dFjJzkYSrw0v7o+NKXhjl4onHzFo4t71hxa0wWmPOhU00jssOFR5s95aO+NOQU
zEYiqPmBcS+FcmZutyeBkZGm86XqzwaalpO0oLn7rf0LH8/E3wJZIa9f3aLRJ4Yvk2V2xSwnaX/H
3Adf9z8WArVAnVNdaNcmv21jvtXjLEcEhOb42BnXI1DyZeLfbRpw0UVV2zZoE9kf1t+6t/rAGnv2
wevdLQOcNKnrT/lhQdUr5bg0j6DnUsFlHst7aMnEjDdKzKvOo/pt+FPcs6sEJQZ5lGS4Qgbz4B8I
abbjDFD1w/5mCf3K9mFsQeGKh3Edo6DUl2UQrF3FRQNi4F6xNfkFSRez3xvX2d8c65t3JL+uq14p
LNR4/SF8INkCvSU1ZwXJeFfjZY50V68CO9Ks6h3I81yX5nlGFPt+tqCZxp+oFcg46w7p+CkL71u2
ldxl040hAOiXWuopGFZJ8RpFfSMxiWTNOi6k+dlpgOUebmcaB5ng5ksPbtmB4ibCJXjOLuwisHCl
LvERyVHeTAs5G5dqPmoa1dKTSVJsOtVmX2Hl6aubLenhCbTI7zQ0dhKkrIRlmFPmGMJ5EZ9lJCx/
CqWUiVMwx/fSgzyzxAyB4LGrA0PpZVhjPjpTuHMvWQt5VUvZSiiYryQs/cs5OicQ3QWvCQtm2cXd
o7d/rGHh8+zpH5gFjnqeftvDXD7zVoPLJxEuop3Jhjz7Z0HfqGhmAyHcjViWpOzoihc2KCT3WgQE
MNSUbWqd/1YXGz2QhRlsQqRAoqeR25Yu5VVf61o8UlLnpDEJpnKRzQHOPmatDWkc9lIpS4I3KJCq
sgaSgoAWvOeHdR025BWj9Hs7n7qDhqiivaiObZSiCYaCWVWx9QNd6YBnNctxsPTceBOdDUkevuPc
fDNRLPMUk+JI06nB3WTdMnzfajhYcAygVBruK32qCJSj194R/XaxJ6FMQeKs7ZJdJxvuaFbHhzI6
XMhBVm07nQ6v8/2IhPMNUOnS7BLSrgfJDcvref1vpNh8Km1d3z47Ic9pFnhidfCl3D4qIbEq/JjS
w52MdbWTQn7zOwCMxpZyQ74V06h5BVi7g5p9UWl5m2l7RoMGfqjznRGst2l9psp86ldbl+pQlKFZ
5i4ZG4/Yee5Skxmm7GZx5XsMpio5hGLE48e/5htTskHviLZe6kaWOHISOET/nYFFozLT/Cyl8RU4
gaVnn8s8hynRJcAMcEkfoJu1daoFMzR49K1LyTDH2nK1VkAhmeQR35odq9ngS8a5zdf7RNBSs2jj
AIvHItpWV1FSQbrUuyv0yLqZnybsVN3BkQc5BkbVZuN7/LbyKQudE5W8bXsOHow7EeS/dElPA9Si
wFfA19hNzl5fkeKo5emPqKjzCOA4oz4NqbNjp1682XYrJZ8WogfqSbjk5CdDbwGBpF5b+iBr62EC
Os5EVieQkRUlQQPnP703yEwSdYziNX7MBjEboatF2tnI0Mca9ygxxxd4k59fPtzmDxnE3sHs6H+Z
1TnvRa+SmTQVe70WJG7PMLNidsR8VWR9CfYl1OC/I2aj25hm+awW3Qki95R90iCKZHJXD95JEP0t
s6enuYItQUCMFI+z66kGSvcx9BD1BR9fO4tBtYDudyYhMqHbxvNtBPip++WEglwiw0RMdbig8frG
0WciTi5u+n6LEN919bGDLTBOUDil8jEiJ3zuO0yT5QHyjcaZRCKut6DOg0idcvBy5XMfbIhNIaq/
B77HCvxV99bqIwS6oxv7f6UAk4AZWP+ijIL3qkEdLTz5FYPCC2joGG0djqkjjjORXDdZvkV62YAF
5TQwM3GoIMs/bK3G9zlGa4jO3AGslozJJsYknngtDIiKDMnSoQz8xbZsC63CErvVf+SuFE/uKPL9
p9dhtRemK2H+Pt1ZxbEoGoUvJW91MINCFWDqemE/vNb1eyFZaGl8H27XrbQ+bK6JFat2iVxxFQ4V
OCkMezOx/1FQtQeOPWzivIO2qi/LKGVrmdDeGbjN9Ww1kmMzi/cMOUWSxGTk1ZgziLi8Idmano0F
D9V6S31G4oZVfbFtfeQUaNn1aKhODm8m9c5/sBPzssSTreMJqTXvqC3E/jXaHljLRfrwhtMti/kN
KxLbCndZX6ss8eMw+a/uHY9xzAhikhUQ+0gkOYZWzsARHbZsci11j5EA0+QscB+Gu+pjCO1VG4ds
chLIR9rII4/tX6pMXkbRtM+Ii5tJnMSLCZmA8EhbtHzeHZRl776i/x1bvQ991ezDeeqqVqtQPTT9
TgyS3nWcOl9fOUItNf9uftAZ2djCLqprDv1hadSJWq+Evy+ScRrs9yGrHOPld7BWaleq88EjchrQ
s0KwO7ZOfBzLfd/Q+Vf65a97+nK/xZDqtRuhg8/3pFPEycxIOCpmBlAFjFi80oUGuwh7kbgESaA1
EX+8rujWM3PniSv9540e8xftKC8ze6XIFbxYFDgWuxDVrvJQrCWr1xT+B37/P4MQcSIBA58aeVDt
Gkfcb/JxTFW3hA7tNWtgfggN0j2Jw0f+hndpwq+ZSczowrYgFbQ/NaHTcxW3eY6mUgljy9HXbfxQ
DwqEHtRYfGnCnjDFoFpvX7BOirnu0NdpyNNhKK1mzVi+/t7zWCwMd1NTA8WJgIJzXJcjSe/b3bP2
GIvD6iYAwTgac8vSLP86uOUk+cdzju6cQiBK3N1c9T+uXhifYo+hGaAkyT2CzyN7bUmUIa0qU872
0DVRnqgmpVo+BF6lb7LWWNmFOV5sVqRHbb/zgDXliocWNThnW86Q0u6VBh3o2tTGkbgy+peZoSDA
QsS91p9nac0QBiyd62VPJ7e8IUA1fUllpIE8TvHr/NaWRTGWnk048neAppQ/rJWflcdgVA8KVg0A
tMIN3cv/GKP5yh50jikUfM8EJRttGezP3P51wnSxXnZHkb5D1NTtQQYJyjAZRFPc9b6zCdT/vSCN
VrIf1t8/LSGRGoVGcYAgpBEzgezWwXpMr/jQvoP5EqlXQl7jlSpIOac3HG9kyitv0Vbp9QyaaE7l
BG1SLowGaq8QzUveYeMmvnnYQRtNLPBH9bUFm5VGdye8I85cJN52FL61m34mCuEToSRjUapN6BTJ
fZ5Cim4WSEA2kSMXk8tpE3xHbvCf1HcK711h4itAEUwJ42z2YCA5DcVs+MOC3agbC5PRISnbL+k9
9+kAVC0RYaBaBqs0ZSKE1CJ8dyaFGnPEcbATktGqU/PlXTFj2oaZQrXC/1XFP77vc/V9I2kpSZbH
BUaFFroOTRxXGeHB6kYipMZpvTjlVJQsHU3iHsjn9y0mCtjmUpyxamkz/8eDDEmDFq0Cd0y3vaa+
O93EXx7aFML346uoOP6PT6n3QXk713oPQgkY3uu3NU7Pa72ncPCSGD13UTevbDB4XvwjVHt9UAyI
xgGB3M3NzkE2WGTFghQW9431tYjcZELAybqmA5277SjmsqKVt6++kt9n5uzbXmgS+ps1668CDFmG
GXdaWFnW30j2pjJjkFrhbPi71xe/+kSrVXFpe+xEALFWvyRBUnEMIklTXN9IqQ7KzjbRHMTnZH9m
M/Ove0L1kizwRibcum+xtbRbGYHlJetCGriL1GIDqCr/XU6GGpRlzZALpqdzISkj95eQM2Ct0ljA
FBgXt8BqSBUf6QDCQwpM/FR8tZ4/GwWCQ8LXPDuiKGi+durUqRp/7DeM4F9D4QMS9GoimRj6SM9A
jQ7laUtiS/b8HNn/0F02MX2ib8sYLftxOzVpmlv9/BKRuxdyYKPnvNu/x1c6wC+zUJmRcq/kxi2e
PW/oE5vXrJX0BmcjBtnkGobSLQ9DN7ioU2HNaj4Cb2Qk0/PIdZo++skROEjojmL1Awzb9WxSH9BR
bBmsHNQh+YiryFtbanBhn9r0Fq9JfDbsD+mYfZb008VrnnpdoiG/ITpfDe2lD1Z7JK/WV3ahwD3y
hh93ZH2vqRJKnXM/ZZEN/BqJjRfO/ppenpyeMml9Z3MXETW689FAYGO5BwH4GAljjF0G62TM5fC0
253ItHNxvzGoj31F7ix71pcGrFHvmPvaPhZzAV6rktrd17ZgWMS357p3nU6wtYlAj7wb3h8xufDV
JktqiUWM8bsv5wciYh3RZjqXBgfWyWQfbwkCg5+RTMBs95EOTvCMVGyHiTh4QhM8JD7U2TRTcFqB
NZN+M+ekk6CuCPoWzwyCunv8BeXpW9cdUkWvJ6srG8Qgiw9fRV7m712H4uAy8owz9+LhJ5Kz5TCs
5+xm7X0byXx5r6W09mqhnHyRNMEDuzY52nBXga77oRy1XUAALYt+5GZR25A7YHhXtqrWu+Uvddva
PKwcekTuAfqK4fVatXEQrjTD3NVimK4lu/TsW+QhDIzYYmLY3e+TSbsTtjujAq+BNoizv+Uc5JdT
aIAGv0XQ1oqjPzALEtskIVlD4gmi2LiEfbAZ26wRx6oDj76z0wzGnDXFj8kWjgaS8bbFcCwbd4RB
7C2jCFBW8am1CIzj/yeJFa51HxUD/3HSLmEissLtVwpssETKLxKCPl1OOaGGWqN5If5Gq+A1LikY
zkezrWPfTugfwQfEhF79JSSefoL3N0dx7rZYuzDhjHYoEUaHMEkSYYNqpBH+DSlkSDunr7v+YefH
UBGoGe0ocMv/UzUu70QvSe3V01kMSFwfEBf48fjq9dqI1rFo8O2tt9f1WRrf0uu2lvEv2imOlbHp
ujHQ1U6wTeSFQcWrojgRKgoURS/mPnDBoDXxamoFZRtfiDZ28p1WGDTIkgNydLJVk9T1fwbCtwL+
u26RdBnzy3QwgEYiDRx2hnf5YG+kRIeVcpbH2GI0fy4FzPLlQBTuN4vIs7xecnlwhkpHCAhZOyfx
TTGnpXCscs+n9dpwWT0Xu8O27Q9OFEmjQWXJmPZa2mwYNfAtuorT043spMrJjUqoFJTO/ARyFcCj
eqgq8tG2k7BdL/tH2MzT2bYVnIie+EIZwbs9K6eAFXYlLlpyIKRfBu/X4DLlolKaB/jnkQmWoV5A
XxbyYKI40yQhKtbwvT3W7bvKlzAAFZH6BgAHpdL3xtmkibi6Owv/k/b3gVVUubNldIJu+fTJ9mXC
JeYky/H2vom14JSG+eiMwbk5oMXU4ZnIjRV6Ws799X7W6oWz0HcmdsvrUZrW6D/RmDHb6npgfET4
tE4UsNvYCZSEGkVhQ5xDw2WsOFqpmElbGxMddRYR/orE1JHZv6JvBvS09Yy3t88aFxIL16zHMIOh
oKua7KnFJy35j88xDmhY1cwq9n/Bt9tQMkYcf3dH/25viKZnD59k860X77UQxX53UET/q8ZFVUCE
yrpW2bwLvlsNax7WxVO7HjEzj4lTATy0Vrdczx7FFLdq+1mPeGk83tphSSljFBMrYVOQy7KIYtjz
N+zsSfFXqrx7qeCYDeruLtGJCj7IinP6Ns9DMYNyDAJyF1ADb0xlXTSRis58i6ZzK7uzBobNFuau
xkx4/LRwsX6qVHKKmiElTQfvK1Z7fKQXqU5G31z0sZMivq1HlZP2SON4CN93nBP7VoiVAL7WhP2q
fD4ZpYQOGGu1IWCBgmocQDmSM4vnVWJ4qo6FyzLDOIFmje5wylJxdV5CkMpbbBfIDYWjCfeWCnMG
4PJy9R1mHaTdAkLXzMw6VehpF52mBXtwb/YoBBIz09TerYg2ebUZ8tVN8Bpjhg30Bbp+JPgYzOGt
mF4vb0oMclJKWPCvNOGpFRGHmCIubyN3v5aDwoo8q4+PtspQmpx+OEIuOhFWqkp8VZNPJ2N96CZd
gBDy42dF9QAz5DUmr+9VLiI26E4vPCRUViAMpeWq0lM4LmuSFNf6GuL+ZJG9G7W2KAOSe7h12y2J
0nXeo7X0yrWb0agGGvbrOteE0r9p5zlmyW5uyWoY1+qGvtynOTOmxfZPLMSl7peJWhUQ45yGIWB+
gWpaVB8sym08BOl4Oq3LjKKAawLMrsjr38O+0661k744uHiYX/pqMWhUtpsQwyjYqPKJOfO36wbp
llqmvre2QIKvxQEuMswTev4oGdg2GvEgI+atSRBXdeGzBnOP27HiwyvX43+lQKnyMrqZECq21Sdt
nI20VdRIeJOIwe4xtvQPZE9rwQFG2FqTMxcL+e5fhg3c+w7NdQHyFfUdb7yPSeagn9UwthHhQBsC
XwsEwmHr8gqrbE1MhwFoeDuRl5ACmK0tjMFAm2ZfKqbt0O4k5EkzXVraSBkLq4L4wi8xmC++LTKO
0be1UMu06+7Nt5iAZMTo1JiLRwLnovvQ6rm3x4FE07UvcaunTnfSDCp1Ue7MlqZ1E037RVUyry8i
Nb8FZt+LVXhTIPhg94eRYXl204IyCHk8aXcMPIZi30Auj2gh6kccPSfm/tdp7JBqnmeqIAxm2pys
9ZFRc3Z2UiGiAAnMDmv+CY2qPeawywjiIvSUHKrv4Kc8aeS59h3EHrGsa4WyCNZThLSU6+gBmalU
TvEoq/CAy/vk4vHlmUd//HjMwOghEniT1uA3OWTZS+WX+o6nVJ5opzlACdX/eDJcEQDpL5PAteLn
cYGEMVMbkpc8ycxEuU1//8ZUh4aLm8ZnM9x008AaPL7pHP13PL1em4OwIGJa21jO6ju8cI6L/7mB
ctmyDfFCl8ggcgZ7bqG34+oF8C5DOfhwVZvkOagkL7SVyDxz7+buLrsTCgtnjxaeu6V+3u/UlLPP
pG9VrcNOyvFSSNOJZMHrtVNtpu3p0Pm07k9gqalI0hdkAYdLvX9rquh17Eck1ria3IyyPMjiZjrQ
bjpTT44MMUbEAJiRoMRh0VObVJt4o9Ej9OtABVfY74uFmL8mCd5Joe+0k3mo/lRzMb3JpckKB1ha
hl+SrP4x61yLc9wk9Oc96PTuk0ZgmYljdi+aYIpY6BFuTJYS1FtbuI6tzW18XG6VdRh34+1PwlTN
qVmRdUfbmv2ClU4MH2sq0P5nvwb0bnCG5BHk3yFPVZUHdnhbjyr2DmqDZuV6qd2V64qd0nzvVYZi
zYseTQLxz0Kn/7rK+FfI4aoDyXrr6MWnBsULcaEKkitXPDkVQa6NgYtKt9n4k1ikWGwoqkeqdKtE
MSEdSOVlgekx0X7globIdhlIBj4uvxL8sbVtGpgRsakjI/TOal2t5IoLJ5wNb4Q1zOHbS8oynQom
zC2gMwwAXrH+gCwroa+5QcaMSdA0aCtxGDmA9boeGcUmnctKyKn4lk5kYxGZCA5jp3K8mj8oKtc6
37B0Y1+B1knbBzwkfkZd78nMXZj5frSWg206lBg9mEPuMTVybhL1NFDrF+sPOCjQHi0oXbKJYee4
IQSVau22ampPYxlWe4mxJoHGRrCsDEviAfVHhdxXdzyGvwfINxTGFiiNlsKVVJg77tqFSLSfJNEO
FMQyjWuxLLk0QfyqzI9fRqt+HWaVNIAwZthF49Y4zrVW7qldkKAb020HCfR4WSbu5IUaZhJ9N5PV
+ZXDtxknjLJcGFxk+bCr3n2hGdKCfqIl2Voquz4ijCMYIdGDTYKAYxa3W6vChtPJ1yixozIfcEzL
8XHwvkw43+7NLTGjVQoeyTUoFHsQwh1in5MkNmOqLCCtrz9qEhn4zhKkY+FHuByaitV54lWWGZJm
0QXzp420bNrOMRkrGpqjGNfGC3NgwLL8ZwSekm9QLvuBfAm9GTnh0wlvv3sTu9bLe6tSpnvmwred
VD7qtCrcmg04hfQjDWEbKrCr/0w//QThrp7/4o1qgmxeh5H250j4VHkYUaPVgFlZqkbWWsjbvlD1
eC/oHnGGhDB4ramVy1QEYlz3NB1KGtkMWX/mcrtfZbppC+9nwEQzScSLieTgaYRAQ2nZrtOFt46Q
9pOOwnA/Bs3ONOFUrAlKtql6vNtDmwXWah5diaknU3hZNly1HkGpVdI/NbiA4CxhTMs0PngrzKpW
ZKfZlEnR+d4x4hbz4lA990nzOSN97TOsYFTDGIJKWTU87un8VQEuTpOO9xkOJGNs15ZCnc0aFUc8
ZWY6mPgs4XP+kT3oqPvORjjjvyhbxR3FGpy85CrW06eYDywLbJhOW1NDVxRIYtrYJRENReBxpSp1
HiAOt9lAEKBffnM6ew8iQtpwksjDRXAs+pgtIsXyJugzntpgxUo4xXNixScwiwWPIjhdlsZXpUse
eRpRiUy9Zy3oGT8lSaImcMXhW0epd6mYnLlLJiPaxMKeCg2mxxSe+ErEEJbyn/ySQ3dortWJOzWd
xW4a2xX/AA4K1ecNkZVVdKThYEB8wTGxiX1bzghsvND+Oat5SewLJ6heFouq9MRm86iCTUDUHcwt
mmS0p3tq4m94JmdxG2P2fxmJ42WTHlcLGd8So49ePYpqfP+lpB1+A2Wg/1junW+VZr+knrBfkxxq
U9NNSdE0puaXws9mC4K0RjR+YniEIjyLO5V2SVst7zHtwjBfmbwK8DUJe16ywxYMqQH+npklIfuJ
oykxvFMYTFtuvSRt2jV/akoeOlw+i5U0qytmdI/M8r5ED6V/TYLmb67tbPrMGzx2yLbzLo0bmnMB
VJVs/XvGWzMt+wHoi/3SoKFz50/+Nt/ISYMAR9R7qAotzPzBFgKcGmn3rhKyxGVhwZeY9AWMuhSw
yF23UDC8MU1CfqiPkF1eMjl6sCzXHU2vkH2ZC4iEPY4LoLgG5IDfQz63bLrJY+/stdcsItMk2f6Q
1jEJJ1vDCOGc7U2CWCnuylcwGu4JKg1676/30iXPvPC30CR70irXGvLsZek48SbeBO3TdKqOXB7O
KTiM2sM6SlKA9Y5iM/NcWGhkHPUCLhxPe+er1lW3GXQe8MakV0X5TYvijaSja6mTaOLpVw+mgyS5
fn59xlFm88Sb0QSAiqb8++xnCRWwlwBPAba7tALDrptTs8S4hyX00FwuiBvSD7NaLMuWL7ZvD8t3
JUrEUloMXSc0HJNrCBT4KbJ58ci0FbEcr/1LjM43WbPaHNKV6JAnR5RS5lbYjnOzdV66fUbQ37V8
IWV5T6wcWDTU2oP8LcaKLXw3i9JzFB1e4Phsq19xby5zy20PHW5x3c2jyV+35vys27qCzmKwsWA4
1JiO+6U8IGEQIXv8j+uO3MB8xe5JF+W81sCdcSEJigqhK/h6sJGy+NZ4jv+3IWmdkuZbUQtd0pLM
8EywZCWkQXDCBwToRXNP6kmF2fB9SVGRduBmfV6PQE0hjAoDqOKXa+5/mB0HQuRysult3pkqQ77x
T27h0s1d9cM1ssqLLDYK7tg3XM107d4KQOWsJN2P5rfSe88UdMHeZByw/aT++BQC7s0EUjdfu8MR
Ww6KAYKGlW6dI/szzLjbrEt6pCHjBmtiSt8nkIrFDTGAriDCGvPIAhzeBKJZwrPzmJ6vi6i925/Z
MZ7TBfAfgpk/CDj3Q3xr4ZAvOf2wHbwYz13pRYH/M28NDxQGoYMHJQerX6icZ5etbxEKMN3hKPGc
5FdOJlhVsFJ8YIlblKSZwTWiH/T5sU8nzN8uZcGEw+KEiHb1Gv7CdUw2Gi/Ly4C8ny3PtGGpQqDk
bvrVYAg6w7fgmj7XmSriQbipC77cSJJXo5b/TaNE6OymkppRqbc0JCJ33WwlRm8qqWwoz4dm+Hwk
r0AmQn443JINIYcnDpZSXpug2M6f0N2jB8GbtUQjNgOWAXtEjhwJyPrE3DraT6wY0IF53wTezUgA
nxSRsn5gUaYKYyVVi5SM2U/cUv237382QvUVA+RQPe1Uy32FHcNa0F6najpHon6UOaWr18JLWlF0
UplGylPNGAdrMOgeG/hKdGQDyGU2GM6J6rnBcgfze7eo68tUdmkaYQxERBZ3f51qS4IPF0l48Gig
v+1hbZgiLxr0LII7yzfYDSZ6M9UvhuFI0PsZLU2buEz58P5fz0pRQOl62rRIxFYTY+4nccB1tqte
/txrQL6UY9lOxkB5En+LgKc+9eENMgwy4kmSI7bSc2RrE8FfWYyE8UdU/XhNvI5S8leWGSaqSdCO
g9uIYuwUFWyKL9wizebZFKmlXoqsqumdOska564k3ia+NGQyYps8TE4okPpQreGpe6F6OTxM+FYj
Ka25szg2hJd+TxLVSMaNmw2x/e7z0sw7FAWhHlT0w5QxjMfM8jCdwNUR3XRNQ/fU8k8V+Gp43Oom
pqECR7kvVVK4eTUXhNtedxLL3QJNufohmqdsM+pdIUOju6lpNzDc6Kc/xn52HTjijN2C8t4cEvop
xhTfCfntii+/Ld8NsAiZrOHv3LzK9JiFW0za4+2SD9FL+9+Dea//0LW8F4Nnmc4YwPJcghqed47H
XqiK+ayTEyxihYZpHWnUwXSUbeK+vT61nrhVKAhm/5vJxC9Sg7TuDqpph9bFFSaHG9EgNaw1G8pi
C4YYfgVCIWgNwvoxmwakdN4n7NiCQ3vdfVw70fWX33yMONFwLzPUdHiUPeEAA+qPTooNEVKa76vS
jC2qd03bcUNixX8ADUfyVNf1E8FaEZhz6rpBCGhayVCiDCireTIPPOKCrKt8EODMEHE96OmroIbI
CmxV0J5u2ySiA6efed3K7wb7uJCgewqx7ZdlXfNHg51hg3jzxFTQeeUw5AWo88ccVtvovzn8Cjpb
8FAWDFYprEcAhxa3jrn8kyoqv9lShuEXMVhH1o5T2HHkbHOoaVgGXSHK4vrGLWP6WIz0pGGPfAof
eQuJ0q1dvMU1sQrlA3po3NTGO0cAnRTeEmu6iGS2yfZRLLZ3VXqMNrjJa6vA9la8N3Jw9S/pUBrt
OoID1p7WF1FMdphjHxq9c6C0XO+rDZ8cVRiihFnBhi4viFGqpwV4qDomh2qiI9LNIJ0bfszYvDHf
//PiEZuEeRigNcz54K9oOvizKBe3WJqiwGLYzkOElU3A7pyvO4PKnZzyiYs1D8I6fo7wnyls+yLi
MZ3i71L7yTXXH2W2tvEKq7MHyxPHSoakraVVX7nBRLENjXIDuk9fNu1uoNEGMlNlW1doHqX+m8Qa
KOuvyU5qvpXhie9aitCC/zuD6FW30jP8lajE61fWehKrndBdKuKTeaYGDQCtWSzPcyRCbHHTZxS1
7FmQRxVvOzFTRPlrtamzvsZEHHZB5frtBwcf8AezkMfUNesINaun7JYg9Z683R+FATpVELJmSu9s
ICjVAhitXYwiyQ92zOhvY+TBLJS9oBfTtzmY+Nu1pn+O5DCLL/hQDwHaUft1DAsgRd8UwG5N8yxl
NWak4B0hBZ4djg58hJqxIwNRkub2IMfzBx/nJMpo4qoZd3+WQueRry+gUYglv016OAX4aQzI2dqZ
Am30j6dvF6QJznMXlHrKTj+bG3QEb/k0Mdwdue7IavaUmkYU5ttp8MXWqLYmO2KZQTEX0eUPW0cA
frzpZg2yPOBFhTOWXGHusgkwG+iXn643ylJ0K+ioiUExhukxrNaxyH5qs2cJgO7V7b5u6ITy3CII
ExK8eecJC6d8/L7UEBPrFggLPEBw2DchZB0/BB2DscSfhLJ/H9q0w6T8vRMXldK1g+JEC6M1RPaj
kkxeNbU5+XPDsbx2Y3+yhzkB9Ye54pqshRXTNeZBFDzhJq6lMLG1tI2hLX1dVpRNfznPCevyr5fE
8MD0jleQUcPO+YasqcZOaT5zZzk5ZimrNtyxFhbwmX256zXowa3/mlhlyLHGB9QvoPlKHhWTM9Bj
APJvc0ncE3ck1QBHF98xfvVyJNFRNVowCT8NiMvCOfjOHWaHaL2B+sRTduWwOKts23Ggvibbx8oP
2AzGiIX7pGl+8ERopOO+q3xY8xaKTX3OAU8Zu2ASESvv1CQPvE0DMABfr1nstgshrXlBUOGHjzxf
CnhLy59WR8Pvu2leHBLLYGCONRE/zuLHyKkLKHGBk1wPKMIF5TwYaLwK1pTgjc+pNLysHAnRt3x1
ZqgifvmKTUOh4XciqApdW4VLXHKI3zE5ct5LJKixldntm5v8ozeO8Sp6euiASA1GqSAO1kGhD7BR
tNApNgqkE3duFwB5rCflLzWAC1QbYnRuUHSkwxj5+DA8IikE+vh8z+VzSQBl7rYKH/TgCfIUpUW1
ZqdkVIv8HDY6F9piNpE4SqWPh81Z/RyYqtN/qy9TQMfNyRQvsthhvWpRm+aOQu2HAZ24wFtY/6Yh
Qw5zlASjkN035RHxHFpxP0200w/GOHpIFRRAIIMBQUje0vk8RwwvDOHTU9TgU9PDf2HxUbHCHsgy
3la8PnLANNq4bMujodde48LMSBNdmyF/+U9TqaXayVd3uakREil93RDH3OoNxa5WNsF6muhz/oDq
OJeQaqoM9aEE+Cv2/kNlj7HLEO0vUhgMLrf9GAJecwTT09yC6r4nMlkFWI0FgKewCV26P9ytvn3G
/37OTJot4orqT+3Y8RCyv0g1kMs3Jhisf9YoDXaSqEq4+GNPRBWWU2YW3c9vdK2lVYQWiPm5twsq
O/dhdBnm5UhkGRHS2ie7Z3D2WCi/b2aZ6oA106wlVLg44Psb/dfuy8HMA+it3eD/Xmyr6RpLkAb9
D0/vpiUnn4DY+jD5TDHfYzzFCRJxCIRlsEZBNFLv32tSKgdIfJ9QNSXXRrOh7/pdZzOAS4fxy/xA
ioOYBIoXJYnS/ygvRIdEJ74f3O705u93jNENzJq7dvJfzu93pQgbFvAksxAanuo/bEoPP5MI2Cmy
txkWK2MnY6zsTg1jARROSrVgCM9oES1zJ7F6FKZGIJ/o08IFe9z4aDmcYSxjAeeh4vAlAz6YTWdW
WTWh+K/kC0XkcfgfLBjXNWqTwbQiggvjGgGY61pHHDa1+PlucM+K9hR1mHlfzSXgqJ70hqpQKmjX
xz194YoNRE+Zso9FN0jDDHxQpfGkvcitpX0WLEOqaTPpoMrcShF8OCrMN71sqk6raOC3ipHvThsR
r8SXsdagfcr0OkNhWHk1eoNXJ2LNQtpSlITCtYwxwCUJmzm5OtQUnT+1g1QSEaJyYT5TAEA24JC8
16sfqAaEGR0xBOul7p9eAMUJUh23ClTb4ulXR9oCYg7pwelLcmMnac+/9iXmsuHdZOp1OkI3k1BG
ZqhhbEnlOnZYKyZBPw2R2m7yr3oALWniD+NxKfT3vMzcQ8ffb+XRLBwuzSUuBSwyD2uMXugRs2QF
Au3Qs50BoULJfXeOWGCmiGo2KoJVwLDvJ423YSr7sYHkTVa6RTWZDfIU4sdcT0xnbfVmQJk+oZ/w
Ai+JoZiVsLnujgbZ5fs+nra7/zOxy1lpZL2FL18NERvVSy0qV3IS/c6TUMwnwoO3kOUPCzx0qSjH
kd4/21uUEtkH0Kc6PsY2EGqiq2iHT4LjriGuW1Bwlqs4Nh9l/3ejPaWN3ox2J6UvgjB5JHf44ddQ
JR7jHDeYGLYonRc3GtHoTas0nrGrM2PfPkwjr+f9lWuvowFEg0+ZSA4dy9IpoaNrS+zWJ8vYuCQY
5lW7UHeOxxnlMoZVUher1EP5PB810KL7xfBsHJy8oDjD1Ooo3mFam9VXCsZT48uwXC/aKLZYVkWz
eKNXdRddDbMAjOcw7z7yWpXzV9F0RL6+WSJMzXnusDIDvyrs1/Sv+lrCPR7Ax0ibtMj590DWkP3C
ou3I3bXCQ1Z58WQP9I1n8ds/+fqWTkzyedCJUMxcc5TSZm5cGgoGlxYPEtFgAO2UY90zR6Xh3MLx
COZ+BkwJDLRC3zxjjsHZg4P/mnN/V4SGsWpGIhd7N0vV4qighlh9nd/lg2OJ+RSjK/ASGvReFg+Z
6Ti8XTZf/LX0od3SV0y9rgnff4mu/4kJIypYQEk9QH7h740dKLQI987l+Yp2Pk5+JzF6IhueGoh4
HCYJoBdyd4P+xxN/saz+smL0rSR2jL1/HWmvudC/fc8gTiIOIDUIzSYoD4paQjICy33BD/tZC2l3
BJhX4z12oFw5Am7YNirA05fywDqBD5iwr/LYoEOIcYwDxGrTysVLHAEX4BcHh9VxkYqFLSh7Ofln
++5edoi8ln/W6hXoSvTE5BLaN8kLvpvgaS0iSoMPSLLeTG9v9PLWJSyqsqgVUy3R1WZpyiErzjTp
avUMNH4GerKZ7GQBB2QvNgQpQWIuSRBzUUIgzolR6LfEgyF29bNlyMZs/UspGzVVKF9W/hfXkH2U
npo5neZzNnf31icab8BWcuvYo+8i9QTPi5SioUAXRun82OR6ZLJ4GuDtF6uP/tCjsBRK4eCQMmPP
eEzzILttdLGucc2NlajrjlpL3KwGdA/UCsJyZZMF6Xvr7vDWJLARL/ke2l1L4pgCAA6QpxEHinO7
poAnsntJttn7w+20G641TrF+D2q8dhOM8XDGEjGNv1BTPTjk9D3yex0gHEOy7IN9J4HCwT9CZFEE
mn/aVaKclAsug4WE89YBIxUdsJICvjantA9iOtvGuLSDtCsYqA3SfGWAAuTyL8ZyJKchHQFcmszc
G55Vb01Gzmd6imZ835zUXohgUYa4iDB8b3L87s5rbvEcn3k7x6mXxcPyW/g19afxAukSBnWrL+Ay
KKVOisvgt7ewcravWfjsBRIahqYn9wCcHB69vGO1y1lpyPNM3G+pWit+jj1Te6JZ7Es47YUzLNhn
Y90jaEG0ewNRA3WI6yVXzPJljjEkc/kOrMZYa/b1xkzRIrY5jPw2hhg0eiN5lAZYW4TilX5jNGNJ
XilLP00M2zMT+eqe37kgZV5ckCEwQFbSkRVd4XThh+wd37J2hR8BDrxALMnx0h0DIZ1XLQuEjY3n
l6dRb4Mud8Bt1Y5ogGepYaPPn6/Jn2EMv2rJ/UUoLgBL2O4elAh4G0tVG1SXvs1bmhhE/xJE5JAf
x9CFLqTXzLkQ0JIrwRYO024zPXvta5T2ZJvW0bto7Qroslh3TMC8m0OrpfiwSjFQXUx6q4NSK/Gd
AkpnYoQvQpNo4MHG+OC6iFY7ysME/eyYjDEOUSTdiVXCTbqBz7gnw7eT1sQs3VFs0REPkT/OeZyj
SFOuo298pYXmPBru8WMidcSUGK1kg7+tI03vN5p1WuH4nC8UceiCW+KS5tjAEop+Ayueil/XOp18
Z2E0rgoWtD+9H3Olqpr1ih3YulenFiHHuLeVqQlF1bf9NxQs/7oNNVNdRa/veovcPVZvNZj2XENO
zcZ2tb/oj6dfFdwF/3Kt3btRVMg9BJm4zSqbfYkWoDr8XP7J3dycK37UgvKL16a5G7H0fiiVrT8U
gy2gIdiOAezDNEZPu2J1b6KayoM9G1e/huahIP5VFKBFX9o99nq+9OguHi+IBt8CQ9ilz7N7yDcf
OySyqpqdEllCOqNLrcVPdr0V5jja2itdsvF9i7kRSHb6Rue1QrQhiUSs5JkBYEmxEDY8x28wnh3x
BXZTAurcKR3GPaJ7o86CgdXtCevYGF4sgkrNITmulLwz1YPmOsEgwn2vZdp8/e+nb57vQuosVMlg
mrik28o+drn6LgOEjCBjC/fEFFJUOAi+oMsCEjDUL7C8MAkT6yE4LTti8T16QsKzrX1SqiEuH+ud
HOJGa4IokzZ05cJzR6BfwJ4TIZpKR9R9hDiN08AEe1euCn1dz4sRSKqLGhXZm4dxpVK0ROzNm2a0
k1epCbAjEjxhcF065/eFbhIwryBkjXOYyyzJDI7N5oL/YVzXjYLLZSl5u3N2pBbJ4x3HhkrJAEtn
ltytSJ0HkWSEMXesHic2UYKt4p6Ee7eHOVb3cyVCWddWlW/H85F9Sc0uxiUsxVaZt1uKCirBbIH+
/v6AtGqlWdhNPvEsHwVhqelkn3k8NEQEYs/Yb0t2Qlgd+a/hhOHUV4HtdRFUbB1P7XsYDTOZ4tui
NORbERskw+FNyG0UEuwELL6s79qdfh1cy06BJyM5U3UOwHSnjXE+LnzF9CO8UpOaW8z2nikWtNPL
razMZCaw1Eq8umdjWd3UVm78nj91i454xYdlQ9e4ysGSjQr+viv5loxnTN/0T1C81rFVNXrOgUEM
1aNbsgZ4pVrDNh5EZlweZ9pQC18KMeXBTo0aS/P7OUtjC4lQ3x3eLij0YfGvuGzvcX1jwEE2pJTk
1INF2KR04KShuW9X9NiVBflzxlAZSbxQE65T2g0OM+yFRixVs6naF/s5lW60IY+gj90sNN17bQQM
87cX1ULfsZXUsm3g2yDK7QgXatHhpmBJ4VAVq6BWsiXxabIzlCA6M2CZktm+1JcscvGrsNMy8Usw
6jupPaOIHkHAdpK6vYWiYhBm6BQhqNVa5JxuULNiN6ekzeL2TC6rycmAPhU1b2InbMgQvW48jW19
ZST4mUxEKtfNyf1N+jdVmI3LL79gVivLNKs5JLQcSSAp+G9v6kxyiFCISu7E4ezqBsWxH+6INoF1
CbOuUiwi+Vt8c3eBR3o+eaMR+e/yohMF9UizZjNk8L5LQeyUeQJx6HWDoI1goC2eAxgLzURKZ72i
686pBNTxKIcNRhBsqPyCVGPRYG60bPjg3fm3K54+a2wrOxDgnxPuGy1dsvs9u1mchsbgz+kfH3zC
kSpKlsLoBtRmAbgivDCstDM0wecxPfXhHME53mUsVwZSnHOqrcOsCpQc+Pl1v10qxryCgozEpC9k
HXFn/WYWB64Z5HFd/t2nPKLPHpTOGNDxIE4Nanj6nThvcjiF/ZxsOx4QAXWopr2KSSLyPd5OegDL
8ZZDNle1WLx54uTK2tZ+p0niRTrDrgGMR0sOtYLCX2oAoTkR2y3wgNQIHluoteLzaNz1voMX9xwS
Oimfm1wSw5i4VarUn8xF1G+cmlo14EdXVW+r2DkOnFelA9j/dv9Fmffj526d9HDMZDWAJqdU45qn
t/mgnwhrZoYFsdKqByhtZY+9A4B4FHWcG8x6mRpW9Ao3Leoix6mNmJ9g1YvqYL2Fd7Pzzay02XKQ
YQ0hZOKdpoLmVF9Mkd72InVFyYv56s1vide71sFECTshBen3f2Lc+m4DwNqPfv87d+/No63W0xRF
vKIz2YAEB5ru8zzeKn9ooovfh0nP3Kl/OP6E61pgLQNd84zAN8Xvcv2Nd+wvKV3Yk1yFjgMulim0
MGi36zx6emDz0pPtheurZghJgbVKM5JFrwSsfT8uHn2eNYJAOdft55XWu+dkIxKtGP02U622ZQos
F+8mG6amKPXW+OByiUVVjh/iDm+5w3QP4tj9mnU1sVt+/kl3rXT/PTy1N8pJyP8m2tkqKJyYjGr4
SKur7XNZDwLLF6Shq9DuGjGakKrRAxxKKIYLpPFpiWuChWVZhcqYjN8jaRuHi9updR+OJfoMva76
WMW+XKplTVh1/+uF91glbUc5hazuqvsRRAwJGSqVKzsCYB1FNkHfA50ri8v+5Dak6ikZdgrlEW44
Mpg12tE91vj6BizsYzDu7lAH2LKNnNLOEhyh5sWJeKxxamSRr8T1JFT8BID+6dz/KYskNYIbugvb
btRtAjSioWzKjYIdqfqkyWuqa578LIImMg9V+vK6g+k+/uHAoZqrNDucdJCZPI91rgLrt2r/dTvf
jjr+sQn0L9s8dPwgR4tYvLn1Ywxzqog7M/hQ+8GSjqiwp4PbNwbpEVpEjPlvLP8HnhCPM5+QHYlC
L2T9zgce2bHlr2mEirgs2nK8Jl0Sndn7Z7bsJjgpSfmT2Vy5tq8NUPAroq03YzpmxXaM3KN/L+z8
7zcPMNn6pFqgyobpF1e1RaXgNoKHwWUNfqJ/sRipVljvLN+gZkIQuEHBticZi8VVjn4WSwGG9Zo9
0N2eFoRfGV78xdYxJU8ugxffBwwJwS4qhsk3m+ZYWPQ4FiAZ1uxB5MmEY6C8NHp4z8int9lpqkBF
ckz3zU+ItKvew3ECXT60yVZ6DYx9RiPnmK4c3Jm1APpv8GJyJ+5DZvKt/dHLz/gxnIfejV8kZ69U
3oPdoKCaaNy6DKF9kjxCLHttwTFMIsBNvgrAuH82Rorm1cdINo5XeSRIZtan2TTm/Stp5Yf4r6gB
KWbYOhGPfT456OyTBwrTvI9ddtwAb2PYEIBnvAdLJL5gKWo5iJEsmv/MlOLvwA1LWzKZPB7vH1aE
C50LhIzHfXOybAMPFYLU7r0H5LI3BWAHAqsFSY3ikV0JMKckTLEuvpnM91Csbbz+le7mpPlqlsAs
HN1fAuLEPaw000Dwxf44uH7GXaTbIr2b5w1zQFbagfaw1rMbbrHfQ8tXNbj69gEJGLdwIxGf/vEK
ijbCb07jqgmgX29nxffBNz1wPy7Hnv11PU+csLV71GggKcZiybRhAM4MN6r0oBkG/IShcXxzwLB2
9TSXtQqWqCKXpZOl2VyfWn7gmevdHaXPAwvhFR2lzxquoC7T9uDtFQVfWL8ihloDSHffhEP+0JMw
N1gZaLyifCia+nxFkyaum5q+RWMu02ie9m85+roiL6zenUx/Zm+rZmRik9xZyy1HCrquOKk7HsiM
W8p6fJKYbifFnXgeAJumfvl2wZP8peUajTua9di2GV0F7avEwS/BS/WwrgijYv4Y55Y6jia9Qk+V
u1GUfxirdm8M+OpKxbSi+5piNtGRD1iLMWgZil4suHNPBy4IEm7u6JAOy0qN4i0llRCI/G2a9GJq
wL9iWDni15782vovW1fUBNftEsuFMFaiiryzNlwdH2NiLmxcv1bNX+3axrrFIl+Xsic2cUCRFLWe
Qlk4ZQpsc6sQS6O2JvVoKUZL2mTwGpvTlbaA/7hUrvkO8LN9L317CYqJpFBnrcHoOtnVphLzoJg4
lXqFojUzFrUk2uU8GcwWoN+5/B+G3niTc5+cnPKWXYOdg5c571MTJAXlz9lGKoZK1/UBVdyBeVY/
3DSeIuIpnZQXSJXIhGdGjhVvcu8bbW0epn5VQFYnUnLC+qWWqw9IzCYYcRL+80q9M4npEIiJlbLa
1jL9uKdKbaFItTs7BM+anrdrNx5T8vf1+CEQnbUd71sH5npxzSVSnqythlUYHx1OfGo2182xrBPM
v2Ok78XquyYhk5alHnjQoFv54rkSgxL+ynpS/G+2NlE0Sb9nkjMI5LkWo5PE9R/KvWqQPX45IZPn
CxRBcduMCbwBsBsS4y7/KsxArcYjf7WP/X5KTwQYWOKWJbivmn8agvKBeQQOBe8+d5JPqhbEb+R3
s82cerHqu3wjlWikMiNnXraj6B3cEvlWmvsF6fBa+dojKRVIkHGd8o9auIMaqyH5Rua3sx3IrAsX
D6eCFM5ifznCjGK4erHeD/N5SqMFcoTZTMKVrvuvA42+txe0vwSimN0omTGvZwdmqkGSEehEoytG
MAqqrm5Rfovh4rHw+1jYRwObPIp5XOuzCVjK8r0XBa1f/nofVgoFOPdUE/0/vYe396U4ky35Wy59
n1/DNkPz57GqLm9hF0q1RByxIrL6Cb204AWOSxIk5XLX98i1Uv0Mlg8BjgRMnpSvMNR4sgVg5wIi
UddWzPMvPgbglSw1lpAARzWMsPwj7VIVospXXavUfYDFx6gS0DqDLA+vjB/kHwZlKR/7Qsbo6/jC
MLh3pgVELPLSy49XB9rI7hAU0ExDGv4VoAWSncX/IBfK2/9LvbSN0XwSj8XyGPdNkqkSXF47ZzSx
9cmlQ1pSgMhoxnvnuxtfqOi1KQ1yk479yDVGlmC40/kMdrYPL9CKfk3tHIJNKEt/fInPVEEeOHIf
yZ7J4sGEHvQhyY0PAD5opEer1BTN6JgIkETP2NxDr0michgqV5aiy2EG+sY6iHs169QRmyY+QsEJ
o4WoCyN5EMvSYi39isAx5+TiWNb1pR5RqcglSg8NYtVcVfkBrqpCfCCjGwWcomqXkecvLP0xPVMe
CqyIRHihb5lyu2270ziVL9tSs3A756P1rvjWM/uoxbVu0RW1+agBE+Ezhl8I72+7Ni+C5cjo1SWz
yIkJ4xrrb24gC7Ff9+DYenS+jVsr6vQn4fPVs1bwtnMH1+GRwg2Z9gBQleTU7nHD13ZAnMlWRdl+
6QKItJXdL4gp5wOF1nk5tyJAO28IlAnI9kx5PzlX5W+zecrxDhN1ILI6c9zpFhIKTY82jrEPVEW3
mmHJsMcyh9kkMdpqP81fBIf6FrLAIvTvjS453HMIGBz0hmR5MA6/0RMWPmS94ouNUIxJvwKj44f2
kzWsaM5TtfHK6FF2CfBbvKmZyBmiAMKB/iL5kW23NDGLUA70mwWiQNMSGxkCWp11h7CkQPz4WnWs
X45FJPZLErIcHMyuByXvAninMDWhDCZoTjc/ppD6kEOPsu3scWOLlhqESLpoRzU7ZTRC520sY+ja
nvzEUcoKEKYc5Ml6GArhjUYGKV+Q7PWqaJdQIrJEaI5WXu7tw901DcKm/HG3bZpWLIMVWukPKCQ0
nmFCbf0MOdMqx0xnRu5nxpkQOqQ8/9RPvCVr+3t5ysbUXlv2kgKtslACJbg5z/yonbDTVHbc1gDW
YvxK3UmbzAtGP1+YFqitSqMlAqooYiC09FoZmHWcnbF5EWCL5c4MLStF/ZigyPXY2YUIrkzmuDq0
9SX90IRc0U9LI4YmcsWZh6pOWV0KDKMvWwn0lMacRh5PdWOdSQQeMXE7OiPbl7689gqpr02/0SSR
xDfRBm8URigHrSgH6Xmc/vBzXc8cvS5LZoO5nv6uf7uBf+WBnTI8H+hKjHCbgc5zDv06q04Du2KN
kVtmLnK/qXRZmQuxedMcLh87/9g2QMQOo0cWoMyGH3+xYKj7C6SUNnv5Wid49q7O3ixgGdWRqUeh
5i/mKMtNIierj5CiQd4rh+2kfyzElCyQ/fYhdzZg1iLG1WFeGi3TUxeweGsu0NWGetV/5X1zEg34
PA7jtqJvkjWl20qfgVsbOckHFHMpcJrCi0Hs3aOHDI/p5oQ0gAJBgZSDEVPEaG/x3w+isXygMi3L
4OOhnQe46ksDnnEtNwVVFCk2MyXUVCRsdz7b1tU7EbBgpftZ3n/p0DeXeyovS8RJ+rrfaYAtd1GC
Fqh2+Hp6YRHZV4/80WQgHFkyDcj9aVkxYecJ4g6iSIoK1QOoJgT0QOpcnMf60wbNgippFyodliMT
QH2X5g3exs3uR0k2udEtPXUj1cfyVmzoJVVjIhHrGSFne5ce76JuXQVkdfnWub9l04UIMcd1TVg3
8tyPzCbmpfMdjMXhlNF0lb3QlgdOBwLiWPU4hl0/JZWZPqaj9VtsHWJdwncBXeZrQxy7myH/FLic
uVF/E/e2N71lue7rWE7WEjgF5ib1A6buoR9he38u1P68H445vZAkeGDxgevn5tKbsnmYgbdfZr/w
Ci2iLARWxcQBnAZfRg3ESMifsPe24HkWuvrd/85a3wfpWld3Voc7CYxrOmheRhUWBl4+W+uyIDTo
I6XaqGmHLAgfmWafsKduzIseIrWQ4CQJQHMcpMc/TFCnrhOJNsaMFEwMZPfM1RefJqtqSftNxzBl
0C8YJCLtcZeANdwey5K0ls7cBIiGMT2tpGVctAvdqjgvncr3bg8REqlu6+yHXsFryQ6LMxA9u6Qv
eDkTAc69EeSVxyjW55XMAKsfdez+sDnnmNAWzkZ6RGjG7e7ACJvGfslkNwkvTm5djcyemYN/oAKD
FHnJ4uukKMueC/KrZOqcIOd4scAbD3uLW+A80niiY4VtoU4k7x4+PjaVUCnt4CEq/U+p8lehTt4l
nCrQP5J4poEP3ChNeJ+azOCx6erEqESfVgSKSpGtLfpUwrmWpU2x5si2MQz1o/Hc4ipc9AxvLFyo
pZWcseNEOvw6OS6sg3nlzgXJKgtXRPuggYBgel6nFRTOmXsywD/gVs8S8FdTtELimxkjpmJEltLj
0R5r1kfKypYX5srcV7yFWFh2xLhvFOouePD5Th7b3WPOrkhH3M2oSKstq7f6BwpykWlgMhrKPdM6
Zdh/TqxuUGqrXgy3P0ay+br92B7MX5WQRJzGCjSuR05fiOXXji26nuz0/+tzZci0DsTgItgjX9By
F6nUnNB450OHgsyNx0g3CqNmy4hLROoSDFbEVRClQJdtlz2uSZIxQBsp7UgxUz27x74WFweSiNaF
PNsChQyUaaolX3MHXxNbfeq1uID4nEGKHG+6abY5VyPVSq9Ykf4FngigyLcfZy0XHuv9CXdT/zNo
GadIIUcOqku2NFSMjhQrM2QhiFPLxESnlcuM2kMbB1NVHYajainzi9ugMzo7YIXmayciH+Pvp7qr
YVye7wI0eWr9iUB+WABxY4Ka80cBP9VID/YHsbr+a5CYW7jDYpp8yXRwflVN1BvOgLwweR+GBHCR
Jzn0ItvgXl2DJEpcR5Mpj5waWDQqUTIadVbEFXLcZg91tvupjvs3Dpt7YUkf4yVpveyEUNQWYv5E
/BwHipuyYibWP+N7HMhVUYtbdu3U14x1eNancUXwgFoCY4aKNPEejBBXNEmG26VT06u0I7x6uf7s
M7NSsEub8mktEa83wQJxQyIE2O/69MDm995fqT+1o4kohGPp9lGII9BzypuHN4QcjX8ErSHTbJJR
dm7SvTU702waHVBTj7f6OWjLlhNalwCKPXrC1a6FxeXy/q0U+lRFOxHGDIHg/dHRfuZz5oMB6G/X
nKkoljFqE1ahHZ4xBnXbf9Ue5sviPxvgRtPUQlVWvldcFGqRgPTi1RBpohZ6UU/HjIpQOmo9gjwW
9Ft1MOM+DaXfImT0zys/TU7c5yPL1odi4wdoZJF0LCAPJiVPg2kayRKLfxJ/g5oQICUCoE11TjKi
udfXONvWMEm7z4t+wmQqX+HPopMgXn8ZaJtqf0E4Cz3Mjf89f3+UF4yncK61ET/5D1Lsm1n4j9yC
wqw8C9wjeOWWX/hPuiOhzTT0ZwuvivCOIHotTpdGg72ybLIyKG725EaZeLXnoZGRxQS82qyO9HP+
H053dxSVoaZn1Lg2xNZY8krDsxNvfid3f3NL0J7nRGXRwXbR8/J2SNYvFRc6TpB+gXF1UlI+Pe1n
aSv+H6Bg0HdRRhVCZC/Iwz0mg6l9y1lBh3GvH+KANV83OmmJJemA3BBLohUG1pTlHqZZ0iVudgxk
KsvP1QxnggP9E/fjxGphVU5KnrqoOrtNTLkJL07YRQ7HkhP7pG7wXL3hlm8EacLr4d6Qo3L0YNxl
D+04HPE+IgemEsJwaRmBFCT+00XX9H7QBG4IPNAVX6vAf+GOhvqMLd7x+bCg0OPzOK9a/wUixRB1
gZKjJEl/IN9Wh/OgrmWgFyDKNWnLXh1iwGa8fppMnHW3TQs/CkIgjgOQSINm/ZgTDnp21E60wADV
N+bTX9mAHrYAzi/ZO8QXHbhIFwjADKB8sS5Wg9AtP+TZDLPob8QmiD1WGKyuTaxKg92L0eTGKG0d
ajXRUW+ZGsLF0QnxAgM3cUPwXy+Q9Ne8LzxLyc7aWG45xlGC3Li+bhVRtq1q6Lji4/StAjPmQKlc
Scii8++Vf0l9R8hQZZrPv9mSsLHjyrwZv9gkT3Tg+rMoaDultqU1OclrTIwr4b21yeZpDZa9MUGR
iRf9PFqcUqxPZuCuTIn10NaXbxcn+mKjg9VkQ2LCYP5ZALeY6eosLEaSOAGXE0dx8OS9fhoBeXPq
FjNfE+/558DBi7Hj2FjIo2duKcAHrpFFktezcv2pn9eQKdzP4DB2E6ggtkgJGDaaw2j7cNRZePGh
J9im8TazgNOz9KzcNVENFrqdi8f/awLZNIMk/Q4xQngLE75qbwwy0AJaW7tX6VIQyQ1Ow5+g51DB
jY7ytXwwHH5SjwMCwDUp1pyhDD1xod8loz3QtnCBwwUM5xfm/t6wlN5476q/g61HnBjuKeyJsslN
U1n3eVkIzpyi7uJRPbNlEgVUk8vqGwuY2OTy0YKFQ9VdCCqPtwFgktbfu962dK+J2CBqzK6vAJBZ
IyHDZVhBlNbhgrG0fESdVOrA7F1Djn5bTkym1tvOBpWLmLPHAJ2ztFhz3p5Ch0KvG4+GxL8KtzIY
KEnwFbhPTlZuSk8/ofnbPIEbXkptUIzvDB4zjaysuwiYCmIQ3FOsigWNQxHybthobAJQKUG/XByf
fkqM6H9pq9gYc8ry+2WkmHp01fLKJEJsYoIBZjMMutURPoPD9+H+WL9wtJmNdp4FHP/LlkWJF+m/
N+Yu7fYO966OH73r7uYO1+u10R6rvEqqLA9A5qS0y/vkEoChXFmC2HhAtQmnBIYRfhMgXQwQyX6f
UvnXwzMGZKyInOjOzyyWqDPBcFMtVx+kKKFc7qfM2cEwcaCs/VsuTLYNgdlBeC9cxlvXjo+mb6aA
zePgi62H2t/4+i6uXTFAGo1m4voKtna9WntQ6sBXA0IbJbbQykrWPt3RQLCsnizh56mEGODxBwIH
QO8rUqf+rBGRdrHUOIvhYumjJt4RTIGpgPr6kAXf04gyRz5J1UGQovJXbdMNW2UiEidA6nU8ZLYF
VXjkxpCJQk8ORGfExHP/v0LAOgLBouYZx7avimtSPHz5dCm+BaV7b4QoDYdSKuORS33HFIm12Q+A
jtgP76Fv0uN1YEHdsRBjZNPAfDdGNaS3vFVy0qSmFX+i/DAW6bSxgpWKRJX9MhYWAcF1LmRGIcAG
zd0ThUDtaBTXwzNTk2qlE4Gpch7/8r94ph7lQVVsmneaUtybyzra9OXSURpccriY8FicVL4GaEW/
uUnYaW5ABEeXzQGNgwbTwtmycL6TkxOcGDyUDMLzMHj2Ahb7HYGPuW31StlRQb+htxTN0o1iVSuy
TdGo1tuKRfO10RWwlv/jE5jY34nwXcnis+88UqLTLnV8b13t1zd+cWKzyBvgfbc5yog0XXpGAr9W
bCDeOo+SDebfhvLFb/10Fg0/rcfr7/hEcowzS0a63gi5RrHEmk7+k9Q2zamnpVpfZ/0Qyusk/IR+
XGjNGcOLTvkmFFlHaNDYFstF01UMYhCd3UC8eEnDsuFz1LIr8su2QCYo/Nhjwrlk5wy1LgM4m8KF
oJrdJ7PMT1guyIHJDSHsg9sO4PhXa9l+l1+lXHsXBSBxSvhBurzWSyXQuv4JoIhwmlwBCFZaUnPr
T2OAWwAd0TulZDnqd2zoSzcvL+zcdIt8fJfyRhMdGbbmEGplIkOgt1WQXjRHQanPgp6PLQSZN8OF
2xYn2biEOtCEydwz5NZZPMC3PCs2ie7i20mg6wPl2rCJuh/f1y4SUHs/BfTw4wjUnUA2qBTvoj2S
6oXMsBD/OK4Eh1gWZBElhFo1IQz169vRAROopergmJ4LkBllShDVBf1NSSfQQhaaIE+FoiPXwoJF
TP8bK18OiZwYFdTx1XlMKoSeolXYGqehcTIcY2rLeEqY2EllN8pfUZQCLQncTKhkqEE/cPSes+l5
5sSGiZxwHO5rfxQmwFD8pcHoCLD7kHB8/fY5FywGBI/DhN+GpzLJX3fZFHV1K4SYjXYwhAusXepO
3JYhgdVN8BLxsRmAf+kt4TQx1BCn2mVJ3CEvK6oKkJb7aSt5bXCH2FKPy3EXDNI9bOSECSSIdhl9
8UloODnQp8TvQFf+SpXaCP9ZVHS1Hpc9LnowaLzPhjEkkyQUk2NSBPjeNmRgnMz12/ES2d9VrN0u
ElxIOtNVjFaZusrogpP4J64eTOwbDCmf+nLie2Z3WtN/0pRwStcc7+7Jv0M9gMtbtIX6VDjEu/RV
uzLXmSBh+hx7hV+fNzkJpD3/vhN3WvI/qsL8HxwA0Uix54ujqOVm5t76DWenBFt0LZVWIB2k2EZh
exhTP+S+Jr2erVnxBp6ribKuF5QUFK1uIE6Z3HE8ceWavLwHCiFrgdOLv14Ucy8XbJqJ0/sdt4XG
ANC5pi+AwuKbex1WYeuR6qrlp/9SKjbqrzDgdW3JvSuS6gAy/s9AUxuSR8p4k/S5Cvmbk9t0N2UN
DusqNdLtQn8nLoMbGrfsqz0y3Eqx5xTyFErunddbKfJheeXouI4JMeaZTDvcxsaqoelYmxtrTP9b
3apIBlG5q8JsJIbM7QVPgui74BADBbT8UFpGY87djNgNCI65OLNbPZo/WQgRKBl4ehFjLRLfDcBD
XGs3MfV569mraU5eFQFx4j5nTXCLLGnpz3An4L5du07soJnJwoZqw4fjA/KRuXPkv9v0Xn9sfXDr
evW1NIbj1NgHYv2kceaEHDKMwTIp0q2TQVw9ULsWLVO6JPld6x9DiAzBiv0J0uYhIuYdewAjRLCk
wNyO7ifhG+Q/P1Xnf564LPM0GiCyC7tFYjyuTTeqhLQ6zKbYYYyj2aWsb4sHqhENSMUX+JV5Xkqt
tzUOuVb9+M4+U52a1LavSg8Leu3vzj6F+hU6E8lOdmLHLnld3efLn3uV5+SErXBsO1Fa8cNAUkY8
K38EAGLXFwjvRjWJD9dgVFoHsdxMfUamginZ2lhYMnp5JlcPaiQi9tNYM0HlcZjw260QXm+iMVDB
iEHfbGpyPsIkx+vdbMYW5QgTzIfr7ExMT3m+msX3XN+8ZI8Dj+KuwGBhUX5a8gTMzW3t+TD3FcWU
A1LBoTHDPvOhUHkTKhyVjtrIs8iGSoO7AZvKgBpc6CHuddL9hyyt7rCr5pTAn+u83+x4D+SPkKcw
3VyQUtMRTlzympC+MZTO7YFAWyxmDu8AZFneQa3nwgSP5jnwC8sjJyuIEdGMQwmto/GvhU+Ib7gI
ohyGPoGudBn/DesZkIGV/GUgWPxpz+xqAFDMvGM3Rj/ZNsBBb66ZK4fEESkV97bLqgE1PHN8998o
7HSRigyCQ03il4oWyd6ufkWvCxJL/5N9nl+dTloAQOJTPBLTs+VvYB+nPV3Q6op80m8PKrzHHDQc
BM+RWurk4f7O45C0E2awmUluLt1LxS3jMwdIoLlWGf12EDh9np42MMHi500sppBbxmy4d2/3Zbxa
vi0VZ5mPjf376PP1AduhYSe8z4BzFHaFQkBgq10QkQOdNuv/mb7ttVerGIwlW3bwfqZMySdG9qPj
ICjtI6yPtBnZCwUv986+dbEY/gcI+gpRoV5BQR77q8mJ6Y+UdRg9cK7AJ38HsrkDFqr2kPGcIbtm
KXVf27Hlpa+hBpiw7jXffP3qI+QLXU1iDHbp0yeoTLQd11iH240XZN4gf9OT2DXSYaCiiQFhDDQq
H4jqD3TeDAo1U0h22LiH6pviRoGjjvcGxaGeZbLiipIJPC4JUQX7Ib0OQre5x4HdvklEazYeIY3v
g2W8fn7j3Pu9FMQwgbIs58D7vZVKJ2XtGISITxltXRSHJgvNKQ3pAeUNnGp8Q8G/yFPqIT1wG4Kh
O5rXllYqhDlYDoqIpCIw9V4xL/v2U1GsWOaQkrPo8QCWJMdhUwGbTmUtcJ5cXiGYFTcFNCGJd/sv
WZ59vfsfzMnDYGyei3sRwUDcfmAXMkPQK23BKOSu6kee7Nm+vSPPiVbrRXSQNnOhdB0CqqQOVTFr
uhbEu4lbNlByOIUNiZphwuMBBMUTxvvsPaNNkhV/x9QxGI4r0/QgoPMCh/nSleYJYTWatJuHppbd
ZLzt3hffx9iQxgInqLTVfQ1g5MZ5VNgvD3wAcp9IIMMHOoYt5njrqBhJt1X6DsDO5qmu6ucPPvmD
Bn+PyQIi7lZJXeykRj/OTATFGdmYmmdtju10cd8bartPLiThYdPCj0QIqlQ+EGkKA4yJ3ZFZqudn
G0hbrwIncmDft/SBefQzPW6y9Ls+A9D+O5QUM54MV2ST5dJPa8VbBlm3B5EWo3GLyiWnub6oRDlt
UmMDmX4KhuFpB93p2ue1LpwGB3xigesycfyK9oGVWkPyhiR+6b3ZEua3qg/RxRODqUcoo53hh6CB
XgXNr78l+XF++uRoyfE1VveiRb1kZVmBd6R4IhYEldXSH30V58yM0BS0aaa0NxNC+YiSbEX/50+1
RsypA3EFM2/a251nCO0BxnproVP6KnBGRSpQaJJBzfo3DbBjvRV+vdIV9eRm0iFcu9p0+hynOqej
u7lsFolblpF1xEkrzslc80QN/Rt2qh1GfnvQZ9v7nWjgOlR3W/lXXIcPf/r6nBrT9dGFe1b8hE6K
dy3JCSbaKVAL3ulX2qxS2EIAq+8fLoD5HHEs4RuOCnE5PGcfQEsMpH/KojeWUqT1t1QUeD5CRZy+
N0DeYLuZEo+LLgGfnrADVvuUdHadqesW5IWR8pAb+3Z8a9puzrGaLlkDDFSq9gKKJvJ5NfX5dWkn
CumMScnfuwz5R4VNAwuWS11FsZsMCip66d6bwU4b4xhCjKN0KI2kFhYEcb2kQ1T9Gt72ImgeWtnF
jp7R2rQQz7SyAPBCq2oDgUOebsOgdG8bnOm+6QvFlSw5u0PpCFbQ08eleNwakzUriDrMEA+vev5b
AV16HAUS0Mtg2oXPVJcCeelHXYSqBCPSRnj0llirjRpkyeVo+ntHtitabcWbWG2wKCFGzzbHG4ec
h7pf2eL5BAClLc6t7vkwWVjxBD+okHHq/nF3E1nVYgaRLPMN2d9BV1QpkVIFI9ZQSSh48duyV3Z/
8/GmEOygl8Q21UaHyo2Byd4RkDH2Enpjxkfh//6C+/3SEtANNEJtQbBIZvrRm4J0ZnM1Ez6iWoyz
pRPMXwMLdpz5MKbUdR9si4PST09iZpi15VCGL6kejTuCmeEMqYjGk92ve31aLubZnDOdEwtakliB
Oe0Jz0J/sDWRoGwL3lq9gOKU1sD4n1X/zgiFlAoGPnUH3xqojQeaATGkbsweP0exB9wGhu5l0CtU
phq98KqNCO2oUdCfnd9eUsrcmLjUxJA7SwTjBupLywX9md0sBqS3Dgg0Wk+W9QqugRn6KNOS32nU
dgo0XPBZeY+SRgqJK01oDv1o8Rg=
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_to_audio_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
audio_out_l : out std_logic_vector(23 downto 0);
audio_out_r : out std_logic_vector(23 downto 0);
audio_out_valid : out std_logic;
audio_in_valid_irq : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXI_to_audio_v1_0_S00_AXI;
architecture arch_imp of AXI_to_audio_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Declaration of user logic
component audio_bridge
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
audio_in_l : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_r : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_valid : in STD_LOGIC;
audio_out_l : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_r : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_valid : out STD_LOGIC);
end component audio_bridge;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Add user logic here
audio_bridge_0 : audio_bridge
port map(
audio_out_valid => audio_out_valid,
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
audio_in_valid => audio_in_valid_irq,
audio_in_l => slv_reg0(23 downto 0),
audio_in_r => slv_reg1(23 downto 0),
rst => S_AXI_ARESETN,
clk => S_AXI_ACLK
);
-- User logic ends
end arch_imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_to_audio_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
audio_out_l : out std_logic_vector(23 downto 0);
audio_out_r : out std_logic_vector(23 downto 0);
audio_out_valid : out std_logic;
audio_in_valid_irq : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXI_to_audio_v1_0_S00_AXI;
architecture arch_imp of AXI_to_audio_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Declaration of user logic
component audio_bridge
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
audio_in_l : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_r : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_valid : in STD_LOGIC;
audio_out_l : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_r : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_valid : out STD_LOGIC);
end component audio_bridge;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Add user logic here
audio_bridge_0 : audio_bridge
port map(
audio_out_valid => audio_out_valid,
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
audio_in_valid => audio_in_valid_irq,
audio_in_l => slv_reg0(23 downto 0),
audio_in_r => slv_reg1(23 downto 0),
rst => S_AXI_ARESETN,
clk => S_AXI_ACLK
);
-- User logic ends
end arch_imp;
|
------------------------------------------------------------------------------------------------
-- DLX
-- Contains CU, Datapath and IRAM
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
entity DLX is
port (
clk : in std_logic;
rst : in std_logic);
end DLX;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
architecture dlx_rtl of DLX is
--------------------------------------------------------------------
-- Components Declaration
--------------------------------------------------------------------
component IRAM is
generic (
RAM_DEPTH : integer := 128;
I_SIZE : integer := 32);
port (
Rst : in std_logic;
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end component;
component cu is
port (
-- INPUTS
opcode : in std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : in std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
-- OUTPUTS
cw : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- Control Word + ALU operation for the current instruction decoded
);
end component;
component DataPath is
port(
-- INPUTS
clk : in std_logic;
rst : in std_logic;
fromIRAM : in std_logic_vector(31 downto 0); -- data coming from IRAM
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- Control Word + ALU operation for the current instruction decoded
-- OUTPUTS
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
Addr : out std_logic_vector(31 downto 0) -- address coming from PC (goes to IRAM)
);
end component;
----------------------------------------------------------------
-- Signals Declaration
----------------------------------------------------------------
signal opcode_i : std_logic_vector(OPCODE_SIZE - 1 downto 0);
signal func_i : std_logic_vector(FUNC_SIZE - 1 downto 0);
signal cw_i : std_logic_vector(CW_SIZE + ALUOP_SIZE - 1 downto 0);
signal IRAM_out_i : std_logic_vector(31 downto 0);
signal Addr_i : std_logic_vector(31 downto 0);
begin -- DLX
-- component instantiations
u_IRAM: IRAM
generic map (
RAM_DEPTH => 128,
I_SIZE => 32
)
port map(
Rst => rst,
Addr => Addr_i,
Dout => IRAM_out_i
);
u_cu: cu port map(
-- INPUTS
opcode => opcode_i, -- opcode field in instruction register
func => func_i, -- func field in instruction register
-- OUTPUTS
cw => cw_i
);
u_DataPath: DataPath port map(
-- INPUTS
clk => clk,
rst => rst,
fromIRAM => IRAM_out_i, -- data coming from IRAM
cw => cw_i,
-- OUTPUTS
opcode => opcode_i, -- opcode field in instruction register
func => func_i, -- func field in instruction register
Addr => Addr_i
);
end dlx_rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_mBuf_128x72_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_mBuf_128x72_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/zqynq_lab_1_design_xbar_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd is
port (
aa_grant_any : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
f_hot2enc_return0 : out STD_LOGIC;
\m_atarget_hot_reg[4]\ : out STD_LOGIC;
\m_atarget_hot_reg[3]\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_axi.s_axi_wready_i_reg_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
s_axi_rid_i : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rlast_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_hot_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
write_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\gen_axi.s_axi_awready_i_reg_0\ : in STD_LOGIC;
mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d0_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_rready : in STD_LOGIC;
\gen_axi.read_cs_reg[0]\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_14_addr_arbiter_sasd";
end zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aa_grant_any\ : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \^f_hot2enc_return0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[1]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_4_n_0\ : STD_LOGIC;
signal \^m_atarget_hot_reg[3]\ : STD_LOGIC;
signal \^m_atarget_hot_reg[4]\ : STD_LOGIC;
signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_6_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_bready[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair13";
begin
E(0) <= \^e\(0);
SR(0) <= \^sr\(0);
aa_grant_any <= \^aa_grant_any\;
aa_grant_rnw <= \^aa_grant_rnw\;
f_hot2enc_return0 <= \^f_hot2enc_return0\;
\m_atarget_hot_reg[3]\ <= \^m_atarget_hot_reg[3]\;
\m_atarget_hot_reg[4]\ <= \^m_atarget_hot_reg[4]\;
\m_axi_arqos[3]\(68 downto 0) <= \^m_axi_arqos[3]\(68 downto 0);
m_ready_d0(0) <= \^m_ready_d0\(0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
m_valid_i <= \^m_valid_i\;
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
O => \gen_axi.s_axi_arready_i_reg\
);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => m_ready_d_0(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \gen_axi.s_axi_awready_i_reg\
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I1 => \^m_axi_arqos[3]\(50),
I2 => \^m_axi_arqos[3]\(51),
I3 => \^m_axi_arqos[3]\(48),
I4 => \^m_axi_arqos[3]\(49),
I5 => mi_rvalid(0),
O => \gen_axi.s_axi_rlast_i_reg\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_rnw\,
I2 => m_ready_d(1),
I3 => \m_atarget_hot_reg[4]_0\(4),
I4 => mi_arready(0),
I5 => mi_rvalid(0),
O => s_axi_rid_i
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^m_axi_arqos[3]\(44),
I1 => \^m_axi_arqos[3]\(45),
I2 => \^m_axi_arqos[3]\(46),
I3 => \^m_axi_arqos[3]\(47),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^m_ready_d_reg[1]_0\,
I1 => s_axi_wlast(0),
I2 => \m_atarget_hot_reg[4]_0\(4),
I3 => write_cs(0),
O => \gen_axi.s_axi_wready_i_reg_0\
);
\gen_axi.s_axi_wready_i_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFFFF"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d_0(2),
I3 => mi_awready(0),
I4 => \m_atarget_hot_reg[4]_0\(4),
O => \gen_axi.s_axi_wready_i_reg\
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(0),
O => \m_ready_d_reg[0]_0\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF4700000044"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => s_axi_awvalid(0),
I3 => \^aa_grant_any\,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(0),
O => s_amesg(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(10),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_grant_any\,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(11),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(1),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(2),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(33)
);
\gen_no_arbiter.m_amesg_i[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(34)
);
\gen_no_arbiter.m_amesg_i[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(35)
);
\gen_no_arbiter.m_amesg_i[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(36)
);
\gen_no_arbiter.m_amesg_i[37]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(37)
);
\gen_no_arbiter.m_amesg_i[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(38)
);
\gen_no_arbiter.m_amesg_i[39]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(39)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(3),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[40]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(40)
);
\gen_no_arbiter.m_amesg_i[41]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(41)
);
\gen_no_arbiter.m_amesg_i[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(42)
);
\gen_no_arbiter.m_amesg_i[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(43)
);
\gen_no_arbiter.m_amesg_i[44]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(0),
O => s_amesg(44)
);
\gen_no_arbiter.m_amesg_i[45]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(1),
O => s_amesg(45)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(2),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(3),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(4),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[49]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(5),
O => s_amesg(49)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(4),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(6),
O => s_amesg(50)
);
\gen_no_arbiter.m_amesg_i[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(7),
O => s_amesg(51)
);
\gen_no_arbiter.m_amesg_i[52]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(0),
O => s_amesg(52)
);
\gen_no_arbiter.m_amesg_i[53]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(1),
O => s_amesg(53)
);
\gen_no_arbiter.m_amesg_i[54]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(2),
O => s_amesg(54)
);
\gen_no_arbiter.m_amesg_i[55]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlock(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlock(0),
O => s_amesg(55)
);
\gen_no_arbiter.m_amesg_i[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(57)
);
\gen_no_arbiter.m_amesg_i[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(58)
);
\gen_no_arbiter.m_amesg_i[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(59)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(5),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[60]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arburst(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awburst(0),
O => s_amesg(60)
);
\gen_no_arbiter.m_amesg_i[61]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awburst(1),
O => s_amesg(61)
);
\gen_no_arbiter.m_amesg_i[62]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(0),
O => s_amesg(62)
);
\gen_no_arbiter.m_amesg_i[63]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(1),
O => s_amesg(63)
);
\gen_no_arbiter.m_amesg_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(2),
O => s_amesg(64)
);
\gen_no_arbiter.m_amesg_i[65]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(3),
O => s_amesg(65)
);
\gen_no_arbiter.m_amesg_i[66]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(0),
O => s_amesg(66)
);
\gen_no_arbiter.m_amesg_i[67]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(1),
O => s_amesg(67)
);
\gen_no_arbiter.m_amesg_i[68]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(2),
O => s_amesg(68)
);
\gen_no_arbiter.m_amesg_i[69]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(3),
O => s_amesg(69)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(6),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(7),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(8),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(9),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(0),
Q => \^m_axi_arqos[3]\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^m_axi_arqos[3]\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^m_axi_arqos[3]\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^m_axi_arqos[3]\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^m_axi_arqos[3]\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^m_axi_arqos[3]\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^m_axi_arqos[3]\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^m_axi_arqos[3]\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^m_axi_arqos[3]\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^m_axi_arqos[3]\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^m_axi_arqos[3]\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^m_axi_arqos[3]\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^m_axi_arqos[3]\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^m_axi_arqos[3]\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^m_axi_arqos[3]\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^m_axi_arqos[3]\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^m_axi_arqos[3]\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^m_axi_arqos[3]\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^m_axi_arqos[3]\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^m_axi_arqos[3]\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^m_axi_arqos[3]\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^m_axi_arqos[3]\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^m_axi_arqos[3]\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^m_axi_arqos[3]\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^m_axi_arqos[3]\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^m_axi_arqos[3]\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(33),
Q => \^m_axi_arqos[3]\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(34),
Q => \^m_axi_arqos[3]\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(35),
Q => \^m_axi_arqos[3]\(35),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(36),
Q => \^m_axi_arqos[3]\(36),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(37),
Q => \^m_axi_arqos[3]\(37),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(38),
Q => \^m_axi_arqos[3]\(38),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(39),
Q => \^m_axi_arqos[3]\(39),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^m_axi_arqos[3]\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(40),
Q => \^m_axi_arqos[3]\(40),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(41),
Q => \^m_axi_arqos[3]\(41),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(42),
Q => \^m_axi_arqos[3]\(42),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(43),
Q => \^m_axi_arqos[3]\(43),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(44),
Q => \^m_axi_arqos[3]\(44),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(45),
Q => \^m_axi_arqos[3]\(45),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^m_axi_arqos[3]\(46),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^m_axi_arqos[3]\(47),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^m_axi_arqos[3]\(48),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(49),
Q => \^m_axi_arqos[3]\(49),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^m_axi_arqos[3]\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(50),
Q => \^m_axi_arqos[3]\(50),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(51),
Q => \^m_axi_arqos[3]\(51),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(52),
Q => \^m_axi_arqos[3]\(52),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(53),
Q => \^m_axi_arqos[3]\(53),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(54),
Q => \^m_axi_arqos[3]\(54),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(55),
Q => \^m_axi_arqos[3]\(55),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(57),
Q => \^m_axi_arqos[3]\(56),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(58),
Q => \^m_axi_arqos[3]\(57),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(59),
Q => \^m_axi_arqos[3]\(58),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^m_axi_arqos[3]\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(60),
Q => \^m_axi_arqos[3]\(59),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(61),
Q => \^m_axi_arqos[3]\(60),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(62),
Q => \^m_axi_arqos[3]\(61),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(63),
Q => \^m_axi_arqos[3]\(62),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(64),
Q => \^m_axi_arqos[3]\(63),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(65),
Q => \^m_axi_arqos[3]\(64),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(66),
Q => \^m_axi_arqos[3]\(65),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(67),
Q => \^m_axi_arqos[3]\(66),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(68),
Q => \^m_axi_arqos[3]\(67),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(69),
Q => \^m_axi_arqos[3]\(68),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^m_axi_arqos[3]\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^m_axi_arqos[3]\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^m_axi_arqos[3]\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^m_axi_arqos[3]\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DDDC0000"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_any\,
I2 => s_axi_awvalid(0),
I3 => s_axi_arvalid(0),
I4 => aresetn_d,
I5 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808080808080B080"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => \^m_ready_d0\(0),
I4 => \m_ready_d[2]_i_6_n_0\,
I5 => \m_ready_d_reg[1]_1\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => \^aa_grant_any\,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => \^m_valid_i\,
I2 => \^aa_grant_any\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_any\,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_atarget_hot_reg[4]\,
I1 => \^f_hot2enc_return0\,
O => \m_atarget_enc_reg[2]\(0)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_atarget_hot[1]_i_2_n_0\,
I1 => \^aa_grant_any\,
I2 => \^m_axi_arqos[3]\(28),
I3 => \^m_axi_arqos[3]\(31),
I4 => \^m_axi_arqos[3]\(30),
I5 => \^m_axi_arqos[3]\(29),
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \^m_axi_arqos[3]\(31),
I1 => \^m_axi_arqos[3]\(30),
I2 => \^m_axi_arqos[3]\(29),
I3 => \m_atarget_hot[1]_i_2_n_0\,
I4 => \^m_axi_arqos[3]\(28),
I5 => \^aa_grant_any\,
O => D(1)
);
\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \m_atarget_hot[2]_i_3_n_0\,
I1 => \^m_axi_arqos[3]\(33),
I2 => \^m_axi_arqos[3]\(34),
I3 => \^m_axi_arqos[3]\(36),
I4 => \m_atarget_hot[1]_i_3_n_0\,
O => \m_atarget_hot[1]_i_2_n_0\
);
\m_atarget_hot[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^m_axi_arqos[3]\(32),
I1 => \^m_axi_arqos[3]\(37),
I2 => \^m_axi_arqos[3]\(35),
O => \m_atarget_hot[1]_i_3_n_0\
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \^m_axi_arqos[3]\(37),
I1 => \^m_axi_arqos[3]\(32),
I2 => \^m_axi_arqos[3]\(35),
I3 => \m_atarget_hot[2]_i_2_n_0\,
I4 => \^aa_grant_any\,
O => D(2)
);
\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \m_atarget_hot[2]_i_3_n_0\,
I1 => \^m_axi_arqos[3]\(33),
I2 => \^m_axi_arqos[3]\(34),
I3 => \^m_axi_arqos[3]\(36),
I4 => \m_atarget_hot[2]_i_4_n_0\,
O => \m_atarget_hot[2]_i_2_n_0\
);
\m_atarget_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \^m_axi_arqos[3]\(43),
I1 => \^m_axi_arqos[3]\(39),
I2 => \^m_axi_arqos[3]\(41),
I3 => \^m_axi_arqos[3]\(40),
I4 => \^m_axi_arqos[3]\(38),
I5 => \^m_axi_arqos[3]\(42),
O => \m_atarget_hot[2]_i_3_n_0\
);
\m_atarget_hot[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^m_axi_arqos[3]\(28),
I1 => \^m_axi_arqos[3]\(31),
I2 => \^m_axi_arqos[3]\(30),
I3 => \^m_axi_arqos[3]\(29),
O => \m_atarget_hot[2]_i_4_n_0\
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_atarget_hot_reg[3]\,
I1 => \^aa_grant_any\,
O => D(3)
);
\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^m_axi_arqos[3]\(35),
I1 => \^m_axi_arqos[3]\(37),
I2 => \^m_axi_arqos[3]\(32),
I3 => \m_atarget_hot[2]_i_2_n_0\,
O => \^m_atarget_hot_reg[3]\
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^f_hot2enc_return0\,
I1 => \^m_atarget_hot_reg[4]\,
I2 => \^aa_grant_any\,
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"1001"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \^m_axi_arqos[3]\(32),
I2 => \^m_axi_arqos[3]\(37),
I3 => \^m_axi_arqos[3]\(35),
O => \^f_hot2enc_return0\
);
\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \^m_axi_arqos[3]\(31),
I1 => \^m_axi_arqos[3]\(30),
I2 => \^m_axi_arqos[3]\(29),
I3 => \m_atarget_hot[1]_i_2_n_0\,
O => \^m_atarget_hot_reg[4]\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(3)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(3)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(3)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000FFFF"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => s_axi_rready(0),
I4 => sr_rvalid,
O => \^e\(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_rnw\,
O => \m_ready_d_reg[0]_1\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA80AA00AA80AA80"
)
port map (
I0 => m_ready_d0_1(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
I4 => \m_atarget_enc_reg[0]\,
I5 => \m_atarget_enc_reg[2]_0\,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d_0(1),
I3 => s_axi_wvalid(0),
O => \^m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"020F0F0F"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[0]\,
I2 => m_ready_d(1),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
O => \m_ready_d_reg[1]\
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0FDF0"
)
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \gen_axi.s_axi_awready_i_reg_0\,
I2 => m_ready_d_0(2),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => \^m_ready_d0\(0)
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020202020222020"
)
port map (
I0 => \^m_ready_d0\(0),
I1 => \m_ready_d[2]_i_6_n_0\,
I2 => m_ready_d_0(1),
I3 => \m_atarget_enc_reg[1]\,
I4 => s_axi_wlast(0),
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d_reg[2]\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF2FFFFF"
)
port map (
I0 => \m_atarget_enc_reg[1]_0\,
I1 => \gen_axi.s_axi_bvalid_i_reg\,
I2 => s_axi_bready(0),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => m_ready_d_0(0),
O => \m_ready_d[2]_i_6_n_0\
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => Q(1),
I1 => \^e\(0),
I2 => m_valid_i_i_2_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAA8AAA8AAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d(0),
I2 => \^aa_grant_rnw\,
I3 => \^m_valid_i\,
I4 => \gen_axi.read_cs_reg[0]\,
I5 => \m_atarget_enc_reg[1]_1\,
O => m_valid_i_i_2_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => s_ready_i,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d_0(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => \^aa_grant_any\,
I4 => \m_atarget_enc_reg[0]_0\,
O => s_axi_bvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d_0(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => \^aa_grant_any\,
I4 => \m_atarget_enc_reg[1]\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => Q(0),
I1 => \^e\(0),
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
\skid_buffer_reg[0]\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\m_atarget_hot_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[2]_0\ : in STD_LOGIC;
aa_rready : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_no_arbiter.m_amesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\gen_no_arbiter.m_amesg_i_reg[50]\ : in STD_LOGIC;
s_axi_rid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_bvalid : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_rmesg : STD_LOGIC_VECTOR ( 144 to 144 );
signal \^mi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_wready : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \skid_buffer[0]_i_2_n_0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair17";
begin
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
mi_arready(0) <= \^mi_arready\(0);
mi_awready(0) <= \^mi_awready\(0);
mi_rvalid(0) <= \^mi_rvalid\(0);
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__1\(0),
I1 => \^mi_rvalid\(0),
I2 => \gen_no_arbiter.m_amesg_i_reg[51]\(0),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01FFFFFE010000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \^mi_rvalid\(0),
I5 => \gen_no_arbiter.m_amesg_i_reg[51]\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(4),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B4FFB400"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(4),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(3),
I2 => \gen_axi.read_cnt_reg__1\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_4_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080F0008080"
)
port map (
I0 => \^mi_arready\(0),
I1 => \m_ready_d_reg[1]_1\,
I2 => Q(0),
I3 => aa_rready,
I4 => \^mi_rvalid\(0),
I5 => \gen_axi.read_cnt[7]_i_3_n_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(6),
I1 => \gen_axi.read_cnt[7]_i_4_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(7),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt[7]_i_4_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(6),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(5),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(3),
I3 => \gen_axi.read_cnt_reg__1\(0),
I4 => \gen_axi.read_cnt_reg__0\(1),
I5 => \gen_axi.read_cnt_reg__0\(4),
O => \gen_axi.read_cnt[7]_i_4_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__1\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFFFFF88008800"
)
port map (
I0 => \^mi_arready\(0),
I1 => \m_ready_d_reg[1]_1\,
I2 => aa_rready,
I3 => Q(0),
I4 => \gen_axi.read_cnt[7]_i_3_n_0\,
I5 => \^mi_rvalid\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^mi_rvalid\(0),
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC888808888888"
)
port map (
I0 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I1 => aresetn_d,
I2 => \m_ready_d_reg[1]_1\,
I3 => Q(0),
I4 => \^mi_arready\(0),
I5 => \^mi_rvalid\(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5557555555555555"
)
port map (
I0 => \^mi_rvalid\(0),
I1 => \gen_axi.read_cnt_reg__0\(7),
I2 => \gen_axi.read_cnt[7]_i_4_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(6),
I4 => Q(0),
I5 => aa_rready,
O => \gen_axi.s_axi_arready_i_i_2_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready\(0),
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFDF30003333"
)
port map (
I0 => \m_ready_d_reg[2]_0\,
I1 => write_cs(0),
I2 => Q(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready\(0),
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready\(0),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7FFF800000"
)
port map (
I0 => \gen_no_arbiter.grant_rnw_reg\,
I1 => Q(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \m_atarget_hot_reg[4]\,
I5 => mi_bvalid(4),
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => mi_bvalid(4),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4FFF4F4F400"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \^mi_rvalid\(0),
I2 => \gen_no_arbiter.m_amesg_i_reg[50]\,
I3 => s_axi_rid_i,
I4 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I5 => mi_rmesg(144),
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \^mi_rvalid\(0),
I2 => \gen_axi.read_cnt_reg__0\(4),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt_reg__0\(2),
I5 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF7"
)
port map (
I0 => aa_rready,
I1 => Q(0),
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \gen_axi.read_cnt_reg__0\(7),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => mi_rmesg(144),
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77770003"
)
port map (
I0 => \m_atarget_hot_reg[4]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => \gen_no_arbiter.grant_rnw_reg_0\,
I4 => mi_wready(4),
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => mi_wready(4),
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1A"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \gen_axi.write_cs[1]_i_3_n_0\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABF00"
)
port map (
I0 => write_cs(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => Q(0),
I3 => \^gen_axi.write_cs_reg[1]_0\(0),
I4 => \gen_axi.write_cs[1]_i_3_n_0\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B88888888888888"
)
port map (
I0 => \m_atarget_hot_reg[4]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => Q(0),
I4 => \^mi_awready\(0),
I5 => \m_ready_d_reg[2]_0\,
O => \gen_axi.write_cs[1]_i_3_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCF7FFF7"
)
port map (
I0 => mi_wready(4),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_wready(0),
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A00F0C00A0000C"
)
port map (
I0 => m_axi_arready(1),
I1 => m_axi_arready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => \^mi_arready\(0),
O => \m_ready_d_reg[1]\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000AFC00000A0C"
)
port map (
I0 => \^mi_awready\(0),
I1 => m_axi_awready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_awready(1),
O => \m_ready_d_reg[2]\
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF0A0000C00A00"
)
port map (
I0 => \^mi_rvalid\(0),
I1 => m_axi_rvalid(1),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_axi_rvalid(0),
O => m_valid_i_reg
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FCFDFFFD"
)
port map (
I0 => m_axi_bvalid(0),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_bvalid(2),
I5 => \^m_ready_d_reg[0]_0\,
O => \m_ready_d_reg[0]\
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A00C0000A00C0"
)
port map (
I0 => m_axi_bvalid(1),
I1 => mi_bvalid(4),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bvalid(3),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FCF7FFF7"
)
port map (
I0 => m_axi_wready(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => mi_wready(4),
I5 => \m_atarget_enc_reg[0]_0\,
O => \m_ready_d_reg[1]_0\
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF1000"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(1),
I3 => m_axi_rlast(1),
I4 => \skid_buffer[0]_i_2_n_0\,
I5 => \m_atarget_enc_reg[0]\,
O => \skid_buffer_reg[0]\
);
\skid_buffer[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => mi_rmesg(144),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rlast(0),
O => \skid_buffer[0]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter is
port (
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55550455"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \gen_axi.s_axi_wready_i_reg\,
I2 => \^m_ready_d_reg[1]_0\,
I3 => s_axi_wlast(0),
I4 => \gen_no_arbiter.grant_rnw_reg\,
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000BA00"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_atarget_enc_reg[0]\,
I2 => \gen_no_arbiter.grant_rnw_reg_0\,
I3 => aresetn_d,
I4 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AABA0000"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_atarget_enc_reg[1]\,
I2 => s_axi_wlast(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => aresetn_d,
I5 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => m_ready_d0(0),
I1 => aresetn_d,
I2 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DCFFDFFF"
)
port map (
I0 => m_axi_awready(1),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_awready(0),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4FFF7"
)
port map (
I0 => m_axi_bvalid(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_bvalid(0),
O => \m_ready_d_reg[2]_1\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000AC000000AC"
)
port map (
I0 => m_axi_wready(1),
I1 => m_axi_wready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_wready(2),
O => \^m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0\ is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_14_splitter";
end \zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAAAAAA"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \gen_no_arbiter.m_valid_i_reg\,
I2 => s_axi_rready(0),
I3 => sr_rvalid,
I4 => \m_payload_i_reg[0]\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCDFFFDF"
)
port map (
I0 => m_axi_arready(0),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_arready(1),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aa_grant_rnw : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_grant_any : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice is
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rdata[31]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \skid_buffer[24]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \skid_buffer[29]_i_2\ : label is "soft_lutpair20";
begin
aa_rready <= \^aa_rready\;
m_valid_i_reg_1(1 downto 0) <= \^m_valid_i_reg_1\(1 downto 0);
\s_axi_rdata[31]\(34 downto 0) <= \^s_axi_rdata[31]\(34 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_1\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_1\(0),
Q => \^m_valid_i_reg_1\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(3),
O => m_axi_rready(3)
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_atarget_enc_reg[2]\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[10]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[11]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[12]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[13]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[14]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[15]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[16]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[17]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[18]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[19]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFAFAFACAFACAFA"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \m_payload_i[1]_i_2_n_0\,
I2 => \^aa_rready\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
I5 => m_axi_rresp(2),
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A0CF0000A0C0"
)
port map (
I0 => m_axi_rresp(6),
I1 => m_axi_rresp(4),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(2),
I5 => m_axi_rresp(0),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => m_atarget_enc(1),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[20]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[21]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[22]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[23]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[24]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[25]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[26]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[27]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[28]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[29]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E0EE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"030E0302FFFFFFFF"
)
port map (
I0 => m_axi_rresp(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rresp(5),
I5 => \^aa_rready\,
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F3F7FFF7"
)
port map (
I0 => m_axi_rresp(3),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rresp(7),
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[30]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[31]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[32]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[33]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[34]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[3]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[4]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[5]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[6]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[7]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[8]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[9]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^s_axi_rdata[31]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^s_axi_rdata[31]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^s_axi_rdata[31]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^s_axi_rdata[31]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^s_axi_rdata[31]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^s_axi_rdata[31]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^s_axi_rdata[31]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^s_axi_rdata[31]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^s_axi_rdata[31]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^s_axi_rdata[31]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^s_axi_rdata[31]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^s_axi_rdata[31]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^s_axi_rdata[31]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^s_axi_rdata[31]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^s_axi_rdata[31]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^s_axi_rdata[31]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^s_axi_rdata[31]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^s_axi_rdata[31]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^s_axi_rdata[31]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^s_axi_rdata[31]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^s_axi_rdata[31]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^s_axi_rdata[31]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^s_axi_rdata[31]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^s_axi_rdata[31]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^s_axi_rdata[31]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^s_axi_rdata[31]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^s_axi_rdata[31]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^s_axi_rdata[31]\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^s_axi_rdata[31]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^s_axi_rdata[31]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^s_axi_rdata[31]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^s_axi_rdata[31]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^s_axi_rdata[31]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^s_axi_rdata[31]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^s_axi_rdata[31]\(9),
R => '0'
);
\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF80000000"
)
port map (
I0 => \^s_axi_rdata[31]\(0),
I1 => \^sr_rvalid\,
I2 => s_axi_rready(0),
I3 => m_valid_i,
I4 => aa_grant_rnw,
I5 => m_ready_d(0),
O => m_ready_d0(0)
);
m_valid_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4FFF7"
)
port map (
I0 => m_axi_rvalid(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rvalid(0),
O => m_valid_i_reg_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^sr_rvalid\,
I1 => aa_grant_any,
O => s_axi_rvalid(0)
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C080008"
)
port map (
I0 => m_axi_rlast(0),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rlast(1),
O => \skid_buffer_reg[0]_0\
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(39),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(71),
I5 => \skid_buffer[10]_i_2_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(103),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(7),
O => \skid_buffer[10]_i_2_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(40),
I5 => \skid_buffer[11]_i_2_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(104),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(8),
O => \skid_buffer[11]_i_2_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(41),
I5 => \skid_buffer[12]_i_2_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(105),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(9),
O => \skid_buffer[12]_i_2_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(42),
I5 => \skid_buffer[13]_i_2_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(106),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(10),
O => \skid_buffer[13]_i_2_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(43),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(75),
I5 => \skid_buffer[14]_i_2_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(107),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(11),
O => \skid_buffer[14]_i_2_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(44),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(76),
I5 => \skid_buffer[15]_i_2_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(108),
O => \skid_buffer[15]_i_2_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(45),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(77),
I5 => \skid_buffer[16]_i_2_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[16]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(109),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(13),
O => \skid_buffer[16]_i_2_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(46),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(78),
I5 => \skid_buffer[17]_i_2_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[17]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(110),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(14),
O => \skid_buffer[17]_i_2_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(47),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(79),
I5 => \skid_buffer[18]_i_2_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[18]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(111),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(15),
O => \skid_buffer[18]_i_2_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(48),
I5 => \skid_buffer[19]_i_2_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(112),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(16),
O => \skid_buffer[19]_i_2_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(49),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(81),
I5 => \skid_buffer[20]_i_2_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[20]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(113),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(17),
O => \skid_buffer[20]_i_2_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(50),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(82),
I5 => \skid_buffer[21]_i_2_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[21]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(114),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(18),
O => \skid_buffer[21]_i_2_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(51),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(83),
I5 => \skid_buffer[22]_i_2_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[22]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(115),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(19),
O => \skid_buffer[22]_i_2_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(52),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(84),
I5 => \skid_buffer[23]_i_2_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(116),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(20),
O => \skid_buffer[23]_i_2_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(53),
I5 => \skid_buffer[24]_i_2_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[24]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(117),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(21),
O => \skid_buffer[24]_i_2_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(54),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(86),
I5 => \skid_buffer[25]_i_2_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[25]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(118),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(22),
O => \skid_buffer[25]_i_2_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(55),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(87),
I5 => \skid_buffer[26]_i_2_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[26]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(119),
O => \skid_buffer[26]_i_2_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(56),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(88),
I5 => \skid_buffer[27]_i_2_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(120),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(24),
O => \skid_buffer[27]_i_2_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(57),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(89),
I5 => \skid_buffer[28]_i_2_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(121),
O => \skid_buffer[28]_i_2_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(90),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(58),
I5 => \skid_buffer[29]_i_2_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(122),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(26),
O => \skid_buffer[29]_i_2_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(59),
I5 => \skid_buffer[30]_i_2_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[30]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(123),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(27),
O => \skid_buffer[30]_i_2_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(60),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(92),
I5 => \skid_buffer[31]_i_2_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(124),
O => \skid_buffer[31]_i_2_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(93),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(61),
I5 => \skid_buffer[32]_i_2_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[32]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(125),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(29),
O => \skid_buffer[32]_i_2_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(62),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(94),
I5 => \skid_buffer[33]_i_2_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[33]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(126),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(30),
O => \skid_buffer[33]_i_2_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(63),
I5 => \skid_buffer[34]_i_2_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[34]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(127),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(31),
O => \skid_buffer[34]_i_2_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(32),
I5 => \skid_buffer[3]_i_2_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(96),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(0),
O => \skid_buffer[3]_i_2_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(33),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(65),
I5 => \skid_buffer[4]_i_2_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(97),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(1),
O => \skid_buffer[4]_i_2_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(34),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(66),
I5 => \skid_buffer[5]_i_2_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(98),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(2),
O => \skid_buffer[5]_i_2_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(35),
I5 => \skid_buffer[6]_i_2_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(99),
O => \skid_buffer[6]_i_2_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(36),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(68),
I5 => \skid_buffer[7]_i_2_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(100),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(4),
O => \skid_buffer[7]_i_2_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(37),
I5 => \skid_buffer[8]_i_2_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(101),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(5),
O => \skid_buffer[8]_i_2_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(38),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(70),
I5 => \skid_buffer[9]_i_2_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(102),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(6),
O => \skid_buffer[9]_i_2_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \m_atarget_enc_reg[2]\,
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd : entity is "axi_crossbar_v2_1_14_crossbar_sasd";
end zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal aa_grant_any : STD_LOGIC;
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_10 : STD_LOGIC;
signal addr_arbiter_inst_n_102 : STD_LOGIC;
signal addr_arbiter_inst_n_107 : STD_LOGIC;
signal addr_arbiter_inst_n_11 : STD_LOGIC;
signal addr_arbiter_inst_n_113 : STD_LOGIC;
signal addr_arbiter_inst_n_117 : STD_LOGIC;
signal addr_arbiter_inst_n_12 : STD_LOGIC;
signal addr_arbiter_inst_n_13 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_5 : STD_LOGIC;
signal addr_arbiter_inst_n_6 : STD_LOGIC;
signal addr_arbiter_inst_n_7 : STD_LOGIC;
signal addr_arbiter_inst_n_85 : STD_LOGIC;
signal addr_arbiter_inst_n_86 : STD_LOGIC;
signal addr_arbiter_inst_n_87 : STD_LOGIC;
signal addr_arbiter_inst_n_9 : STD_LOGIC;
signal addr_arbiter_inst_n_94 : STD_LOGIC;
signal addr_arbiter_inst_n_95 : STD_LOGIC;
signal addr_arbiter_inst_n_96 : STD_LOGIC;
signal any_error : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal f_hot2enc_return0 : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_10\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_11\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_9\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_atarget_enc[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_enc[1]_i_1_n_0\ : STD_LOGIC;
signal m_atarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 2 to 2 );
signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_awready : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_39 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rdata[31]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal s_axi_rid_i : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair41";
begin
Q(68 downto 0) <= \^q\(68 downto 0);
\s_axi_rdata[31]\(34 downto 0) <= \^s_axi_rdata[31]\(34 downto 0);
addr_arbiter_inst: entity work.zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd
port map (
D(4) => addr_arbiter_inst_n_10,
D(3) => addr_arbiter_inst_n_11,
D(2) => addr_arbiter_inst_n_12,
D(1) => addr_arbiter_inst_n_13,
D(0) => m_atarget_hot0(0),
E(0) => p_1_in,
Q(1) => reg_slice_r_n_45,
Q(0) => reg_slice_r_n_46,
SR(0) => reset,
aa_grant_any => aa_grant_any,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
f_hot2enc_return0 => f_hot2enc_return0,
\gen_axi.read_cs_reg[0]\ => \gen_decerr.decerr_slave_inst_n_5\,
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_inst_n_6,
\gen_axi.s_axi_awready_i_reg\ => addr_arbiter_inst_n_107,
\gen_axi.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_7\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_11\,
\gen_axi.s_axi_rlast_i_reg\ => addr_arbiter_inst_n_117,
\gen_axi.s_axi_wready_i_reg\ => addr_arbiter_inst_n_87,
\gen_axi.s_axi_wready_i_reg_0\ => addr_arbiter_inst_n_94,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_atarget_enc_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_6,
\m_atarget_enc_reg[1]_1\ => reg_slice_r_n_39,
\m_atarget_enc_reg[2]\(0) => any_error,
\m_atarget_enc_reg[2]_0\ => splitter_ar_n_0,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_5,
\m_atarget_hot_reg[3]\ => addr_arbiter_inst_n_86,
\m_atarget_hot_reg[4]\ => addr_arbiter_inst_n_85,
\m_atarget_hot_reg[4]_0\(4 downto 0) => m_atarget_hot(4 downto 0),
\m_axi_arqos[3]\(68 downto 0) => \^q\(68 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0(2),
m_ready_d0_1(0) => m_ready_d0_0(0),
m_ready_d_0(2 downto 0) => m_ready_d_1(2 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_4,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_102,
\m_ready_d_reg[0]_1\ => addr_arbiter_inst_n_113,
\m_ready_d_reg[1]\ => addr_arbiter_inst_n_5,
\m_ready_d_reg[1]_0\ => addr_arbiter_inst_n_95,
\m_ready_d_reg[1]_1\ => splitter_aw_n_0,
\m_ready_d_reg[2]\ => addr_arbiter_inst_n_96,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_9,
mi_arready(0) => mi_arready(4),
mi_awready(0) => mi_awready(4),
mi_rvalid(0) => mi_rvalid(4),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rid_i => s_axi_rid_i,
s_axi_rready(0) => s_axi_rready(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_7,
sr_rvalid => sr_rvalid,
write_cs(0) => write_cs(1)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave
port map (
Q(0) => m_atarget_hot(4),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_102,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_87,
\gen_no_arbiter.m_amesg_i_reg[50]\ => addr_arbiter_inst_n_117,
\gen_no_arbiter.m_amesg_i_reg[51]\(7 downto 0) => \^q\(51 downto 44),
\gen_no_arbiter.m_valid_i_reg\ => \gen_decerr.decerr_slave_inst_n_9\,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[0]\ => reg_slice_r_n_38,
\m_atarget_enc_reg[0]_0\ => splitter_aw_n_4,
\m_atarget_hot_reg[4]\ => addr_arbiter_inst_n_94,
m_axi_arready(1) => m_axi_arready(3),
m_axi_arready(0) => m_axi_arready(0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rlast(1) => m_axi_rlast(2),
m_axi_rlast(0) => m_axi_rlast(0),
m_axi_rvalid(1) => m_axi_rvalid(3),
m_axi_rvalid(0) => m_axi_rvalid(1),
m_axi_wready(0) => m_axi_wready(2),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_11\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_6,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_107,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_5\,
mi_arready(0) => mi_arready(4),
mi_awready(0) => mi_awready(4),
mi_rvalid(0) => mi_rvalid(4),
s_axi_rid_i => s_axi_rid_i,
\skid_buffer_reg[0]\ => \gen_decerr.decerr_slave_inst_n_4\
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C0E000E0"
)
port map (
I0 => \^q\(28),
I1 => addr_arbiter_inst_n_86,
I2 => aresetn_d,
I3 => addr_arbiter_inst_n_85,
I4 => f_hot2enc_return0,
O => \m_atarget_enc[0]_i_1_n_0\
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aresetn_d,
I1 => f_hot2enc_return0,
O => \m_atarget_enc[1]_i_1_n_0\
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[0]_i_1_n_0\,
Q => m_atarget_enc(0),
R => '0'
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[1]_i_1_n_0\,
Q => m_atarget_enc(1),
R => '0'
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => any_error,
Q => m_atarget_enc(2),
R => reset
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(0),
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_13,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_12,
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_11,
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_10,
Q => m_atarget_hot(4),
R => reset
);
reg_slice_r: entity work.zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice
port map (
E(0) => p_1_in,
Q(3 downto 0) => m_atarget_hot(3 downto 0),
SR(0) => reset,
aa_grant_any => aa_grant_any,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_7,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_9,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_4\,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast(1) => m_axi_rlast(3),
m_axi_rlast(0) => m_axi_rlast(1),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(1) => m_axi_rvalid(2),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_ready_d(0) => m_ready_d(0),
m_ready_d0(0) => m_ready_d0_0(0),
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_39,
m_valid_i_reg_1(1) => reg_slice_r_n_45,
m_valid_i_reg_1(0) => reg_slice_r_n_46,
\s_axi_rdata[31]\(34 downto 0) => \^s_axi_rdata[31]\(34 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
\skid_buffer_reg[0]_0\ => reg_slice_r_n_38,
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1410"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_axi_bresp(4),
I4 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CA000F00CA0000"
)
port map (
I0 => m_axi_bresp(2),
I1 => m_axi_bresp(6),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(0),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1410"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_axi_bresp(5),
I4 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A000C0F0A000C00"
)
port map (
I0 => m_axi_bresp(7),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(1),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
splitter_ar: entity work.\zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0\
port map (
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_4,
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_inst_n_113,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(2 downto 1),
\m_payload_i_reg[0]\(0) => \^s_axi_rdata[31]\(0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0_0(0),
\m_ready_d_reg[1]_0\ => splitter_ar_n_0,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_5,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_wready_i_reg\ => \gen_decerr.decerr_slave_inst_n_9\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_95,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_102,
\gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_0,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_8\,
m_axi_awready(1 downto 0) => m_axi_awready(3 downto 2),
m_axi_bvalid(1) => m_axi_bvalid(2),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_wready(2) => m_axi_wready(3),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0(2),
\m_ready_d_reg[1]_0\ => splitter_aw_n_4,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_96,
\m_ready_d_reg[2]_0\ => splitter_aw_n_5,
\m_ready_d_reg[2]_1\ => splitter_aw_n_6,
s_axi_wlast(0) => s_axi_wlast(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 112 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 112) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlock(3) <= \^m_axi_arlock\(0);
m_axi_arlock(2) <= \^m_axi_arlock\(0);
m_axi_arlock(1) <= \^m_axi_arlock\(0);
m_axi_arlock(0) <= \^m_axi_arlock\(0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 112) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_awburst(7 downto 6) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
m_axi_awcache(15 downto 12) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
m_axi_awid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_arlock\(0);
m_axi_awlock(2) <= \^m_axi_arlock\(0);
m_axi_awlock(1) <= \^m_axi_arlock\(0);
m_axi_awlock(0) <= \^m_axi_arlock\(0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(15 downto 12) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
s_axi_buser(0) <= \<const0>\;
s_axi_rid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd
port map (
Q(68 downto 65) => \^m_axi_arqos\(3 downto 0),
Q(64 downto 61) => \^m_axi_arcache\(3 downto 0),
Q(60 downto 59) => \^m_axi_arburst\(1 downto 0),
Q(58 downto 56) => \^m_axi_arprot\(2 downto 0),
Q(55) => \^m_axi_arlock\(0),
Q(54 downto 52) => \^m_axi_arsize\(2 downto 0),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 28) => \^m_axi_awaddr\(127 downto 112),
Q(27 downto 12) => \^m_axi_araddr\(15 downto 0),
Q(11 downto 0) => \^m_axi_arid\(11 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(34 downto 3) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rdata[31]\(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_xbar_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_xbar_1 : entity is "zqynq_lab_1_design_xbar_1,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_xbar_1 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end zqynq_lab_1_design_xbar_1;
architecture STRUCTURE of zqynq_lab_1_design_xbar_1 is
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => B"000000000000000000000000000000000000000000000000",
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => B"000000000000000000000000000000000000000000000000",
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
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