content stringlengths 1 1.04M ⌀ |
|---|
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-----------------------------------------... |
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-----------------------------------------... |
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-----------------------------------------... |
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-----------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Sep 25 09:53:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
package p is
type t_int_file is file of integer;
type t_int_access is access integer;
type t_access_array is array (0 to 1) of t_int_access;
type t_access_record is record
a : integer;
b : t_int_access;
end record;
constant c1 : t_int_access; -- Error
constant ... |
package p is
type t_int_file is file of integer;
type t_int_access is access integer;
type t_access_array is array (0 to 1) of t_int_access;
type t_access_record is record
a : integer;
b : t_int_access;
end record;
constant c1 : t_int_access; -- Error
constant ... |
package p is
type t_int_file is file of integer;
type t_int_access is access integer;
type t_access_array is array (0 to 1) of t_int_access;
type t_access_record is record
a : integer;
b : t_int_access;
end record;
constant c1 : t_int_access; -- Error
constant ... |
package p is
type t_int_file is file of integer;
type t_int_access is access integer;
type t_access_array is array (0 to 1) of t_int_access;
type t_access_record is record
a : integer;
b : t_int_access;
end record;
constant c1 : t_int_access; -- Error
constant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:44 04/10/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/NexTEST.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Ben... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:44 04/10/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/NexTEST.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Ben... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autoge... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split6 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split6 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major re... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.types_pkg.all;
use work.robot_layer_3_pkg.all;
entity robot_layer_3 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic; ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/29/2014 09:07:43 PM
-- Design Name:
-- Module Name: dat_if_standalone_1bit - testbench
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : IR Remote Shutter release for Canon DSLR - Controller Package
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
----------------------------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:30:26 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "ParamIntf"
-- Project :
-------------------------------------------------------------------------------
-- File : ParamIntf_tb.vhd
-- Author : Johann Glaser
-- Company :
-- Created ... |
-------------------------------------------------------------------------------
-- Title : asynchronous fall-through fifo
-- Author : Gideon Zweijtzer (gideon.zweijtzer@gmail.com)
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Fri Sep 26 21:45:05 2014
-- Host : ECE-411-6 running 64-bit Service Pack... |
library ieee;
use ieee.std_logic_1164.all;
entity bcd_controller is
port(
rst: in std_logic;
clk: in std_logic;
anod_out: out std_logic_vector(3 downto 0);
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed Apr 13 17:20:49 2016
-- Host : Dries007-Arch running 64-bit unknown... |
--Módulo somador simples de duas entradas
--usado para obter pc+4 e tambem para calcular o endereço destino de um branch
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity somador is
generic (DATA_WIDTH : natural := 32);
port (
dataIn1, dataIn2 : in std_logic_vector (DATA_WIDTH - 1 downt... |
--Módulo somador simples de duas entradas
--usado para obter pc+4 e tambem para calcular o endereço destino de um branch
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity somador is
generic (DATA_WIDTH : natural := 32);
port (
dataIn1, dataIn2 : in std_logic_vector (DATA_WIDTH - 1 downt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
----------------------------------------------------------------------------
---- Create Date: 13:06:08 07/28/2010 ----
---- Design Name: lfsr ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- A random number generator based on ... |
library verilog;
use verilog.vl_types.all;
entity FFT_Mag is
port(
clk : in vl_logic;
reset : in vl_logic;
\next\ : in vl_logic;
X0 : in vl_logic_vector(11 downto 0);
X1 : in vl_logic_vector(11 downt... |
library verilog;
use verilog.vl_types.all;
entity FFT_Mag is
port(
clk : in vl_logic;
reset : in vl_logic;
\next\ : in vl_logic;
X0 : in vl_logic_vector(11 downto 0);
X1 : in vl_logic_vector(11 downt... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------------------------------------------
-- VIDEO DELAY - SDRAM Controller
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
-----------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:02:25 10/12/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool vers... |
-------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface
--
-- This component is designed to interface an FT2232H USB chip with two
-- dual-port FIFOs in first-word-fall-through (zero read latency) mode. The
-- FIFOs are used for buffering and (de)serializing data w... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
entity E2 is
end entity;
architecture behav of E2 is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
signal s : a (7 downto 0)(3 downto 0);
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity DFF_PC_tb is
end DFF_PC_tb;
architecture tb of DFF_PC_tb is
component DFF_PC
port( D, CLK, preset, clear: in std_logic;
Q : out std_logic;
Qnot : out std_logic
);
end component;
signal D : std_logic := '0';
signal CLK : std_lo... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
--
-- SpaceWire Receiver
--
-- This entity decodes the sequence of incoming data bits into tokens.
-- Data bits are passed to this entity from the Receiver Front-end
-- in groups of rxchunk bits at a time.
--
-- The bitrate of the incoming SpaceWire signal must be strictly less
-- than rxchunk times the system cl... |
--
-- SpaceWire Receiver
--
-- This entity decodes the sequence of incoming data bits into tokens.
-- Data bits are passed to this entity from the Receiver Front-end
-- in groups of rxchunk bits at a time.
--
-- The bitrate of the incoming SpaceWire signal must be strictly less
-- than rxchunk times the system cl... |
--------------------------------------------------------------------------------
--
-- Creation Date: Sat May 6 16:30:50 GMT+2 2017
-- Creator: Steffen Reith
-- Module Name: Board_Nexys4 - Behavioral
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
-- Remark: The pmod pins a... |
-- -------------------------------------------------------------
--
-- Entity Declaration for vor
--
-- Generated
-- by: wig
-- on: Wed Nov 30 08:56:01 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-e.vhd,v ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_... |
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions o... |
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Rxunit.vhd
-- Author : Philippe CARTON
-- (philippe.carton2@libertysurf.fr)
-- Or... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
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