content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Eth_TestSig_Cfg.all;
entity ethrx_input is
generic(
HEAD_AWIDTH : natural := 5; -- ½ÓÊÕ¶ÓÁеØÖ·¿í¶È 2^5 = 32 ×Ö½Ú
BUFF_AWIDTH : natural := 16 -- BUFF16λµØÖ·Ïß
);
port(
-- ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig... |
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
library verilog;
use verilog.vl_types.all;
entity SeqEightBitAdder is
port(
SW : in vl_logic_vector(15 downto 0);
KEY0 : in vl_logic;
LEDR : out vl_logic_vector(8 downto 0)
);
end SeqEightBitAdder;
|
architecture rtl of fifo is
begin
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
end process;
end architecture rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Display4 is
generic(
CLOCK_FREQUENCY: positive := 32_000_000;
DIGIT_COUNT: positive := 4
);
port(
-- main clock
clock: in std_logic;
-- d... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF h... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF h... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF h... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF h... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
use std.textio.all;
entity memory is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in pctype;
wd : in STD_LOGIC_VECTOR (7 downto 0)... |
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
p1: process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC buffers Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-17-10
-- Platform : F... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
architecture base of blader is
begin
-- This file is the basic skeleton of what the bladeRF FPGA
-- should drive for outputs. All of the outputs are defined
-- here.
--
-- Use this file as a template for new targets.... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrCuenta8bits_conFin.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it unde... |
-------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
------------------------------------------------... |
--------------------------------------------------------------------------------
--|
--| Filename : cntr_bhv
--| Author : R. Friesenhahn
--| Origin Date : 20130906
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--|
--|
--------------------------------... |
library verilog;
use verilog.vl_types.all;
entity tlb is
generic(
LRU_TIMER_N : integer := 10
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iRD_REQ : in vl_logic;
iRD_ADDR ... |
--
-- File Name: TextUtilPkg.vhd
-- Design Unit Name: TextUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Shared Utilities for handling text files
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:41 05/06/2017
-- Design Name:
-- Module Name: Mux_reg1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library ieee;
use ieee.std_logic_1164.all;
entity bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of bar_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a xor b;
y <= not (a and b);
... |
library ieee;
use ieee.std_logic_1164.all;
entity bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of bar_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a xor b;
y <= not (a and b);
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:37:32 07/10/2014
-- Design Name:
-- Module Name:
-- Project Name: CPU_1st_edition
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Tar... |
---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- l... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY input_data_demux IS
PORT(
ADDR, DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON, NOTE_OFF: out std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
WAV_SELECT : out std_logi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- a goes through when s='1', b with s='0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
A: In std_logic_vector(NBIT-1 downto 0);
B: In std_logic_vector(NBIT-1 downto 0);
S: In std_logic;
Y: Out std_logic_vector(NB... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------... |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and ... |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and ... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:51 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: channel_error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard,... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:51 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: channel_error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard,... |
-------------------------------------------------------------------------------
-- plb_v46_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_04_a;
use plb_v46_v1_04_a.a... |
------------------------------------------------------------------------
-- One element fifo
--
-- Copyright (c) 2014-2014 Rinat Zakirov
-- SPDX-License-Identifier: BSL-1.0
--
------------------------------------------------------------------------
NOT TESTED
library ieee;
use ieee.std_logic_1164.all;
e... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:38 10/17/2014
-- Design Name:
-- Module Name: fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when inpu... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity pintoggler is
port (
clk_50 : in std_logic;
data : out std_logic_vector(15 downto 0);
addr : out std_logic_vector(15 downto 0);
div : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of pintoggler is
signal counter : integer := 0;
... |
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
ENTITY debouncer IS
PORT (
Clk : IN STD_LOGIC;
SW : IN STD_LOGIC; -- sw input
Vsync : in std_logic;
SWout : OUT STD_LOGIC;
Aclr : out std_logic
);
END debouncer;
ARCHITECTURE cle... |
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--********************************************************************************... |
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--********************************************************************************... |
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--********************************************************************************... |
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--********************************************************************************... |
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