content stringlengths 1 1.04M ⌀ |
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Eth_TestSig_Cfg.all;
entity ethrx_input is
generic(
HEAD_AWIDTH : natural := 5; -- ½ÓÊÕ¶ÓÁеØÖ·¿í¶È 2^5 = 32 ×Ö½Ú
BUFF_AWIDTH : natural := 16 -- BUFF16λµØÖ·Ïß
);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic; -- FPGAʱÖÓ
reset : in std_logic;
rxclk : in std_logic; -- MIIÊä³öʱÖÓ
rxd : in std_logic_vector(3 downto 0); -- ²¢¿ÚÊäÈëÊý¾Ý£¬4bitΪµ¥Î»£¨nipple£©
rxdv : in std_logic; -- ÔÚRXDV='1'µÄÇé¿öϼì²âµ½"5..5D"£¬±íʾһ¸öÒÔÌ«°üµÄ¿ªÊ¼
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0); --ÿһ¸ö°ü´Ó0¿ªÊ¼µÝÔö¼ÆÊý
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic; -- ָʾCRC½á¹û£¬'1'±íʾÕýÈ·£¬'0'±íʾ²»ÕýÈ·
buff_wren : out std_logic;
buff_waddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_wdata : out std_logic_vector(7 downto 0) -- ÒÔÌ«°üÊý¾Ý°´×Ö½Úд³ö£¬Ð´µØÖ·´ÓÉÏ´ÎдµØÖ·µÄĩβµÝÔö£¬°üº¬ÒÔÌ«°üÍ·
);
end ethrx_input;
architecture arch_ethrx_input of ethrx_input is
component fifo_async
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async use entity WORK.fifo_async(fast_read);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
component crcrom
port(
addr : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
constant INFO_LENGTH : natural := 4;
constant HEAD_LENGTH : natural := 2 ** HEAD_AWIDTH - INFO_LENGTH;
signal rxdv_buf : std_logic;
signal rxd_buf : std_logic_vector(3 downto 0);
signal d_ext : std_logic_vector(4 downto 0);
signal rxdv_int : std_logic;
signal rxd_int : std_logic_vector(3 downto 0);
signal d_int : std_logic_vector(4 downto 0);
signal ce : std_logic;
signal rd_ena : std_logic;
signal empty : std_logic;
signal rx_state : std_logic_vector(1 downto 0);
signal nibble_cnt : std_logic_vector(11 downto 0);
signal rxd_int_d1 : std_logic_vector(3 downto 0);
signal rxd_int_d2 : std_logic_vector(3 downto 0);
signal byte_data : std_logic_vector(7 downto 0);
signal buff_wren_buf : std_logic;
signal buff_waddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(3 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(3 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal crc_flag : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_ena : std_logic;
signal start_addr : std_logic_vector(15 downto 0);
signal length : std_logic_vector(15 downto 0);
signal head_wren_buf : std_logic;
signal head_waddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wr_block_buf: std_logic;
signal rxclk_temp : std_logic;
signal localtime_locked_reg: std_logic;
begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if info_ena = '1' then
-- test_crc(0) <= crc_flag;
-- test_crc(1) <= crc_reg(2);
-- test_crc(2) <= crc_reg(4);
-- test_crc(3) <= crc_reg(8);
-- end if;
-- end if;
-- end process;
p_mii_din : process(rxclk) -- MII->ETH-RX ÊäÈëÊý¾Ý»º´æ
begin
if rising_edge(rxclk) then
-- if falling_edge(rxclk) then
rxdv_buf <= rxdv;
rxd_buf <= rxd;
end if;
end process;
-- rxclk_temp <= not rxclk;
u_din_sync : fifo_async
generic map(
DEPTH => 4,
AWIDTH => 2,
DWIDTH => 5,
RAM_TYPE => "DIS_RAM")
port map(
reset => reset,
clr => '0',
clka => rxclk,
-- clka => rxclk_temp,
wea => '1',
dia => d_ext,
clkb => clk,
rdb => rd_ena,
dob => d_int,
empty => empty,
full => open,
dn => open
);
d_ext <= rxdv_buf & rxd_buf;
rxdv_int <= d_int(4);
rxd_int <= d_int(3 downto 0);
rd_ena <= not empty;
p_ce : process(clk)
begin
if rising_edge(clk) then
ce <= rd_ena;
end if;
end process;
------------------------------------------------------------------------------
p_state_machine : process(clk, reset)
begin
if reset = '1' then
rx_state <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
case rx_state is
when "00" =>
if rxdv_int = '1' and rxd_int = "0101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
when "01" =>
if rxdv_int = '1' then
if rxd_int = "1101" then
rx_state <= "10";
elsif rxd_int = "0101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
else
rx_state <= "00";
end if;
when "10" =>
if rxdv_int = '1' then
rx_state <= "11";
end if;
when "11" =>
if rxdv_int = '0' then
rx_state <= "00";
end if;
when others =>
NULL;
end case;
end if;
end if;
end process;
p_nibble_cnt : process(clk, reset) -- nibble count
begin
if reset = '1' then
nibble_cnt <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "00" then
nibble_cnt <= (others => '0');
elsif rx_state = "11" then
nibble_cnt <= nibble_cnt + 1;
end if;
end if;
end if;
end process;
p_s2p : process(clk, reset)
begin
if reset = '1' then
rxd_int_d1 <= (others => '0');
rxd_int_d2 <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
rxd_int_d1 <= rxd_int;
rxd_int_d2 <= rxd_int_d1;
end if;
end if;
end process;
byte_data <= rxd_int_d1 & rxd_int_d2;
------------------------------------------------------------------------------
p_recvtime : process(clk, reset)
begin
if reset = '1' then
recvtime(31 downto 0) <= (others => '0');
recvtime_valid <= '0';
elsif rising_edge(clk) then
if ce = '1' then
case nibble_cnt is
when X"01B" => recvtime(27 downto 24) <= rxd_int;
when X"01c" => recvtime(31 downto 28) <= rxd_int;
when X"01d" => recvtime(19 downto 16) <= rxd_int;
when X"01e" => recvtime(23 downto 20) <= rxd_int;
when X"01f" => recvtime(11 downto 8) <= rxd_int;
when X"020" => recvtime(15 downto 12) <= rxd_int;
when X"021" => recvtime(3 downto 0) <= rxd_int;
when X"022" => recvtime(7 downto 4) <= rxd_int;
when X"023" => recvtime_valid <= '1';
when others => recvtime_valid <= '0';
end case;
end if;
end if;
end process;
p_localtime_locked : process(clk, reset)
begin
if reset = '1' then
localtime_locked_reg <= '0';
elsif rising_edge(clk) then
if ce = '1' and rx_state = "10" and localtime_locked_reg = '0' then
localtime_locked_reg <= '1';
elsif localtime_locked_reg = '1' then
localtime_locked_reg <= '0';
end if;
end if;
end process;
localtime_locked <= localtime_locked_reg;
------------------------------------------------------------------------------
p_buff_wren : process(clk, reset)
begin
if reset = '1' then
buff_wren_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if nibble_cnt(0) = '1' and rx_state = "11" then -- 2nibbleдʹÄÜ£¿
buff_wren_buf <= '1';
else
buff_wren_buf <= '0';
end if;
end if;
end if;
end process;
p_buff_waddr : process(clk, reset)
begin
if reset = '1' then
buff_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if buff_wren_buf = '1' then
buff_waddr_buf <= buff_waddr_buf + 1; -- buffer address ++
end if;
end if;
end if;
end process;
p_buff_wdata : process(clk, reset)
begin
if reset = '1' then
buff_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
buff_wdata <= byte_data;
end if;
end if;
end process;
buff_wren <= buff_wren_buf and ce;
buff_waddr <= buff_waddr_buf;
------------------------------------------------------------------------------
u_crc_rom : CRCRom
port map(
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 28);
p_calc_crc : process(clk, reset)
begin
if reset = '1' then
crc_din <= (others => '0');
crc_reg <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if nibble_cnt < 7 then
crc_din <= not (rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3));
else
crc_din <= rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3);
end if;
if rx_state = "10" then
crc_reg <= (others => '0');
elsif rx_state = "11" then
crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
end if;
end if;
end if;
end process;
p_crc_flag : process(clk, reset)
begin
if reset = '1' then
crc_flag <= '0';
g_Test_EthRec_CRCFlag <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "00" and crc_reg = X"FFFFFFFF" then
crc_flag <= '1';
elsif rx_state = "10" then
crc_flag <= '0';
end if;
end if;
g_Test_EthRec_CRCFlag <= crc_flag;
end if;
end process;
------------------------------------------------------------------------------
p_start_addr : process(clk, reset)
begin
if reset = '1' then
start_addr <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "10" then
start_addr <= EXT(buff_waddr_buf, 16); -- °üÀ¨CRCµØÖ·
end if;
end if;
end if;
end process;
p_length : process(clk, reset)
begin
if reset = '1' then
length <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "11" and rxdv_int = '0' then
length <= "00000" & nibble_cnt(11 downto 1) - 3; -- Êý¾Ý³¤¶È£¬³ýµô4Bytes CRCУÑé
end if;
end if;
end if;
end process;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "11" and rxdv_int = '0' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
p_head_wren : process(clk, reset)
begin
if reset = '1' then
head_wren_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if (nibble_cnt(0) = '1' and rx_state = "11" and rxdv_int = '1' and nibble_cnt(11 downto 1) < HEAD_LENGTH) or info_ena = '1' then -- Ç°32¸ö×Ö½Úдʱ£¬ÒÔ¼°×îºóдµØÖ·Ó볤¶È4×Ö½ÚʱΪ1
head_wren_buf <= '1';
else
head_wren_buf <= '0';
end if;
end if;
end if;
end process;
p_head_waddr : process(clk, reset)
begin
if reset = '1' then
head_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "10" then
head_waddr_buf <= conv_std_logic_vector(INFO_LENGTH, HEAD_AWIDTH);
elsif rx_state = "11" and rxdv_int = '0' then
head_waddr_buf <= conv_std_logic_vector(0, HEAD_AWIDTH);
elsif head_wren_buf = '1' then
head_waddr_buf <= head_waddr_buf + 1;
end if;
end if;
end if;
end process;
p_head_wdata : process(clk, reset)
begin
if reset = '1' then
head_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 => head_wdata <= length(7 downto 0);
when 1 => head_wdata <= length(15 downto 8);
when 2 => head_wdata <= start_addr(7 downto 0);
when 3 => head_wdata <= start_addr(15 downto 8);
when others => null;
end case;
else
head_wdata <= byte_data;
end if;
end if;
end if;
end process;
head_wren <= head_wren_buf and ce;
head_waddr <= head_waddr_buf;
p_head_wr_block : process(clk, reset)
begin
if reset = '1' then
head_wr_block_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if info_cnt = INFO_LENGTH and crc_flag = '1' then -- crcУÑéÕýÈ·
head_wr_block_buf <= '1';
else
head_wr_block_buf <= '0';
end if;
end if;
end if;
end process;
head_wr_block <= head_wr_block_buf and ce; -- crcУÑéÖ¸Õë
end arch_ethrx_input;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: mde_tests-c.vhd,v 1.1 2004/04/06 10:50:33 wig Exp $
-- $Date: 2004/04/06 10:50:33 $
-- $Log: mde_tests-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:33 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
-- Start of Generated Configuration inst_c_e_rtl_conf / inst_c_e
--
configuration inst_c_e_rtl_conf of inst_c_e is
for rtl
-- Generated Configuration
end for;
end inst_c_e_rtl_conf;
--
-- End of Generated Configuration inst_c_e_rtl_conf
--
--
-- Start of Generated Configuration inst_d_e_rtl_conf / inst_d_e
--
configuration inst_d_e_rtl_conf of inst_d_e is
for rtl
-- Generated Configuration
end for;
end inst_d_e_rtl_conf;
--
-- End of Generated Configuration inst_d_e_rtl_conf
--
--
-- Start of Generated Configuration inst_e_e_rtl_conf / inst_e_e
--
configuration inst_e_e_rtl_conf of inst_e_e is
for rtl
-- Generated Configuration
for inst_ea : inst_ea_e
use configuration work.inst_ea_e_rtl_conf;
end for;
for inst_eb : inst_eb_e
use configuration work.inst_eb_e_rtl_conf;
end for;
for inst_ec : inst_ec_e
use configuration work.inst_ec_e_rtl_conf;
end for;
for inst_ed : inst_ed_e
use configuration work.inst_ed_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ee : inst_ee_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ee_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ef : inst_ef_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ef_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_eg : inst_eg_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eg_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_e_e_rtl_conf;
--
-- End of Generated Configuration inst_e_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ea_e_rtl_conf / inst_ea_e
--
configuration inst_ea_e_rtl_conf of inst_ea_e is
for rtl
-- Generated Configuration
for inst_eaa : inst_eaa_e
use configuration work.inst_eaa_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_eab : inst_eab_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eab_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_eac : inst_eac_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eac_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ea_e_rtl_conf;
--
-- End of Generated Configuration inst_ea_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eaa_e_rtl_conf / inst_eaa_e
--
configuration inst_eaa_e_rtl_conf of inst_eaa_e is
for rtl
-- Generated Configuration
end for;
end inst_eaa_e_rtl_conf;
--
-- End of Generated Configuration inst_eaa_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eab_e_rtl_conf / inst_eab_e
--
configuration inst_eab_e_rtl_conf of inst_eab_e is
for rtl
-- Generated Configuration
end for;
end inst_eab_e_rtl_conf;
--
-- End of Generated Configuration inst_eab_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eac_e_rtl_conf / inst_eac_e
--
configuration inst_eac_e_rtl_conf of inst_eac_e is
for rtl
-- Generated Configuration
end for;
end inst_eac_e_rtl_conf;
--
-- End of Generated Configuration inst_eac_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eb_e_rtl_conf / inst_eb_e
--
configuration inst_eb_e_rtl_conf of inst_eb_e is
for rtl
-- Generated Configuration
for inst_eba : inst_eba_e
use configuration work.inst_eba_e_rtl_conf;
end for;
for inst_ebb : inst_ebb_e
use configuration work.inst_ebb_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ebc : inst_ebc_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ebc_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_eb_e_rtl_conf;
--
-- End of Generated Configuration inst_eb_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eba_e_rtl_conf / inst_eba_e
--
configuration inst_eba_e_rtl_conf of inst_eba_e is
for rtl
-- Generated Configuration
end for;
end inst_eba_e_rtl_conf;
--
-- End of Generated Configuration inst_eba_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ebb_e_rtl_conf / inst_ebb_e
--
configuration inst_ebb_e_rtl_conf of inst_ebb_e is
for rtl
-- Generated Configuration
end for;
end inst_ebb_e_rtl_conf;
--
-- End of Generated Configuration inst_ebb_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ebc_e_rtl_conf / inst_ebc_e
--
configuration inst_ebc_e_rtl_conf of inst_ebc_e is
for rtl
-- Generated Configuration
end for;
end inst_ebc_e_rtl_conf;
--
-- End of Generated Configuration inst_ebc_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ec_e_rtl_conf / inst_ec_e
--
configuration inst_ec_e_rtl_conf of inst_ec_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eca : inst_eca_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eca_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecb : inst_ecb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecc : inst_ecc_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecc_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ec_e_rtl_conf;
--
-- End of Generated Configuration inst_ec_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eca_e_rtl_conf / inst_eca_e
--
configuration inst_eca_e_rtl_conf of inst_eca_e is
for rtl
-- Generated Configuration
end for;
end inst_eca_e_rtl_conf;
--
-- End of Generated Configuration inst_eca_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ecb_e_rtl_conf / inst_ecb_e
--
configuration inst_ecb_e_rtl_conf of inst_ecb_e is
for rtl
-- Generated Configuration
end for;
end inst_ecb_e_rtl_conf;
--
-- End of Generated Configuration inst_ecb_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ecc_e_rtl_conf / inst_ecc_e
--
configuration inst_ecc_e_rtl_conf of inst_ecc_e is
for rtl
-- Generated Configuration
end for;
end inst_ecc_e_rtl_conf;
--
-- End of Generated Configuration inst_ecc_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ed_e_rtl_conf / inst_ed_e
--
configuration inst_ed_e_rtl_conf of inst_ed_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eda : inst_eda_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eda_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_edb : inst_edb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_edb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ed_e_rtl_conf;
--
-- End of Generated Configuration inst_ed_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eda_e_rtl_conf / inst_eda_e
--
configuration inst_eda_e_rtl_conf of inst_eda_e is
for rtl
-- Generated Configuration
end for;
end inst_eda_e_rtl_conf;
--
-- End of Generated Configuration inst_eda_e_rtl_conf
--
--
-- Start of Generated Configuration inst_edb_e_rtl_conf / inst_edb_e
--
configuration inst_edb_e_rtl_conf of inst_edb_e is
for rtl
-- Generated Configuration
end for;
end inst_edb_e_rtl_conf;
--
-- End of Generated Configuration inst_edb_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ee_e_rtl_conf / inst_ee_e
--
configuration inst_ee_e_rtl_conf of inst_ee_e is
for rtl
-- Generated Configuration
end for;
end inst_ee_e_rtl_conf;
--
-- End of Generated Configuration inst_ee_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ef_e_rtl_conf / inst_ef_e
--
configuration inst_ef_e_rtl_conf of inst_ef_e is
for rtl
-- Generated Configuration
end for;
end inst_ef_e_rtl_conf;
--
-- End of Generated Configuration inst_ef_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eg_e_rtl_conf / inst_eg_e
--
configuration inst_eg_e_rtl_conf of inst_eg_e is
for rtl
-- Generated Configuration
end for;
end inst_eg_e_rtl_conf;
--
-- End of Generated Configuration inst_eg_e_rtl_conf
--
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
for inst_c : inst_c_e
use configuration work.inst_c_e_rtl_conf;
end for;
for inst_d : inst_d_e
use configuration work.inst_d_e_rtl_conf;
end for;
for inst_e : inst_e_e
use configuration work.inst_e_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
entity repro2 is
end;
architecture behav of repro2 is
function zeros (a, b : bit_vector) return bit_vector is
begin
if a'length = 1 then
return "0";
end if;
end;
begin
end behav;
|
library verilog;
use verilog.vl_types.all;
entity SeqEightBitAdder is
port(
SW : in vl_logic_vector(15 downto 0);
KEY0 : in vl_logic;
LEDR : out vl_logic_vector(8 downto 0)
);
end SeqEightBitAdder;
|
architecture rtl of fifo is
begin
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
end process;
end architecture rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:StackPointer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_StackPointer_0_0 IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_StackPointer_0_0;
ARCHITECTURE RAT_StackPointer_0_0_arch OF RAT_StackPointer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT StackPointer IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT StackPointer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "StackPointer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_StackPointer_0_0_arch : ARCHITECTURE IS "RAT_StackPointer_0_0,StackPointer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "RAT_StackPointer_0_0,StackPointer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=StackPointer,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : StackPointer
PORT MAP (
DATA => DATA,
RST => RST,
LD => LD,
INCR => INCR,
DECR => DECR,
CLK => CLK,
DOUT => DOUT
);
END RAT_StackPointer_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00761pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00761pkg;
use work.c01s01b01x01p05n02i00761pkg.ALL;
ENTITY c01s01b01x01p05n02i00761ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen70 : boolean_vector_st :=(others => true);
Vgen71 : severity_level_vector_st :=(others => note);
Vgen72 : integer_vector_st :=(others => 3);
Vgen73 : real_vector_st :=(others => 3.0);
Vgen74 : time_vector_st :=(others => 3 ns);
Vgen75 : natural_vector_st :=(others => 1);
Vgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00761ent;
ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00761"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00761arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00761pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00761pkg;
use work.c01s01b01x01p05n02i00761pkg.ALL;
ENTITY c01s01b01x01p05n02i00761ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen70 : boolean_vector_st :=(others => true);
Vgen71 : severity_level_vector_st :=(others => note);
Vgen72 : integer_vector_st :=(others => 3);
Vgen73 : real_vector_st :=(others => 3.0);
Vgen74 : time_vector_st :=(others => 3 ns);
Vgen75 : natural_vector_st :=(others => 1);
Vgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00761ent;
ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00761"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00761arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00761pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00761pkg;
use work.c01s01b01x01p05n02i00761pkg.ALL;
ENTITY c01s01b01x01p05n02i00761ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen70 : boolean_vector_st :=(others => true);
Vgen71 : severity_level_vector_st :=(others => note);
Vgen72 : integer_vector_st :=(others => 3);
Vgen73 : real_vector_st :=(others => 3.0);
Vgen74 : time_vector_st :=(others => 3 ns);
Vgen75 : natural_vector_st :=(others => 1);
Vgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00761ent;
ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00761"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00761arch;
|
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Display4 is
generic(
CLOCK_FREQUENCY: positive := 32_000_000;
DIGIT_COUNT: positive := 4
);
port(
-- main clock
clock: in std_logic;
-- digit data, decimal point input, and write enable flag
data_write_enable: in std_logic;
data: in std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0);
dps: in std_logic_vector(DIGIT_COUNT - 1 downto 0);
-- display and selection output
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(DIGIT_COUNT - 1 downto 0)
);
end Display4;
architecture behavioral of Display4 is
-- component to decode nibble to 7-segment display
component SevenSegment is
port(
clock: in std_logic;
num: in std_logic_vector(3 downto 0);
segments: out std_logic_vector(6 downto 0)
);
end component;
-- timer component that fires at a regular interval
component Timer is
generic(
CLOCK_FREQUENCY: positive;
TIMER_FREQUENCY: positive
);
port(
clock: in std_logic;
reset: in std_logic;
tick: out std_logic
);
end component;
-- registers for digit data and decimal points
signal digit_data_register: std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0) := (others => '0');
signal decimal_points_register: std_logic_vector(DIGIT_COUNT - 1 downto 0) := (others => '0');
-- signal indicating when the timer has expired
signal advance_tick: std_logic := '0';
-- the current digit index and the digit's value
signal current_value: std_logic_vector(3 downto 0) := "0000";
signal digit_index: integer range 0 to DIGIT_COUNT - 1;
begin
-- decode nibble to 7-segment display
ss: SevenSegment
port map(
clock => clock,
num => current_value,
segments => segments
);
-- timer used to time multiplex the digits in the display
advance_timer: Timer
generic map(
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMER_FREQUENCY => 1000 * (DIGIT_COUNT + 1)
)
port map(
clock => clock,
reset => '0',
tick => advance_tick
);
-- possibly update digit data and decimal point registers
set_registers: process(clock, data_write_enable)
begin
if clock'event and clock = '1' then
if data_write_enable = '1' then
digit_data_register <= data;
decimal_points_register <= dps;
end if;
end if;
end process;
-- update currently active digit
update_digit_index: process(clock)
begin
if clock'event and clock = '1' then
if advance_tick = '1' then
digit_index <= digit_index + 1;
end if;
end if;
end process;
-- update current value based on current digit index
update_current_value: process(clock, digit_index)
variable top: integer;
begin
if clock'event and clock = '1' then
-- digits are numbered left-to-right, but we need them right-to-left
-- calculate segment offsets based on (corrected) digit index
top := DIGIT_COUNT * ((DIGIT_COUNT - 1) - digit_index) + 3;
-- grab slice for the current digit
current_value <= digit_data_register(top downto top - 3);
end if;
end process;
-- activate current digit on display
activate_digit: process(clock, digit_index)
begin
-- TODO: use generic mux which will probably require an enable signal as well
if clock'event and clock = '1' then
case digit_index is
when 0 => sel <= "0001";
when 1 => sel <= "0010";
when 2 => sel <= "0100";
when 3 => sel <= "1000";
when others => sel <= "0000";
end case;
end if;
end process;
-- activate decimal point for current digit
activate_decimal_point: process(clock, digit_index)
begin
if clock'event and clock = '1' then
dp <= not decimal_points_register(digit_index);
end if;
end process;
end behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
use std.textio.all;
entity memory is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in pctype;
wd : in STD_LOGIC_VECTOR (7 downto 0);
d1 : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC);
end memory;
architecture Behavioral of memory is
type memtype is array(0 to 2**INST_MEM_SIZE-1) of std_logic_vector(7 downto 0);
impure function init_mem(mif_file_name : in string) return memtype is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(7 downto 0);
variable temp_mem : memtype;
variable i : integer := 0;
begin
for j in 0 to memtype'length-1 loop
if not endfile(mif_file) then
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
else
temp_mem(j) := (others => '0');
end if;
end loop;
return temp_mem;
end function;
signal mem : memtype := init_mem(CONTENTS);
begin
process(clk, we, a1, mem)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(a1))) <= wd;
end if;
d1 <= mem(to_integer(unsigned(a1)));
end if;
end process;
end Behavioral;
|
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
p1: process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc65.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p02n01i00065ent IS
END c04s03b01x02p02n01i00065ent;
ARCHITECTURE c04s03b01x02p02n01i00065arch OF c04s03b01x02p02n01i00065ent IS
signal S1 Integer:= 10 ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b01x02p02n01i00065 - Missing colon."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p02n01i00065arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc65.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p02n01i00065ent IS
END c04s03b01x02p02n01i00065ent;
ARCHITECTURE c04s03b01x02p02n01i00065arch OF c04s03b01x02p02n01i00065ent IS
signal S1 Integer:= 10 ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b01x02p02n01i00065 - Missing colon."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p02n01i00065arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc65.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p02n01i00065ent IS
END c04s03b01x02p02n01i00065ent;
ARCHITECTURE c04s03b01x02p02n01i00065arch OF c04s03b01x02p02n01i00065ent IS
signal S1 Integer:= 10 ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b01x02p02n01i00065 - Missing colon."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p02n01i00065arch;
|
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC buffers Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-17-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: ADC differential buffers for clock and data.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-12 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
entity fmc_adc_buf is
generic
(
g_with_clk_single_ended : boolean := false;
g_with_data_single_ended : boolean := false;
g_with_data_sdr : boolean := false
);
port
(
-----------------------------
-- External ports
-----------------------------
-- ADC differential clocks. One clock per ADC channel
adc_clk0_p_i : in std_logic := '0';
adc_clk0_n_i : in std_logic := '0';
adc_clk1_p_i : in std_logic := '0';
adc_clk1_n_i : in std_logic := '0';
adc_clk2_p_i : in std_logic := '0';
adc_clk2_n_i : in std_logic := '0';
adc_clk3_p_i : in std_logic := '0';
adc_clk3_n_i : in std_logic := '0';
-- ADC single ended clocks. One clock per ADC channel
adc_clk0_i : in std_logic := '0';
adc_clk1_i : in std_logic := '0';
adc_clk2_i : in std_logic := '0';
adc_clk3_i : in std_logic := '0';
-- Differential ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch0_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
-- Single ended ADC data channels.
adc_data_ch0_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
-- Output clocks
adc_clk0_o : out std_logic;
adc_clk1_o : out std_logic;
adc_clk2_o : out std_logic;
adc_clk3_o : out std_logic;
-- Output data
adc_data_ch0_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch1_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch2_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch3_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0)
);
end fmc_adc_buf;
architecture rtl of fmc_adc_buf is
-- Number of ADC input pins. This is differente for SDR or DDR ADCs.
constant c_num_in_adc_pins : natural := f_num_adc_pins(g_with_data_sdr);
signal adc_clk0_p_t : std_logic;
signal adc_clk0_n_t : std_logic;
signal adc_clk1_p_t : std_logic;
signal adc_clk1_n_t : std_logic;
signal adc_clk2_p_t : std_logic;
signal adc_clk2_n_t : std_logic;
signal adc_clk3_p_t : std_logic;
signal adc_clk3_n_t : std_logic;
signal adc_data_ch0_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch0_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch1_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch1_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch2_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch2_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch3_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch3_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
begin
-- Clock Input
gen_with_input_clk_single_ended : if (g_with_clk_single_ended) generate
adc_clk0_p_t <= adc_clk0_i;
adc_clk1_p_t <= adc_clk1_i;
adc_clk2_p_t <= adc_clk2_i;
adc_clk3_p_t <= adc_clk3_i;
end generate;
gen_without_input_clk_single_ended : if (not g_with_clk_single_ended) generate
adc_clk0_p_t <= adc_clk0_p_i;
adc_clk0_n_t <= adc_clk0_n_i;
adc_clk1_p_t <= adc_clk1_p_i;
adc_clk1_n_t <= adc_clk1_n_i;
adc_clk2_p_t <= adc_clk2_p_i;
adc_clk2_n_t <= adc_clk2_n_i;
adc_clk3_p_t <= adc_clk3_p_i;
adc_clk3_n_t <= adc_clk3_n_i;
end generate;
-- Data Input
gen_with_input_data_single_ended : if (g_with_data_single_ended) generate
adc_data_ch0_p_t <= adc_data_ch0_i;
adc_data_ch1_p_t <= adc_data_ch1_i;
adc_data_ch2_p_t <= adc_data_ch2_i;
adc_data_ch3_p_t <= adc_data_ch3_i;
end generate;
gen_without_input_data_single_ended : if (not g_with_data_single_ended) generate
adc_data_ch0_p_t <= adc_data_ch0_p_i;
adc_data_ch0_n_t <= adc_data_ch0_n_i;
adc_data_ch1_p_t <= adc_data_ch1_p_i;
adc_data_ch1_n_t <= adc_data_ch1_n_i;
adc_data_ch2_p_t <= adc_data_ch2_p_i;
adc_data_ch2_n_t <= adc_data_ch2_n_i;
adc_data_ch3_p_t <= adc_data_ch3_p_i;
adc_data_ch3_n_t <= adc_data_ch3_n_i;
end generate;
-----------------------------
-- ADC clock signal datapath
-----------------------------
gen_with_clk_single_ended : if (g_with_clk_single_ended) generate
cmp_ibuf_adc_clk0 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk0_p_t,
o => adc_clk0_o
);
cmp_ibuf_adc_clk1 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk1_p_t,
o => adc_clk1_o
);
cmp_ibuf_adc_clk2 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk2_p_t,
o => adc_clk2_o
);
cmp_ibuf_adc_clk3 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk3_p_t,
o => adc_clk3_o
);
end generate;
-- An IBUGDS intructs the mapper to use the glabal clock nets
--(GCLK pins). Therefore, it gives an error for the following
-- clock topology components, like: BUFIO, BUFR and IODELAY
gen_with_clk_diff : if (not g_with_clk_single_ended) generate
cmp_ibufds_adc_clk0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk0_p_t,
ib => adc_clk0_n_t,
o => adc_clk0_o
);
cmp_ibufds_adc_clk1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk1_p_t,
ib => adc_clk1_n_t,
o => adc_clk1_o
);
cmp_ibufds_adc_clk2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk2_p_t,
ib => adc_clk2_n_t,
o => adc_clk2_o
);
cmp_ibufds_adc_clk3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk3_p_t,
ib => adc_clk3_n_t,
o => adc_clk3_o
);
end generate;
-----------------------------
-- ADC data signal datapath
-----------------------------
gen_with_data_single_ended : if (g_with_data_single_ended) generate
gen_adc_data_buf : for i in 0 to c_num_in_adc_pins-1 generate
cmp_ibuf_adc_data_ch0 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch0_p_t(i),
o => adc_data_ch0_o(i)
);
cmp_ibuf_adc_data_ch1 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch1_p_t(i),
o => adc_data_ch1_o(i)
);
cmp_ibuf_adc_data_ch2 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch2_p_t(i),
o => adc_data_ch2_o(i)
);
cmp_ibuf_adc_data_ch3 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch3_p_t(i),
o => adc_data_ch3_o(i)
);
end generate;
end generate;
gen_with_data_diff : if (not g_with_data_single_ended) generate
gen_adc_data_buf : for i in 0 to c_num_in_adc_pins-1 generate
cmp_ibufds_adc_data_ch0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch0_p_t(i),
ib => adc_data_ch0_n_t(i),
o => adc_data_ch0_o(i)
);
cmp_ibufds_adc_data_ch1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch1_p_t(i),
ib => adc_data_ch1_n_t(i),
o => adc_data_ch1_o(i)
);
cmp_ibufds_adc_data_ch2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch2_p_t(i),
ib => adc_data_ch2_n_t(i),
o => adc_data_ch2_o(i)
);
cmp_ibufds_adc_data_ch3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch3_p_t(i),
ib => adc_data_ch3_n_t(i),
o => adc_data_ch3_o(i)
);
end generate;
end generate;
end rtl;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
architecture base of blader is
begin
-- This file is the basic skeleton of what the bladeRF FPGA
-- should drive for outputs. All of the outputs are defined
-- here.
--
-- Use this file as a template for new targets.
-- VCTCXO DAC
dac_sclk <= '1' ;
dac_sdi <= '1' ;
dac_csx <= '1' ;
-- LEDs
led <= (others =>'0') ;
-- LMS RX Interface
lms_rx_enable <= '0' ;
lms_rx_v <= (others =>'0') ;
-- LMS TX Interface
lms_tx_data <= (others =>'0') ;
lms_iq_select <= '0' ;
lms_tx_v <= (others =>'0') ;
-- LMS SPI Interface
lms_sclk <= '1' ;
lms_sen <= '1' ;
lms_sdio <= '0' ;
-- LMS Control Interface
lms_reset <= '0' ;
-- Si5338 I2C Interface
si_scl <= '1' ;
si_sda <= '1' ;
-- FX3 Interface
fx3_gpif <= (others =>'Z') ;
fx3_ctl <= (others =>'Z') ;
fx3_uart_rxd <= '1' ;
-- Mini expansion
mini_exp1 <= '0' ;
mini_exp2 <= '0' ;
-- Expansion Interface
exp_spi_clock <= '1' ;
exp_spi_mosi <= '0' ;
exp_gpio <= (others =>'0') ;
end architecture ;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_8_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(7 downto 0);
din2 :in std_logic_vector(7 downto 0);
din3 :in std_logic_vector(7 downto 0);
din4 :in std_logic_vector(7 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(7 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_8_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(7 downto 0);
signal mux_1_1 : std_logic_vector(7 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(7 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_8_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(7 downto 0);
din2 :in std_logic_vector(7 downto 0);
din3 :in std_logic_vector(7 downto 0);
din4 :in std_logic_vector(7 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(7 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_8_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(7 downto 0);
signal mux_1_1 : std_logic_vector(7 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(7 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_8_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(7 downto 0);
din2 :in std_logic_vector(7 downto 0);
din3 :in std_logic_vector(7 downto 0);
din4 :in std_logic_vector(7 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(7 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_8_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(7 downto 0);
signal mux_1_1 : std_logic_vector(7 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(7 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrCuenta8bits_conFin.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: albertomg994@gmail.com
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity incrCuenta8bits_conFin is
Port ( num_in : in STD_LOGIC_VECTOR (7 downto 0);
num_out : out STD_LOGIC_VECTOR (7 downto 0);
fin: out std_logic
);
end incrCuenta8bits_conFin;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of incrCuenta8bits_conFin is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal aux: std_logic_vector(6 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT adder1bit_comb
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => num_in(0),
B => '1',
Cin => '0',
Z => num_out(0),
Cout => aux(0)
);
adder_1: adder1bit_comb port map(
A => num_in(1),
B => aux(0),
Cin => '0',
Z => num_out(1),
Cout => aux(1)
);
adder_2: adder1bit_comb port map(
A => num_in(2),
B => aux(1),
Cin => '0',
Z => num_out(2),
Cout => aux(2)
);
adder_3: adder1bit_comb port map(
A => num_in(3),
B => aux(2),
Cin => '0',
Z => num_out(3),
Cout => aux(3)
);
adder_4: adder1bit_comb port map(
A => num_in(4),
B => aux(3),
Cin => '0',
Z => num_out(4),
Cout => aux(4)
);
adder_5: adder1bit_comb port map(
A => num_in(5),
B => aux(4),
Cin => '0',
Z => num_out(5),
Cout => aux(5)
);
adder_6: adder1bit_comb port map(
A => num_in(6),
B => aux(5),
Cin => '0',
Z => num_out(6),
Cout => aux(6)
);
adder_7: adder1bit_comb PORT MAP(
A => num_in(7),
B => aux(6),
Cin => '0',
Z => num_out(7),
Cout => fin
);
end rtl;
|
-------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
--------------------------------------------------------------------------------
--|
--| Filename : cntr_bhv
--| Author : R. Friesenhahn
--| Origin Date : 20130906
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
architecture bhv of cntr is
signal cntr : unsigned(CntrWidth-1 downto 0);
begin
CntrValue <= std_ulogic_vector(cntr);
P_CNTR : process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
cntr <= (others => '0');
CntReached <= '0';
else
CntReached <= '0';
if En = '1' then
if Clr = '1' then
cntr <= (others => '0');
elsif cntr = (unsigned(CritValue) - to_unsigned(1, CritValue'length)) then
CntReached <= '1';
cntr <= (others => '0');
else
cntr <= cntr + 1;
end if;
end if;
end if;
end if;
end process P_CNTR;
end architecture bhv;
|
library verilog;
use verilog.vl_types.all;
entity tlb is
generic(
LRU_TIMER_N : integer := 10
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iRD_REQ : in vl_logic;
iRD_ADDR : in vl_logic_vector(31 downto 0);
oRD_VALID : out vl_logic;
oRD_HIT : out vl_logic;
oRD_FLAGS : out vl_logic_vector(27 downto 0);
oRD_PHYS_ADDR : out vl_logic_vector(63 downto 0);
iWR_REQ : in vl_logic;
iWR_ADDR : in vl_logic_vector(31 downto 0);
iWR_FLAGS : in vl_logic_vector(27 downto 0);
iWR_PHYS_ADDR : in vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of LRU_TIMER_N : constant is 1;
end tlb;
|
--
-- File Name: TextUtilPkg.vhd
-- Design Unit Name: TextUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Shared Utilities for handling text files
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated to_hxstring to print U, X, Z, W, - when there are 4 in a row and ? for mixed meta
-- Added Justify that aligns LEFT, RIGHT, and CENTER with parameters in a sensible order.
-- 01/2022 2022.01 Added to_hxstring - based on hxwrite (in TbUtilPkg prior to release)
-- 08/2020 2020.08 Added ReadUntilDelimiterOrEOL and FindDelimiter
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Added IsUpper, IsLower, to_upper, to_lower
-- 01/2016 2016.01 Update for L.all(L'left)
-- 01/2015 2015.05 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package TextUtilPkg is
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean ;
function IsLower (constant Char : character ) return boolean ;
function to_lower (constant Char : character ) return character ;
function to_lower (constant Str : string ) return string ;
function to_upper (constant Char : character ) return character ;
function to_upper (constant Str : string ) return string ;
function IsHex (constant Char : character ) return boolean ;
function IsNumber (constant Char : character ) return boolean ;
function IsNumber (Name : string ) return boolean ;
function isstd_logic (constant Char : character ) return boolean ;
-- Crutch until VHDL-2019 conditional initialization
function IfElse(Expr : boolean ; A, B : string) return string ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) ;
procedure SkipWhiteSpace (variable L : InOut line) ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
-- to_hxstring
-- print in hex. If string contains X, then also print in binary
------------------------------------------------------------
function to_hxstring ( A : std_ulogic_vector) return string ;
function to_hxstring ( A : unsigned) return string ;
function to_hxstring ( A : signed) return string ;
------------------------------------------------------------
-- Justify
-- w/ Fill Character
-- w/o Fill character, Parameter order & names sensible
------------------------------------------------------------
type AlignType is (RIGHT, LEFT, CENTER) ;
function Justify (
S : string ;
Amount : natural ;
Align : AlignType := LEFT
) return string ;
function Justify (
S : string ;
Fill : character ;
Amount : natural ;
Align : AlignType := LEFT
) return string ;
------------------------------------------------------------
-- FileExists
-- Return TRUE if file exists
------------------------------------------------------------
impure function FileExists(FileName : string) return boolean ;
end TextUtilPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TextUtilPkg is
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant LOWER_TO_UPPER_OFFSET : integer := character'POS('a') - character'POS('A') ;
------------------------------------------------------------
function "-" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) - L) ;
end function "-" ;
------------------------------------------------------------
function "+" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) + L) ;
end function "+" ;
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'A' and Char <= 'Z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsUpper ;
------------------------------------------------------------
function IsLower (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'a' and Char <= 'z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsLower ;
------------------------------------------------------------
function to_lower (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsUpper(Char) then
return Char + LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_lower ;
------------------------------------------------------------
function to_lower (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_lower(Str(i)) ;
end loop ;
return result ;
end function to_lower ;
------------------------------------------------------------
function to_upper (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsLower(Char) then
return Char - LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_upper ;
------------------------------------------------------------
function to_upper (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_upper(Str(i)) ;
end loop ;
return result ;
end function to_upper ;
------------------------------------------------------------
function IsHex (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= '0' and Char <= '9' then
return TRUE ;
elsif Char >= 'a' and Char <= 'f' then
return TRUE ;
elsif Char >= 'A' and Char <= 'F' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsHex ;
------------------------------------------------------------
function IsNumber (constant Char : character ) return boolean is
------------------------------------------------------------
begin
return Char >= '0' and Char <= '9' ;
end function IsNumber ;
------------------------------------------------------------
function IsNumber (Name : string ) return boolean is
------------------------------------------------------------
begin
for i in Name'range loop
if not IsNumber(Name(i)) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function IsNumber ;
------------------------------------------------------------
function isstd_logic (constant Char : character ) return boolean is
------------------------------------------------------------
begin
case Char is
when 'U' | 'X' | '0' | '1' | 'Z' | 'W' | 'L' | 'H' | '-' =>
return TRUE ;
when others =>
return FALSE ;
end case ;
end function isstd_logic ;
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : string) return string is
------------------------------------------------------------
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
-- ------------------------------------------------------------
-- function iscomment (constant Char : character ) return boolean is
-- ------------------------------------------------------------
-- begin
-- case Char is
-- when '#' | '/' | '-' =>
-- return TRUE ;
-- when others =>
-- return FALSE ;
-- end case ;
-- end function iscomment ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) is
variable Valid : boolean ;
variable Char : character ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
Empty := TRUE ;
WhiteSpLoop : while L /= null and L.all'length > 0 loop
if (L.all(L'left) = ' ' or L.all(L'left) = NBSP or L.all(L'left) = HT) then
read (L, Char, Valid) ;
exit when not Valid ;
else
Empty := FALSE ;
return ;
end if ;
end loop WhiteSpLoop ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line
) is
variable Empty : boolean ;
begin
SkipWhiteSpace(L, Empty) ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
-- Package Local
procedure FindCommentEnd (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Char : character ;
begin
MultiLineComment := TRUE ;
Empty := TRUE ;
FindEndOfCommentLoop : while L /= null and L.all'length > 1 loop
read(L, Char, Valid) ;
if Char = '*' and L.all(L'left) = '/' then
read(L, Char, Valid) ;
Empty := FALSE ;
MultiLineComment := FALSE ;
exit FindEndOfCommentLoop ;
end if ;
end loop ;
end procedure FindCommentEnd ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Next2Char : string(1 to 2) ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
if MultiLineComment then
FindCommentEnd(L, Empty, MultiLineComment) ;
end if ;
EmptyCheckLoop : while not MultiLineComment loop
SkipWhiteSpace(L, Empty) ;
exit when Empty ; -- line null or 0 in length detected by SkipWhite
Empty := TRUE ;
exit when L.all(L'left) = '#' ; -- shell style comment
if L.all'length >= 2 then
if L'ascending then
Next2Char := L.all(L'left to L'left+1) ;
else
Next2Char := L.all(L'left downto L'left-1) ;
end if;
exit when Next2Char = "//" ; -- C style comment
exit when Next2Char = "--" ; -- VHDL style comment
if Next2Char = "/*" then -- C style multi line comment
FindCommentEnd(L, Empty, MultiLineComment) ;
exit when Empty ;
next EmptyCheckLoop ; -- Found end of comment, restart processing line
end if ;
end if ;
Empty := FALSE ;
exit ;
end loop EmptyCheckLoop ;
end procedure EmptyOrCommentLine ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) is
variable NameStr : string(1 to L'length) ;
variable ReadLen : integer := 1 ;
variable Good : boolean ;
begin
ReadValid := TRUE ;
for i in NameStr'range loop
Read(L, NameStr(i), Good) ;
ReadValid := ReadValid and Good ;
if NameStr(i) = Delimiter then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i-1)) ;
exit ;
elsif i = NameStr'length then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i)) ;
exit ;
end if ;
end loop ;
end procedure ReadUntilDelimiterOrEOL ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) is
variable Char : Character ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop : loop
if Delimiter /= ' ' then
SkipWhiteSpace(L) ;
end if ;
Read(L, Char, ReadValid) ;
exit when ReadValid = FALSE or Char /= Delimiter ;
Found := TRUE ;
exit ;
end loop ;
end procedure FindDelimiter ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
constant NumHexChars : integer := (Result'length+3)/4 ;
constant ResultNormLen : integer := NumHexChars * 4 ;
variable NextChar : character ;
variable CharCount : integer ;
variable ReturnVal : std_logic_vector(ResultNormLen-1 downto 0) ;
variable ReadVal : std_logic_vector(3 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if ishex(NextChar) or NextChar = 'X' or NextChar = 'Z' then
hread(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(ResultNormLen-5 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= NumHexChars ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
if CharCount >= NumHexChars then
StrLen := Result'length ;
else
StrLen := CharCount * 4 ;
end if ;
Result := ReturnVal(Result'length-1 downto 0) ;
end procedure ReadHexToken ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
variable NextChar : character ;
variable CharCount : integer ;
variable ReadVal : std_logic ;
variable ReturnVal : std_logic_vector(Result'length-1 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if isstd_logic(NextChar) then
read(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(Result'length-2 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= Result'length ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
StrLen := CharCount ;
Result := ReturnVal ;
end procedure ReadBinaryToken ;
------------------------------------------------------------
-- RemoveHLTable
-- Convert L to 0 and H to 1, and nothing else
------------------------------------------------------------
constant RemoveHLTable : stdulogic_indexby_stdulogic := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => '0',
'H' => '1',
'-' => '-'
);
------------------------------------------------------------
-- local
function RemoveHL(A : std_ulogic_vector) return std_ulogic_vector is
------------------------------------------------------------
variable result : A'subtype ;
begin
for i in result'range loop
result(i) := RemoveHLTable(A(i)) ;
end loop ;
return result ;
end function RemoveHL ;
------------------------------------------------------------
-- local_to_hxstring
function local_to_hxstring ( A : std_ulogic_vector; IsSigned : Boolean := TRUE ) return string is
-- Code based on to_hstring from std_logic_1164-body.vhd
-- Copyright 2019 IEEE P1076 WG Authors
-- License: Apache License 2.0 - same as this package
------------------------------------------------------------
constant STRING_LEN : integer := (A'length+3)/4;
variable result : string(1 to STRING_LEN);
constant EXTEND_A_LEN : integer := STRING_LEN*4 ;
variable ExtendedA : std_ulogic_vector(1 to EXTEND_A_LEN) ;
variable PadA : std_ulogic_vector(1 to EXTEND_A_LEN - A'length) ;
variable HexVal : std_ulogic_vector(1 to 4) ;
variable PrintBinary : boolean := FALSE ;
begin
if A'length = 0 then
return "" ;
end if ;
if IsSigned or is_x(A(A'left)) then
PadA := (others => A(A'left)) ;
else
PadA := (others => '0') ;
end if ;
ExtendedA := RemoveHL(PadA & A) ;
for i in result'range loop
HexVal := ExtendedA(4*i-3 to 4*i);
case HexVal is
when X"0" => result(i) := '0';
when X"1" => result(i) := '1';
when X"2" => result(i) := '2';
when X"3" => result(i) := '3';
when X"4" => result(i) := '4';
when X"5" => result(i) := '5';
when X"6" => result(i) := '6';
when X"7" => result(i) := '7';
when X"8" => result(i) := '8';
when X"9" => result(i) := '9';
when X"A" => result(i) := 'A';
when X"B" => result(i) := 'B';
when X"C" => result(i) := 'C';
when X"D" => result(i) := 'D';
when X"E" => result(i) := 'E';
when X"F" => result(i) := 'F';
when "UUUU" => result(i) := 'U';
when "XXXX" => result(i) := 'X';
when "ZZZZ" => result(i) := 'Z';
when "WWWW" => result(i) := 'W';
when "----" => result(i) := '-';
when others => result(i) := '?'; PrintBinary := TRUE ;
end case;
end loop;
if PrintBinary then
return result & " (" & to_string(A) & ")" ;
else
return result ;
end if ;
end function local_to_hxstring;
------------------------------------------------------------
-- to_hxstring
function to_hxstring ( A : std_ulogic_vector) return string is
------------------------------------------------------------
begin
return local_to_hxstring(A, IsSigned => FALSE) ;
end function to_hxstring ;
------------------------------------------------------------
-- to_hxstring
function to_hxstring ( A : unsigned) return string is
------------------------------------------------------------
begin
return local_to_hxstring(std_ulogic_vector(A), IsSigned => FALSE) ;
end function to_hxstring ;
------------------------------------------------------------
-- to_hxstring
function to_hxstring (A : signed) return string is
------------------------------------------------------------
begin
return local_to_hxstring(std_ulogic_vector(A), IsSigned => TRUE) ;
end function to_hxstring ;
------------------------------------------------------------
-- Justify
-- w/ Fill Character
-- w/o Fill character, Parameter order & names sensible
------------------------------------------------------------
function Justify (
S : string ;
Fill : character ;
Amount : natural ;
Align : AlignType := LEFT
) return string is
constant FillLen : integer := maximum(1, Amount - S'length) ;
constant HalfFillLen : integer := (FillLen+1)/2 ;
constant FillString : string(1 to FillLen) := (others => FILL) ;
begin
if S'length >= Amount then
return S ;
end if ;
case Align is
when LEFT => return S & FillString ;
when RIGHT => return FillString & S ;
when CENTER => return FillString(1 to HalfFillLen) & S & FillString(HalfFillLen+1 to FillLen) ;
end case ;
end function Justify ;
function Justify (
S : string ;
Amount : natural ;
Align : AlignType := LEFT
) return string is
begin
return Justify(S, ' ', Amount, Align) ;
end function Justify ;
------------------------------------------------------------
-- FileExists
-- Return TRUE if file exists
------------------------------------------------------------
impure function FileExists(FileName : string) return boolean is
file FileID : text ;
variable status : file_open_status ;
begin
file_open(status, FileID, FileName, READ_MODE) ;
file_close(FileID) ;
return status = OPEN_OK ;
end function FileExists ;
end package body TextUtilPkg ; |
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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|
`protect begin_protected
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|
`protect begin_protected
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|
`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:41 05/06/2017
-- Design Name:
-- Module Name: Mux_reg1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_reg1 is
Port ( alusrca : in STD_LOGIC_VECTOR (1 downto 0);
muxreg1 : in STD_LOGIC_VECTOR (15 downto 0);
mux_PC : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataA : out STD_LOGIC_VECTOR (15 downto 0));
end mux_reg1;
architecture Behavioral of mux_reg1 is
begin
process(alusrca)
begin
case alusrca is
when "00"=>
mux_dataA<=muxreg1;
when "01"=>
mux_dataA<=mux_PC;
when others=>null;
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of bar_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a xor b;
y <= not (a and b);
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of bar_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a xor b;
y <= not (a and b);
end if;
end process;
end architecture;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:37:32 07/10/2014
-- Design Name:
-- Module Name:
-- Project Name: CPU_1st_edition
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
enable_t : IN std_logic;
ir : IN std_logic_vector(15 downto 0);
sig_reg7aluout : OUT std_logic_vector(15 downto 0);
sig_reg7addrout : OUT std_logic_vector(15 downto 0);
enable_wb : IN std_logic;
reg_wb : IN std_logic_vector(7 downto 0);
cy : OUT std_logic
);
END COMPONENT;
--Inputs
signal enable_t : std_logic := '0';
signal ir : std_logic_vector(15 downto 0) := (others => '0');
signal enable_wb : std_logic := '0';
signal reg_wb : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal sig_reg7aluout : std_logic_vector(15 downto 0);
signal sig_reg7addrout : std_logic_vector(15 downto 0);
signal cy : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
enable_t => enable_t,
ir => ir,
sig_reg7aluout => sig_reg7aluout,
sig_reg7addrout => sig_reg7addrout,
enable_wb => enable_wb,
reg_wb => reg_wb,
cy => cy
);
-- Stimulus process
stim_proc: process
begin
-- ²âÊÔ»Øдģ
ir <= "0000011100000000";
reg_wb <= "00000000";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000011000000000";
reg_wb <= "11111111";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000010100000000";
reg_wb <= "11111111";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000010000000000";
reg_wb <= "01000100";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000001100000000";
reg_wb <= "00110011";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000001000000000";
reg_wb <= "00100010";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000000100000000";
reg_wb <= "00010001";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
ir <= "0000000000000000";
reg_wb <= "00000000";
enable_wb <= '0';
wait for 20 ns;
enable_wb <= '1';
wait for 20 ns;
enable_wb <= '0';
-- ²âÊÔ²Ù×÷Â룬ͬʱ²âÊÔ½øλ±êÖ¾
--ADD
ir <= "0000011000000110";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--SUB
ir <= "0000111000000001";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--MOV
ir <= "0001010100000001";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--MVI
ir <= "1001011010101010";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--LDA
ir <= "1101100010101010";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--STA
ir <= "1100011010101010";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--JMP
ir <= "1000111010101010";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
--JZ
ir <= "1000011010101010";
enable_t <= '0';
wait for 20 ns ;
enable_t <= '1';
wait for 20 ns ;
enable_t <= '0' ;
wait for 20 ns;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Double Bank behavioral, where it can output
-- number_of_memories at once and have 2 interfaces, so it can read and write on the same cycle
-- Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Double Bank
--
-- ram_address_size :
-- Address size of the RAM Double Bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Double Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Double Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double_bank is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_double_bank;
architecture simple of ram_double_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a) + index)) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b) + index)) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a)) + index);
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b)) + index);
end loop;
end if;
end process;
end simple;
|
---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "nco".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile nco.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl nco.ngc nco_netlist.vhd
--
-- Compile nco_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_nco is
end tb_nco;
architecture tb of tb_nco is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.nco
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 5;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2937.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02937pkg is
end c02s02b00x00p07n03i02937pkg;
package body c02s02b00x00p07n03i02937pkg is
procedure proc1 (i,l:integer; res: boolean);
-- ERROR: non-existent body for procedure proc1
end c02s02b00x00p07n03i02937pkg;
ENTITY c02s02b00x00p07n03i02937ent IS
END c02s02b00x00p07n03i02937ent;
ARCHITECTURE c02s02b00x00p07n03i02937arch OF c02s02b00x00p07n03i02937ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02937 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02937arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2937.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02937pkg is
end c02s02b00x00p07n03i02937pkg;
package body c02s02b00x00p07n03i02937pkg is
procedure proc1 (i,l:integer; res: boolean);
-- ERROR: non-existent body for procedure proc1
end c02s02b00x00p07n03i02937pkg;
ENTITY c02s02b00x00p07n03i02937ent IS
END c02s02b00x00p07n03i02937ent;
ARCHITECTURE c02s02b00x00p07n03i02937arch OF c02s02b00x00p07n03i02937ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02937 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02937arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2937.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02937pkg is
end c02s02b00x00p07n03i02937pkg;
package body c02s02b00x00p07n03i02937pkg is
procedure proc1 (i,l:integer; res: boolean);
-- ERROR: non-existent body for procedure proc1
end c02s02b00x00p07n03i02937pkg;
ENTITY c02s02b00x00p07n03i02937ent IS
END c02s02b00x00p07n03i02937ent;
ARCHITECTURE c02s02b00x00p07n03i02937arch OF c02s02b00x00p07n03i02937ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02937 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02937arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 54448)
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`protect end_protected
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY input_data_demux IS
PORT(
ADDR, DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON, NOTE_OFF: out std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
WAV_SELECT : out std_logic_vector(7 downto 0)
);
END input_data_demux;
ARCHITECTURE behav of input_data_demux is
BEGIN
process(CLK,RESET)
variable cooleshit : std_logic;
begin
if reset = '0' then
NOTE_ON <= (others => '0');
NOTE_OFF <= (others => '0');
WAV_SELECT <= (others => '0');
elsif rising_edge(CLK) then
case ADDR is
when X"80" => NOTE_OFF <= DATA;
NOTE_ON <= (others => '0');
when X"FF" => NOTE_ON <= DATA;
NOTE_OFF <= (others => '0');
when X"AA" => WAV_SELECT <= DATA;
when others => NOTE_ON <= (others => '0');
NOTE_OFF <= (others => '0');
end case;
end if;
end process;
END behav; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- a goes through when s='1', b with s='0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
A: In std_logic_vector(NBIT-1 downto 0);
B: In std_logic_vector(NBIT-1 downto 0);
S: In std_logic;
Y: Out std_logic_vector(NBIT-1 downto 0)
);
end mux21;
architecture beh of MUX21 is
begin
Y <= A when S='1' else B;
end beh;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_2_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_3_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_4_re_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_4_im_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block IS
-- Signals
SIGNAL dout_2_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_2_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_4_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_4_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_3_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_3_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_4_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_4_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
BEGIN
dout_2_re_signed <= signed(dout_2_re);
din1_re <= resize(dout_2_re_signed, 18);
dout_2_im_signed <= signed(dout_2_im);
din1_im <= resize(dout_2_im_signed, 18);
dout_4_re_signed <= signed(dout_4_re);
din2_re <= resize(dout_4_re_signed, 18);
dout_4_im_signed <= signed(dout_4_im);
din2_im <= resize(dout_4_im_signed, 18);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_3)
VARIABLE add_cast : signed(18 DOWNTO 0);
VARIABLE add_cast_0 : signed(18 DOWNTO 0);
VARIABLE add_cast_1 : signed(18 DOWNTO 0);
VARIABLE add_cast_2 : signed(18 DOWNTO 0);
VARIABLE sub_cast : signed(18 DOWNTO 0);
VARIABLE sub_cast_0 : signed(18 DOWNTO 0);
VARIABLE sub_cast_1 : signed(18 DOWNTO 0);
VARIABLE sub_cast_2 : signed(18 DOWNTO 0);
VARIABLE add_cast_3 : signed(18 DOWNTO 0);
VARIABLE add_cast_4 : signed(18 DOWNTO 0);
VARIABLE add_cast_5 : signed(18 DOWNTO 0);
VARIABLE add_cast_6 : signed(18 DOWNTO 0);
VARIABLE sub_cast_3 : signed(18 DOWNTO 0);
VARIABLE sub_cast_4 : signed(18 DOWNTO 0);
VARIABLE sub_cast_5 : signed(18 DOWNTO 0);
VARIABLE sub_cast_6 : signed(18 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 19);
add_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 19);
sub_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 19);
add_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 19);
sub_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 19);
add_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 19);
sub_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 19);
add_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 19);
sub_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_3_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(17 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(17 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(17 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(17 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re_1 <= std_logic_vector(dout_4_re_tmp);
dout_4_im_1 <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_10000: out std_logic;
ce_1120: out std_logic;
ce_1400000: out std_logic;
ce_2: out std_logic;
ce_2240: out std_logic;
ce_22400000: out std_logic;
ce_224000000: out std_logic;
ce_2500: out std_logic;
ce_2800000: out std_logic;
ce_35: out std_logic;
ce_4480: out std_logic;
ce_44800000: out std_logic;
ce_5000: out std_logic;
ce_560: out std_logic;
ce_5600000: out std_logic;
ce_56000000: out std_logic;
ce_70: out std_logic;
ce_logic_1: out std_logic;
ce_logic_1400000: out std_logic;
ce_logic_2240: out std_logic;
ce_logic_22400000: out std_logic;
ce_logic_2800000: out std_logic;
ce_logic_560: out std_logic;
ce_logic_5600000: out std_logic;
ce_logic_70: out std_logic;
clk_1: out std_logic;
clk_10000: out std_logic;
clk_1120: out std_logic;
clk_1400000: out std_logic;
clk_2: out std_logic;
clk_2240: out std_logic;
clk_22400000: out std_logic;
clk_224000000: out std_logic;
clk_2500: out std_logic;
clk_2800000: out std_logic;
clk_35: out std_logic;
clk_4480: out std_logic;
clk_44800000: out std_logic;
clk_5000: out std_logic;
clk_560: out std_logic;
clk_5600000: out std_logic;
clk_56000000: out std_logic;
clk_70: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_10000_ce: std_logic;
signal xlclockdriver_10000_clk: std_logic;
signal xlclockdriver_1120_ce: std_logic;
signal xlclockdriver_1120_clk: std_logic;
signal xlclockdriver_1400000_ce: std_logic;
signal xlclockdriver_1400000_ce_logic: std_logic;
signal xlclockdriver_1400000_clk: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_ce_logic: std_logic;
signal xlclockdriver_1_clk: std_logic;
signal xlclockdriver_224000000_ce: std_logic;
signal xlclockdriver_224000000_clk: std_logic;
signal xlclockdriver_22400000_ce: std_logic;
signal xlclockdriver_22400000_ce_logic: std_logic;
signal xlclockdriver_22400000_clk: std_logic;
signal xlclockdriver_2240_ce: std_logic;
signal xlclockdriver_2240_ce_logic: std_logic;
signal xlclockdriver_2240_clk: std_logic;
signal xlclockdriver_2500_ce: std_logic;
signal xlclockdriver_2500_clk: std_logic;
signal xlclockdriver_2800000_ce: std_logic;
signal xlclockdriver_2800000_ce_logic: std_logic;
signal xlclockdriver_2800000_clk: std_logic;
signal xlclockdriver_2_ce: std_logic;
signal xlclockdriver_2_clk: std_logic;
signal xlclockdriver_35_ce: std_logic;
signal xlclockdriver_35_clk: std_logic;
signal xlclockdriver_44800000_ce: std_logic;
signal xlclockdriver_44800000_clk: std_logic;
signal xlclockdriver_4480_ce: std_logic;
signal xlclockdriver_4480_clk: std_logic;
signal xlclockdriver_5000_ce: std_logic;
signal xlclockdriver_5000_clk: std_logic;
signal xlclockdriver_56000000_ce: std_logic;
signal xlclockdriver_56000000_clk: std_logic;
signal xlclockdriver_5600000_ce: std_logic;
signal xlclockdriver_5600000_ce_logic: std_logic;
signal xlclockdriver_5600000_clk: std_logic;
signal xlclockdriver_560_ce: std_logic;
signal xlclockdriver_560_ce_logic: std_logic;
signal xlclockdriver_560_clk: std_logic;
signal xlclockdriver_70_ce: std_logic;
signal xlclockdriver_70_ce_logic: std_logic;
signal xlclockdriver_70_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
ce_10000 <= xlclockdriver_10000_ce;
ce_1120 <= xlclockdriver_1120_ce;
ce_1400000 <= xlclockdriver_1400000_ce;
ce_2 <= xlclockdriver_2_ce;
ce_2240 <= xlclockdriver_2240_ce;
ce_22400000 <= xlclockdriver_22400000_ce;
ce_224000000 <= xlclockdriver_224000000_ce;
ce_2500 <= xlclockdriver_2500_ce;
ce_2800000 <= xlclockdriver_2800000_ce;
ce_35 <= xlclockdriver_35_ce;
ce_4480 <= xlclockdriver_4480_ce;
ce_44800000 <= xlclockdriver_44800000_ce;
ce_5000 <= xlclockdriver_5000_ce;
ce_560 <= xlclockdriver_560_ce;
ce_5600000 <= xlclockdriver_5600000_ce;
ce_56000000 <= xlclockdriver_56000000_ce;
ce_70 <= xlclockdriver_70_ce;
ce_logic_1 <= xlclockdriver_1_ce_logic;
ce_logic_1400000 <= xlclockdriver_1400000_ce_logic;
ce_logic_2240 <= xlclockdriver_2240_ce_logic;
ce_logic_22400000 <= xlclockdriver_22400000_ce_logic;
ce_logic_2800000 <= xlclockdriver_2800000_ce_logic;
ce_logic_560 <= xlclockdriver_560_ce_logic;
ce_logic_5600000 <= xlclockdriver_5600000_ce_logic;
ce_logic_70 <= xlclockdriver_70_ce_logic;
clk_1 <= xlclockdriver_1_clk;
clk_10000 <= xlclockdriver_10000_clk;
clk_1120 <= xlclockdriver_1120_clk;
clk_1400000 <= xlclockdriver_1400000_clk;
clk_2 <= xlclockdriver_2_clk;
clk_2240 <= xlclockdriver_2240_clk;
clk_22400000 <= xlclockdriver_22400000_clk;
clk_224000000 <= xlclockdriver_224000000_clk;
clk_2500 <= xlclockdriver_2500_clk;
clk_2800000 <= xlclockdriver_2800000_clk;
clk_35 <= xlclockdriver_35_clk;
clk_4480 <= xlclockdriver_4480_clk;
clk_44800000 <= xlclockdriver_44800000_clk;
clk_5000 <= xlclockdriver_5000_clk;
clk_560 <= xlclockdriver_560_clk;
clk_5600000 <= xlclockdriver_5600000_clk;
clk_56000000 <= xlclockdriver_56000000_clk;
clk_70 <= xlclockdriver_70_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
ce_logic => xlclockdriver_1_ce_logic,
clk => xlclockdriver_1_clk
);
xlclockdriver_10000: entity work.xlclockdriver
generic map (
log_2_period => 14,
period => 10000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_10000_ce,
clk => xlclockdriver_10000_clk
);
xlclockdriver_1120: entity work.xlclockdriver
generic map (
log_2_period => 11,
period => 1120,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1120_ce,
clk => xlclockdriver_1120_clk
);
xlclockdriver_1400000: entity work.xlclockdriver
generic map (
log_2_period => 21,
period => 1400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1400000_ce,
ce_logic => xlclockdriver_1400000_ce_logic,
clk => xlclockdriver_1400000_clk
);
xlclockdriver_2: entity work.xlclockdriver
generic map (
log_2_period => 2,
period => 2,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2_ce,
clk => xlclockdriver_2_clk
);
xlclockdriver_2240: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2240,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2240_ce,
ce_logic => xlclockdriver_2240_ce_logic,
clk => xlclockdriver_2240_clk
);
xlclockdriver_22400000: entity work.xlclockdriver
generic map (
log_2_period => 25,
period => 22400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_22400000_ce,
ce_logic => xlclockdriver_22400000_ce_logic,
clk => xlclockdriver_22400000_clk
);
xlclockdriver_224000000: entity work.xlclockdriver
generic map (
log_2_period => 28,
period => 224000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_224000000_ce,
clk => xlclockdriver_224000000_clk
);
xlclockdriver_2500: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2500,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2500_ce,
clk => xlclockdriver_2500_clk
);
xlclockdriver_2800000: entity work.xlclockdriver
generic map (
log_2_period => 22,
period => 2800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2800000_ce,
ce_logic => xlclockdriver_2800000_ce_logic,
clk => xlclockdriver_2800000_clk
);
xlclockdriver_35: entity work.xlclockdriver
generic map (
log_2_period => 6,
period => 35,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_35_ce,
clk => xlclockdriver_35_clk
);
xlclockdriver_4480: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 4480,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_4480_ce,
clk => xlclockdriver_4480_clk
);
xlclockdriver_44800000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 44800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_44800000_ce,
clk => xlclockdriver_44800000_clk
);
xlclockdriver_5000: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 5000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5000_ce,
clk => xlclockdriver_5000_clk
);
xlclockdriver_560: entity work.xlclockdriver
generic map (
log_2_period => 10,
period => 560,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_560_ce,
ce_logic => xlclockdriver_560_ce_logic,
clk => xlclockdriver_560_clk
);
xlclockdriver_5600000: entity work.xlclockdriver
generic map (
log_2_period => 23,
period => 5600000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5600000_ce,
ce_logic => xlclockdriver_5600000_ce_logic,
clk => xlclockdriver_5600000_clk
);
xlclockdriver_56000000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 56000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_56000000_ce,
clk => xlclockdriver_56000000_clk
);
xlclockdriver_70: entity work.xlclockdriver
generic map (
log_2_period => 7,
period => 70,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_70_ce,
ce_logic => xlclockdriver_70_ce_logic,
clk => xlclockdriver_70_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity ddc_bpm_476_066_cw is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce: in std_logic := '1';
ce_clr: in std_logic := '1';
clk: in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066_cw;
architecture structural of ddc_bpm_476_066_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_10000_sg_x2: signal is "REDUCE";
signal ce_1120_sg_x32: std_logic;
attribute MAX_FANOUT of ce_1120_sg_x32: signal is "REDUCE";
signal ce_1400000_sg_x3: std_logic;
attribute MAX_FANOUT of ce_1400000_sg_x3: signal is "REDUCE";
signal ce_1_sg_x96: std_logic;
attribute MAX_FANOUT of ce_1_sg_x96: signal is "REDUCE";
signal ce_224000000_sg_x7: std_logic;
attribute MAX_FANOUT of ce_224000000_sg_x7: signal is "REDUCE";
signal ce_22400000_sg_x28: std_logic;
attribute MAX_FANOUT of ce_22400000_sg_x28: signal is "REDUCE";
signal ce_2240_sg_x28: std_logic;
attribute MAX_FANOUT of ce_2240_sg_x28: signal is "REDUCE";
signal ce_2500_sg_x3: std_logic;
attribute MAX_FANOUT of ce_2500_sg_x3: signal is "REDUCE";
signal ce_2800000_sg_x4: std_logic;
attribute MAX_FANOUT of ce_2800000_sg_x4: signal is "REDUCE";
signal ce_2_sg_x38: std_logic;
attribute MAX_FANOUT of ce_2_sg_x38: signal is "REDUCE";
signal ce_35_sg_x22: std_logic;
attribute MAX_FANOUT of ce_35_sg_x22: signal is "REDUCE";
signal ce_44800000_sg_x2: std_logic;
attribute MAX_FANOUT of ce_44800000_sg_x2: signal is "REDUCE";
signal ce_4480_sg_x9: std_logic;
attribute MAX_FANOUT of ce_4480_sg_x9: signal is "REDUCE";
signal ce_5000_sg_x9: std_logic;
attribute MAX_FANOUT of ce_5000_sg_x9: signal is "REDUCE";
signal ce_56000000_sg_x5: std_logic;
attribute MAX_FANOUT of ce_56000000_sg_x5: signal is "REDUCE";
signal ce_5600000_sg_x12: std_logic;
attribute MAX_FANOUT of ce_5600000_sg_x12: signal is "REDUCE";
signal ce_560_sg_x3: std_logic;
attribute MAX_FANOUT of ce_560_sg_x3: signal is "REDUCE";
signal ce_70_sg_x27: std_logic;
attribute MAX_FANOUT of ce_70_sg_x27: signal is "REDUCE";
signal ce_clr_x0: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clkNet: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_clr_x0 <= ce_clr;
clkNet <= clk;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
ddc_bpm_476_066_x0: entity work.ddc_bpm_476_066
port map (
adc_ch0_i => adc_ch0_i_net,
adc_ch1_i => adc_ch1_i_net,
adc_ch2_i => adc_ch2_i_net,
adc_ch3_i => adc_ch3_i_net,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27,
dds_config_valid_ch0_i => dds_config_valid_ch0_i_net,
dds_config_valid_ch1_i => dds_config_valid_ch1_i_net,
dds_config_valid_ch2_i => dds_config_valid_ch2_i_net,
dds_config_valid_ch3_i => dds_config_valid_ch3_i_net,
dds_pinc_ch0_i => dds_pinc_ch0_i_net,
dds_pinc_ch1_i => dds_pinc_ch1_i_net,
dds_pinc_ch2_i => dds_pinc_ch2_i_net,
dds_pinc_ch3_i => dds_pinc_ch3_i_net,
dds_poff_ch0_i => dds_poff_ch0_i_net,
dds_poff_ch1_i => dds_poff_ch1_i_net,
dds_poff_ch2_i => dds_poff_ch2_i_net,
dds_poff_ch3_i => dds_poff_ch3_i_net,
del_sig_div_fofb_thres_i => del_sig_div_fofb_thres_i_net,
del_sig_div_monit_thres_i => del_sig_div_monit_thres_i_net,
del_sig_div_tbt_thres_i => del_sig_div_tbt_thres_i_net,
ksum_i => ksum_i_net,
kx_i => kx_i_net,
ky_i => ky_i_net,
adc_ch0_dbg_data_o => adc_ch0_dbg_data_o_net,
adc_ch1_dbg_data_o => adc_ch1_dbg_data_o_net,
adc_ch2_dbg_data_o => adc_ch2_dbg_data_o_net,
adc_ch3_dbg_data_o => adc_ch3_dbg_data_o_net,
bpf_ch0_o => bpf_ch0_o_net,
bpf_ch1_o => bpf_ch1_o_net,
bpf_ch2_o => bpf_ch2_o_net,
bpf_ch3_o => bpf_ch3_o_net,
cic_fofb_q_01_missing_o => cic_fofb_q_01_missing_o_net,
cic_fofb_q_23_missing_o => cic_fofb_q_23_missing_o_net,
fofb_amp_ch0_o => fofb_amp_ch0_o_net,
fofb_amp_ch1_o => fofb_amp_ch1_o_net,
fofb_amp_ch2_o => fofb_amp_ch2_o_net,
fofb_amp_ch3_o => fofb_amp_ch3_o_net,
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o_net,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o_net,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o_net,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o_net,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o_net,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o_net,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o_net,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o_net,
fofb_pha_ch0_o => fofb_pha_ch0_o_net,
fofb_pha_ch1_o => fofb_pha_ch1_o_net,
fofb_pha_ch2_o => fofb_pha_ch2_o_net,
fofb_pha_ch3_o => fofb_pha_ch3_o_net,
mix_ch0_i_o => mix_ch0_i_o_net,
mix_ch0_q_o => mix_ch0_q_o_net,
mix_ch1_i_o => mix_ch1_i_o_net,
mix_ch1_q_o => mix_ch1_q_o_net,
mix_ch2_i_o => mix_ch2_i_o_net,
mix_ch2_q_o => mix_ch2_q_o_net,
mix_ch3_i_o => mix_ch3_i_o_net,
mix_ch3_q_o => mix_ch3_q_o_net,
monit_amp_ch0_o => monit_amp_ch0_o_net,
monit_amp_ch1_o => monit_amp_ch1_o_net,
monit_amp_ch2_o => monit_amp_ch2_o_net,
monit_amp_ch3_o => monit_amp_ch3_o_net,
monit_cfir_incorrect_o => monit_cfir_incorrect_o_net,
monit_cic_unexpected_o => monit_cic_unexpected_o_net,
monit_pfir_incorrect_o => monit_pfir_incorrect_o_net,
monit_pos_1_incorrect_o => monit_pos_1_incorrect_o_net,
q_fofb_o => q_fofb_o_net,
q_fofb_valid_o => q_fofb_valid_o_net,
q_monit_1_o => q_monit_1_o_net,
q_monit_1_valid_o => q_monit_1_valid_o_net,
q_monit_o => q_monit_o_net,
q_monit_valid_o => q_monit_valid_o_net,
q_tbt_o => q_tbt_o_net,
q_tbt_valid_o => q_tbt_valid_o_net,
sum_fofb_o => sum_fofb_o_net,
sum_fofb_valid_o => sum_fofb_valid_o_net,
sum_monit_1_o => sum_monit_1_o_net,
sum_monit_1_valid_o => sum_monit_1_valid_o_net,
sum_monit_o => sum_monit_o_net,
sum_monit_valid_o => sum_monit_valid_o_net,
sum_tbt_o => sum_tbt_o_net,
sum_tbt_valid_o => sum_tbt_valid_o_net,
tbt_amp_ch0_o => tbt_amp_ch0_o_net,
tbt_amp_ch1_o => tbt_amp_ch1_o_net,
tbt_amp_ch2_o => tbt_amp_ch2_o_net,
tbt_amp_ch3_o => tbt_amp_ch3_o_net,
tbt_decim_ch01_incorrect_o => tbt_decim_ch01_incorrect_o_net,
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o_net,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o_net,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o_net,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o_net,
tbt_decim_ch23_incorrect_o => tbt_decim_ch23_incorrect_o_net,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o_net,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o_net,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o_net,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o_net,
tbt_pha_ch0_o => tbt_pha_ch0_o_net,
tbt_pha_ch1_o => tbt_pha_ch1_o_net,
tbt_pha_ch2_o => tbt_pha_ch2_o_net,
tbt_pha_ch3_o => tbt_pha_ch3_o_net,
x_fofb_o => x_fofb_o_net,
x_fofb_valid_o => x_fofb_valid_o_net,
x_monit_1_o => x_monit_1_o_net,
x_monit_1_valid_o => x_monit_1_valid_o_net,
x_monit_o => x_monit_o_net,
x_monit_valid_o => x_monit_valid_o_net,
x_tbt_o => x_tbt_o_net,
x_tbt_valid_o => x_tbt_valid_o_net,
y_fofb_o => y_fofb_o_net,
y_fofb_valid_o => y_fofb_valid_o_net,
y_monit_1_o => y_monit_1_o_net,
y_monit_1_valid_o => y_monit_1_valid_o_net,
y_monit_o => y_monit_o_net,
y_monit_valid_o => y_monit_valid_o_net,
y_tbt_o => y_tbt_o_net,
y_tbt_valid_o => y_tbt_valid_o_net
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => ce_clr_x0,
sysclk => clkNet,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
end structural;
|
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_10000: out std_logic;
ce_1120: out std_logic;
ce_1400000: out std_logic;
ce_2: out std_logic;
ce_2240: out std_logic;
ce_22400000: out std_logic;
ce_224000000: out std_logic;
ce_2500: out std_logic;
ce_2800000: out std_logic;
ce_35: out std_logic;
ce_4480: out std_logic;
ce_44800000: out std_logic;
ce_5000: out std_logic;
ce_560: out std_logic;
ce_5600000: out std_logic;
ce_56000000: out std_logic;
ce_70: out std_logic;
ce_logic_1: out std_logic;
ce_logic_1400000: out std_logic;
ce_logic_2240: out std_logic;
ce_logic_22400000: out std_logic;
ce_logic_2800000: out std_logic;
ce_logic_560: out std_logic;
ce_logic_5600000: out std_logic;
ce_logic_70: out std_logic;
clk_1: out std_logic;
clk_10000: out std_logic;
clk_1120: out std_logic;
clk_1400000: out std_logic;
clk_2: out std_logic;
clk_2240: out std_logic;
clk_22400000: out std_logic;
clk_224000000: out std_logic;
clk_2500: out std_logic;
clk_2800000: out std_logic;
clk_35: out std_logic;
clk_4480: out std_logic;
clk_44800000: out std_logic;
clk_5000: out std_logic;
clk_560: out std_logic;
clk_5600000: out std_logic;
clk_56000000: out std_logic;
clk_70: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_10000_ce: std_logic;
signal xlclockdriver_10000_clk: std_logic;
signal xlclockdriver_1120_ce: std_logic;
signal xlclockdriver_1120_clk: std_logic;
signal xlclockdriver_1400000_ce: std_logic;
signal xlclockdriver_1400000_ce_logic: std_logic;
signal xlclockdriver_1400000_clk: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_ce_logic: std_logic;
signal xlclockdriver_1_clk: std_logic;
signal xlclockdriver_224000000_ce: std_logic;
signal xlclockdriver_224000000_clk: std_logic;
signal xlclockdriver_22400000_ce: std_logic;
signal xlclockdriver_22400000_ce_logic: std_logic;
signal xlclockdriver_22400000_clk: std_logic;
signal xlclockdriver_2240_ce: std_logic;
signal xlclockdriver_2240_ce_logic: std_logic;
signal xlclockdriver_2240_clk: std_logic;
signal xlclockdriver_2500_ce: std_logic;
signal xlclockdriver_2500_clk: std_logic;
signal xlclockdriver_2800000_ce: std_logic;
signal xlclockdriver_2800000_ce_logic: std_logic;
signal xlclockdriver_2800000_clk: std_logic;
signal xlclockdriver_2_ce: std_logic;
signal xlclockdriver_2_clk: std_logic;
signal xlclockdriver_35_ce: std_logic;
signal xlclockdriver_35_clk: std_logic;
signal xlclockdriver_44800000_ce: std_logic;
signal xlclockdriver_44800000_clk: std_logic;
signal xlclockdriver_4480_ce: std_logic;
signal xlclockdriver_4480_clk: std_logic;
signal xlclockdriver_5000_ce: std_logic;
signal xlclockdriver_5000_clk: std_logic;
signal xlclockdriver_56000000_ce: std_logic;
signal xlclockdriver_56000000_clk: std_logic;
signal xlclockdriver_5600000_ce: std_logic;
signal xlclockdriver_5600000_ce_logic: std_logic;
signal xlclockdriver_5600000_clk: std_logic;
signal xlclockdriver_560_ce: std_logic;
signal xlclockdriver_560_ce_logic: std_logic;
signal xlclockdriver_560_clk: std_logic;
signal xlclockdriver_70_ce: std_logic;
signal xlclockdriver_70_ce_logic: std_logic;
signal xlclockdriver_70_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
ce_10000 <= xlclockdriver_10000_ce;
ce_1120 <= xlclockdriver_1120_ce;
ce_1400000 <= xlclockdriver_1400000_ce;
ce_2 <= xlclockdriver_2_ce;
ce_2240 <= xlclockdriver_2240_ce;
ce_22400000 <= xlclockdriver_22400000_ce;
ce_224000000 <= xlclockdriver_224000000_ce;
ce_2500 <= xlclockdriver_2500_ce;
ce_2800000 <= xlclockdriver_2800000_ce;
ce_35 <= xlclockdriver_35_ce;
ce_4480 <= xlclockdriver_4480_ce;
ce_44800000 <= xlclockdriver_44800000_ce;
ce_5000 <= xlclockdriver_5000_ce;
ce_560 <= xlclockdriver_560_ce;
ce_5600000 <= xlclockdriver_5600000_ce;
ce_56000000 <= xlclockdriver_56000000_ce;
ce_70 <= xlclockdriver_70_ce;
ce_logic_1 <= xlclockdriver_1_ce_logic;
ce_logic_1400000 <= xlclockdriver_1400000_ce_logic;
ce_logic_2240 <= xlclockdriver_2240_ce_logic;
ce_logic_22400000 <= xlclockdriver_22400000_ce_logic;
ce_logic_2800000 <= xlclockdriver_2800000_ce_logic;
ce_logic_560 <= xlclockdriver_560_ce_logic;
ce_logic_5600000 <= xlclockdriver_5600000_ce_logic;
ce_logic_70 <= xlclockdriver_70_ce_logic;
clk_1 <= xlclockdriver_1_clk;
clk_10000 <= xlclockdriver_10000_clk;
clk_1120 <= xlclockdriver_1120_clk;
clk_1400000 <= xlclockdriver_1400000_clk;
clk_2 <= xlclockdriver_2_clk;
clk_2240 <= xlclockdriver_2240_clk;
clk_22400000 <= xlclockdriver_22400000_clk;
clk_224000000 <= xlclockdriver_224000000_clk;
clk_2500 <= xlclockdriver_2500_clk;
clk_2800000 <= xlclockdriver_2800000_clk;
clk_35 <= xlclockdriver_35_clk;
clk_4480 <= xlclockdriver_4480_clk;
clk_44800000 <= xlclockdriver_44800000_clk;
clk_5000 <= xlclockdriver_5000_clk;
clk_560 <= xlclockdriver_560_clk;
clk_5600000 <= xlclockdriver_5600000_clk;
clk_56000000 <= xlclockdriver_56000000_clk;
clk_70 <= xlclockdriver_70_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
ce_logic => xlclockdriver_1_ce_logic,
clk => xlclockdriver_1_clk
);
xlclockdriver_10000: entity work.xlclockdriver
generic map (
log_2_period => 14,
period => 10000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_10000_ce,
clk => xlclockdriver_10000_clk
);
xlclockdriver_1120: entity work.xlclockdriver
generic map (
log_2_period => 11,
period => 1120,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1120_ce,
clk => xlclockdriver_1120_clk
);
xlclockdriver_1400000: entity work.xlclockdriver
generic map (
log_2_period => 21,
period => 1400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1400000_ce,
ce_logic => xlclockdriver_1400000_ce_logic,
clk => xlclockdriver_1400000_clk
);
xlclockdriver_2: entity work.xlclockdriver
generic map (
log_2_period => 2,
period => 2,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2_ce,
clk => xlclockdriver_2_clk
);
xlclockdriver_2240: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2240,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2240_ce,
ce_logic => xlclockdriver_2240_ce_logic,
clk => xlclockdriver_2240_clk
);
xlclockdriver_22400000: entity work.xlclockdriver
generic map (
log_2_period => 25,
period => 22400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_22400000_ce,
ce_logic => xlclockdriver_22400000_ce_logic,
clk => xlclockdriver_22400000_clk
);
xlclockdriver_224000000: entity work.xlclockdriver
generic map (
log_2_period => 28,
period => 224000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_224000000_ce,
clk => xlclockdriver_224000000_clk
);
xlclockdriver_2500: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2500,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2500_ce,
clk => xlclockdriver_2500_clk
);
xlclockdriver_2800000: entity work.xlclockdriver
generic map (
log_2_period => 22,
period => 2800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2800000_ce,
ce_logic => xlclockdriver_2800000_ce_logic,
clk => xlclockdriver_2800000_clk
);
xlclockdriver_35: entity work.xlclockdriver
generic map (
log_2_period => 6,
period => 35,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_35_ce,
clk => xlclockdriver_35_clk
);
xlclockdriver_4480: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 4480,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_4480_ce,
clk => xlclockdriver_4480_clk
);
xlclockdriver_44800000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 44800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_44800000_ce,
clk => xlclockdriver_44800000_clk
);
xlclockdriver_5000: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 5000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5000_ce,
clk => xlclockdriver_5000_clk
);
xlclockdriver_560: entity work.xlclockdriver
generic map (
log_2_period => 10,
period => 560,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_560_ce,
ce_logic => xlclockdriver_560_ce_logic,
clk => xlclockdriver_560_clk
);
xlclockdriver_5600000: entity work.xlclockdriver
generic map (
log_2_period => 23,
period => 5600000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5600000_ce,
ce_logic => xlclockdriver_5600000_ce_logic,
clk => xlclockdriver_5600000_clk
);
xlclockdriver_56000000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 56000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_56000000_ce,
clk => xlclockdriver_56000000_clk
);
xlclockdriver_70: entity work.xlclockdriver
generic map (
log_2_period => 7,
period => 70,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_70_ce,
ce_logic => xlclockdriver_70_ce_logic,
clk => xlclockdriver_70_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity ddc_bpm_476_066_cw is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce: in std_logic := '1';
ce_clr: in std_logic := '1';
clk: in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066_cw;
architecture structural of ddc_bpm_476_066_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_10000_sg_x2: signal is "REDUCE";
signal ce_1120_sg_x32: std_logic;
attribute MAX_FANOUT of ce_1120_sg_x32: signal is "REDUCE";
signal ce_1400000_sg_x3: std_logic;
attribute MAX_FANOUT of ce_1400000_sg_x3: signal is "REDUCE";
signal ce_1_sg_x96: std_logic;
attribute MAX_FANOUT of ce_1_sg_x96: signal is "REDUCE";
signal ce_224000000_sg_x7: std_logic;
attribute MAX_FANOUT of ce_224000000_sg_x7: signal is "REDUCE";
signal ce_22400000_sg_x28: std_logic;
attribute MAX_FANOUT of ce_22400000_sg_x28: signal is "REDUCE";
signal ce_2240_sg_x28: std_logic;
attribute MAX_FANOUT of ce_2240_sg_x28: signal is "REDUCE";
signal ce_2500_sg_x3: std_logic;
attribute MAX_FANOUT of ce_2500_sg_x3: signal is "REDUCE";
signal ce_2800000_sg_x4: std_logic;
attribute MAX_FANOUT of ce_2800000_sg_x4: signal is "REDUCE";
signal ce_2_sg_x38: std_logic;
attribute MAX_FANOUT of ce_2_sg_x38: signal is "REDUCE";
signal ce_35_sg_x22: std_logic;
attribute MAX_FANOUT of ce_35_sg_x22: signal is "REDUCE";
signal ce_44800000_sg_x2: std_logic;
attribute MAX_FANOUT of ce_44800000_sg_x2: signal is "REDUCE";
signal ce_4480_sg_x9: std_logic;
attribute MAX_FANOUT of ce_4480_sg_x9: signal is "REDUCE";
signal ce_5000_sg_x9: std_logic;
attribute MAX_FANOUT of ce_5000_sg_x9: signal is "REDUCE";
signal ce_56000000_sg_x5: std_logic;
attribute MAX_FANOUT of ce_56000000_sg_x5: signal is "REDUCE";
signal ce_5600000_sg_x12: std_logic;
attribute MAX_FANOUT of ce_5600000_sg_x12: signal is "REDUCE";
signal ce_560_sg_x3: std_logic;
attribute MAX_FANOUT of ce_560_sg_x3: signal is "REDUCE";
signal ce_70_sg_x27: std_logic;
attribute MAX_FANOUT of ce_70_sg_x27: signal is "REDUCE";
signal ce_clr_x0: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clkNet: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_clr_x0 <= ce_clr;
clkNet <= clk;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
ddc_bpm_476_066_x0: entity work.ddc_bpm_476_066
port map (
adc_ch0_i => adc_ch0_i_net,
adc_ch1_i => adc_ch1_i_net,
adc_ch2_i => adc_ch2_i_net,
adc_ch3_i => adc_ch3_i_net,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27,
dds_config_valid_ch0_i => dds_config_valid_ch0_i_net,
dds_config_valid_ch1_i => dds_config_valid_ch1_i_net,
dds_config_valid_ch2_i => dds_config_valid_ch2_i_net,
dds_config_valid_ch3_i => dds_config_valid_ch3_i_net,
dds_pinc_ch0_i => dds_pinc_ch0_i_net,
dds_pinc_ch1_i => dds_pinc_ch1_i_net,
dds_pinc_ch2_i => dds_pinc_ch2_i_net,
dds_pinc_ch3_i => dds_pinc_ch3_i_net,
dds_poff_ch0_i => dds_poff_ch0_i_net,
dds_poff_ch1_i => dds_poff_ch1_i_net,
dds_poff_ch2_i => dds_poff_ch2_i_net,
dds_poff_ch3_i => dds_poff_ch3_i_net,
del_sig_div_fofb_thres_i => del_sig_div_fofb_thres_i_net,
del_sig_div_monit_thres_i => del_sig_div_monit_thres_i_net,
del_sig_div_tbt_thres_i => del_sig_div_tbt_thres_i_net,
ksum_i => ksum_i_net,
kx_i => kx_i_net,
ky_i => ky_i_net,
adc_ch0_dbg_data_o => adc_ch0_dbg_data_o_net,
adc_ch1_dbg_data_o => adc_ch1_dbg_data_o_net,
adc_ch2_dbg_data_o => adc_ch2_dbg_data_o_net,
adc_ch3_dbg_data_o => adc_ch3_dbg_data_o_net,
bpf_ch0_o => bpf_ch0_o_net,
bpf_ch1_o => bpf_ch1_o_net,
bpf_ch2_o => bpf_ch2_o_net,
bpf_ch3_o => bpf_ch3_o_net,
cic_fofb_q_01_missing_o => cic_fofb_q_01_missing_o_net,
cic_fofb_q_23_missing_o => cic_fofb_q_23_missing_o_net,
fofb_amp_ch0_o => fofb_amp_ch0_o_net,
fofb_amp_ch1_o => fofb_amp_ch1_o_net,
fofb_amp_ch2_o => fofb_amp_ch2_o_net,
fofb_amp_ch3_o => fofb_amp_ch3_o_net,
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o_net,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o_net,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o_net,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o_net,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o_net,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o_net,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o_net,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o_net,
fofb_pha_ch0_o => fofb_pha_ch0_o_net,
fofb_pha_ch1_o => fofb_pha_ch1_o_net,
fofb_pha_ch2_o => fofb_pha_ch2_o_net,
fofb_pha_ch3_o => fofb_pha_ch3_o_net,
mix_ch0_i_o => mix_ch0_i_o_net,
mix_ch0_q_o => mix_ch0_q_o_net,
mix_ch1_i_o => mix_ch1_i_o_net,
mix_ch1_q_o => mix_ch1_q_o_net,
mix_ch2_i_o => mix_ch2_i_o_net,
mix_ch2_q_o => mix_ch2_q_o_net,
mix_ch3_i_o => mix_ch3_i_o_net,
mix_ch3_q_o => mix_ch3_q_o_net,
monit_amp_ch0_o => monit_amp_ch0_o_net,
monit_amp_ch1_o => monit_amp_ch1_o_net,
monit_amp_ch2_o => monit_amp_ch2_o_net,
monit_amp_ch3_o => monit_amp_ch3_o_net,
monit_cfir_incorrect_o => monit_cfir_incorrect_o_net,
monit_cic_unexpected_o => monit_cic_unexpected_o_net,
monit_pfir_incorrect_o => monit_pfir_incorrect_o_net,
monit_pos_1_incorrect_o => monit_pos_1_incorrect_o_net,
q_fofb_o => q_fofb_o_net,
q_fofb_valid_o => q_fofb_valid_o_net,
q_monit_1_o => q_monit_1_o_net,
q_monit_1_valid_o => q_monit_1_valid_o_net,
q_monit_o => q_monit_o_net,
q_monit_valid_o => q_monit_valid_o_net,
q_tbt_o => q_tbt_o_net,
q_tbt_valid_o => q_tbt_valid_o_net,
sum_fofb_o => sum_fofb_o_net,
sum_fofb_valid_o => sum_fofb_valid_o_net,
sum_monit_1_o => sum_monit_1_o_net,
sum_monit_1_valid_o => sum_monit_1_valid_o_net,
sum_monit_o => sum_monit_o_net,
sum_monit_valid_o => sum_monit_valid_o_net,
sum_tbt_o => sum_tbt_o_net,
sum_tbt_valid_o => sum_tbt_valid_o_net,
tbt_amp_ch0_o => tbt_amp_ch0_o_net,
tbt_amp_ch1_o => tbt_amp_ch1_o_net,
tbt_amp_ch2_o => tbt_amp_ch2_o_net,
tbt_amp_ch3_o => tbt_amp_ch3_o_net,
tbt_decim_ch01_incorrect_o => tbt_decim_ch01_incorrect_o_net,
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o_net,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o_net,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o_net,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o_net,
tbt_decim_ch23_incorrect_o => tbt_decim_ch23_incorrect_o_net,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o_net,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o_net,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o_net,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o_net,
tbt_pha_ch0_o => tbt_pha_ch0_o_net,
tbt_pha_ch1_o => tbt_pha_ch1_o_net,
tbt_pha_ch2_o => tbt_pha_ch2_o_net,
tbt_pha_ch3_o => tbt_pha_ch3_o_net,
x_fofb_o => x_fofb_o_net,
x_fofb_valid_o => x_fofb_valid_o_net,
x_monit_1_o => x_monit_1_o_net,
x_monit_1_valid_o => x_monit_1_valid_o_net,
x_monit_o => x_monit_o_net,
x_monit_valid_o => x_monit_valid_o_net,
x_tbt_o => x_tbt_o_net,
x_tbt_valid_o => x_tbt_valid_o_net,
y_fofb_o => y_fofb_o_net,
y_fofb_valid_o => y_fofb_valid_o_net,
y_monit_1_o => y_monit_1_o_net,
y_monit_1_valid_o => y_monit_1_valid_o_net,
y_monit_o => y_monit_o_net,
y_monit_valid_o => y_monit_valid_o_net,
y_tbt_o => y_tbt_o_net,
y_tbt_valid_o => y_tbt_valid_o_net
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => ce_clr_x0,
sysclk => clkNet,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
end structural;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:51 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: channel_error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- CHANNEL_ERROR_DETECT
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: the CHANNEL_ERROR_DETECT module monitors the error signals
-- from the Aurora Lanes in the channel. If one or more errors
-- are detected, the error is reported as a channel error. If
-- a hard error is detected, it sends a message to the channel
-- initialization state machine to reset the channel.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CHANNEL_ERROR_DETECT is
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end CHANNEL_ERROR_DETECT;
architecture RTL of CHANNEL_ERROR_DETECT is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal CHANNEL_SOFT_ERROR_Buffer : std_logic := '1';
signal CHANNEL_HARD_ERROR_Buffer : std_logic := '1';
signal RESET_CHANNEL_Buffer : std_logic := '1';
-- Internal Register Declarations --
signal soft_error_r : std_logic;
signal hard_error_r : std_logic;
-- Wire Declarations --
signal channel_soft_error_c : std_logic;
signal channel_hard_error_c : std_logic;
signal reset_channel_c : std_logic;
begin
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
RESET_CHANNEL <= RESET_CHANNEL_Buffer;
-- Main Body of Code --
-- Register all of the incoming error signals. This is neccessary for timing.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
soft_error_r <= SOFT_ERROR after DLY;
hard_error_r <= HARD_ERROR after DLY;
end if;
end process;
-- Assert Channel soft error if any of the soft error signals are asserted.
channel_soft_error_c <= soft_error_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_SOFT_ERROR_Buffer <= channel_soft_error_c after DLY;
end if;
end process;
-- Assert Channel hard error if any of the hard error signals are asserted.
channel_hard_error_c <= hard_error_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_HARD_ERROR_Buffer <= channel_hard_error_c after DLY;
end if;
end process;
-- "reset_channel_r" is asserted when any of the LANE_UP signals are low.
reset_channel_c <= not LANE_UP;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;
end if;
end process;
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:51 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: channel_error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- CHANNEL_ERROR_DETECT
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: the CHANNEL_ERROR_DETECT module monitors the error signals
-- from the Aurora Lanes in the channel. If one or more errors
-- are detected, the error is reported as a channel error. If
-- a hard error is detected, it sends a message to the channel
-- initialization state machine to reset the channel.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CHANNEL_ERROR_DETECT is
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end CHANNEL_ERROR_DETECT;
architecture RTL of CHANNEL_ERROR_DETECT is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal CHANNEL_SOFT_ERROR_Buffer : std_logic := '1';
signal CHANNEL_HARD_ERROR_Buffer : std_logic := '1';
signal RESET_CHANNEL_Buffer : std_logic := '1';
-- Internal Register Declarations --
signal soft_error_r : std_logic;
signal hard_error_r : std_logic;
-- Wire Declarations --
signal channel_soft_error_c : std_logic;
signal channel_hard_error_c : std_logic;
signal reset_channel_c : std_logic;
begin
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
RESET_CHANNEL <= RESET_CHANNEL_Buffer;
-- Main Body of Code --
-- Register all of the incoming error signals. This is neccessary for timing.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
soft_error_r <= SOFT_ERROR after DLY;
hard_error_r <= HARD_ERROR after DLY;
end if;
end process;
-- Assert Channel soft error if any of the soft error signals are asserted.
channel_soft_error_c <= soft_error_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_SOFT_ERROR_Buffer <= channel_soft_error_c after DLY;
end if;
end process;
-- Assert Channel hard error if any of the hard error signals are asserted.
channel_hard_error_c <= hard_error_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_HARD_ERROR_Buffer <= channel_hard_error_c after DLY;
end if;
end process;
-- "reset_channel_r" is asserted when any of the LANE_UP signals are low.
reset_channel_c <= not LANE_UP;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;
end if;
end process;
end RTL;
|
-------------------------------------------------------------------------------
-- plb_v46_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_04_a;
use plb_v46_v1_04_a.all;
entity plb_v46_0_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 9);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 9);
Sl_MRdErr : in std_logic_vector(0 to 9);
Sl_MWrErr : in std_logic_vector(0 to 9);
Sl_MBusy : in std_logic_vector(0 to 9);
Sl_rdBTerm : in std_logic_vector(0 to 9);
Sl_rdComp : in std_logic_vector(0 to 9);
Sl_rdDAck : in std_logic_vector(0 to 9);
Sl_rdDBus : in std_logic_vector(0 to 1279);
Sl_rdWdAddr : in std_logic_vector(0 to 39);
Sl_rearbitrate : in std_logic_vector(0 to 9);
Sl_SSize : in std_logic_vector(0 to 19);
Sl_wait : in std_logic_vector(0 to 9);
Sl_wrBTerm : in std_logic_vector(0 to 9);
Sl_wrComp : in std_logic_vector(0 to 9);
Sl_wrDAck : in std_logic_vector(0 to 9);
Sl_MIRQ : in std_logic_vector(0 to 9);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 9);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 9);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of plb_v46_0_wrapper : entity is "plb_v46_v1_04_a";
end plb_v46_0_wrapper;
architecture STRUCTURE of plb_v46_0_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
plb_v46_0 : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 1,
C_PLBV46_NUM_SLAVES => 10,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 128,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
------------------------------------------------------------------------
-- One element fifo
--
-- Copyright (c) 2014-2014 Rinat Zakirov
-- SPDX-License-Identifier: BSL-1.0
--
------------------------------------------------------------------------
NOT TESTED
library ieee;
use ieee.std_logic_1164.all;
entity one_element_fifo is
generic
(
BW: positive := 8
);
port
(
clk : in std_ulogic;
rst : in std_ulogic;
in_data : in std_ulogic_vector(BW - 1 downto 0);
in_valid : in std_ulogic;
in_ready : out std_ulogic;
out_data : out std_ulogic_vector(BW - 1 downto 0);
out_valid : out std_ulogic;
out_ready : in std_ulogic
);
end entity;
architecture rtl of one_element_fifo is
signal buf_val: std_ulogic;
signal buf: std_ulogic_vector(in_data'range);
signal in_ready_i, out_valid_i: std_ulogic;
begin
in_ready <= in_ready_i;
out_valid <= out_valid_i;
in_ready_i <= '1' when out_ready = '1' or buf_val = '0' else '0';
out_valid_i <= '1' when in_valid = '1' or buf_val = '1' else '0';
out_data <= in_data when buf_val = '0' else buf;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
buf_val <= '0';
else
if in_valid = '1' then
if out_ready = '1' then
assert (in_ready_i = '1') report "BAD FIFO LOGIC" severity failure;
if buf_val = '1' then
buf <= in_data;
end if;
else
if buf_val = '1' then
assert (in_ready_i = '0') report "BAD FIFO LOGIC" severity failure;
else
buf <= in_data;
buf_val <= '1';
end if;
end if;
else
if out_ready = '1' then
if buf_val = '1' then
buf_val <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the int_const_multiplier module.
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.tb_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_tb1 of int_const_mult_tb is
/* constants 1 */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true); --default
constant SPEED_opt : T_speed_tb := (t_min, false); --exception: value not set
constant MULTIPLICANDS : integer_v := (2, 7); --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_MULTIPLICANDS : integer_v := MULTIPLICANDS;
/* signals 2 */
/**************************************************************************************************/
constant NORMALIZED_IN_HIGH : integer := 1;
constant NORMALIZED_IN_LOW : integer := -2;
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant used_MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(used_MULTIPLICANDS);
constant IN_HIGH : integer := NORMALIZED_IN_HIGH + SULV_NEW_ZERO;
constant IN_LOW : integer := NORMALIZED_IN_LOW + SULV_NEW_ZERO;
constant OUT_HIGH : integer := SULV_NEW_ZERO + real_const_mult_OH(fixed_truncate,--used_ROUND_STYLE_opt,
integer'low,--used_ROUND_TO_BIT_opt,
real'low,--used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS_real,
NORMALIZED_IN_HIGH,
NORMALIZED_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant OUT_LOW : integer := SULV_NEW_ZERO + real_const_mult_OL(fixed_truncate,--used_ROUND_STYLE_opt,
integer'low,--used_ROUND_TO_BIT_opt,
real'low,--used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS_real,
NORMALIZED_IN_LOW,
not used_UNSIGNED_2COMP_opt);
--IN
signal input : std_ulogic_vector(IN_HIGH DOWNTO IN_LOW);
signal clk : std_ulogic;
signal valid_input : std_ulogic;
--OUT
signal output : sulv_v(1 to MULTIPLICANDS'length)(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_2:
entity work.real_const_mult
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
SPEED_opt => used_SPEED_opt,
--ROUND_STYLE_opt => used_ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => used_ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => used_MAX_ERROR_PCT_opt,
MULTIPLICANDS => used_MULTIPLICANDS_real)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(3 downto 0);
mem_ras_n : out std_logic_vector(0 downto 0);
mem_cas_n : out std_logic_vector(0 downto 0);
mem_we_n : out std_logic_vector(0 downto 0);
mem_reset_n : out std_logic;
mem_dq : inout std_logic_vector(31 downto 0);
mem_dqs : inout std_logic_vector(3 downto 0);
mem_dqs_n : inout std_logic_vector(3 downto 0);
mem_odt : out std_logic_vector(0 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(127 downto 0);
avl_wdata : in std_logic_vector(127 downto 0);
avl_be : in std_logic_vector(15 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of ddr3ctrl1 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_reset_n <= '0';
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_ca : out std_logic_vector(9 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(1 downto 0);
mem_dq : inout std_logic_vector(15 downto 0);
mem_dqs : inout std_logic_vector(1 downto 0);
mem_dqs_n : inout std_logic_vector(1 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(63 downto 0);
avl_wdata : in std_logic_vector(63 downto 0);
avl_be : in std_logic_vector(7 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of lpddr2ctrl1 is
signal lafi_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_reset_n <= '0';
afi_reset_export_n <= '0';
mem_ca <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
avl_ready <= '1';
avl_rdata_valid <= '1';
avl_rdata <= (others => '0');
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
variable vclk,vhclk: std_logic := '0';
begin
lafi_clk <= vclk;
afi_half_clk <= vhclk;
wait for 4 ns;
vclk := not vclk;
if vclk='0' then vhclk:=not vhclk; end if;
end process;
rstproc: process
begin
afi_reset_n <= '0';
for x in 1 to 10 loop
wait until rising_edge(lafi_clk);
end loop;
afi_reset_n <= '1';
wait;
end process;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oscillator is
generic (
g_num_voices : integer := 8);
port (
clock : in std_logic;
reset : in std_logic;
enable_i : in std_logic;
voice_i : in unsigned(3 downto 0);
freq : in unsigned(15 downto 0);
test : in std_logic := '0';
sync : in std_logic := '0';
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
test_o : out std_logic;
osc_val : out unsigned(23 downto 0);
carry_20 : out std_logic;
msb_other: out std_logic );
end oscillator;
architecture Gideon of oscillator is
type accu_array_t is array (natural range <>) of unsigned(23 downto 0);
signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type int4_array is array (natural range <>) of integer range 0 to 15;
constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6,
10, 8, 9, 15, 11, 12, 13, 14 );
signal ring_index : integer range 0 to 15;
signal sync_index : integer range 0 to 15;
signal msb_register : std_logic_vector(0 to 15) := (others => '0');
signal car_register : std_logic_vector(0 to 15) := (others => '0');
signal do_sync : std_logic;
begin
sync_index <= voice_linkage(to_integer(voice_i));
do_sync <= sync and car_register(sync_index);
ring_index <= voice_linkage(to_integer(voice_i));
process(clock)
variable cur_accu : unsigned(23 downto 0);
variable new_accu : unsigned(24 downto 0);
variable cur_20 : std_logic;
begin
if rising_edge(clock) then
cur_accu := accu_reg(0);
cur_20 := cur_accu(20);
if reset='1' or test='1' or do_sync='1' then
new_accu := (others => '0');
else
new_accu := ('0' & cur_accu) + freq;
end if;
osc_val <= new_accu(23 downto 0);
-- carry <= new_accu(24);
carry_20 <= new_accu(20) xor cur_20;
msb_other <= msb_register(ring_index);
voice_o <= voice_i;
enable_o <= enable_i;
test_o <= test;
if enable_i='1' then
accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1);
accu_reg(g_num_voices-1) <= new_accu(23 downto 0);
car_register(to_integer(voice_i)) <= new_accu(24);
msb_register(to_integer(voice_i)) <= cur_accu(23);
end if;
end if;
end process;
end Gideon;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi_flash
-- File: spi_flash.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description:
--
-- SPI flash simulation models.
--
-- +--------------------------------------------------------+
-- | ftype | Memory device |
-- +--------+-----------------------------------------------+
-- | 1 | SD card |
-- +--------+-----------------------------------------------+
-- | 3 | Simple SPI |
-- +--------+-----------------------------------------------+
-- | 4 | SPI memory device |
-- +--------+-----------------------------------------------+
--
-- For ftype => 4, the memoffset generic can be used to specify an address
-- offset that till be automatically be removed by the memory model. For
-- instance, memoffset => 16#1000# and an access to 0x1000 will read the
-- internal memory array at offset 0x0. This is a quick hack to support booting
-- from SPIMCTRL that has an offset specified and not having to modify the
-- SREC.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib, gaisler;
use grlib.stdlib.all;
use grlib.stdio.all;
--use gaisler.sim.all;
entity spi_flash is
generic (
ftype : integer := 0; -- Flash type
debug : integer := 0; -- Debug output
fname : string := "prom.srec"; -- File to read from
readcmd : integer := 16#0B#; -- SPI memory device read command
dummybyte : integer := 1;
dualoutput : integer := 0;
memoffset : integer := 0); -- Addr. offset automatically removed
-- by Flash model
port (
sck : in std_ulogic;
di : inout std_logic;
do : inout std_logic;
csn : inout std_logic;
-- Test control inputs
sd_cmd_timeout : in std_ulogic := '0';
sd_data_timeout : in std_ulogic := '0'
);
end spi_flash;
architecture sim of spi_flash is
-- Description: Simple, incomplete, model of SD card
procedure simple_sd_model (
constant dbg : in integer;
signal sck : in std_ulogic;
signal di : in std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic;
-- Test control inputs
signal cmd_to : in std_ulogic; -- force command response timeout
signal data_to : in std_ulogic) is -- force data token timeout
type sd_state_type is (idle, wait_cmd55, wait_acmd41, wait_cmd16,
wait_cmd17);
type response_type is array (0 to 10) of std_logic_vector(7 downto 0);
variable state : sd_state_type := idle;
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : response_type;
variable resp_size : integer;
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(47 downto 0);
variable index : integer;
variable bcnt : integer;
constant CMD0 : std_logic_vector(5 downto 0) := "000000";
constant CMD16 : std_logic_vector(5 downto 0) := "010000";
constant CMD17 : std_logic_vector(5 downto 0) := "010001";
constant CMD55 : std_logic_vector(5 downto 0) := "110111";
constant ACMD41 : std_logic_vector(5 downto 0) := "101001";
constant R1 : std_logic_vector(7 downto 0) := X"00";
constant DATA_TOKEN : std_logic_vector(7 downto 0) := X"FE";
constant DATA_ERR_TOKEN : std_logic_vector(7 downto 0) := X"01";
begin -- simple_sd_model
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
-- Receive data
do <= '1';
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then -- Received a byte
command := command(39 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received byte: " &
tost(indata));
end if;
if (command(47 downto 46) = "01" and command(7 downto 0) = X"95") then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
case state is
when idle =>
if command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd55 =>
if command(45 downto 40) = CMD55 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD55");
end if;
state := wait_acmd41;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_acmd41 =>
if command(45 downto 40) = ACMD41 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD41");
end if;
if cmd_to = '0' then
state := wait_cmd16;
else
state := idle;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd16 =>
if command(45 downto 40) = CMD16 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD16");
Print(time'image(now) & ": simple_sd_model: BLOCKLEN set to " &
tost(conv_integer(command(39 downto 8))));
end if;
state := wait_cmd17;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd17 =>
if command(45 downto 40) = CMD17 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD17");
Print(time'image(now) & ": simple_sd_model: Read from address " &
tost(conv_integer(command(39 downto 8))));
end if;
response(0) := R1;
response(1) := (others => '1');
response(2) := (others => '1');
response(3) := DATA_TOKEN;
-- Data response is address
response(4) := command(39 downto 32);
response(5) := command(31 downto 24);
response(6) := command(23 downto 16);
response(7) := command(15 downto 8);
if data_to = '1' then
resp_size := 1;
else
resp_size := 8;
end if;
respond := not cmd_to;
elsif command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
end case;
received_command := '0';
end if;
if respond = '1' then
bcnt := 0;
while resp_size > bcnt loop
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: Responding with " &
tost(response(bcnt)));
end if;
index := 0;
while index < 8 loop
wait until falling_edge(sck);
do <= response(bcnt)(7);
response(bcnt)(7 downto 1) := response(bcnt)(6 downto 0);
index := index + 1;
end loop;
bcnt := bcnt + 1;
end loop;
respond := '0';
wait until rising_edge(sck);
else
do <= '1';
end if;
end loop;
end simple_sd_model;
-- purpose: Simple, incomplete, model of SPI Flash device
procedure simple_spi_flash_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
begin -- simple_spi_flash_model
di <= 'Z'; do <= 'Z';
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_spi_flash_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
response(23 downto 0) := command(31 downto 8);
else
response(23 downto 0) := command(23 downto 0);
end if;
index := 31 - conv_integer(response(1 downto 0)) * 8;
response(1 downto 0) := (others => '0');
while csn = '0' loop
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
response := response + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
received_command := '0';
else
do <= '1';
end if;
end loop;
end simple_spi_flash_model;
-- purpose: SPI memory device that reads input from prom.srec
procedure spi_memory_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : inout std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable address : std_logic_vector(23 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
file fload : text open read_mode is fname;
variable fline : line;
variable fchar : character;
variable rtype : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(31 downto 0);
variable rlen : std_logic_vector(7 downto 0);
variable rdata : std_logic_vector(0 to 127);
variable wordaddr : integer;
type mem_type is array (0 to 8388607) of std_logic_vector(31 downto 0);
variable mem : mem_type := (others => (others => '1'));
begin -- spi_memory_model
di <= 'Z'; do <= 'Z';
-- Load memory data from file
while not endfile(fload) loop
readline(fload, fline);
read(fline, fchar);
if fchar /= 'S' or fchar /= 's' then
hread(fline, rtype);
hread(fline, rlen);
raddr := (others => '0');
case rtype is
when "0001" =>
hread(fline, raddr(15 downto 0));
when "0010" =>
hread(fline, raddr(23 downto 0));
when "0011" =>
hread(fline, raddr);
raddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(fline, rdata);
for i in 0 to 3 loop
mem(conv_integer(raddr(31 downto 2)+i)) :=
rdata(i*32 to i*32+31);
end loop;
end if;
end loop;
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
address := command(31 downto 8);
else
address := command(23 downto 0);
end if;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received address: " &
tost(address));
if memoffset /= 0 then
Print(time'image(now) & ": spi_memory_model: address after removed offset " &
tost(address-memoffset));
end if;
end if;
if memoffset /= 0 then
address := address - memoffset;
end if;
index := 31 - conv_integer(address(1 downto 0)) * 8;
while csn = '0' loop
response := mem(conv_integer(address(23 downto 2)));
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: responding with data: " &
tost(response(index downto 0)));
end if;
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
address := address + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
do <= 'Z';
received_command := '0';
else
do <= 'Z';
end if;
end loop;
end spi_memory_model;
signal vdd : std_ulogic := '1';
signal gnd : std_ulogic := '0';
begin -- sim
-- ftype0: if ftype = 0 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : s25fl064a
-- generic map (tdevice_PU => 1 us,
-- TimingChecksOn => true,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (SCK => sck, SI => di, CSNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, SO => do);
-- end generate ftype0;
ftype1: if ftype = 1 generate
csn <= 'H';
di <= 'Z';
simple_sd_model(debug, sck, di, do, csn, sd_cmd_timeout, sd_data_timeout);
end generate ftype1;
-- ftype2: if ftype = 2 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : m25p80
-- generic map (TimingChecksOn => false,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (C => sck, D => di, SNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, Q => do);
-- end generate ftype2;
ftype3: if ftype = 3 generate
csn <= 'Z';
simple_spi_flash_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
end generate ftype3;
ftype4: if ftype = 4 generate
spi_memory_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
csn <= 'Z';
end generate ftype4;
notsupported: if ftype > 4 generate
assert false report "spi_flash: no model" severity failure;
end generate notsupported;
end sim;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000011110000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNI2J5SAO3 is
Begin
-- Constant
output <= "0000000011110000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000011110000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNI2J5SAO3 is
Begin
-- Constant
output <= "0000000011110000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNI2J5SAO3 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000011110000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNI2J5SAO3 is
Begin
-- Constant
output <= "0000000011110000";
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:38 10/17/2014
-- Design Name:
-- Module Name: fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm is
Port ( clk : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC);
end fsm;
architecture Behavioral of fsm is
signal output : std_logic;
begin
process (clk)
begin
if clk'event and clk='1' then
if (J = '0' and K = '0') then
output <= output;
elsif (J = '1' and K = '0') then
output <= '1';
elsif (J = '0' and K = '1') then
output <= '0';
elsif (J = '1' and K = '1') then
output <= not(output);
end if;
end if;
Q <= output;
end process;
end Behavioral; |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux2x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux2x1_8_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux2x1_8_0_0;
ARCHITECTURE RAT_Mux2x1_8_0_0_arch OF RAT_Mux2x1_8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux2x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux2x1_8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "Mux2x1_8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux2x1_8_0_0_arch : ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux2x1_8,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux2x1_8
PORT MAP (
A => A,
B => B,
SEL => SEL,
X => X
);
END RAT_Mux2x1_8_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux2x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux2x1_8_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux2x1_8_0_0;
ARCHITECTURE RAT_Mux2x1_8_0_0_arch OF RAT_Mux2x1_8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux2x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux2x1_8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "Mux2x1_8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux2x1_8_0_0_arch : ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux2x1_8,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux2x1_8
PORT MAP (
A => A,
B => B,
SEL => SEL,
X => X
);
END RAT_Mux2x1_8_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity pintoggler is
port (
clk_50 : in std_logic;
data : out std_logic_vector(15 downto 0);
addr : out std_logic_vector(15 downto 0);
div : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of pintoggler is
signal counter : integer := 0;
signal toggler : std_logic_vector(15 downto 0) := (others => '0');
constant clk_ticks : integer := 5000000;
begin
data <= toggler;
addr <= toggler;
count: process (clk_50)
begin
if (rising_edge(clk_50)) then
if ((counter mod clk_ticks) = 0) then toggler(0) <= not toggler(0); end if;
if ((counter mod (clk_ticks/2)) = 0) then toggler(1) <= not toggler(1); end if;
if ((counter mod (clk_ticks/4)) = 0) then toggler(2) <= not toggler(2); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(3) <= not toggler(3); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(4) <= not toggler(4); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(5) <= not toggler(5); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(6) <= not toggler(6); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(7) <= not toggler(7); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(8) <= not toggler(8); end if;
if ((counter mod (clk_ticks/512)) = 0) then toggler(9) <= not toggler(9); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(10) <= not toggler(10); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(11) <= not toggler(11); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(12) <= not toggler(12); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(13) <= not toggler(13); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(14) <= not toggler(14); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(15) <= not toggler(15); end if;
if (counter > clk_ticks) then
counter <= 0;
else
counter <= (counter + 1);
end if;
end if;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
ENTITY debouncer IS
PORT (
Clk : IN STD_LOGIC;
SW : IN STD_LOGIC; -- sw input
Vsync : in std_logic;
SWout : OUT STD_LOGIC;
Aclr : out std_logic
);
END debouncer;
ARCHITECTURE clean_pulse OF debouncer IS
signal cnt : natural range 0 to 6;
signal cnt1 : natural range 0 to 6; -- makes switch momentary action for about 2 seconds
signal reset : std_logic:='0';
signal reset1 : std_logic:='0';
signal q: std_logic;
signal qout: std_logic;
signal carry: std_logic;
signal carry1: std_logic :='1'; -- ovflo from count1 for monostable action on switch input
signal clr3: std_logic;
signal SWbar: std_logic;
component dff port(d,clk,clrn,prn:in std_logic; q:out std_logic);end component;
BEGIN
u1: reset <= SWbar xnor q;
u2: dff port map(SWbar,carry,'1','1',q);
u3: dff port map('1',reset1,clr3,'1',qout);
SWbar <= not SW;
Swout <= qout; -- was not q;
reset1 <= not q; -- enable 2nd counter
clr3<= carry1 ; -- assume Trained pulse is always longer than a FRAME period*******
---------------------------------------------------------------
CLOCK: PROCESS (Clk, reset)
BEGIN
if reset = '1' then
cnt <= 0;
elsif (clk'EVENT and Clk = '1') then
cnt <= cnt + 1;
end if;
end process CLOCK;
---------------------------------------------------------------
AclrPULSE: process (cnt,q)
begin
if (cnt = 1) and (q='1') then
Aclr <= '1';
else
Aclr <='0';
end if;
end process AclrPULSE;
---------------------------------------------------------------
carryPULSE: process (cnt)
begin
if (cnt = 3) then
carry <= '1';
else
carry <='0';
end if;
end process carryPULSE;
---------------------------------------------------------------
CLOCK1: PROCESS (Clk, reset1)
BEGIN
if (reset1='0') then
cnt1 <= 0;
elsif (clk'EVENT and Clk = '1') then
cnt1 <= cnt1 + 1;
if cnt1 = 4 then
carry1 <='0';
else
carry1 <='1';
end if;
end if;
end process CLOCK1;
---------------------------------------------------------------
END clean_pulse; |
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGProgrammerPack is
-- JTAG Programming Instruction (Page 311 Table 131)
constant CPrgComdRgLength : positive := 15;
-- ---------------------------------------------------------------------------------------------------
-- 1a. Chip erase
constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000";
constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000"
constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- 1b. Poll for chip erase complete
constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- ---------------------------------------------------------------------------------------------------
-- 2a. Enter Flash Write
constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000";
-- 2b. Load Address High Byte (+ 8 Bit)
constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 2c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 2d. Load Data Low Byte (+ 8 Bit)
constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 2e. Load Data High Byte (+ 8 Bit)
constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111";
-- 2f. Latch Data
constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2g. Write Flash Page
constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2h. Poll for Page Write complete
constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 3a. Enter Flash Read
constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010";
-- 3b. Load Address High Byte (+ 8 Bit)
constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 3c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 3d. Read Data Low and High Byte
constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 4a. Enter EEPROM Write
constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001";
-- 4b. Load Address High Byte (+ 8 Bit)
constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 4c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 4d. Load Data Byte (+ 8 Bit)
constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 4e. Latch Data
constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 4f. Write EEPROM Page
constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 4g. Poll for Page Write complete
constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 5a. Enter EEPROM Read
constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011";
-- 5b. Load Address High Byte (+ 8 Bit)
constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 5c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 5d. Read Data Byte
constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011";
constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 6a. Enter Fuse Write
constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000";
-- 6b. Load Data Low Byte(6) (+ 8 Bit)
constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6c. Write Fuse Extended byte
constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000";
constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 6d. Poll for Fuse Write complete
constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6e. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6f. Write Fuse High byte
constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6g. Poll for Fuse Write complete
constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6h. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6i. Write Fuse Low byte
constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 6j. Poll for Fuse Write complete
constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 7a. Enter Lock bit Write
constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000";
-- 7b. Load Data Byte (+6 Bit)
constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111";
-- 7c. Write Lock bits
constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 7d. Poll for Lock bit Write complete
constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 8a. Enter Fuse/Lock bit Read
constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100";
-- 8b. Read Extended Fuse Byte
constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 8c. Read Fuse High Byte
constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000";
-- 8d. Read Fuse Low Byte
constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 8e. Read Lock bits
constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
--8f. Read Fuses and Lock bits 0111010000000
constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 9a. Enter Signature Byte Read 0100010001000
constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 9b. Load Address Byte (+ 8 Bit)
constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 9c. Read Signature Byte
constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 10a. Enter Calibration Byte Read
constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 10b. Load Address Byte (+ 8 Bit)
constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 10c. Read Calibration Byte
constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 11a. Load No Operation Command
constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000";
constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
end JTAGProgrammerPack;
|
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGProgrammerPack is
-- JTAG Programming Instruction (Page 311 Table 131)
constant CPrgComdRgLength : positive := 15;
-- ---------------------------------------------------------------------------------------------------
-- 1a. Chip erase
constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000";
constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000"
constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- 1b. Poll for chip erase complete
constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- ---------------------------------------------------------------------------------------------------
-- 2a. Enter Flash Write
constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000";
-- 2b. Load Address High Byte (+ 8 Bit)
constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 2c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 2d. Load Data Low Byte (+ 8 Bit)
constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 2e. Load Data High Byte (+ 8 Bit)
constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111";
-- 2f. Latch Data
constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2g. Write Flash Page
constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2h. Poll for Page Write complete
constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 3a. Enter Flash Read
constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010";
-- 3b. Load Address High Byte (+ 8 Bit)
constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 3c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 3d. Read Data Low and High Byte
constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 4a. Enter EEPROM Write
constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001";
-- 4b. Load Address High Byte (+ 8 Bit)
constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 4c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 4d. Load Data Byte (+ 8 Bit)
constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 4e. Latch Data
constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 4f. Write EEPROM Page
constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 4g. Poll for Page Write complete
constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 5a. Enter EEPROM Read
constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011";
-- 5b. Load Address High Byte (+ 8 Bit)
constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 5c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 5d. Read Data Byte
constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011";
constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 6a. Enter Fuse Write
constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000";
-- 6b. Load Data Low Byte(6) (+ 8 Bit)
constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6c. Write Fuse Extended byte
constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000";
constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 6d. Poll for Fuse Write complete
constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6e. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6f. Write Fuse High byte
constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6g. Poll for Fuse Write complete
constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6h. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6i. Write Fuse Low byte
constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 6j. Poll for Fuse Write complete
constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 7a. Enter Lock bit Write
constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000";
-- 7b. Load Data Byte (+6 Bit)
constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111";
-- 7c. Write Lock bits
constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 7d. Poll for Lock bit Write complete
constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 8a. Enter Fuse/Lock bit Read
constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100";
-- 8b. Read Extended Fuse Byte
constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 8c. Read Fuse High Byte
constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000";
-- 8d. Read Fuse Low Byte
constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 8e. Read Lock bits
constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
--8f. Read Fuses and Lock bits 0111010000000
constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 9a. Enter Signature Byte Read 0100010001000
constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 9b. Load Address Byte (+ 8 Bit)
constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 9c. Read Signature Byte
constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 10a. Enter Calibration Byte Read
constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 10b. Load Address Byte (+ 8 Bit)
constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 10c. Read Calibration Byte
constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 11a. Load No Operation Command
constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000";
constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
end JTAGProgrammerPack;
|
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGProgrammerPack is
-- JTAG Programming Instruction (Page 311 Table 131)
constant CPrgComdRgLength : positive := 15;
-- ---------------------------------------------------------------------------------------------------
-- 1a. Chip erase
constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000";
constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000"
constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- 1b. Poll for chip erase complete
constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- ---------------------------------------------------------------------------------------------------
-- 2a. Enter Flash Write
constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000";
-- 2b. Load Address High Byte (+ 8 Bit)
constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 2c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 2d. Load Data Low Byte (+ 8 Bit)
constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 2e. Load Data High Byte (+ 8 Bit)
constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111";
-- 2f. Latch Data
constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2g. Write Flash Page
constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2h. Poll for Page Write complete
constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 3a. Enter Flash Read
constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010";
-- 3b. Load Address High Byte (+ 8 Bit)
constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 3c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 3d. Read Data Low and High Byte
constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 4a. Enter EEPROM Write
constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001";
-- 4b. Load Address High Byte (+ 8 Bit)
constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 4c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 4d. Load Data Byte (+ 8 Bit)
constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 4e. Latch Data
constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 4f. Write EEPROM Page
constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 4g. Poll for Page Write complete
constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 5a. Enter EEPROM Read
constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011";
-- 5b. Load Address High Byte (+ 8 Bit)
constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 5c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 5d. Read Data Byte
constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011";
constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 6a. Enter Fuse Write
constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000";
-- 6b. Load Data Low Byte(6) (+ 8 Bit)
constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6c. Write Fuse Extended byte
constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000";
constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 6d. Poll for Fuse Write complete
constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6e. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6f. Write Fuse High byte
constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6g. Poll for Fuse Write complete
constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6h. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6i. Write Fuse Low byte
constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 6j. Poll for Fuse Write complete
constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 7a. Enter Lock bit Write
constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000";
-- 7b. Load Data Byte (+6 Bit)
constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111";
-- 7c. Write Lock bits
constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 7d. Poll for Lock bit Write complete
constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 8a. Enter Fuse/Lock bit Read
constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100";
-- 8b. Read Extended Fuse Byte
constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 8c. Read Fuse High Byte
constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000";
-- 8d. Read Fuse Low Byte
constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 8e. Read Lock bits
constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
--8f. Read Fuses and Lock bits 0111010000000
constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 9a. Enter Signature Byte Read 0100010001000
constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 9b. Load Address Byte (+ 8 Bit)
constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 9c. Read Signature Byte
constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 10a. Enter Calibration Byte Read
constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 10b. Load Address Byte (+ 8 Bit)
constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 10c. Read Calibration Byte
constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 11a. Load No Operation Command
constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000";
constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
end JTAGProgrammerPack;
|
--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGProgrammerPack is
-- JTAG Programming Instruction (Page 311 Table 131)
constant CPrgComdRgLength : positive := 15;
-- ---------------------------------------------------------------------------------------------------
-- 1a. Chip erase
constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000";
constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000"
constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- 1b. Poll for chip erase complete
constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- ---------------------------------------------------------------------------------------------------
-- 2a. Enter Flash Write
constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000";
-- 2b. Load Address High Byte (+ 8 Bit)
constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 2c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 2d. Load Data Low Byte (+ 8 Bit)
constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 2e. Load Data High Byte (+ 8 Bit)
constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111";
-- 2f. Latch Data
constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2g. Write Flash Page
constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2h. Poll for Page Write complete
constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 3a. Enter Flash Read
constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010";
-- 3b. Load Address High Byte (+ 8 Bit)
constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 3c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 3d. Read Data Low and High Byte
constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 4a. Enter EEPROM Write
constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001";
-- 4b. Load Address High Byte (+ 8 Bit)
constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 4c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 4d. Load Data Byte (+ 8 Bit)
constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 4e. Latch Data
constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 4f. Write EEPROM Page
constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 4g. Poll for Page Write complete
constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 5a. Enter EEPROM Read
constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011";
-- 5b. Load Address High Byte (+ 8 Bit)
constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 5c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 5d. Read Data Byte
constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011";
constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 6a. Enter Fuse Write
constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000";
-- 6b. Load Data Low Byte(6) (+ 8 Bit)
constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6c. Write Fuse Extended byte
constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000";
constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 6d. Poll for Fuse Write complete
constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6e. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6f. Write Fuse High byte
constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6g. Poll for Fuse Write complete
constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6h. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6i. Write Fuse Low byte
constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 6j. Poll for Fuse Write complete
constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 7a. Enter Lock bit Write
constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000";
-- 7b. Load Data Byte (+6 Bit)
constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111";
-- 7c. Write Lock bits
constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 7d. Poll for Lock bit Write complete
constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 8a. Enter Fuse/Lock bit Read
constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100";
-- 8b. Read Extended Fuse Byte
constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 8c. Read Fuse High Byte
constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000";
-- 8d. Read Fuse Low Byte
constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 8e. Read Lock bits
constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
--8f. Read Fuses and Lock bits 0111010000000
constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 9a. Enter Signature Byte Read 0100010001000
constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 9b. Load Address Byte (+ 8 Bit)
constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 9c. Read Signature Byte
constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 10a. Enter Calibration Byte Read
constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 10b. Load Address Byte (+ 8 Bit)
constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 10c. Read Calibration Byte
constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 11a. Load No Operation Command
constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000";
constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
end JTAGProgrammerPack;
|
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