content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_transitionrow is
end tb_transitionrow;
architecture behavior of tb_transitionrow is
constant TotalInputWidth : integer := 10;
constant MyInputWidth : integer := 5;
constant StateWidth : integer := 5;
constant OutputWidth : integer := 7;
constant ConfigLength : integer := CalcTRConfigLength(StateWidth,TotalInputWidth,MyInputWidth,OutputWidth);
-- Attention: don't make symmetric values because otherwise we can't find
-- problems with the order
constant CfgOurState : std_logic_vector(StateWidth-1 downto 0) := "10111";
-- constant CfgInputSelect : std_logic_vector(TotalInputWidth-1 downto 0) := "1001110010";
-- constant CfgInputPattern : std_logic_vector(2**MyInputWidth-1 downto 0) := "00000010000010000000000000000000";
constant CfgNextState : std_logic_vector(StateWidth-1 downto 0) := "01011";
constant CfgOutput : std_logic_vector(OutputWidth-1 downto 0) := "1100110";
constant ConfigBitStream : std_logic_vector(ConfigLength-1 downto 0)
:= GenTRConfigBitStream(StateWidth,TotalInputWidth,MyInputWidth,OutputWidth,
"1xx001xx1x,1xx100xx1x",CfgOurState,CfgNextState,CfgOutput);
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n_i : std_logic;
signal Input_i : std_logic_vector(TotalInputWidth-1 downto 0);
signal State_i : std_logic_vector(StateWidth-1 downto 0);
signal Match_o : std_logic;
signal NextState_o : std_logic_vector(StateWidth-1 downto 0);
signal Output_o : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
-- purpose: Set inputs and check outputs
procedure CheckTransitionRow (
constant Input : in std_logic_vector(TotalInputWidth-1 downto 0);
constant State : in std_logic_vector(StateWidth-1 downto 0);
constant Match : in std_logic;
constant NextState : in std_logic_vector(StateWidth-1 downto 0);
constant Output : in std_logic_vector(OutputWidth-1 downto 0);
signal Input_i : out std_logic_vector(TotalInputWidth-1 downto 0);
signal State_i : out std_logic_vector(StateWidth-1 downto 0);
signal Match_o : in std_logic;
signal NextState_o : in std_logic_vector(StateWidth-1 downto 0);
signal Output_o : in std_logic_vector(OutputWidth-1 downto 0)
) is
variable l : line;
begin -- CheckTransitionRow
Input_i <= Input;
State_i <= State;
write(l,string'("Input = "));
write(l,Input);
write(l,string'(", State = "));
write(l,State);
wait for CheckOutputDelay;
if CheckStdLogic (Match_o, Match, "Match") and
CheckStdLogicVector(NextState_o,NextState,"NextState") and
CheckStdLogicVector(Output_o, Output, "Output") then
write(l,string'(": OK!"));
end if;
writeline(std.textio.output,l);
wait for SetupNextInputDelay;
end CheckTransitionRow;
begin -- behavior
TransitionRow_1: TransitionRow
generic map (
TotalInputWidth => TotalInputWidth,
MyInputWidth => MyInputWidth,
StateWidth => StateWidth,
OutputWidth => OutputWidth)
port map (
Reset_n_i => Reset_n_i,
Input_i => Input_i,
State_i => State_i,
Match_o => Match_o,
NextState_o => NextState_o,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
Check: process
begin -- process Check
Input_i <= (others => '0');
State_i <= (others => '0');
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
CfgMode_i <= '1';
CfgShift_i <= '1';
for i in 0 to ConfigLength-1 loop
CfgDataIn_i <= ConfigBitStream(i);
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CfgClk_i <= '0';
wait for CfgClkHalfPeriode;
end loop; -- i
CfgMode_i <= '0';
CfgShift_i <= '0';
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- CfgInputSelect = "1001110010" -> 1,4,5,6,9 are sensitive
-- CfgInputPattern = "00000010000010000000000000000000"; -> 19 = 10011, 25 = 11001
-- -> 1xx001xx1x, 1xx100xx1x
-- Test with wrong current states and wrong inputs
for i in 0 to 2**StateWidth-1 loop
if i /= conv_integer(CfgOurState) then
CheckTransitionRow("0000000000",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111111111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1000010011",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1101000010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
end if;
end loop; -- i
-- Test matching state but wrong inputs
CheckTransitionRow("0000000000",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111111111",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1000110010",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001100010",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
-- Test wrong current states but matching inputs
CheckTransitionRow("1000010010","00000",'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010","00000",'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
for i in 0 to 2**StateWidth-1 loop
if i /= conv_integer(CfgOurState) then
CheckTransitionRow("1000010010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1110011111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111001111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
end if;
end loop; -- i
-- Test matching state and inputs
CheckTransitionRow("1000010010",CfgOurState,'1',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010",CfgOurState,'1',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process Check;
end behavior;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_mii_data : std_logic;
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(4 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal configuration_finished : boolean;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal usb_clkout : std_logic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
-- GRUSB_DCL test signals
signal ddelay : std_ulogic := '0';
signal dstart : std_ulogic := '0';
signal drw : std_ulogic;
signal daddr : std_logic_vector(31 downto 0);
signal dlen : std_logic_vector(14 downto 0);
signal ddi : grusb_dcl_debug_data;
signal ddone : std_ulogic;
signal ddo : grusb_dcl_debug_data;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal txp_eth, txn_eth : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false;
autonegotiation : integer := 1
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(4 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
usb_refclk_opt : in std_logic;
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
emdio : inout std_logic;
emdc : out std_ulogic;
eint : in std_ulogic;
erst : out std_ulogic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(3 downto 0) <= "0000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL,
autonegotiation => 0
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
usb_refclk_opt => '0',
usb_clkout => usb_clkout,
usb_d => usb_d,
usb_nxt => usb_nxt,
usb_stp => usb_stp,
usb_dir => usb_dir,
usb_resetn => usb_resetn,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
txp => txp_eth,
txn => txn_eth,
rxp => txp_eth,
rxn => txn_eth,
emdio => phy_mdio,
emdc => phy_mdc,
eint => '0',
erst => OPEN,
can_txd => OPEN,
can_rxd => "0",
spi_data_out => '0',
spi_data_in => OPEN,
spi_data_cs_b => OPEN,
spi_clk => OPEN
);
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(dsurst, phy_mdio, OPEN , OPEN , OPEN ,
OPEN , OPEN , OPEN , OPEN , "00000000",
'0', '0', phy_mdc, clkethp);
end generate;
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 26, fname => promfile)
port map (address(25 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory model instantiation
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_SERIES7 = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
usbdevsim: if (CFG_GRUSBDC = 1) generate
u0: grusbdcsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir);
end generate usbdevsim;
usb_dclsim: if (CFG_GRUSB_DCL = 1) generate
u0: grusb_dclsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
ddelay, dstart, drw, daddr, dlen, ddi, ddone, ddo);
usb_dcl_proc : process
begin
wait for 10 ns;
Print("GRUSB_DCL test started");
wait until rising_edge(ddone);
-- Write 128 bytes to memory
daddr <= X"40000000";
dlen <= conv_std_logic_vector(32,15);
for i in 0 to 127 loop
ddi(i) <= conv_std_logic_vector(i+8,8);
end loop; -- i
grusb_dcl_write(usb_clkout, drw, dstart, ddone);
-- Read back written data
grusb_dcl_read(usb_clkout, drw, dstart, ddone);
-- Compare data
for i in 0 to 127 loop
if ddo(i) /= ddi(i) then
Print("ERROR: Data mismatch using GRUSB_DCL");
end if;
end loop;
Print("GRUSB_DCL test finished");
wait;
end process;
end generate usb_dclsim;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(4) <= '0';
wait for 2500 ns;
if (USE_MIG_INTERFACE_MODEL /= true) then
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
end if;
dsurst <= '1';
switch(4) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
--
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity VIDEO_zpuino_wb_char_ram_8x8_sp is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0)
);
end entity VIDEO_zpuino_wb_char_ram_8x8_sp;
architecture behave of VIDEO_zpuino_wb_char_ram_8x8_sp is
subtype ramword is std_logic_vector(7 downto 0);
type ramtype is array(0 to 2047) of ramword;
shared variable charram: ramtype := (
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);
signal selected: std_logic;
--signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_dat_o(31 downto 8) <= (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o<='0';
if selected='1' then
if wb_we_i='1' then
charram(conv_integer(wb_adr_i(12 downto 2))):=wb_dat_i(7 downto 0);
end if;
wb_dat_o(7 downto 0) <= charram(conv_integer(wb_adr_i(12 downto 2)));
wb_ack_o<='1';
end if;
end if;
end process;
end behave;
|
-----------------------------------------------------------------------------------
--! @file sha1_core.vhd
--! @brief SHA-1 CORE MODULE :
--! @version 0.9.0
--! @date 2012/12/20
--! @author Ichiro Kawazome <ichiro_k@ca2.so-net.ne.jp>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library IKWZM_SECURE_HASH;
use IKWZM_SECURE_HASH.SHA1.HASH_BITS;
-----------------------------------------------------------------------------------
--! @brief SHA-1 計算モジュール.
-----------------------------------------------------------------------------------
entity SHA1_CORE is
generic (
SYMBOL_BITS : --! @brief INPUT SYMBOL BITS :
--! 入力データの１シンボルのビット数を指定する.
integer := 8;
SYMBOLS : --! @brief INPUT SYMBOL SIZE :
--! 入力データのシンボル数を指定する.
integer := 4;
REVERSE : --! @brief INPUT SYMBOL REVERSE :
--! 入力データのシンボルのビット並びを逆にするかどうかを指定する.
integer := 1;
WORDS : --! @brief WORD SIZE :
--! 一度に処理するワード数を指定する.
integer := 1;
BLOCK_GAP : --! @brief BLOCK GAP CYCLE :
--! １ブロック(16word)処理する毎に挿入するギャップのサイクル
--! 数を指定する.
--! サイクル数分だけスループットが落ちるが、動作周波数が上が
--! る可能性がある.
integer := 1
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
I_DATA : --! @brief INPUT SYMBOL DATA :
in std_logic_vector(SYMBOL_BITS*SYMBOLS-1 downto 0);
I_ENA : --! @brief INPUT SYMBOL DATA ENABLE :
in std_logic_vector( SYMBOLS-1 downto 0);
I_DONE : --! @brief INPUT SYMBOL DATA DONE :
in std_logic;
I_LAST : --! @brief INPUT SYMBOL DATA LAST :
in std_logic;
I_VAL : --! @brief INPUT SYMBOL DATA VALID :
in std_logic;
I_RDY : --! @brief INPUT SYMBOL DATA READY :
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT WORD DATA :
out std_logic_vector(HASH_BITS-1 downto 0);
O_VAL : --! @brief OUTPUT WORD VALID :
out std_logic;
O_RDY : --! @brief OUTPUT WORD READY :
in std_logic
);
end SHA1_CORE;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library IKWZM_SECURE_HASH;
use IKWZM_SECURE_HASH.SHA1.WORD_BITS;
use IKWZM_SECURE_HASH.SHA1.SHA_PRE_PROC;
use IKWZM_SECURE_HASH.SHA1.SHA1_PROC;
architecture RTL of SHA1_CORE is
-------------------------------------------------------------------------------
-- 内部信号
-------------------------------------------------------------------------------
signal m_word : std_logic_vector(WORD_BITS*WORDS-1 downto 0);
signal m_done : std_logic;
signal m_valid : std_logic;
signal m_ready : std_logic;
begin
-------------------------------------------------------------------------------
-- 入力処理(パディング、入力ビット数の付加).
-------------------------------------------------------------------------------
PRE_PROC: SHA_PRE_PROC --
generic map( --
WORD_BITS => 32 , --
WORDS => WORDS , --
SYMBOL_BITS => SYMBOL_BITS , --
SYMBOLS => SYMBOLS , --
REVERSE => REVERSE --
) --
port map ( --
CLK => CLK , -- In :
RST => RST , -- In :
CLR => CLR , -- In :
I_DATA => I_DATA , -- In :
I_ENA => I_ENA , -- In :
I_DONE => I_DONE , -- In :
I_LAST => I_LAST , -- In :
I_VAL => I_VAL , -- In :
I_RDY => I_RDY , -- Out :
M_DATA => m_word , -- Out :
M_DONE => m_done , -- Out :
M_VAL => m_valid , -- Out :
M_RDY => m_ready -- In :
);
-------------------------------------------------------------------------------
-- Digestの計算.
-------------------------------------------------------------------------------
PROC: SHA1_PROC --
generic map ( --
WORDS => WORDS , --
PIPELINE => 1 , --
BLOCK_GAP => BLOCK_GAP --
) --
port map ( --
CLK => CLK , -- In :
RST => RST , -- In :
CLR => CLR , -- In :
M_DATA => m_word , -- In :
M_DONE => m_done , -- In :
M_VAL => m_valid , -- In :
M_RDY => m_ready , -- Out :
O_DATA => O_DATA , -- Out :
O_VAL => O_VAL , -- Out :
O_RDY => O_RDY -- In :
);
end RTL;
|
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-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
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-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY fir_lp_800kHz IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END fir_lp_800kHz;
ARCHITECTURE fir_lp_800kHz_arch OF fir_lp_800kHz IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_lp_800kHz_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(111 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "fir_lp_800kHz",
C_COEF_FILE => "fir_lp_800kHz.mif",
C_COEF_FILE_LINES => 1024,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 16,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 1024,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "32",
C_OPTIMIZATION => 2046,
C_DATA_PATH_WIDTHS => "16,16,16,16",
C_DATA_IP_PATH_WIDTHS => "16,16",
C_DATA_PX_PATH_WIDTHS => "16,16",
C_DATA_WIDTH => 16,
C_COEF_PATH_WIDTHS => "12,13,12,13",
C_COEF_WIDTH => 25,
C_DATA_PATH_SRC => "0,0,2,2",
C_COEF_PATH_SRC => "0,1,0,1",
C_DATA_PATH_SIGN => "0,0,0,0",
C_COEF_PATH_SIGN => "1,1,1,1",
C_ACCUM_PATH_WIDTHS => "37,38,37,38",
C_OUTPUT_WIDTH => 50,
C_OUTPUT_PATH_WIDTHS => "50,50",
C_ACCUM_OP_PATH_WIDTHS => "50,50",
C_EXT_MULT_CNFG => "0,1,0,12;2,3,0,12",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 32,
C_OPT_MADDS => "none;none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 16,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 44,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 32,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 112,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END fir_lp_800kHz_arch;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_COMPLEX package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to clarify such semantics and
-- provide a guideline for implementations to verify their
-- implementation of MATH_COMPLEX. Tool developers may choose to
-- implement the package body in the most efficient manner
-- available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end "/";
end MATH_COMPLEX;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_COMPLEX package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to clarify such semantics and
-- provide a guideline for implementations to verify their
-- implementation of MATH_COMPLEX. Tool developers may choose to
-- implement the package body in the most efficient manner
-- available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end "/";
end MATH_COMPLEX;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_COMPLEX package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to clarify such semantics and
-- provide a guideline for implementations to verify their
-- implementation of MATH_COMPLEX. Tool developers may choose to
-- implement the package body in the most efficient manner
-- available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end "/";
end MATH_COMPLEX;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_COMPLEX package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to clarify such semantics and
-- provide a guideline for implementations to verify their
-- implementation of MATH_COMPLEX. Tool developers may choose to
-- implement the package body in the most efficient manner
-- available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end "/";
end MATH_COMPLEX;
|
-- NEED RESULT: ARCH00527: f3 passed
-- NEED RESULT: ARCH00527: f4 passed
-- NEED RESULT: ARCH00527: f5 passed
-- NEED RESULT: ARCH00527: f6 passed
-- NEED RESULT: ARCH00527: Actual parameter list present in function calls passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00527
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.3 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00527)
-- ENT00527_Test_Bench(ARCH00527_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00527 of E00000 is
type arr_1 is array ( boolean range <> , integer range <> ) of bit ;
type arr_2 is array ( integer range <> ) of integer ;
type rec_1 is record
f1 : boolean ;
f2 : integer ;
end record ;
subtype st_arr_1 is arr_1 ( true downto false , 1 to 4 ) ;
subtype st_arr_2 is arr_2 ( -2 to 3 ) ;
begin
process
variable correct : boolean := true ;
function f1 ( p1 : boolean := false ;
p2 : integer := 3 ) return boolean is
begin
return p1 ;
end f1 ;
function f2 ( p1 : boolean := false ;
p2 : integer := 3 ) return integer is
begin
return p2 ;
end f2 ;
function f3 ( p1 : boolean := false ;
p2 : integer := 3 ) return arr_1 is
variable v_st_arr_1 : st_arr_1 ;
begin
v_st_arr_1(false, 1) := '1' ;
v_st_arr_1(false, 2) := '0' ;
v_st_arr_1(false, 3) := '1' ;
v_st_arr_1(false, 4) := '0' ;
v_st_arr_1(true, 1) := '0' ;
v_st_arr_1(true, 2) := '1' ;
v_st_arr_1(true, 3) := '0' ;
v_st_arr_1(true, 4) := '1' ;
return v_st_arr_1 ;
end f3 ;
function f4 ( p1 : boolean := false ;
p2 : integer := 3 ) return st_arr_1 is
begin
return (
( '0' , '1', '0', '1' ) ,
( '1' , '0', '1', '0' ) ) ;
end f4 ;
function f5 ( p1 : boolean := false ;
p2 : integer := 3 ) return st_arr_2 is
begin
return (-2, -1, 0, 1, 2, 3) ;
end f5 ;
function f6 ( p1 : boolean := false ;
p2 : integer := 3 ) return rec_1 is
begin
return (p1, p2) ;
end f6 ;
begin
correct := correct and
f3(false, 3)(false, 1) = '1' and
f3(false, 3)(false, 2) = '0' and
f3(false, 3)(false, 3) = '1' and
f3(false, 3)(false, 4) = '0' and
f3(false, 3)(true, 1) = '0' and
f3(false, 3)(true, 2) = '1' and
f3(false, 3)(true, 3) = '0' and
f3(false, 3)(true, 4) = '1' ;
test_report ( "ARCH00527" , "f3", correct);
correct := correct and
f4(false, 3)(false, 1) = '1' and
f4(false, 3)(false, 2) = '0' and
f4(false, 3)(false, 3) = '1' and
f4(false, 3)(false, 4) = '0' and
f4(false, 3)(true, 1) = '0' and
f4(false, 3)(true, 2) = '1' and
f4(false, 3)(true, 3) = '0' and
f4(false, 3)(true, 4) = '1' ;
test_report ( "ARCH00527" , "f4", correct);
correct := correct and
f5(true, 0)(-2 to 3) = (-2, -1, 0, 1, 2, 3) ;
test_report ( "ARCH00527" , "f5", correct);
correct := correct and
f6(false, 3).f1 = false and f6(false, 3).f2 = 3 ;
test_report ( "ARCH00527" , "f6", correct);
test_report ( "ARCH00527" ,
"Actual parameter list present in function calls" ,
correct and f1(false, 53) = false and
f2(true, 3) = 3 ) ;
wait ;
end process ;
end ARCH00527 ;
--
entity ENT00527_Test_Bench is
end ENT00527_Test_Bench ;
architecture ARCH00527_Test_Bench of ENT00527_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00527 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00527_Test_Bench ;
--
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab8_new_lib;
CONFIGURATION Decoder_Structure_config OF Decoder IS
FOR Structure
FOR ALL : ALU_ROM
USE ENTITY lab8_new_lib.ALU_ROM(Behavior);
END FOR;
FOR ALL : Decode_ROM
USE ENTITY lab8_new_lib.Decode_ROM(Behavior);
END FOR;
FOR ALL : Reg
USE ENTITY lab8_new_lib.Reg(Behavior);
END FOR;
FOR ALL : SimpleMux2
USE ENTITY lab8_new_lib.SimpleMux2(Behavior);
END FOR;
FOR ALL : SimpleMux3
USE ENTITY lab8_new_lib.SimpleMux3(Behavior);
END FOR;
FOR ALL : SimpleMux4
USE ENTITY lab8_new_lib.SimpleMux4(Behavior);
END FOR;
END FOR;
END Decoder_Structure_config;
|
--
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@SynthWorks.com
-- Contributor(s):
-- Jim Lewis email: jim@SynthWorks.com
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 01/2020 2020.01 Updated Licenses to Apache
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max_c) return integer ;
--
-- ToTransaction and FromTransaction for _max provided to support a
-- common methodology, conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max) return integer ;
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector is
variable extA : std_logic_vector(Size downto 1) := (others => '0') ;
begin
extA(A'length downto 1) := A ;
return extA ;
end function Extend ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector is
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
return aA(Size-1 downto 0) ;
end function Reduce ;
-- SafeResize - handles std_logic_vector as unsigned
impure function SafeResize(A: std_logic_vector; Size : natural) return std_logic_vector is
variable Result : std_logic_vector(Size-1 downto 0) := (others => '0') ;
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
if A'length <= Size then
-- Extend A
Result(A'length-1 downto 0) := aA ;
else
-- Reduce A and Error if any extra bits of A are a '1'
AlertIf((OR aA(A'length-1 downto Size) = '1'), "ToTransaction/FromTransaction, threw away a 1") ;
Result := aA(Size-1 downto 0) ;
end if ;
return Result ;
end function SafeResize ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(A) ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(SafeResize(A, Size)) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector is
begin
return std_logic_vector(A) ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector is
begin
return SafeResize(std_logic_vector(A), Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
----------------------
-- Support for _max provided to support a common methodology,
-- conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max is
begin
return A ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max is
begin
return SafeResize(A, Size) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max is
begin
return std_logic_vector_max(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector is
begin
return A ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector is
begin
return SafeResize(A, Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench FIFO stream assembly: module fifo_ic_assembly.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo_ic_assembly_hwtb is
generic (
D_BITS : positive := 9; -- Data Width
A_BITS : positive := 9; -- Address Bits
G_BITS : positive := 1 -- Generation Guard Bits
);
port (
clk : in std_logic;
rst : in std_logic;
leds : out std_logic_vector(7 downto 0)
);
end entity fifo_ic_assembly_hwtb;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
architecture rtl of fifo_ic_assembly_hwtb is
constant SEQ : t_intvec := (1, 0, 2, 3, 5, 4, 7, 6, 8, 10, 9, 12, 11, 13, 15, 14);
-- DUT Connectivity
signal base : std_logic_vector(A_BITS-1 downto 0);
signal failed : std_logic;
signal addr : std_logic_vector(A_BITS-1 downto 0);
signal din : std_logic_vector(D_BITS-1 downto 0);
signal put : std_logic;
signal dout : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
signal got : std_logic;
-- Writer State
signal Ptr : unsigned(A_BITS-1 downto 0) := (others => '0');
alias Seg : unsigned(A_BITS-1 downto A_BITS-4) is Ptr(A_BITS-1 downto A_BITS-4);
alias Ofs : unsigned(A_BITS-5 downto 0) is Ptr(A_BITS-5 downto 0);
signal tmp : unsigned(A_BITS-1 downto 0);
-- Reader State
signal Count : unsigned(A_BITS-1 downto 0) := (others => '0');
signal Failure : std_logic_vector(1 downto 0) := "00";
begin
DUT: fifo_ic_assembly
generic map (
D_BITS => D_BITS,
A_BITS => A_BITS,
G_BITS => G_BITS
)
port map (
clk_wr => clk,
rst_wr => rst,
base => base,
failed => failed,
addr => addr,
din => din,
put => put,
clk_rd => clk,
rst_rd => rst,
dout => dout,
vld => vld,
got => got
);
-- Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ptr <= (others => '0');
elsif put = '1' then
Ptr <= Ptr + 1;
end if;
end if;
end process;
addr <= std_logic_vector(to_unsigned(SEQ(to_integer(Seg)), Seg'length) & Ofs);
din <= not addr(D_BITS-1 downto 0);
tmp <= unsigned(addr) - unsigned(base);
put <= '1' when tmp(A_BITS-1 downto A_BITS-G_BITS) = 0 else '0';
-- Reading Checker
got <= '1';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Count <= (others => '0');
Failure <= "00";
elsif vld = '1' then
if Count /= unsigned(not dout) then
Failure(0) <= '1';
end if;
if failed = '1' then
Failure(1) <= '1';
end if;
Count <= Count + 1;
end if;
end if;
end process;
-- Outputs
leds <= Failure & std_logic_vector(base(base'left downto base'left-5));
end rtl;
|
library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report 2start of tb" severity note;
for i in 0 to 10 loop
case i is
when 0 | 3 =>
for i,in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 =>ehav;
|
library verilog;
use verilog.vl_types.all;
entity EmitOneCH is
port(
Transmit_CLK : in vl_logic;
RX_Gate : in vl_logic;
EmitDelay : in vl_logic_vector(7 downto 0);
Emit_Width : in vl_logic_vector(6 downto 0);
TXP : out vl_logic;
TXN : out vl_logic
);
end EmitOneCH;
|
------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Waldemar Koprek, Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_common_array_pkg is
type t_aslv2 is array (natural range <>) of std_logic_vector( 1 downto 0);
type t_aslv3 is array (natural range <>) of std_logic_vector( 2 downto 0);
type t_aslv4 is array (natural range <>) of std_logic_vector( 3 downto 0);
type t_aslv5 is array (natural range <>) of std_logic_vector( 4 downto 0);
type t_aslv6 is array (natural range <>) of std_logic_vector( 5 downto 0);
type t_aslv7 is array (natural range <>) of std_logic_vector( 6 downto 0);
type t_aslv8 is array (natural range <>) of std_logic_vector( 7 downto 0);
type t_aslv9 is array (natural range <>) of std_logic_vector( 8 downto 0);
type t_aslv10 is array (natural range <>) of std_logic_vector( 9 downto 0);
type t_aslv11 is array (natural range <>) of std_logic_vector(10 downto 0);
type t_aslv12 is array (natural range <>) of std_logic_vector(11 downto 0);
type t_aslv13 is array (natural range <>) of std_logic_vector(12 downto 0);
type t_aslv14 is array (natural range <>) of std_logic_vector(13 downto 0);
type t_aslv15 is array (natural range <>) of std_logic_vector(14 downto 0);
type t_aslv16 is array (natural range <>) of std_logic_vector(15 downto 0);
type t_aslv17 is array (natural range <>) of std_logic_vector(16 downto 0);
type t_aslv18 is array (natural range <>) of std_logic_vector(17 downto 0);
type t_aslv19 is array (natural range <>) of std_logic_vector(18 downto 0);
type t_aslv20 is array (natural range <>) of std_logic_vector(19 downto 0);
type t_aslv21 is array (natural range <>) of std_logic_vector(20 downto 0);
type t_aslv22 is array (natural range <>) of std_logic_vector(21 downto 0);
type t_aslv23 is array (natural range <>) of std_logic_vector(22 downto 0);
type t_aslv24 is array (natural range <>) of std_logic_vector(23 downto 0);
type t_aslv25 is array (natural range <>) of std_logic_vector(24 downto 0);
type t_aslv26 is array (natural range <>) of std_logic_vector(25 downto 0);
type t_aslv27 is array (natural range <>) of std_logic_vector(26 downto 0);
type t_aslv28 is array (natural range <>) of std_logic_vector(27 downto 0);
type t_aslv29 is array (natural range <>) of std_logic_vector(28 downto 0);
type t_aslv30 is array (natural range <>) of std_logic_vector(29 downto 0);
type t_aslv32 is array (natural range <>) of std_logic_vector(31 downto 0);
type t_aslv36 is array (natural range <>) of std_logic_vector(35 downto 0);
type t_aslv48 is array (natural range <>) of std_logic_vector(47 downto 0);
type t_aslv64 is array (natural range <>) of std_logic_vector(63 downto 0);
type t_ainteger is array (natural range <>) of integer;
type t_areal is array (natural range <>) of real;
type t_abool is array (natural range <>) of boolean;
end psi_common_array_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TW_8254_CNT is
Port ( m_clk : in STD_LOGIC;
m_reset : in STD_LOGIC;
m_gate : in STD_LOGIC;
m_out : out STD_LOGIC;
m_data : in STD_LOGIC_VECTOR (7 downto 0);
m_cw : in std_logic;
m_wr_b : in STD_LOGIC);
end TW_8254_CNT;
architecture Behavioral of TW_8254_CNT is
signal s_cw : std_logic;
signal s_wr : std_logic;
signal s_out2 : std_logic;
signal s_out3 : std_logic;
signal s_gate : std_logic;
signal s_wr_M : std_logic;
signal s_wr_L : std_logic;
signal s_wr_LM : std_logic;
signal s_wr_wait : std_logic;
signal s_mode : std_logic; -- 0 : mode2, 1 : mode3
signal s_REG : std_logic_vector(15 downto 0);
signal s_CNT2 : std_logic_vector(15 downto 0);
signal s_CNT3_1 : std_logic_vector(15 downto 0);
signal s_CNT3_2 : std_logic_vector(15 downto 0);
signal s_CNT3_1_rst : STD_LOGIC_VECTOR(15 downto 0);
signal s_CNT3_2_rst : STD_LOGIC_VECTOR(15 downto 0);
signal s_even : std_logic;
signal s_CNT3 : std_logic_vector(15 downto 0);
signal s_CNT3_U : std_logic_vector(14 downto 0);
signal s_CNT3_D : std_logic_vector(14 downto 0);
signal s_CNT3_UD : std_logic;
signal s_temp1 : std_logic;
signal s_temp2 : std_logic;
constant c_0 : std_logic_vector(15 downto 0):=(others=>'0');
constant c_1 : std_logic_vector(15 downto 0):=(0=>'1',others=>'0');
constant c_1_2 : std_logic_vector(14 downto 0) :=(0=>'1',others=>'0');
constant c_0_2 : std_logic_vector(14 downto 0) :=(others=>'0');
begin
-- signal / port
s_gate <= m_gate;
s_cw <= m_cw;
m_out <= s_out2 when s_mode='0' and s_gate='1' else
s_out3 when s_mode='1' and s_gate='1' else '1';
s_wr <= not m_wr_b;
-- control LSB, MSB reg ( not for control word )
process(s_wr,m_reset)
begin
if m_reset='1' then
s_REG(15 downto 8) <= (8=>'1',others=>'0');
s_REG(7 downto 0) <= conv_std_logic_vector(4,8);
s_wr_wait <= '0';
elsif rising_edge(s_wr) then
if s_cw='0' then
s_wr_wait <='0';
if s_wr_L='1' and s_wr_LM='0' then
s_REG(7 downto 0) <= m_data;
elsif s_wr_M='1' and s_wr_LM='0' then
s_REG(15 downto 8) <= m_data;
elsif s_wr_LM='1' and s_wr_wait='0' then
s_REG(7 downto 0) <= m_data;
s_wr_wait<='1';
elsif s_wr_LM='1' and s_wr_wait='1' then
s_REG(15 downto 8) <= m_data;
end if;
end if;
end if;
end process;
-- control mode and write command
process(m_reset,s_wr)
begin
if m_reset='1' then
s_mode <= '0'; -- default mode : rate gen.
s_wr_L <='0';
s_wr_M <='0';
elsif rising_edge(s_wr) then
if s_cw='1' then
s_mode <= m_data(1);
s_wr_L <= m_data(4);
s_wr_M <= m_data(5);
end if;
end if;
end process;
s_wr_LM <= '1' when s_wr_L='1' and s_wr_M='1' else '0';
-----------------------------------------------------------------------------
-- MODE 2
process(m_reset,m_clk)
begin
if m_reset='1' then
s_CNT2 <= "0000000100000100";
elsif falling_edge(m_clk) then
if s_gate = '1' and s_mode='0' then
s_CNT2 <= s_CNT2 - '1' ;
if s_CNT2=c_1 then
s_CNT2<=s_REG;
end if;
end if;
end if;
end process;
s_out2 <= '0' when s_CNT2=c_1 OR (s_mode='0' and (s_REG=c_1 OR s_REG=c_0)) else '1';
------------------------------------------------------------------------------
-- MODE 3
s_CNT3_1 <= s_REG + '1';
s_CNT3_2 <= s_REG - '1';
s_CNT3_1_rst <= x"0105";
s_CNT3_2_rst <= x"0103";
s_even <= s_REG(0); -- 1 : odd, 0 : even
process(m_reset,m_clk)
begin
if falling_edge(m_clk) then
if m_reset='1' then
s_CNT3 <= x"0104";--s_REG;
s_CNT3_UD <= '1';
if s_even='1' then
s_CNT3_U <= s_CNT3_1_rst(15 downto 1);
s_CNT3_D <= s_CNT3_2_rst(15 downto 1);
else
s_CNT3_U <= ("000"&x"082");--s_REG(15 downto 1);
s_CNT3_D <= ("000"&x"082");--s_REG(15 downto 1);
end if;
elsif s_gate='1' and s_even='1' and s_mode='1' then -- odd
s_CNT3_D <= s_CNT3_D - 1;
s_CNT3_UD <='0';
if s_CNT3_D = c_1_2 and s_CNT3_U = c_0_2 then
s_CNT3_U <= s_CNT3_1(15 downto 1);
s_CNT3_D <= s_CNT3_2(15 downto 1);
elsif s_CNT3_D = c_1_2 then
s_CNT3_U <= s_CNT3_U - 1;
s_CNT3_D <= c_1_2(14 downto 0);
s_CNT3_UD <='1';
end if;
elsif s_gate='1' and s_even='0' and s_mode='1' then -- even
s_CNT3_D <= s_CNT3_D - 1;
s_CNT3_UD <='0';
if s_CNT3_U = c_0_2 then
s_CNT3_U <= s_REG(15 downto 1);
s_CNT3_D <= s_REG(15 downto 1);
elsif s_CNT3_D = c_1_2 then
s_CNT3_U <= s_CNT3_U - 1;
s_CNT3_D <= c_1_2;
s_CNT3_UD <='1';
end if;
end if;
end if;
end process;
s_out3 <= m_clk when ((s_REG=c_1 OR s_REG=c_0) and s_mode='1') else s_CNT3_UD;
end Behavioral;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file boundbox_big.vhd
--! @brief Computes the boundboxes of each label after equal labels matched
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
use IEEE.math_real.all;
--! The big version needs for each possible label a boundbox storage space
entity boundbox is
generic(
--! Max image
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT;
--! Only for compatibility purposes
G_MAX_BOUNDBOXES : NATURAL := div_ceil(C_MAX_IMAGE_WIDTH,2)+div_ceil(C_MAX_IMAGE_HEIGHT,2)
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! stall the output of bound box
stall_in : in STD_LOGIC;
--! High if the lable input valid
lbl_valid_in : in STD_LOGIC;
--! Input of Lables
label_in : in T_LABEL;
--! High if the boundbox output valid
box_valid_out : out STD_LOGIC;
--! output of bound box
box_out : out T_BOX;
--! high if all boxes are computed
box_done_out : out STD_LOGIC;
--! High if the memory free manager can't find fast new storage
--! The result of the bounding box are wrong
error_out : out STD_LOGIC;
--! width of the image at the input
img_width_in : in UNSIGNED(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in UNSIGNED(log2_ceil(G_MAX_IMG_HEIGHT) downto 0)
);
end entity boundbox;
--! @brief arc description
--! @details more detailed description
architecture boundbox_arc of boundbox is
-- Types --------------------------------------------------------------------
type T_BOX_STORE is array (2**T_LABEL'length - 1 downto 0) of T_BOX;
-- Constants ----------------------------------------------------------------
-- Signals ------------------------------------------------------------------
signal box_store_s : T_BOX_STORE;
signal box_used_s : unsigned(T_BOX_STORE'range);
signal col_cnt_s : UNSIGNED(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
signal row_cnt_s : UNSIGNED(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
signal next_chk_s : T_LABEL;
begin
box_done_out <= '1' when box_used_s = 0 else '0';
p_counter : process (clk_in, rst_in)
begin
if rst_in = '1' then
col_cnt_s <= (others => '0');
row_cnt_s <= (others => '0');
elsif rising_edge(clk_in) and rst_in = '0' then
if lbl_valid_in = '1' and stall_in = '0' then
if col_cnt_s = img_width_in - 1 then
col_cnt_s <= (others => '0');
row_cnt_s <= row_cnt_s + 1;
else
col_cnt_s <= col_cnt_s + 1;
end if;
end if;
end if;
end process p_counter;
p_box : process (clk_in, rst_in)
variable tmp_x_0_v : unsigned(log2_ceil(G_MAX_IMG_WIDTH)-1 downto 0);
variable tmp_y_0_v : unsigned(log2_ceil(G_MAX_IMG_HEIGHT)-1 downto 0);
variable tmp_x_1_v : unsigned(log2_ceil(G_MAX_IMG_WIDTH)-1 downto 0);
variable tmp_y_1_v : unsigned(log2_ceil(G_MAX_IMG_HEIGHT)-1 downto 0);
begin
if rst_in = '1' then
box_used_s <= (others => '0');
next_chk_s <= (others => '0');
error_out <= '0';
box_valid_out <= '0';
elsif rising_edge(clk_in) and rst_in = '0' then
if stall_in = '0' then
box_valid_out <= '0';
if lbl_valid_in = '1' and label_in /= C_UNLABELD then
--resize to map lable 256 to position 0
if box_used_s(to_integer(label_in)) = '0' then
-- first label of this box
-- mark heap position as inuse
box_used_s(to_integer(label_in)) <= '1';
-- store this pixel as the start of the box
box_store_s(to_integer(label_in))(T_X_END) <= col_cnt_s;
box_store_s(to_integer(label_in))(T_Y_END) <= resize(row_cnt_s, row_cnt_s'length-1);
box_store_s(to_integer(label_in))(T_X_START) <= col_cnt_s;
box_store_s(to_integer(label_in))(T_Y_START) <= resize(row_cnt_s, row_cnt_s'length-1);
else
-- the box of this label allready has stored a start point
-- x and y value of the start (0) can't be smaller
tmp_x_1_v := box_store_s(to_integer(label_in))(T_X_END);
tmp_y_1_v := box_store_s(to_integer(label_in))(T_Y_END);
tmp_x_0_v := box_store_s(to_integer(label_in))(T_X_START);
tmp_y_0_v := box_store_s(to_integer(label_in))(T_Y_START);
-- has the end point moved to the right?
if tmp_x_1_v < col_cnt_s then
tmp_x_1_v := col_cnt_s;
end if;
-- has the start point moved to the left?
if tmp_x_0_v > col_cnt_s then
tmp_x_0_v := col_cnt_s;
end if;
-- the y value need no check it can only be bigger or equals
tmp_y_1_v := resize(row_cnt_s, row_cnt_s'length-1);
-- write the new bounderies
box_store_s(to_integer(label_in))(T_X_END) <= tmp_x_1_v;
box_store_s(to_integer(label_in))(T_Y_END) <= tmp_y_1_v;
box_store_s(to_integer(label_in))(T_X_START) <= tmp_x_0_v;
box_store_s(to_integer(label_in))(T_Y_START) <= tmp_y_0_v;
end if;
else
--TODO: use the biggest possible lable to reduce the check_s range
next_chk_s <= next_chk_s + 1;
if box_used_s(to_integer(next_chk_s)) = '1' then
tmp_x_1_v := box_store_s(to_integer(next_chk_s))(T_X_END);
tmp_y_1_v := box_store_s(to_integer(next_chk_s))(T_Y_END);
if (tmp_y_1_v < row_cnt_s and resize(tmp_x_1_v, tmp_x_1_v'length+1) + 2 < col_cnt_s) or -- last lable one row before and in x at least one pixle space
tmp_y_1_v + 1 < row_cnt_s or -- one row without a pixle of this lable
(row_cnt_s = img_height_in - 1 and resize(tmp_x_1_v, tmp_x_1_v'length+1) + 1 < col_cnt_s) or -- last line
(row_cnt_s = img_height_in and col_cnt_s >= 0) -- end of image
then
-- output the processed box
box_out <= box_store_s(to_integer(next_chk_s));
box_valid_out <= '1';
-- mark heap memory as free
box_used_s(to_integer(next_chk_s)) <= '0';
end if;
end if;
end if;
end if;
end if;
end process p_box;
end architecture boundbox_arc;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
entity ParamPow is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic;
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamPow;
architecture RTL of ParamPow is
signal output_internal : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_internal_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal done_next : std_logic;
begin
process(A,start,init_model,count,X,output_internal,init_model)
variable Sel : integer;
begin
output_internal_next <= output_internal;
count_next <= count;
done_next <= '0';
if init_model = '1' then
output_internal_next <= to_sfixed(0,BIT_TOP, BIT_BOTTOM);
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '1';
else
if start = '1' then
output_internal_next <= A;
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
if To_slv ( resize (count - X ,BIT_TOP, BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '1' then
count_next <= resize (count + to_sfixed(1,1,0) ,BIT_TOP, BIT_BOTTOM);
output_internal_next <= resize (output_internal * A,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
output_internal_next <= output_internal;
count_next <= count;
done_next <= '1';
end if;
end if;
end if;
end process;
process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_internal <= output_internal_next;
count <= count_next;
Done <= done_next;
end if;
end process;
Output <= output_internal;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
entity ParamPow is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic;
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamPow;
architecture RTL of ParamPow is
signal output_internal : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_internal_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal done_next : std_logic;
begin
process(A,start,init_model,count,X,output_internal,init_model)
variable Sel : integer;
begin
output_internal_next <= output_internal;
count_next <= count;
done_next <= '0';
if init_model = '1' then
output_internal_next <= to_sfixed(0,BIT_TOP, BIT_BOTTOM);
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '1';
else
if start = '1' then
output_internal_next <= A;
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
if To_slv ( resize (count - X ,BIT_TOP, BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '1' then
count_next <= resize (count + to_sfixed(1,1,0) ,BIT_TOP, BIT_BOTTOM);
output_internal_next <= resize (output_internal * A,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
output_internal_next <= output_internal;
count_next <= count;
done_next <= '1';
end if;
end if;
end if;
end process;
process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_internal <= output_internal_next;
count <= count_next;
Done <= done_next;
end if;
end process;
Output <= output_internal;
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p22n01i00925ent IS
END c10s03b00x00p22n01i00925ent;
ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
constant x : integer := 3;
procedure xxx is
constant x : integer := 5;
variable y : bit;
begin
if x > 3 then
y := '1';
else
y := '0';
end if;
assert NOT( y='1' )
report "***PASSED TEST: c10s03b00x00p22n01i00925"
severity NOTE;
assert ( y='1' )
report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p22n01i00925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p22n01i00925ent IS
END c10s03b00x00p22n01i00925ent;
ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
constant x : integer := 3;
procedure xxx is
constant x : integer := 5;
variable y : bit;
begin
if x > 3 then
y := '1';
else
y := '0';
end if;
assert NOT( y='1' )
report "***PASSED TEST: c10s03b00x00p22n01i00925"
severity NOTE;
assert ( y='1' )
report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p22n01i00925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p22n01i00925ent IS
END c10s03b00x00p22n01i00925ent;
ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
constant x : integer := 3;
procedure xxx is
constant x : integer := 5;
variable y : bit;
begin
if x > 3 then
y := '1';
else
y := '0';
end if;
assert NOT( y='1' )
report "***PASSED TEST: c10s03b00x00p22n01i00925"
severity NOTE;
assert ( y='1' )
report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p22n01i00925arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_dcache
-- File: mmu_dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libmmu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end;
architecture rtl of mmu_dcache is
constant M_EN : boolean := (mmuen = 1);
constant DSNOOP2 : integer := dsnoop mod 4;
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant M_TLB_TYPE : integer range 0 to 1 := -- either split or combined
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(1, 2));
constant M_TLB_FASTWRITE : integer range 0 to 3 := -- fast writebuffer
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(2, 2));
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(ilramstart, 8);
constant DIR_BITS : integer := log2x(DSETS);
constant bend : std_logic_vector(4 downto 2) := "101";
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory,
sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
lock2 : std_ulogic;
smask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, rburst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
efaddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- error flush address
dstate : dstatetype; -- FSM vector
hit, valid : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
bmexc : std_ulogic; -- latched mexc from burst read
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
flushl2 : std_ulogic;
tadj, dadj, sadj : std_logic_vector(1 downto 0);
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
dlock : std_logic;
su : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
reqst : std_logic;
set : integer range 0 to DSETS-1;
noflush : std_logic;
cmiss : std_ulogic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag address
mask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
snhit : std_logic_vector(0 to MAXSETS-1);
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0);
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else
xset(0) := xlru(0);
end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset: std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'),
data1 => (others => '0'),
data2 => (others => '0'),
size => (others => '0'),
asi => (others => '0'),
read => '0',
lock => '0',
lock2 => '0',
smask => (others => '0')
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : dcache_control_type := (
read => '0',
size => (others => '0'),
req => '0',
burst => '0',
rburst => '0',
holdn => '1',
nomds => '0',
stpend => '0',
xaddress => (others => '0'),
paddress => (others => '0'),
faddr => (others => '0'),
efaddr => (others => '0'),
dstate => idle,
hit => '0',
valid => '0',
flush => '0',
flush2 => '1',
mexc => '0',
bmexc => '0',
wb => write_buffer_none,
asi => (others => '0'),
icenable => '0',
rndcnt => (others => '0'),
setrepl => (others => '0'),
lrr => '0',
dsuset => (others => '0'),
lock => '0',
lramrd => '0',
ilramen => '0',
cctrl => cctrl_none,
cctrlwr => '0',
flushl2 => '0',
tadj => (others => '0'),
dadj => (others => '0'),
sadj => (others => '0'),
mmctrl1 => mmctrl_type1_none,
mmctrl1wr => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
vaddr => (others => '0'),
ready => '0',
wbinit => '0',
cache => '0',
dlock => '0',
su => '0',
trans_op => '0',
flush_op => '0',
diag_op => '0',
reqst => '0',
set => 0,
noflush => '0',
cmiss => '0'
);
constant SRES : snoop_reg_type := (
snoop => '0',
addr => (others => '0'),
mask => (others => '0'),
snhit => (others => '0')
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
begin
dctrl : process(rst, r, rs, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco, ahbso)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable flushaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set, eset : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validraw : std_logic_vector(0 to DSETS-1);
variable validv, hitv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe, snhit : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable lrusetval: std_logic_vector(SETBITS-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable cache : std_ulogic;
variable ctx : ctxdatatype;
variable flushl : std_ulogic;
variable flushlv : std_logic_vector(0 to MAXSETS-1);
variable miscdata : std_logic_vector(31 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable su : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
variable pagesize : integer range 0 to 3;
variable mhold : std_logic; -- MMU hold
variable wbhold : std_logic; -- write-buffer hold
begin
-- init local variables
v := r; vs := rs; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; v.flush2 := r.flush;
snhit := (others => '0'); v.cmiss := '0'; mhold := '0'; wbhold := '0';
pagesize := MMU_getpagesize(mmupgsz,r.mmctrl1);
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
v.mmctrl1wr := '0';
tagclear := '0'; paddress := r.paddress;
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
paddress := r.xaddress;
end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0;
vs.snoop := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
flushaddr := r.xaddress(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); hitv := (others => '0'); cache := '0';
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
ctx := (others => (others => '0'));
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
v.flushl2 := dci.flushl and not r.flush;
newptag := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => '0'); -- scanen no longer handled here
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP2 /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and (not mcdo.bg or r.mmctrl1.e)) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
if (r.mmctrl1.e = '1') and (mcdo.bg = '1') then vs.mask := r.wb.smask;
else vs.mask := (others => '1'); end if;
end if;
if DSNOOP /= 0 then
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
end if;
for i in DSETS-1 downto 0 loop
if ((rs.snoop and not (r.flush or r.flush2)) = '1') then
if (DSNOOP2 /= 0) and (rs.mask(i) = '1') and
((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW))
)
then
if DSNOOPSEP then flushaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
else snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); end if;
snoopwe := '1'; snoopset := i; snhit(i) := '1';
end if;
end if;
end loop;
end if;
vs.snhit := snhit; -- not needed, debug only
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read and not r.dlock;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read and not dci.lock;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
if (dsnoop = 6) and (r.cctrl.dsnoop = '0') then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
senable := enable;
end if;
lrusetval := lru_set(rl.lru(conv_integer(maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- generate cache hit and valid bits
if (r.mmctrl1.e = '0') then hcache := ahb_slv_dec_cache(dci.maddress, ahbso, cached);
else hcache := '1'; end if;
forcemiss := (not dci.asi(3)) or dci.lock;
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or
((r.flush or r.flush2) = '1')
then hcache := '0'; end if;
hit := '0'; set := 0;
for i in DSETS-1 downto 0 loop
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := '1'; end if;
validv(i) := hcache and hitv(i) and (not r.flush) and (not r.flush2) and dcramov.tag(i)(dlinesize-1);
validraw(i) := dcramov.tag(i)(dlinesize-1);
end loop;
if drepl = dir then
hit := hitv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1))) and not r.flush and (not r.flush2);
valid := validv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1)));
else
hit := orv(hitv) and not r.flush and (not r.flush2);
valid := orv(validv);
end if;
-- force cache miss if mmu-enabled but off or BYPASS, or on flush
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or ((r.flush or r.flush2) = '1')
then hit := '0'; end if;
if DSETS > 1 then
if drepl = dir then
set := conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1));
else
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then set := i; end if;
end loop;
end if;
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
v.su := dci.msu; v.set := set;
v.valid := valid; v.dlock := dci.lock;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(LINE_HIGH downto 2) := r.wb.addr(LINE_HIGH downto 2) + 1;
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (mcdo.grant and r.req) = '1' then v.wb.lock2 := r.wb.lock; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (r.cctrlwr and not dci.nullify) = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.noflush := dci.maddress(30);
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
if (memtech = rhlib18t) and (r.xaddress(7 downto 2) = "000001") and (dci.read = '0') then
v.tadj := dci.maddress(5 downto 4);
v.sadj := dci.maddress(3 downto 2);
v.dadj := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
v.nomds := r.nomds and not eholdn; v.bmexc := '0';
if ((r.reqst = '0') and (r.stpend = '0')) or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock and not dci.nullify and ico.hold;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and
((M_TLB_FASTWRITE /= 0) or ((dci.enaddr and eholdn and dci.lock and not dci.read) = '1')))
then
if (dci.enaddr and eholdn and dci.lock and not dci.read) = '1' then -- skip address translation on store in LDST
v.wb.addr := r.wb.addr(31 downto 8) & dci.maddress(7 downto 0);
newptag := r.wb.addr(TAG_HIGH downto TAG_LOW);
else
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (dci.read and hcache and andv(r.cctrl.dcs)) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => if M_EN then rdatasel := dctx; end if;
when ASI_MMUREGS | ASI_MMUREGS_V8 => if M_EN then rdatasel := misc; end if;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
v.cctrlwr := not dci.read and not (dci.dsuen and not dci.eenaddr);
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
if M_EN then
if (dsu = 0) or dci.dsuen = '0' then
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
end if;
end if;
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := asi_idtag; v.ilramen := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') then -- No access on flush
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if DSNOOPSEP then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if dci.read = '0' then iflush := '1'; end if;
if M_EN then
if dci.read = '0' then
flush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE | ASI_MMUFLUSHPROBE_V8 =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
v.rburst := hcache and (andv(r.cctrl.dcs) or andv(dci.size)); -- and not forcemiss;
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if not ((hit and valid and not forcemiss) = '1') then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cmiss := hcache;
v.cache := hcache and andv(r.cctrl.dcs);
if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
-- cache disabled if mmu-enabled but off or BYPASS
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then
v.req := '1'; v.burst := v.rburst;
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.wbinit := '1'; -- wb init in idle
v.burst := v.rburst;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
cache := '1';
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := dblwrite; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1'))
then -- wait for store queue
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0'; v.wb.read := r.wb.read;
end if;
else
-- ## mmu case > false and
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and
(((mmudco.wbtransdata.accexc = '0') and (M_TLB_FASTWRITE /= 0)) or (dci.lock = '1'))
then
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
-- ## < mmu case
end if;
end if;
if (hit and valid) = '1' then -- write hit
dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
eset := set;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (andv(validraw) = '0') and (drepl /= dir) and false then
for i in DSETS-1 downto 0 loop
if validraw(i) = '0' then eset := i; end if;
end loop;
v.setrepl := conv_std_logic_vector(eset, SETBITS);
elsif ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := dci.maddress(OFFSET_HIGH+log2x(DSETS) downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lrusetval;
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
v.rburst := r.rburst and v.cache;
if r.wbinit = '1' then
v.wb.addr := v.paddress; --mmudco.transdata.data;
v.req := '1';
v.burst := v.rburst;
if v.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
end if;
end if;
end if;
mhold := '1';
end if;
when wread => -- read miss, wait for memory data
if drepl=lru and mcdo.ready='0' and r.hit='0' then
v.setrepl := lrusetval;
end if;
taddr := r.wb.addr(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if (r.rburst) = '1' then
if (mcdo.grant = '1') and ((r.cctrl.dcs = "01") or
((r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) and not
((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')))) then
v.burst := '0';
else v.burst := r.burst; end if;
end if;
if mcdo.ready = '1' then
if (r.cache or r.hit) = '0' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
else
if r.wb.addr(LINE_HIGH downto LINE_LOW) = r.xaddress(LINE_HIGH downto LINE_LOW) then
mds := '0';
end if;
end if;
dwrite := r.cache; rdatasel := memory;
mexc := mcdo.mexc;
v.bmexc := r.bmexc or mcdo.mexc or dci.flushl;
if r.req = '0' then
twrite := r.cache; tagclear := v.bmexc;
if (((dci.enaddr and not mds) = '1') or (dci.flushl = '1') or ((dci.enaddr and twrite) = '1'))
and ((r.cctrl.dcs(0) = '1') or (dlram = 1))
then v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; v.holdn := '1'; end if;
else v.nomds := not r.cache; end if;
tpwrite := twrite;
end if;
v.mexc := mcdo.mexc and not r.rburst; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.wb.addr := paddress;
v.wb.size := r.size;
v.burst := r.rburst;
if r.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
wbhold := '1';
end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
if (r.flushl2 and dci.enaddr) = '1' then
v.holdn := '0';
else
v.dstate := idle;
end if;
when dblwrite => -- second part of double store cycle
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if r.hit = '1' then dwrite := r.valid; end if;
v.wb.data2 := dci.edata;
end if;
if (dci.flushl and ico.hold) = '1' then
v.dstate := loadpend; v.holdn := '0';
elsif ico.hold = '0' then v.reqst := '0';
else v.dstate := idle; end if;
when asi_idtag => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; v.ilramen := '0';
if (dsu = 0) or ((dsu = 1) and (dci.dsuen = '0')) then
mds := not r.read;
end if;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
if (dci.nullify = '0')
then
v.req := '1'; v.stpend := '1';
else v.reqst := '1'; end if;
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
if (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := r.valid;
end if;
end if;
end if;
end if;
end if;
mhold := '1';
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (
(dci.lock = '1')) and (dci.nullify = '1') then
v.dstate := idle; v.wb.lock := '0';
elsif ((v.ready or (mcdo.ready and not r.req)) = '1') or (
(dci.lock = '1')) then -- store queue emptied
if (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := r.valid;
end if;
v.dstate := idle;
v.burst := r.size(1) and r.size(0);
if (dci.nullify = '0') then v.reqst := '1'; end if;
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
v.wb.smask := (others => '1');
if r.hit = '1' then v.wb.smask(r.set) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
wbhold := '1';
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
v.req := v.req or v.reqst; v.stpend := v.stpend or v.reqst; v.reqst := '0';
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if DSNOOPSEP then snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
tdiagwrite := dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag; senable := (others => '1');
when ASI_DDATA =>
if M_EN then
ddiagwrite := dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
end if;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
rdatasel := misc;
when others =>
end case;
end if;
-- read
if M_EN then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0001";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(MMCTRL_TLBSEP) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
miscdata(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D) := conv_std_logic_vector(pagesize,2); -- r.mmctrl1.pagesize;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
end if;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
if M_EN then set := 0; rdatav(0) := miscdata; end if;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0;
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" =>
rdatav(0)(30) := r.noflush;
rdatav(0)(23) := r.cctrl.dsnoop;
if dsnoop > 4 then rdatav(0)(17) := '1'; end if;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "01" =>
rdatav(0)(7 downto 0) := "00" & r.tadj & r.sadj & r.dadj;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, mmuen);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
if r.wb.read = '0' then
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
else
v.burst := ((r.rburst) and not andv(r.wb.addr(LINE_HIGH downto LINE_LOW))) or
(not r.rburst and r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2));
end if;
v.wb.lock := r.wb.lock2;
end if;
-- Generate new valid bits
if r.flush = '1' then twrite := '0'; dwrite := '0'; end if;
vmask := (others => (others => '1'));
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if r.mmctrl1wr = '1' then
case r.xaddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
v.mmctrl1.e := dci.maddress(MMCTRL_E);
v.mmctrl1.nf := dci.maddress(MMCTRL_NF);
v.mmctrl1.pso := dci.maddress(MMCTRL_PSO);
v.mmctrl1.tlbdis := dci.maddress(MMCTRL_TLBDIS);
v.mmctrl1.pagesize := dci.maddress(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := dci.maddress(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := dci.maddress(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
if ((dci.flush or dci.flushl or flush) = '1') and (dcen /= 0) then
v.flush := not r.noflush; v.faddr := (others => '0');
if (dci.flushl = '1') then v.flush := '1'; v.faddr := r.efaddr; end if;
end if;
if eholdn = '1' then v.efaddr := v.xaddress(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag := (others => '0');
if DSNOOPSEP then flushaddr := r.faddr; end if;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if ((r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) or r.flushl2) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop
ddatainv(i) := mcdo.data;
end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if DSNOOPSEP then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if DSNOOPSEP then
ctpwrite := (others => '1');
end if;
end if;
csnoopwe := (others => '0'); flushl := '0';
flushlv := (others => r.flush);
if (snoopwe = '1') then csnoopwe := snhit; end if;
if DSNOOPSEP then
csnoopwe := csnoopwe or ctwrite;
flushlv := flushlv or snhit; -- flush tag on snoop hit
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.tadj := (others => '0'); v.dadj := (others => '0');
v.sadj := (others => '0');
--if M_EN then
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.pagesize := (others => '0');
--end if;
v.mmctrl1.bar := (others => '0');
v.faddr := (others => '0');
v.reqst := '0';
v.cache := '0'; v.wb.lock := '0'; v.wb.lock2 := '0';
v.wb.data1 := (others => '0'); v.wb.data2 := (others => '0');
v.noflush := '0'; v.mexc := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
if not M_EN then v.mmctrl1 := mmctrl_type1_none; end if; -- kill MMU regs if not enabled
-- Drive signals
c <= v; cs <= vs; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag; -- virtual tag
dcrami.ptag <= ptag; -- physical tag
dcrami.ctx <= ctx; -- context
dcrami.tenable <= enable; -- virtual tag ram enable
dcrami.twrite <= ctwrite; -- virtual tag ram write (port 1)
dcrami.tpwrite <= ctpwrite; -- virtual tag ram write (port 2)
dcrami.flush <= flushlv;
dcrami.senable <= senable; -- physical tag ram enable
dcrami.swrite <= csnoopwe; -- physical tag ram write
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.faddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.faddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= flushaddr;
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr);
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= r.cache;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.cache <= cache;
dco.hit <= r.hit;
if r.dstate = idle then dco.idle <= not r.stpend;
else dco.idle <= '0'; end if;
dco.cstat.cmiss <= r.cmiss;
dco.cstat.chold <= not r.holdn;
dco.cstat.tmiss <= mmudco.tlbmiss;
dco.cstat.mhold <= mhold;
dco.wbhold <= wbhold;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin
if rising_edge(sclk) then
rs <= cs;
if RESET_ALL and (rst = '0') then rs <= SRES; end if;
end if;
end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.addr <= (others => '0');
rs.snhit <= (others => '0'); rs.mask <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then rl <= LRES; end if;
end if;
end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 ways"
severity failure;
assert not ((DSETS = 3) and (drepl = dir)) report
"Wrong data cache configuration detected: Direct replacement requires 2 or 4 ways"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy status registers
---------------------------------------------------------------------------------------
-- File : ../../GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd
-- Author : auto-generated by wbgen2 from ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- Created : Wed Nov 10 14:42:59 2010
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_stat_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 1' in reg: 'DUMMY_1'
dummy_stat_reg_1_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_stat_reg_2_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_stat_reg_3_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for switch status' in reg: 'DUMMY_SWITCH'
dummy_stat_reg_switch_i : in std_logic_vector(31 downto 0)
);
end dummy_stat_regs_wb_slave;
architecture syn of dummy_stat_regs_wb_slave is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_switch_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Dummy register 1
-- Dummy register 2
-- Dummy register 3
-- Dummy register for switch status
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy status registers
---------------------------------------------------------------------------------------
-- File : ../../GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd
-- Author : auto-generated by wbgen2 from ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- Created : Wed Nov 10 14:42:59 2010
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_stat_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_stat_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 1' in reg: 'DUMMY_1'
dummy_stat_reg_1_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_stat_reg_2_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_stat_reg_3_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for switch status' in reg: 'DUMMY_SWITCH'
dummy_stat_reg_switch_i : in std_logic_vector(31 downto 0)
);
end dummy_stat_regs_wb_slave;
architecture syn of dummy_stat_regs_wb_slave is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= dummy_stat_reg_switch_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Dummy register 1
-- Dummy register 2
-- Dummy register 3
-- Dummy register for switch status
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02167ent IS
END c07s02b04x00p22n01i02167ent;
ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_2 is character_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : character_2;
variable l_operand : character := 'A';
variable r_operand : character := 'z';
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('A', 'z')) and (result(1)='A'))
report "***PASSED TEST: c07s02b04x00p22n01i02167"
severity NOTE;
assert ((result = ('A', 'z')) and (result(1)='A'))
report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02167arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02167ent IS
END c07s02b04x00p22n01i02167ent;
ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_2 is character_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : character_2;
variable l_operand : character := 'A';
variable r_operand : character := 'z';
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('A', 'z')) and (result(1)='A'))
report "***PASSED TEST: c07s02b04x00p22n01i02167"
severity NOTE;
assert ((result = ('A', 'z')) and (result(1)='A'))
report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02167arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02167ent IS
END c07s02b04x00p22n01i02167ent;
ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_2 is character_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : character_2;
variable l_operand : character := 'A';
variable r_operand : character := 'z';
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('A', 'z')) and (result(1)='A'))
report "***PASSED TEST: c07s02b04x00p22n01i02167"
severity NOTE;
assert ((result = ('A', 'z')) and (result(1)='A'))
report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02167arch;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
use IEEE.Std_Logic_arith.all;
entity Cont_asc is
port ( clk, rst: in std_logic;--a lógica de reset do contador ascendente está definida no topo contador.
s: out std_logic_vector(15 downto 0)
);
end Cont_asc;
architecture Cont_asc_estr of Cont_asc is
signal s0, s1, m0, m1: std_logic_vector(3 downto 0):="0000";--signals definidos para receber a contagem de segundos e minutos.
begin
s <= m1 & m0 & s1 & s0;--signals concatenados atribuídos a saída "s" do contador.
process (clk,rst)
begin
if rst = '0' then
s0 <= "0000";
s1 <= "0000";
m0 <= "0000";
m1 <= "0000";
elsif (clk'event and clk = '1') then
s0 <= s0+'1';
if s0 = "1001" then
s0 <= "0000";
s1 <= s1+1;
if s1 = "0101" then
s1 <= "0000";
m0 <= m0+1;
if m0 = "1001" then
m0 <= "0000";
m1 <= m1+1;
if m1 = "0101" then
m1 <= "0000";
end if;
end if;
end if;
end if;
end if;
end process;
end Cont_asc_estr; |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
use axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_9.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
use axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_9.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
use axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_9.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
use axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_9.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_transform:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_transform_0_1 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_transform_0_1;
ARCHITECTURE system_vga_transform_0_1_arch OF system_vga_transform_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_transform_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT vga_transform IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_transform;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_transform
PORT MAP (
clk => clk,
enable => enable,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out
);
END system_vga_transform_0_1_arch;
|
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end component;
component round_f
port(enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END component;
component reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- intermediate key (in words)
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
signal ct_in_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_in_1 : std_logic_vector(63 downto 0);
signal ct_in_2 : std_logic_vector(63 downto 0);
signal ct_in_3 : std_logic_vector(63 downto 0);
signal ct_in_4 : std_logic_vector(63 downto 0);
signal ct_in_5 : std_logic_vector(63 downto 0);
signal ct_in_6 : std_logic_vector(63 downto 0);
signal ct_in_7 : std_logic_vector(63 downto 0);
signal ct_in_8 : std_logic_vector(63 downto 0);
signal ct_in_9 : std_logic_vector(63 downto 0);
signal ct_in_10 : std_logic_vector(63 downto 0);
signal ct_in_11 : std_logic_vector(63 downto 0);
signal ct_in_12 : std_logic_vector(63 downto 0);
signal ct_in_13 : std_logic_vector(63 downto 0);
signal ct_in_14 : std_logic_vector(63 downto 0);
signal ct_in_15 : std_logic_vector(63 downto 0);
signal ct_in_16 : std_logic_vector(63 downto 0);
signal ct_in_17 : std_logic_vector(63 downto 0);
signal ct_in_18 : std_logic_vector(63 downto 0);
signal ct_in_19 : std_logic_vector(63 downto 0);
signal ct_in_20 : std_logic_vector(63 downto 0);
signal ct_in_21 : std_logic_vector(63 downto 0);
signal ct_in_22 : std_logic_vector(63 downto 0);
signal ct_in_23 : std_logic_vector(63 downto 0);
signal ct_in_24 : std_logic_vector(63 downto 0);
signal ct_in_25 : std_logic_vector(63 downto 0);
signal ct_in_26 : std_logic_vector(63 downto 0);
signal ct_in_27 : std_logic_vector(63 downto 0);
signal ct_in_28 : std_logic_vector(63 downto 0);
signal ct_in_29 : std_logic_vector(63 downto 0);
signal ct_in_30 : std_logic_vector(63 downto 0);
signal ct_in_31 : std_logic_vector(63 downto 0);
signal ct_in_32 : std_logic_vector(63 downto 0);
signal ct_in_33 : std_logic_vector(63 downto 0);
signal ct_in_34 : std_logic_vector(63 downto 0);
signal ct_in_35 : std_logic_vector(63 downto 0);
signal ct_in_36 : std_logic_vector(63 downto 0);
signal ct_in_37 : std_logic_vector(63 downto 0);
signal ct_in_38 : std_logic_vector(63 downto 0);
signal ct_in_39 : std_logic_vector(63 downto 0);
signal ct_in_40 : std_logic_vector(63 downto 0);
signal ct_in_41 : std_logic_vector(63 downto 0);
signal ct_in_42 : std_logic_vector(63 downto 0);
signal ct_in_43 : std_logic_vector(63 downto 0);
signal ct_out_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_out_1 : std_logic_vector(63 downto 0);
signal ct_out_2 : std_logic_vector(63 downto 0);
signal ct_out_3 : std_logic_vector(63 downto 0);
signal ct_out_4 : std_logic_vector(63 downto 0);
signal ct_out_5 : std_logic_vector(63 downto 0);
signal ct_out_6 : std_logic_vector(63 downto 0);
signal ct_out_7 : std_logic_vector(63 downto 0);
signal ct_out_8 : std_logic_vector(63 downto 0);
signal ct_out_9 : std_logic_vector(63 downto 0);
signal ct_out_10 : std_logic_vector(63 downto 0);
signal ct_out_11 : std_logic_vector(63 downto 0);
signal ct_out_12 : std_logic_vector(63 downto 0);
signal ct_out_13 : std_logic_vector(63 downto 0);
signal ct_out_14 : std_logic_vector(63 downto 0);
signal ct_out_15 : std_logic_vector(63 downto 0);
signal ct_out_16 : std_logic_vector(63 downto 0);
signal ct_out_17 : std_logic_vector(63 downto 0);
signal ct_out_18 : std_logic_vector(63 downto 0);
signal ct_out_19 : std_logic_vector(63 downto 0);
signal ct_out_20 : std_logic_vector(63 downto 0);
signal ct_out_21 : std_logic_vector(63 downto 0);
signal ct_out_22 : std_logic_vector(63 downto 0);
signal ct_out_23 : std_logic_vector(63 downto 0);
signal ct_out_24 : std_logic_vector(63 downto 0);
signal ct_out_25 : std_logic_vector(63 downto 0);
signal ct_out_26 : std_logic_vector(63 downto 0);
signal ct_out_27 : std_logic_vector(63 downto 0);
signal ct_out_28 : std_logic_vector(63 downto 0);
signal ct_out_29 : std_logic_vector(63 downto 0);
signal ct_out_30 : std_logic_vector(63 downto 0);
signal ct_out_31 : std_logic_vector(63 downto 0);
signal ct_out_32 : std_logic_vector(63 downto 0);
signal ct_out_33 : std_logic_vector(63 downto 0);
signal ct_out_34 : std_logic_vector(63 downto 0);
signal ct_out_35 : std_logic_vector(63 downto 0);
signal ct_out_36 : std_logic_vector(63 downto 0);
signal ct_out_37 : std_logic_vector(63 downto 0);
signal ct_out_38 : std_logic_vector(63 downto 0);
signal ct_out_39 : std_logic_vector(63 downto 0);
signal ct_out_40 : std_logic_vector(63 downto 0);
signal ct_out_41 : std_logic_vector(63 downto 0);
signal ct_out_42 : std_logic_vector(63 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (
key_s(0), key_s(1), key_s(2), key_s(3),
k_0, k_1, k_2, k_3, k_4, k_5, k_6, k_7, k_8, k_9, k_10,
k_11, k_12, k_13, k_14, k_15, k_16, k_17, k_18, k_19, k_20,
k_21, k_22, k_23, k_24, k_25, k_26, k_27, k_28, k_29, k_30,
k_31, k_32, k_33, k_34, k_35, k_36, k_37, k_38, k_39, k_40,
k_41, k_42, k_43);
-- Outer-round registers
REG_STAGE_0 : reg_64 port map (clk, rst, ct_in_0, ct_out_0);
REG_STAGE_1 : reg_64 port map (clk, rst, ct_in_1, ct_out_1);
REG_STAGE_2 : reg_64 port map (clk, rst, ct_in_2, ct_out_2);
REG_STAGE_3 : reg_64 port map (clk, rst, ct_in_3, ct_out_3);
REG_STAGE_4 : reg_64 port map (clk, rst, ct_in_4, ct_out_4);
REG_STAGE_5 : reg_64 port map (clk, rst, ct_in_5, ct_out_5);
REG_STAGE_6 : reg_64 port map (clk, rst, ct_in_6, ct_out_6);
REG_STAGE_7 : reg_64 port map (clk, rst, ct_in_7, ct_out_7);
REG_STAGE_8 : reg_64 port map (clk, rst, ct_in_8, ct_out_8);
REG_STAGE_9 : reg_64 port map (clk, rst, ct_in_9, ct_out_9);
REG_STAGE_10 : reg_64 port map (clk, rst, ct_in_10, ct_out_10);
REG_STAGE_11 : reg_64 port map (clk, rst, ct_in_11, ct_out_11);
REG_STAGE_12 : reg_64 port map (clk, rst, ct_in_12, ct_out_12);
REG_STAGE_13 : reg_64 port map (clk, rst, ct_in_13, ct_out_13);
REG_STAGE_14 : reg_64 port map (clk, rst, ct_in_14, ct_out_14);
REG_STAGE_15 : reg_64 port map (clk, rst, ct_in_15, ct_out_15);
REG_STAGE_16 : reg_64 port map (clk, rst, ct_in_16, ct_out_16);
REG_STAGE_17 : reg_64 port map (clk, rst, ct_in_17, ct_out_17);
REG_STAGE_18 : reg_64 port map (clk, rst, ct_in_18, ct_out_18);
REG_STAGE_19 : reg_64 port map (clk, rst, ct_in_19, ct_out_19);
REG_STAGE_20 : reg_64 port map (clk, rst, ct_in_20, ct_out_20);
REG_STAGE_21 : reg_64 port map (clk, rst, ct_in_21, ct_out_21);
REG_STAGE_22 : reg_64 port map (clk, rst, ct_in_22, ct_out_22);
REG_STAGE_23 : reg_64 port map (clk, rst, ct_in_23, ct_out_23);
REG_STAGE_24 : reg_64 port map (clk, rst, ct_in_24, ct_out_24);
REG_STAGE_25 : reg_64 port map (clk, rst, ct_in_25, ct_out_25);
REG_STAGE_26 : reg_64 port map (clk, rst, ct_in_26, ct_out_26);
REG_STAGE_27 : reg_64 port map (clk, rst, ct_in_27, ct_out_27);
REG_STAGE_28 : reg_64 port map (clk, rst, ct_in_28, ct_out_28);
REG_STAGE_29 : reg_64 port map (clk, rst, ct_in_29, ct_out_29);
REG_STAGE_30 : reg_64 port map (clk, rst, ct_in_30, ct_out_30);
REG_STAGE_31 : reg_64 port map (clk, rst, ct_in_31, ct_out_31);
REG_STAGE_32 : reg_64 port map (clk, rst, ct_in_32, ct_out_32);
REG_STAGE_33 : reg_64 port map (clk, rst, ct_in_33, ct_out_33);
REG_STAGE_34 : reg_64 port map (clk, rst, ct_in_34, ct_out_34);
REG_STAGE_35 : reg_64 port map (clk, rst, ct_in_35, ct_out_35);
REG_STAGE_36 : reg_64 port map (clk, rst, ct_in_36, ct_out_36);
REG_STAGE_37 : reg_64 port map (clk, rst, ct_in_37, ct_out_37);
REG_STAGE_38 : reg_64 port map (clk, rst, ct_in_38, ct_out_38);
REG_STAGE_39 : reg_64 port map (clk, rst, ct_in_39, ct_out_39);
REG_STAGE_40 : reg_64 port map (clk, rst, ct_in_40, ct_out_40);
REG_STAGE_41 : reg_64 port map (clk, rst, ct_in_41, ct_out_41);
REG_STAGE_42 : reg_64 port map (clk, rst, ct_in_42, ct_out_42);
-- round function combinatorial logic
ROUND_F_0 : round_f port map (enc, block_in, k_0, k_43, ct_in_0);
ROUND_F_1 : round_f port map (enc, ct_out_0, k_1, k_42, ct_in_1);
ROUND_F_2 : round_f port map (enc, ct_out_1, k_2, k_41, ct_in_2);
ROUND_F_3 : round_f port map (enc, ct_out_2, k_3, k_40, ct_in_3);
ROUND_F_4 : round_f port map (enc, ct_out_3, k_4, k_39, ct_in_4);
ROUND_F_5 : round_f port map (enc, ct_out_4, k_5, k_38, ct_in_5);
ROUND_F_6 : round_f port map (enc, ct_out_5, k_6, k_37, ct_in_6);
ROUND_F_7 : round_f port map (enc, ct_out_6, k_7, k_36, ct_in_7);
ROUND_F_8 : round_f port map (enc, ct_out_7, k_8, k_35, ct_in_8);
ROUND_F_9 : round_f port map (enc, ct_out_8, k_9, k_34, ct_in_9);
ROUND_F_10 : round_f port map (enc, ct_out_9, k_10, k_33, ct_in_10);
ROUND_F_11 : round_f port map (enc, ct_out_10, k_11, k_32, ct_in_11);
ROUND_F_12 : round_f port map (enc, ct_out_11, k_12, k_31, ct_in_12);
ROUND_F_13 : round_f port map (enc, ct_out_12, k_13, k_30, ct_in_13);
ROUND_F_14 : round_f port map (enc, ct_out_13, k_14, k_29, ct_in_14);
ROUND_F_15 : round_f port map (enc, ct_out_14, k_15, k_28, ct_in_15);
ROUND_F_16 : round_f port map (enc, ct_out_15, k_16, k_27, ct_in_16);
ROUND_F_17 : round_f port map (enc, ct_out_16, k_17, k_26, ct_in_17);
ROUND_F_18 : round_f port map (enc, ct_out_17, k_18, k_25, ct_in_18);
ROUND_F_19 : round_f port map (enc, ct_out_18, k_19, k_24, ct_in_19);
ROUND_F_20 : round_f port map (enc, ct_out_19, k_20, k_23, ct_in_20);
ROUND_F_21 : round_f port map (enc, ct_out_20, k_21, k_22, ct_in_21);
ROUND_F_22 : round_f port map (enc, ct_out_21, k_22, k_21, ct_in_22);
ROUND_F_23 : round_f port map (enc, ct_out_22, k_23, k_20, ct_in_23);
ROUND_F_24 : round_f port map (enc, ct_out_23, k_24, k_19, ct_in_24);
ROUND_F_25 : round_f port map (enc, ct_out_24, k_25, k_18, ct_in_25);
ROUND_F_26 : round_f port map (enc, ct_out_25, k_26, k_17, ct_in_26);
ROUND_F_27 : round_f port map (enc, ct_out_26, k_27, k_16, ct_in_27);
ROUND_F_28 : round_f port map (enc, ct_out_27, k_28, k_15, ct_in_28);
ROUND_F_29 : round_f port map (enc, ct_out_28, k_29, k_14, ct_in_29);
ROUND_F_30 : round_f port map (enc, ct_out_29, k_30, k_13, ct_in_30);
ROUND_F_31 : round_f port map (enc, ct_out_30, k_31, k_12, ct_in_31);
ROUND_F_32 : round_f port map (enc, ct_out_31, k_32, k_11, ct_in_32);
ROUND_F_33 : round_f port map (enc, ct_out_32, k_33, k_10, ct_in_33);
ROUND_F_34 : round_f port map (enc, ct_out_33, k_34, k_9, ct_in_34);
ROUND_F_35 : round_f port map (enc, ct_out_34, k_35, k_8, ct_in_35);
ROUND_F_36 : round_f port map (enc, ct_out_35, k_36, k_7, ct_in_36);
ROUND_F_37 : round_f port map (enc, ct_out_36, k_37, k_6, ct_in_37);
ROUND_F_38 : round_f port map (enc, ct_out_37, k_38, k_5, ct_in_38);
ROUND_F_39 : round_f port map (enc, ct_out_38, k_39, k_4, ct_in_39);
ROUND_F_40 : round_f port map (enc, ct_out_39, k_40, k_3, ct_in_40);
ROUND_F_41 : round_f port map (enc, ct_out_40, k_41, k_2, ct_in_41);
ROUND_F_42 : round_f port map (enc, ct_out_41, k_42, k_1, ct_in_42);
ROUND_F_43 : round_f port map (enc, ct_out_42, k_43, k_0, ct_in_43);
block_out <= ct_in_43;
-- SIMON Core
pr_smn : process(clk, rst, enc, key, key_s)
begin
-- no rst switch/phase distinction needed due to full unrolling of key schedule
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_GAUSS_COE_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF ROM_GAUSS_COE_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.ROM_GAUSS_COE_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9216)
`protect data_block
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9216)
`protect data_block
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9216)
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
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|
-- File name: tb_sbox.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: S-Box tester
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_sbox is
generic (
clk_per : time := 4 ns
);
end entity tb_sbox;
architecture test of tb_sbox is
signal clk : std_logic := '0';
signal lut_a, lut_b : byte;
signal data_a, data_b : byte;
signal pipe_a, pipe_b : byte;
signal stop : std_logic := '1';
signal gold : byte;
begin
lut : entity work.sbox(lut) port map (
clk => clk, a => lut_a, b => lut_b
);
data : entity work.sbox(dataflow) port map (
clk => clk, a => data_a, b => data_b
);
pipe : entity work.sbox(pipelined) port map (
clk => clk, a => pipe_a, b => pipe_b
);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
for i in 0 to 255 loop
lut_a <= to_unsigned(i, 8);
data_a <= to_unsigned(i, 8);
wait for 10 ns;
gold <= work.aes.sbox(i);
assert lut_b = work.aes.sbox(i);
assert data_b = work.aes.sbox(i);
end loop;
stop <= '0';
for i in 0 to 256 loop
if (i <= 255) then
pipe_a <= to_unsigned(i, 8);
end if;
wait for clk_per;
if (i >= 1) then
gold <= work.aes.sbox(i-1);
assert pipe_b = work.aes.sbox(i-1);
end if;
end loop;
stop <= '1';
wait;
end process;
end architecture test;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block1.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block1
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block1 IS
-- Signals
SIGNAL dout_5_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_5_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_5_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_5_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_5_re_signed <= signed(dout_5_re);
dout_5_im_signed <= signed(dout_5_im);
dout_13_re_signed <= signed(dout_13_re);
dout_13_im_signed <= signed(dout_13_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_5_re_signed, dout_5_im_signed,
dout_13_re_signed, dout_13_im_signed, dout_1_vld, rotate_5)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_5 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_5_re_signed, 18) + resize(dout_13_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_5_re_signed, 18) - resize(dout_13_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_5_im_signed, 18) + resize(dout_13_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_5_im_signed, 18) - resize(dout_13_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_5_re_signed, 18) + resize(dout_13_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_5_re_signed, 18) - resize(dout_13_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_5_im_signed, 18) + resize(dout_13_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_5_im_signed, 18) - resize(dout_13_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_5_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_5_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_6_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_6_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
dout_5_re_1 <= std_logic_vector(dout_5_re_tmp);
dout_5_im_1 <= std_logic_vector(dout_5_im_tmp);
END rtl;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
end architecture ARCH;
|
library verilog;
use verilog.vl_types.all;
entity read_analog_input is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_input;
|
library verilog;
use verilog.vl_types.all;
entity read_analog_input is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_input;
|
library verilog;
use verilog.vl_types.all;
entity read_analog_input is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_input;
|
-- $Id: tb_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n3 - sim
-- Description: Test bench for sys_tst_serloop1_n3
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop1_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_tst_serloop1_n3 is
end tb_tst_serloop1_n3;
architecture sim of tb_tst_serloop1_n3 is
signal CLK100 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK100,
CLKH => CLK100,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
---------------------------------------------------------------------------------
-- Title : 1-bit synchronizer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : SyncBit.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Simple one-bit synchronizer.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library unisim;
use unisim.vcomponents.all;
entity SyncBit is
generic (
SYNC_STAGES_G : integer := 2;
CLK_POL_G : sl := '1';
RST_POL_G : sl := '1';
INIT_STATE_G : sl := '0';
GATE_DELAY_G : time := 1 ns
);
port (
-- Clock and reset
clk : in sl;
rst : in sl := '0';
-- Incoming bit, asynchronous
asyncBit : in sl;
-- Outgoing bit, synced to clk
syncBit : out sl
);
end SyncBit;
-- Define architecture
architecture structural of SyncBit is
-- Internal Signals
signal data_sync1 : std_logic;
signal syncBitPipe : std_logic_vector(SYNC_STAGES_G-2 downto 0);
-- These attributes will stop Vivado translating the desired flip-flops into an
-- SRL based shift register.
attribute ASYNC_REG : string;
-- attribute ASYNC_REG of "G_RisingEdgeClock.cdc_reg1" : label is "TRUE";
-- attribute ASYNC_REG of "G_RisingEdgeClock.cdc_reg2" : label is "TRUE";
-- attribute ASYNC_REG of "G_FallingEdgeClock.cdc_reg1" : label is "TRUE";
-- attribute ASYNC_REG of "G_FallingEdgeClock.cdc_reg2" : label is "TRUE";
-- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
-- Unfortunately this does not seem to fix timing errors in implementation.
-- To do this, modify the UCF to add something like:
--
attribute MSGON : string;
-- attribute MSGON of "G_RisingEdgeClock.cdc_reg1" : label is "FALSE";
-- attribute MSGON of "G_RisingEdgeClock.cdc_reg2" : label is "FALSE";
-- attribute MSGON of "G_FallingEdgeClock.cdc_reg1" : label is "FALSE";
-- attribute MSGON of "G_FallingEdgeClock.cdc_reg2" : label is "FALSE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
-- attribute shreg_extract of "G_RisingEdgeClock.cdc_reg1" : label is "no";
-- attribute shreg_extract of "G_RisingEdgeClock.cdc_reg2" : label is "no";
-- attribute shreg_extract of "G_FallingEdgeClock.cdc_reg1" : label is "no";
-- attribute shreg_extract of "G_FallingEdgeClock.cdc_reg2" : label is "no";
begin
G_RisingEdgeClock : if CLK_POL_G = '1' generate
cdc_reg1 : FDRE
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
R => rst,
D => asyncBit,
Q => data_sync1
);
cdc_reg2 : FDRE
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
R => rst,
D => data_sync1,
Q => syncBitPipe(0)
);
end generate;
G_FallingEdgeClock : if CLK_POL_G = '0' generate
cdc_reg1 : FDCE_1
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => asyncBit,
Q => data_sync1
);
cdc_reg2 : FDCE_1
generic map (
INIT => to_bit(INIT_STATE_G)
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => data_sync1,
Q => syncBitPipe(0)
);
end generate;
G_SyncPipe : if SYNC_STAGES_G > 2 generate
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
syncBitPipe(syncBitPipe'left downto 1) <= (others => INIT_STATE_G);
else
for i in syncBitPipe'left downto 1 loop
syncBitPipe(i) <= syncBitPipe(i-1);
end loop;
end if;
end if;
end process;
end generate;
syncBit <= syncBitPipe(syncBitPipe'left);
end structural;
|
entity tb_dff03 is
end tb_dff03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff03 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff03
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= x"00";
pulse;
assert dout = x"00" severity failure;
din <= x"ab";
pulse;
assert dout = x"ab" severity failure;
pulse;
assert dout = x"ab" severity failure;
din <= x"12";
pulse;
assert dout = x"12" severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 6,
C_PLBV46_NUM_SLAVES => 12,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
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