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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00230ent IS
END c03s01b02x00p02n01i00230ent;
ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
BEGIN
TESTING: PROCESS
variable k : a := 11;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00230"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00230arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00230ent IS
END c03s01b02x00p02n01i00230ent;
ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
BEGIN
TESTING: PROCESS
variable k : a := 11;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00230"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00230arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00230ent IS
END c03s01b02x00p02n01i00230ent;
ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
BEGIN
TESTING: PROCESS
variable k : a := 11;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00230"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00230arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000019#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (256);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
architecture rtl of fifo is
begin
GEN_LABEL : for x in range (3 downto 0) generate
end generate;
GEN_LABEL : for x in range (3 downto 0) generate
end GENERATE;
end architecture;
|
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
-- Input file : core.vhd
-- Design name : core
-- Author : Muhammad Bin Rosli
-- Company :
-- :
-- :
--
-- Description : Top level entity of the processor modified
-- : for Vivado IP Packager
--
-- Date : 01 November 2015
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
entity core is generic
(
CFG_IMEM_WIDTH : integer := 32;
CFG_IMEM_SIZE : integer := 16;
CFG_DMEM_WIDTH : integer := 32;
CFG_DMEM_SIZE : integer := 32;
G_INTERRUPT : boolean := true;
G_USE_HW_MUL : boolean := true;
G_USE_BARREL : boolean := true;
G_DEBUG : boolean := true
);
port
(
-- instruction memory interface
imem_dat_i : in std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
imem_adr_o : out std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
imem_ena_o : out std_logic;
-- data memory interfa
dmem_dat_i : in std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_ena_i : in std_logic;
dmem_dat_o : out std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_adr_o : out std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
dmem_sel_o : out std_logic_vector(3 downto 0);
dmem_we_o : out std_logic;
dmem_ena_o : out std_logic;
int_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end core;
architecture arch of core is
signal imem_o : imem_out_type;
signal dmem_o : dmem_out_type;
signal imem_i : imem_in_type;
signal dmem_i : dmem_in_type;
signal fetch_i : fetch_in_type;
signal fetch_o : fetch_out_type;
signal decode_i : decode_in_type;
signal decode_o : decode_out_type;
signal gprf_o : gprf_out_type;
signal exec_i : execute_in_type;
signal exec_o : execute_out_type;
signal mem_i : mem_in_type;
signal mem_o : mem_out_type;
signal ena_i : std_logic;
begin
-- connecting the entity port
imem_i.dat_i <= imem_dat_i;
imem_adr_o <= imem_o.adr_o;
imem_ena_o <= imem_o.ena_o;
dmem_i.dat_i <= dmem_dat_i;
dmem_i.ena_i <= dmem_ena_i;
dmem_dat_o <= dmem_o.dat_o;
dmem_adr_o <= dmem_o.adr_o;
dmem_sel_o <= dmem_o.sel_o;
dmem_we_o <= dmem_o.we_o;
dmem_ena_o <= dmem_o.ena_o;
ena_i <= dmem_i.ena_i;
fetch_i.hazard <= decode_o.hazard;
fetch_i.branch <= exec_o.branch;
fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 downto 0);
fetch0 : fetch port map
(
fetch_o => fetch_o,
imem_o => imem_o,
fetch_i => fetch_i,
rst_i => rst_i,
ena_i => ena_i,
clk_i => clk_i
);
decode_i.program_counter <= fetch_o.program_counter;
decode_i.instruction <= imem_i.dat_i;
decode_i.ctrl_wrb <= mem_o.ctrl_wrb;
decode_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
decode_i.mem_result <= dmem_i.dat_i;
decode_i.alu_result <= mem_o.alu_result;
decode_i.interrupt <= int_i;
decode_i.flush_id <= exec_o.flush_id;
decode0: decode generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
decode_o => decode_o,
decode_i => decode_i,
gprf_o => gprf_o,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
exec_i.fwd_dec <= decode_o.fwd_dec;
exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
exec_i.dat_a <= gprf_o.dat_a_o;
exec_i.dat_b <= gprf_o.dat_b_o;
exec_i.dat_d <= gprf_o.dat_d_o;
exec_i.reg_a <= decode_o.reg_a;
exec_i.reg_b <= decode_o.reg_b;
exec_i.imm <= decode_o.imm;
exec_i.program_counter <= decode_o.program_counter;
exec_i.ctrl_wrb <= decode_o.ctrl_wrb;
exec_i.ctrl_mem <= decode_o.ctrl_mem;
exec_i.ctrl_ex <= decode_o.ctrl_ex;
exec_i.fwd_mem <= mem_o.ctrl_wrb;
exec_i.mem_result <= dmem_i.dat_i;
exec_i.alu_result <= mem_o.alu_result;
exec_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
execute0 : execute generic map
(
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL
)
port map
(
exec_o => exec_o,
exec_i => exec_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
mem_i.alu_result <= exec_o.alu_result;
mem_i.program_counter <= exec_o.program_counter;
mem_i.branch <= exec_o.branch;
mem_i.dat_d <= exec_o.dat_d;
mem_i.ctrl_wrb <= exec_o.ctrl_wrb;
mem_i.ctrl_mem <= exec_o.ctrl_mem;
mem_i.mem_result <= dmem_i.dat_i;
mem0 : mem port map
(
mem_o => mem_o,
dmem_o => dmem_o,
mem_i => mem_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
end arch;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixgx_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixgx_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixgx_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixgx_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixgx_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixgx_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixgx_pllpack;
package body stratixgx_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixgx_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixgx_dffe : entity is TRUE;
end stratixgx_dffe;
-- architecture body --
architecture behave of stratixgx_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixgx_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixgx_mux21 : entity is TRUE;
end stratixgx_mux21;
architecture AltVITAL of stratixgx_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixgx_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_mux41 : entity is TRUE;
end stratixgx_mux41;
architecture AltVITAL of stratixgx_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixgx_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
-- entity declaration --
entity stratixgx_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixgx_and1 : entity is TRUE;
end stratixgx_and1;
-- architecture body --
architecture AltVITAL of stratixgx_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for STRATIXGX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- STRATIXGX Lcell.
--
-- Outputs : Asynchnous LUT function of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_asynch_lcell : ENTITY is TRUE;
END stratixgx_asynch_lcell;
ARCHITECTURE vital_le of stratixgx_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- STRATIXGX Lcell.
--
-- Outputs : Registered output of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_lcell_register : ENTITY is TRUE;
end stratixgx_lcell_register;
ARCHITECTURE vital_le_reg of stratixgx_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant stratixgx_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => stratixgx_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lcell
--
-- Description : VHDL simulation model for STRATIXGX Lcell.
--
-- Outputs : Output of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_asynch_lcell;
use work.stratixgx_lcell_register;
ENTITY stratixgx_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratixgx_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end stratixgx_lcell;
ARCHITECTURE vital_le_atom of stratixgx_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT stratixgx_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: stratixgx_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: stratixgx_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_ASYNCH_IO
--
-- Description : Timing simulation model for the asynchronous submodule
-- of STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_asynch_io is
GENERIC (
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
phase_shift_delay : time := 0 ps;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsundelayedout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout: out STD_LOGIC;
dqsundelayedout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of stratixgx_asynch_io : ENTITY is TRUE;
end stratixgx_asynch_io;
ARCHITECTURE behave of stratixgx_asynch_io is
attribute VITAL_LEVEL0 of behave : ARCHITECTURE is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_ipd, delayctrlin, tipd_delayctrlin);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, delayctrlin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable dqsundelayedout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable combout_tmp : std_logic;
variable dqs_delay : VitalDelayType01 := (0 ps, 0 ps);
variable warn_x : boolean := false;
variable combout_delay : VitalDelayType01;
variable dqs_delay_is_applied : boolean := false;
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (delayctrlin_ipd = '1') then
if (not dqs_delay_is_applied) then
for i in combout_delay'range loop
combout_delay(i) := combout_delay(i) + phase_shift_delay;
end loop;
dqs_delay_is_applied := true;
end if;
warn_x := false;
elsif (delayctrlin_ipd = '0') then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
warn_x := false;
elsif (delayctrlin_ipd'event) then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
if (not warn_x) then
assert false report "Illegal value detected on input DELAYCTRLIN" severity warning;
warn_x := true;
end if;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsundelayedout,
OutSignalName => "dqsundelayedout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dqsundelayedout, TRUE)),
GlitchData => dqsundelayedout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_IO_REGISTER
--
-- Description : Timing simulation model for the register submodule
-- of STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_io_register is
GENERIC (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_io_register : ENTITY is TRUE;
end stratixgx_io_register;
ARCHITECTURE vital_io_reg of stratixgx_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : ARCHITECTURE is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd,
areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_IO
--
-- Description : Timing simulation model for STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_pllpack.all;
use work.stratixgx_asynch_io;
use work.stratixgx_io_register;
use work.stratixgx_mux21;
use work.stratixgx_and1;
ENTITY stratixgx_io is
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratixgx_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
end stratixgx_io;
ARCHITECTURE structure of stratixgx_io is
COMPONENT stratixgx_asynch_io
GENERIC
(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
phase_shift_delay : time := 0 ps);
PORT
(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC;
dqsundelayedout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_io_register
GENERIC
(
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01);
PORT
(
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_mux21
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
PORT
(
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_and1
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT
(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
constant phase_shift_delay : time := (dqs_str2int(sim_dll_phase_shift) * dqs_str2int(sim_dqs_input_frequency) * 1 ps) / 360;
begin
not_inclk <= not inclk;
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio0_reg
in_ddio0_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio1_reg
-- this register does not have sync_reset
in_ddio1_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => "none",
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn
);
-- out_reg
out_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up
)
PORT map
(
regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- out ddio reg
out_ddio_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
PORT map
(
regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe reg
oe_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe_pulse reg
oe_pulse_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratixgx_and1
PORT map
(
Y => outclk_delayed,
IN1 => outclk
);
ddio_data_mux : stratixgx_mux21
PORT map
(
MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed
);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or
ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratixgx_asynch_io
GENERIC map
(
OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
PHASE_SHIFT_DELAY => phase_shift_delay
)
PORT map
(
datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
delayctrlin => delayctrlin,
padio => padio,
combout => combout,
regout => regout,
ddioregout => ddioregout,
dqsundelayedout => dqsundelayedout
);
end structure;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_BIT_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_bit_register is
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end stratixgx_mac_bit_register;
architecture reg_arch OF stratixgx_mac_bit_register IS
signal data_ipd : STD_LOGIC := '0';
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC := '0';
begin
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC := '0';
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := '0';
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
end process;
-- Path Delay Selection
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_register is
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end stratixgx_mac_register;
architecture reg_arch OF stratixgx_mac_register IS
signal data_ipd : STD_LOGIC_VECTOR (71 downto 0) := (others => '0');
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := (others => '0');
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
end process;
sh: block
begin
g0 : for i in data'range generate
process(data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "data(i)",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
END PROCESS;
end generate g0;
end block;
-- Path Delay Selection
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_MULT_INTERNAL
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_mult_internal is
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
port
(
dataa : IN std_logic_vector (dataa_width - 1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width - 1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end stratixgx_mac_mult_internal;
architecture mult_internal_arch OF stratixgx_mac_mult_internal IS
signal dataa_ipd : std_logic_vector (dataa_width-1 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector (datab_width-1 downto 0) := (others => '0');
signal dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
process(dataa_ipd, datab_ipd, signa, signb)
begin
if((signa = '0') and (signb = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '1')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa = '0') and (signb = '0')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
PathDelay :block
begin
g1: for i in dataa_width + datab_width -1 downto 0 generate
p1: process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin -- process p1
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process p1;
a: if i < dataa_width generate
p2: PROCESS(dataa_ipd(i))
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p2;
end generate a;
b: if i < datab_width generate
p3: PROCESS(datab_ipd(i))
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p3;
end generate b;
end generate g1;
end block;
end mult_internal_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_OUT_INTERNAL
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_mac_out_internal IS
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0) := (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
-- /////////////////////////////////////////////////////////////////////////////
-- //
-- // ADD_OR_SUB_ACCUM
-- //
-- /////////////////////////////////////////////////////////////////////////////
function add_or_sub_accum
(
sign_a : in std_logic := '0';
data_a : in std_logic_vector(dataout_width-1 downto 0)
:= (others => '0');
sign_b : in std_logic := '0';
data_b : in std_logic_vector(dataa_width-1 downto 0)
:= (others => '0');
operation : in string
) return std_logic_vector is
variable sign : std_logic := '0';
variable unsigned_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable unsigned_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
begin
-- signed or unsigned
sign := ((data_a(dataout_width-1) and (sign_a))
or (data_b(dataa_width-1) and (sign_b)));
if(sign = '1') then
signed_add(dataout_width downto 0) :=
sxt((signed(data_a) + signed(data_b)), dataout_width+1);
signed_sub(dataout_width downto 0) :=
sxt((signed(data_a) - signed(data_b)), dataout_width+1);
else
unsigned_add(dataout_width downto 0) :=
ext((unsigned('0' & data_a) + unsigned('0' & data_b)), dataout_width+1);
unsigned_sub(dataout_width downto 0) :=
sxt((unsigned('0' & data_a) - unsigned('0' & data_b)), dataout_width+1);
end if;
if (operation = "ADD") then
if (sign = '1') then
return signed_add(dataout_width downto 0);
else
return unsigned_add(dataout_width downto 0);
end if;
elsif (operation = "SUB") then
if (sign = '1') then
return signed_sub(dataout_width downto 0);
else
return unsigned_sub(dataout_width downto 0);
end if;
end if;
end add_or_sub_accum;
end stratixgx_mac_out_internal;
ARCHITECTURE mac_add OF stratixgx_mac_out_internal IS
signal dataa_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datac_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datad_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal dataa_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_s : std_logic_vector(71 downto 0) := (others => '0');
signal datac_u : std_logic_vector(71 downto 0) := (others => '0');
signal datac_s : std_logic_vector(71 downto 0) := (others => '0');
signal datad_u : std_logic_vector(71 downto 0) := (others => '0');
signal datad_s : std_logic_vector(71 downto 0) := (others => '0');
signal signx_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal signy_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub0_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub1_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal zeroacc_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal dataout_t : std_logic_vector(72 downto 0) := (others => '0');
signal next_dataout : std_logic_vector(72 downto 0) := (others => '0');
signal sll_36 : std_logic_vector(35 downto 0) := (others => '0');
signal sll_18 : std_logic_vector(17 downto 0) := (others => '0');
signal accoverflow_tmp: std_logic := '0';
signal sign_a_or_b : std_logic := '0';
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 : for i in datac'range generate
VitalWireDelay (datac_ipd(i), datac(i), tipd_datac(i));
end generate;
g4 : for i in datad'range generate
VitalWireDelay (datad_ipd(i), datad(i), tipd_datad(i));
end generate;
end block;
signx_tmp(0) <= signx;
signy_tmp(0) <= signy;
addnsub0_tmp(0) <= addnsub0;
addnsub1_tmp(0) <= addnsub1;
zeroacc_tmp(0) <= zeroacc;
sign_a_or_b <= '1' when ((signx_tmp(0) = '1') or (signy_tmp(0) = '1'))
else '0';
main : process (dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
signx_tmp, signy_tmp, addnsub0_tmp, addnsub1_tmp,
dataout_t, zeroacc_tmp, dataout_global,
sign_a_or_b, next_dataout, dataa_u, datab_u, datac_u,
datad_u, datab_s, datac_s, datad_s)
begin
if operation_mode = "output_only" then
dataout_tmp(dataa_width-1 downto 0) <= dataa_ipd(dataa_width-1 downto 0);
elsif operation_mode = "accumulator" then
if(zeroacc_tmp(0) = '0') then
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
else
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
end if;
dataout_tmp(dataout_width-1 downto 0) <=
next_dataout(dataout_width-1 downto 0);
if(sign_a_or_b = '1') then
accoverflow_tmp <=
next_dataout(dataa_width+16) xor next_dataout(dataa_width+15);
else
accoverflow_tmp <= next_dataout(dataa_width+16);
end if;
elsif operation_mode = "one_level_adder" then
if(addnsub0_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
end if;
elsif operation_mode = "two_level_adder" then
-- dataout = (dataa - datab) + (datac - datad);
if(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac - datad);
elsif(addnsub0_tmp(0) = '1' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa - datab) + (datac + datad);
elsif(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '1') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac + datad);
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
end if;
elsif operation_mode = "36_bit_multiply" then
dataa_u <= (others => '0');
datab_u <= (others => '0');
datac_u <= (others => '0');
datad_u <= (others => '0');
datab_s <= (others => '0');
datac_s <= (others => '0');
sll_36 <= (others => '0');
sll_18 <= (others => '0');
dataa_u(35 downto 0) <= dataa_ipd;
datab_u(71 downto 36) <= datab_ipd;
datab_s(71 downto 36) <= datab_ipd;
datac_u(53 downto 18) <= datac_ipd;
datac_s(71 downto 18) <= sxt(datac_ipd(datac_width-1 downto 0), 54);
datad_u(53 downto 18) <= datad_ipd;
datad_s(71 downto 18) <= sxt(datad_ipd(datad_width-1 downto 0), 54);
if((signx_tmp(0) = '0') and (signy_tmp(0) = '0')) then
dataout_tmp <= unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signx_tmp(0) = '0') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '0')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
end if;
end if;
end process;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx_tmp'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy_tmp'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0_tmp'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1_tmp'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc_tmp'last_event, tpd_zeroacc_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate g1;
g2 : for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx_tmp'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy_tmp'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0_tmp'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1_tmp'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc_tmp'last_event, tpd_zeroacc_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
end generate g2;
end block;
END mac_add;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_MULT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_mac_register;
use work.stratixgx_mac_mult_internal;
entity stratixgx_mac_mult IS
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
-- SELECT THE CLOCK, CLEAR, or ENABLE LINE FUNCTION
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratixgx_mac_mult;
architecture mult_arch OF stratixgx_mac_mult IS
component stratixgx_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratixgx_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratixgx_mac_mult_internal
GENERIC
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT
(
dataa : IN std_logic_vector (dataa_width-1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width-1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end component;
signal mult_output : std_logic_vector(71 downto 0) := (others => '0');
signal scanouta_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal scanoutb_tmp : std_logic_vector(71 downto 0) := (others => '0') ;
signal signa_out : std_logic := '1';
signal signb_out : std_logic := '1';
signal dataa_tmp : std_logic_vector(71 downto 0);
signal datab_tmp : std_logic_vector(71 downto 0);
signal dataout_tmp : std_logic_vector(71 downto 0);
signal dataa_async : std_logic := '0';
signal datab_async : std_logic := '0';
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal signa_internally : std_logic := '0';
signal signb_internally : std_logic := '0';
signal clk_dataa : std_logic;
signal aclr_dataa : std_logic;
signal ena_dataa : std_logic;
signal clk_datab : std_logic;
signal aclr_datab : std_logic;
signal ena_datab : std_logic;
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal dataa_if_clear : std_logic;
signal datab_if_clear : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
begin
signa_tmp <= signa;
signb_tmp <= signb;
dataa_async <= '1' when (dataa_clock = "none" or dataa_clear = "none") else '0';
datab_async <= '1' when (datab_clock = "none" or datab_clear = "none") else '0';
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
dataout_async <=
'1' when (output_clock = "none" or output_clear = "none") else '0';
signa_internally <= signa_out when (signa_internally_grounded = "false") else '0';
signb_internally <= signb_out when (signb_internally_grounded = "false") else '0';
--Assign the values for if_aclr ports
dataa_if_clear <= '1' when (dataa_clear /= "none") else '0';
datab_if_clear <= '1' when (datab_clear /= "none") else '0';
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
dataa_tmp(dataa_width-1 downto 0) <= dataa;
datab_tmp(datab_width-1 downto 0) <= datab;
dataout <= dataout_tmp((dataa_width+datab_width)-1 downto 0);
clk_dataa <= clk(select_the(dataa_clock));
aclr_dataa <= aclr(select_the(dataa_clear))or not(devclrn) or not(devpor);
ena_dataa <= ena(select_the(dataa_clock));
dataa_mac_reg : stratixgx_mac_register
generic map (data_width => dataa_width)
port map (data => dataa_tmp,
clk => clk_dataa,
aclr => aclr_dataa,
ena => ena_dataa,
if_aclr => dataa_if_clear,
dataout => scanouta_tmp,
async => dataa_async);
clk_datab <= clk(select_the(datab_clock));
aclr_datab <= aclr(select_the(datab_clear)) or not(devclrn) or not(devpor);
ena_datab <= ena(select_the(datab_clock));
datab_mac_reg : stratixgx_mac_register
generic map (data_width => datab_width)
port map (data => datab_tmp,
clk => clk_datab,
aclr => aclr_datab,
ena => ena_datab,
if_aclr => datab_if_clear,
dataout => scanoutb_tmp,
async => datab_async);
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear))or not(devclrn) or not(devpor);
ena_signa <= ena(select_the(signa_clock));
signa_mac_reg : stratixgx_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_out,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear))or not(devclrn) or not(devpor);
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratixgx_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_out,
async => signb_async);
mac_multiply : stratixgx_mac_mult_internal
generic map (dataa_width => dataa_width,
datab_width => datab_width)
port map(dataa => scanouta_tmp(dataa_width-1 downto 0),
datab => scanoutb_tmp(datab_width-1 downto 0),
signa => signa_internally,
signb => signb_internally,
scanouta => scanouta,
scanoutb => scanoutb,
dataout => mult_output(dataa_width+datab_width-1 downto 0)
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear))or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_mac_reg : stratixgx_mac_register
generic map (data_width => (dataa_width+datab_width))
port map (data => mult_output,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
END mult_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_OUT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_mac_register;
use work.stratixgx_mac_out_internal;
entity stratixgx_mac_out IS
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratixgx_mac_out;
ARCHITECTURE out_arch OF stratixgx_mac_out IS
component stratixgx_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratixgx_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr: IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratixgx_mac_out_internal
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0)
:= (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
end component;
signal signa_pipe : std_logic;
signal signb_pipe : std_logic;
signal zeroacc_pipe : std_logic;
signal addnsub0_pipe : std_logic;
signal addnsub1_pipe : std_logic;
signal signa_out : std_logic;
signal signb_out : std_logic;
signal zeroacc_out : std_logic;
signal addnsub0_out : std_logic;
signal addnsub1_out : std_logic;
signal dataout_sig : std_logic_vector (71 downto 0);
signal accoverflow_sig : std_logic;
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal zeroacc_async : std_logic := '0';
signal addnsub0_async : std_logic := '1';
signal addnsub1_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal accoverflow_async : std_logic := '0';
signal signa_pipeline_async : std_logic := '0';
signal signb_pipeline_async : std_logic := '0';
signal zeroacc_pipeline_async : std_logic := '0';
signal addnsub0_pipeline_async : std_logic := '1';
signal addnsub1_pipeline_async : std_logic := '1';
signal dataout_tmp : std_logic_vector(71 downto 0);
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_zeroacc : std_logic;
signal aclr_zeroacc : std_logic;
signal ena_zeroacc : std_logic;
signal clk_addnsub0 : std_logic;
signal aclr_addnsub0 : std_logic;
signal ena_addnsub0 : std_logic;
signal clk_addnsub1 : std_logic;
signal aclr_addnsub1 : std_logic;
signal ena_addnsub1 : std_logic;
signal clk_signa_pipeline : std_logic;
signal aclr_signa_pipeline : std_logic;
signal ena_signa_pipeline : std_logic;
signal clk_signb_pipeline : std_logic;
signal aclr_signb_pipeline : std_logic;
signal ena_signb_pipeline : std_logic;
signal clk_zeroacc_pipeline : std_logic;
signal aclr_zeroacc_pipeline : std_logic;
signal ena_zeroacc_pipeline : std_logic;
signal clk_addnsub0_pipeline : std_logic;
signal aclr_addnsub0_pipeline : std_logic;
signal ena_addnsub0_pipeline : std_logic;
signal clk_addnsub1_pipeline : std_logic;
signal aclr_addnsub1_pipeline : std_logic;
signal ena_addnsub1_pipeline : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal clk_accoverflow : std_logic;
signal aclr_accoverflow : std_logic;
signal ena_accoverflow : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal signa_pip_if_clear : std_logic;
signal signb_pip_if_clear : std_logic;
signal zeroacc_if_clear : std_logic;
signal zeroacc_pip_if_clear : std_logic;
signal addnsub0_if_clear : std_logic;
signal addnsub1_if_clear : std_logic;
signal addnsub0_pip_if_clear : std_logic;
signal addnsub1_pip_if_clear : std_logic;
signal accoverflow_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal accoverflow_tmp : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
signal addnsub0_tmp : std_logic;
signal addnsub1_tmp : std_logic;
signal zeroacc_tmp : std_logic;
BEGIN
signa_tmp <= signa ;
signb_tmp <= signb ;
addnsub0_tmp <= addnsub0 ;
addnsub1_tmp <= addnsub1 ;
zeroacc_tmp <= zeroacc ;
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
addnsub0_async <= '1' when
(addnsub0_clock = "none" or addnsub0_clear = "none") else '0';
addnsub1_async <= '1' when
(addnsub1_clock = "none" or addnsub1_clear = "none") else '0';
zeroacc_async <= '1' when
(zeroacc_clock = "none" or zeroacc_clear = "none") else '0';
signa_pipeline_async <= '1' when
(signa_pipeline_clock = "none" or signa_pipeline_clear = "none") else '0';
signb_pipeline_async <= '1' when
(signb_pipeline_clock = "none" or signb_pipeline_clear = "none") else '0';
addnsub0_pipeline_async <= '1' when
(addnsub0_pipeline_clock = "none" or addnsub0_pipeline_clear = "none") else '0';
addnsub1_pipeline_async <= '1' when
(addnsub1_pipeline_clock = "none" or addnsub1_pipeline_clear = "none") else '0';
zeroacc_pipeline_async <= '1' when
(zeroacc_pipeline_clock = "none" or zeroacc_pipeline_clear = "none") else '0';
dataout_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
accoverflow_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear));
ena_signa <= ena(select_the(signa_clock));
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
signa_pip_if_clear <= '1' when (signa_pipeline_clear /= "none") else '0';
signb_pip_if_clear <= '1' when (signb_pipeline_clear /= "none") else '0';
zeroacc_if_clear <= '1' when (zeroacc_clear /= "none") else '0';
zeroacc_pip_if_clear <= '1' when (zeroacc_pipeline_clear /= "none") else '0';
addnsub0_if_clear <= '1' when (addnsub0_clear /= "none") else '0';
addnsub0_pip_if_clear <= '1' when (addnsub0_pipeline_clear /= "none") else '0';
addnsub1_if_clear <= '1' when (addnsub1_clear /= "none") else '0';
addnsub1_pip_if_clear <= '1' when (addnsub1_pipeline_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
accoverflow_if_clear <='1' when (output_clear /= "none") else '0';
signa_mac_reg : stratixgx_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_pipe,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear)) or not(devclrn) or not(devpor) ;
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratixgx_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_pipe,
async => signb_async);
clk_zeroacc <= clk(select_the(zeroacc_clock));
aclr_zeroacc <= aclr(select_the(zeroacc_clear)) or not(devclrn) or not(devpor);
ena_zeroacc <= ena(select_the(zeroacc_clock));
zeroacc_mac_reg : stratixgx_mac_bit_register
port map (data => zeroacc_tmp,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
ena => ena_zeroacc,
if_aclr => zeroacc_if_clear,
dataout => zeroacc_pipe,
async => zeroacc_async);
clk_addnsub0 <= clk(select_the(addnsub0_clock));
aclr_addnsub0 <= aclr(select_the(addnsub0_clear)) or not(devclrn) or not(devpor);
ena_addnsub0 <= ena(select_the(addnsub0_clock));
addnsub0_mac_reg : stratixgx_mac_bit_register
port map (data => addnsub0_tmp,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
ena => ena_addnsub0,
if_aclr => addnsub0_if_clear,
dataout => addnsub0_pipe,
async => addnsub0_async);
clk_addnsub1 <= clk(select_the(addnsub1_clock));
aclr_addnsub1 <= aclr(select_the(addnsub1_clear)) or not(devclrn) or not(devpor);
ena_addnsub1 <= ena(select_the(addnsub1_clock));
addnsub1_mac_reg : stratixgx_mac_bit_register
port map (data => addnsub1_tmp,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
ena => ena_addnsub1,
if_aclr => addnsub1_if_clear,
dataout => addnsub1_pipe,
async => addnsub1_async);
clk_signa_pipeline <= clk(select_the(signa_pipeline_clock));
aclr_signa_pipeline <= aclr(select_the(signa_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signa_pipeline <= ena(select_the(signa_pipeline_clock));
signa_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
ena => ena_signa_pipeline,
if_aclr => signa_pip_if_clear,
dataout => signa_out,
async => signa_pipeline_async);
clk_signb_pipeline <= clk(select_the(signb_pipeline_clock));
aclr_signb_pipeline <= aclr(select_the(signb_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signb_pipeline <= ena(select_the(signb_pipeline_clock));
signb_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
ena => ena_signb_pipeline,
if_aclr => signb_pip_if_clear,
dataout => signb_out,
async => signb_pipeline_async);
clk_zeroacc_pipeline <= clk(select_the(zeroacc_pipeline_clock));
aclr_zeroacc_pipeline <= aclr(select_the(zeroacc_pipeline_clear)) or not(devclrn) or not(devpor);
ena_zeroacc_pipeline <= ena(select_the(zeroacc_pipeline_clock));
zeroacc_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
if_aclr => zeroacc_pip_if_clear,
dataout => zeroacc_out,
async => zeroacc_pipeline_async);
clk_addnsub0_pipeline <= clk(select_the(addnsub0_pipeline_clock));
aclr_addnsub0_pipeline <= aclr(select_the(addnsub0_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub0_pipeline <= ena(select_the(addnsub0_pipeline_clock));
addnsub0_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
if_aclr => addnsub0_pip_if_clear,
dataout => addnsub0_out,
async => addnsub0_pipeline_async);
clk_addnsub1_pipeline <= clk(select_the(addnsub1_pipeline_clock));
aclr_addnsub1_pipeline <= aclr(select_the(addnsub1_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub1_pipeline <= ena(select_the(addnsub1_pipeline_clock));
addnsub1_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
if_aclr => addnsub1_pip_if_clear,
dataout => addnsub1_out,
async => addnsub1_pipeline_async);
mac_adder : stratixgx_mac_out_internal
generic map (operation_mode => operation_mode,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
signa_clock => signa_clock,
signb_clock => signb_clock,
signa_clear => signa_clear,
signb_clear => signb_clear,
output_clock => output_clock,
output_clear => output_clear)
port map (dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
dataout_global => dataout_tmp(dataout_width-1 downto 0),
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
zeroacc => zeroacc_out,
dataout => dataout_sig,
accoverflow => accoverflow_sig
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_out_reg : stratixgx_mac_register
generic map (data_width => 72)
port map (data => dataout_sig,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
clk_accoverflow <= clk(select_the(output_clock));
aclr_accoverflow <=aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_accoverflow <= ena(select_the(output_clock));
accoverflow_out_reg : stratixgx_mac_bit_register
port map (data => accoverflow_sig,
clk => clk_accoverflow,
aclr => aclr_accoverflow,
ena => ena_accoverflow,
if_aclr => accoverflow_if_clear,
dataout => accoverflow_tmp,
async => accoverflow_async);
dataout <= dataout_tmp(dataout'range) xor data_out_programmable_invert(dataout'range);
accoverflow <= accoverflow_tmp xor overflow_programmable_invert;
END out_arch;
----------------------------------------------------------------------------
-- Module Name : stratixgx_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixgx_ram_register;
ARCHITECTURE reg_arch OF stratixgx_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixgx_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixgx_ram_pulse_generator:ENTITY IS TRUE;
END stratixgx_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixgx_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_ram_register;
USE work.stratixgx_ram_pulse_generator;
ENTITY stratixgx_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratixgx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixgx_ram_block;
ARCHITECTURE block_arch OF stratixgx_ram_block IS
COMPONENT stratixgx_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixgx_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= ena0;
active_b_in <= ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixgx_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratixgx_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixgx_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_m_cntr
--
-- Description : Timing simulation model for the M counter. This is a
-- model for the loop feedback counter of the STRATIXGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_m_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0);
END stratixgx_m_cntr;
ARCHITECTURE behave of stratixgx_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_n_cntr
--
-- Description : Timing simulation model for the N counter. This is a
-- model for the input counter of the STRATIXGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_n_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END stratixgx_n_cntr;
ARCHITECTURE behave of stratixgx_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on STRATIXGX PLL input clk. This edge will be ignored" severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge and (clk_last_valid_value /= clk)) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the L0, L1, G0, G1, G2, G3, E0,
-- E1, E2 and E3 output counters of the STRATIXGX PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_scale_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
initial : IN integer;
high : IN integer;
low : IN integer;
mode : IN string := "bypass";
time_delay : IN integer;
ph_tap : IN natural;
cout : OUT std_logic);
END stratixgx_scale_cntr;
ARCHITECTURE behave of stratixgx_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 0;
variable first_rising_edge : boolean := false;
variable high_reg : integer := 0;
variable low_reg : integer := 0;
variable init : boolean := true;
variable high_cnt_xfer_done : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 0;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (init) then
init := false;
high_reg := high;
low_reg := low;
end if;
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
elsif (not first_rising_edge) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high_reg*2) + 1)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (mode = " odd" and (count = high_reg*2)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (count = (high_reg + low_reg)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
if (high_reg /= high) then
high_cnt_xfer_done := true;
high_reg := high;
end if;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixgx_pll_reg is
PORT ( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic);
end stratixgx_pll_reg;
ARCHITECTURE behave of stratixgx_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_pll
--
-- Description : Timing simulation model for the STRATIXGX STRATIXGXGX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_pllpack.all;
USE work.stratixgx_m_cntr;
USE work.stratixgx_n_cntr;
USE work.stratixgx_scale_cntr;
USE work.stratixgx_dffe;
USE work.stratixgx_pll_reg;
ENTITY stratixgx_pll is
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratixgx_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
-- LVDS mode parameters
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
-- Simulation only generics
family_name : string := "STRATIXGX";
skip_vco : string := "off";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
-- lvds specific ports
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END stratixgx_pll;
ARCHITECTURE vital_pll of stratixgx_pll is
-- internal advanced parameter signals
signal i_vco_min : natural;
signal i_vco_max : natural;
signal i_vco_center : natural;
signal i_pfd_min : natural;
signal i_pfd_max : natural;
signal l0_ph_val : natural;
signal l1_ph_val : natural;
signal g0_ph_val : natural;
signal g1_ph_val : natural;
signal g2_ph_val : natural;
signal g3_ph_val : natural;
signal e0_ph_val : natural;
signal e1_ph_val : natural;
signal e2_ph_val : natural;
signal e3_ph_val : natural;
signal i_extclk3_counter : string(1 to 2) := "e3";
signal i_extclk2_counter : string(1 to 2) := "e2";
signal i_extclk1_counter : string(1 to 2) := "e1";
signal i_extclk0_counter : string(1 to 2) := "e0";
signal i_clk5_counter : string(1 to 2) := "l1";
signal i_clk4_counter : string(1 to 2) := "l0";
signal i_clk3_counter : string(1 to 2) := "g3";
signal i_clk2_counter : string(1 to 2) := "g2";
signal i_clk1_counter : string(1 to 2) := "g1";
signal i_clk0_counter : string(1 to 2) := "g0";
signal i_charge_pump_current : natural;
signal i_loop_filter_r : natural;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT EGPP_SCAN_CHAIN : integer := 289;
CONSTANT GPP_SCAN_CHAIN : integer := 193;
CONSTANT TRST : time := 5000 ps;
CONSTANT TRSTCLK : time := 5000 ps;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal l0_clk : std_logic;
signal l1_clk : std_logic;
signal g0_clk : std_logic;
signal g1_clk : std_logic;
signal g2_clk : std_logic;
signal g3_clk : std_logic;
signal e0_clk : std_logic;
signal e1_clk : std_logic;
signal e2_clk : std_logic;
signal e3_clk : std_logic;
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal m_val_tmp : integer := 1;
signal m2_val : integer := 1;
signal n_val : integer := 1;
signal n_val_tmp : integer := 1;
signal n2_val : integer := 1;
signal m_time_delay_val, n_time_delay_val : integer := 0;
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal l0_initial_val : integer := l0_initial;
signal l1_initial_val : integer := l1_initial;
signal l0_high_val : integer := l0_high;
signal l1_high_val : integer := l1_high;
signal l0_low_val : integer := l0_low;
signal l1_low_val : integer := l1_low;
signal l0_mode_val : string(1 to 6) := "bypass";
signal l1_mode_val : string(1 to 6) := "bypass";
signal l0_time_delay_val : integer := l0_time_delay;
signal l1_time_delay_val : integer := l1_time_delay;
signal g0_initial_val : integer := g0_initial;
signal g1_initial_val : integer := g1_initial;
signal g2_initial_val : integer := g2_initial;
signal g3_initial_val : integer := g3_initial;
signal g0_high_val : integer := g0_high;
signal g1_high_val : integer := g1_high;
signal g2_high_val : integer := g2_high;
signal g3_high_val : integer := g3_high;
signal g0_mode_val : string(1 to 6) := "bypass";
signal g1_mode_val : string(1 to 6) := "bypass";
signal g2_mode_val : string(1 to 6) := "bypass";
signal g3_mode_val : string(1 to 6) := "bypass";
signal g0_low_val : integer := g0_low;
signal g1_low_val : integer := g1_low;
signal g2_low_val : integer := g2_low;
signal g3_low_val : integer := g3_low;
signal g0_time_delay_val : integer := g0_time_delay;
signal g1_time_delay_val : integer := g1_time_delay;
signal g2_time_delay_val : integer := g2_time_delay;
signal g3_time_delay_val : integer := g3_time_delay;
signal e0_initial_val : integer := e0_initial;
signal e1_initial_val : integer := e1_initial;
signal e2_initial_val : integer := e2_initial;
signal e3_initial_val : integer := e3_initial;
signal e0_high_val : integer := e0_high;
signal e1_high_val : integer := e1_high;
signal e2_high_val : integer := e2_high;
signal e3_high_val : integer := e3_high;
signal e0_low_val : integer := e0_low;
signal e1_low_val : integer := e1_low;
signal e2_low_val : integer := e2_low;
signal e3_low_val : integer := e3_low;
signal e0_time_delay_val : integer := e0_time_delay;
signal e1_time_delay_val : integer := e1_time_delay;
signal e2_time_delay_val : integer := e2_time_delay;
signal e3_time_delay_val : integer := e3_time_delay;
signal e0_mode_val : string(1 to 6) := "bypass";
signal e1_mode_val : string(1 to 6) := "bypass";
signal e2_mode_val : string(1 to 6) := "bypass";
signal e3_mode_val : string(1 to 6) := "bypass";
signal m_mode_val : string(1 to 6) := " ";
signal m2_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal n2_mode_val : string(1 to 6) := " ";
signal cntr_e0_initial : integer := 1;
signal cntr_e1_initial : integer := 1;
signal cntr_e2_initial : integer := 1;
signal cntr_e3_initial : integer := 1;
signal ext_fbk_delay : integer := 0;
signal cntr_e0_delay : integer := 0;
signal cntr_e1_delay : integer := 0;
signal cntr_e2_delay : integer := 0;
signal cntr_e3_delay : integer := 0;
signal transfer : std_logic := '0';
signal scan_data : std_logic_vector(288 downto 0) := (OTHERS => '0');
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
signal ena4 : std_logic;
signal ena5 : std_logic;
signal extena0 : std_logic;
signal extena1 : std_logic;
signal extena2 : std_logic;
signal extena3 : std_logic;
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal extclk0_tmp : std_logic;
signal extclk1_tmp : std_logic;
signal extclk2_tmp : std_logic;
signal extclk3_tmp : std_logic;
signal not_clk0_tmp : std_logic;
signal not_clk1_tmp : std_logic;
signal not_clk2_tmp : std_logic;
signal not_clk3_tmp : std_logic;
signal not_clk4_tmp : std_logic;
signal not_clk5_tmp : std_logic;
signal not_extclk0_tmp : std_logic;
signal not_extclk1_tmp : std_logic;
signal not_extclk2_tmp : std_logic;
signal not_extclk3_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal quiet_period_violation : boolean := false;
signal reconfig_err : boolean := false;
signal scanclr_violation : boolean := false;
signal scanclr_clk_violation : boolean := false;
signal inclk_l0 : std_logic;
signal inclk_l1 : std_logic;
signal inclk_g0 : std_logic;
signal inclk_g1 : std_logic;
signal inclk_g2 : std_logic;
signal inclk_g3 : std_logic;
signal inclk_e0 : std_logic;
signal inclk_e1 : std_logic;
signal inclk_e2 : std_logic;
signal inclk_e3 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal comparator_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal clkena0_ipd : std_logic;
signal clkena1_ipd : std_logic;
signal clkena2_ipd : std_logic;
signal clkena3_ipd : std_logic;
signal clkena4_ipd : std_logic;
signal clkena5_ipd : std_logic;
signal extclkena0_ipd : std_logic;
signal extclkena1_ipd : std_logic;
signal extclkena2_ipd : std_logic;
signal extclkena3_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanaclr_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal lvds_dffa_clk : std_logic;
signal lvds_dffb_clk : std_logic;
signal lvds_dffc_clk : std_logic;
signal lvds_dffd_clk : std_logic;
signal dffa_out : std_logic := '0';
signal dffb_out : std_logic := '0';
signal dffc_out : std_logic := '0';
signal dffd_out : std_logic := '0';
signal nce_temp : std_logic := '0';
signal nce_l0 : std_logic := '0';
signal nce_l1 : std_logic := '0';
signal inclk_l0_dly1 : std_logic := '0';
signal inclk_l0_dly2 : std_logic := '0';
signal inclk_l0_dly3 : std_logic := '0';
signal inclk_l0_dly4 : std_logic := '0';
signal inclk_l0_dly5 : std_logic := '0';
signal inclk_l0_dly6 : std_logic := '0';
signal inclk_l1_dly1 : std_logic := '0';
signal inclk_l1_dly2 : std_logic := '0';
signal inclk_l1_dly3 : std_logic := '0';
signal inclk_l1_dly4 : std_logic := '0';
signal inclk_l1_dly5 : std_logic := '0';
signal inclk_l1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal sig_current_clock : string(1 to 6);
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal sig_curr_clock : string(1 to 6) := primary_clock;
signal scan_chain_length : integer := GPP_SCAN_CHAIN;
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_delay : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "e0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal sdataout_trig : std_logic := '0';
signal sdataout_rst_trig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal done_with_param_calc : boolean := false;
COMPONENT stratixgx_m_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0 );
END COMPONENT;
COMPONENT stratixgx_n_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END COMPONENT;
COMPONENT stratixgx_scale_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
time_delay : IN integer := 0;
ph_tap : IN natural );
END COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixgx_pll_reg
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (clkena0_ipd, clkena(0), tipd_clkena(0));
VitalWireDelay (clkena1_ipd, clkena(1), tipd_clkena(1));
VitalWireDelay (clkena2_ipd, clkena(2), tipd_clkena(2));
VitalWireDelay (clkena3_ipd, clkena(3), tipd_clkena(3));
VitalWireDelay (clkena4_ipd, clkena(4), tipd_clkena(4));
VitalWireDelay (clkena5_ipd, clkena(5), tipd_clkena(5));
VitalWireDelay (extclkena0_ipd, extclkena(0), tipd_extclkena(0));
VitalWireDelay (extclkena1_ipd, extclkena(1), tipd_extclkena(1));
VitalWireDelay (extclkena2_ipd, extclkena(2), tipd_extclkena(2));
VitalWireDelay (extclkena3_ipd, extclkena(3), tipd_extclkena(3));
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanaclr_ipd, scanaclr, tipd_scanaclr);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (comparator_ipd, comparator, tipd_comparator);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
-- User to Advanced parameter conversion
i_extclk3_counter <= "e3" when m=0 else extclk3_counter;
i_extclk2_counter <= "e2" when m=0 else extclk2_counter;
i_extclk1_counter <= "e1" when m=0 else extclk1_counter;
i_extclk0_counter <= "e0" when m=0 else extclk0_counter;
i_clk5_counter <= "l1" when m=0 else clk5_counter;
i_clk4_counter <= "l0" when m=0 else clk4_counter;
i_clk3_counter <= "g3" when m=0 else clk3_counter;
i_clk2_counter <= "g2" when m=0 else clk2_counter;
i_clk1_counter <= "g1" when m=0 else clk1_counter;
i_clk0_counter <= "l0" when m=0 and pll_type = "lvds" else
"g0" when m=0 else clk0_counter;
-- end parameter conversion
inclk_m <= extclk0_tmp when operation_mode = "external_feedback" and feedback_source = "extclk0" else
extclk1_tmp when operation_mode = "external_feedback" and feedback_source = "extclk1" else
extclk2_tmp when operation_mode = "external_feedback" and feedback_source = "extclk2" else
extclk3_tmp when operation_mode = "external_feedback" and feedback_source = "extclk3" else
vco_out(m_ph_val);
ext_fbk_cntr <= "e0" when (feedback_source = "extclk0" and extclk0_counter = "e0") or (feedback_source = "extclk1" and extclk1_counter = "e0") or (feedback_source = "extclk2" and extclk2_counter = "e0") or (feedback_source = "extclk3" and extclk3_counter = "e0") else
"e1" when (feedback_source = "extclk0" and extclk0_counter = "e1") or (feedback_source = "extclk1" and extclk1_counter = "e1") or (feedback_source = "extclk2" and extclk2_counter = "e1") or (feedback_source = "extclk3" and extclk3_counter = "e1") else
"e2" when (feedback_source = "extclk0" and extclk0_counter = "e2") or (feedback_source = "extclk1" and extclk1_counter = "e2") or (feedback_source = "extclk2" and extclk2_counter = "e2") or (feedback_source = "extclk3" and extclk3_counter = "e2") else
"e3" when (feedback_source = "extclk0" and extclk0_counter = "e3") or (feedback_source = "extclk1" and extclk1_counter = "e3") or (feedback_source = "extclk2" and extclk2_counter = "e3") or (feedback_source = "extclk3" and extclk3_counter = "e3") else
"e0";
ext_fbk_cntr_high <= e0_high_val when ext_fbk_cntr = "e0" else
e1_high_val when ext_fbk_cntr = "e1" else
e2_high_val when ext_fbk_cntr = "e2" else
e3_high_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_low <= e0_low_val when ext_fbk_cntr = "e0" else
e1_low_val when ext_fbk_cntr = "e1" else
e2_low_val when ext_fbk_cntr = "e2" else
e3_low_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_delay <= e0_time_delay_val when ext_fbk_cntr = "e0" else
e1_time_delay_val when ext_fbk_cntr = "e1" else
e2_time_delay_val when ext_fbk_cntr = "e2" else
e3_time_delay_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_ph <= e0_ph_val when ext_fbk_cntr = "e0" else
e1_ph_val when ext_fbk_cntr = "e1" else
e2_ph_val when ext_fbk_cntr = "e2" else
e3_ph_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_initial <= e0_initial_val when ext_fbk_cntr = "e0" else
e1_initial_val when ext_fbk_cntr = "e1" else
e2_initial_val when ext_fbk_cntr = "e2" else
e3_initial_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_mode <= e0_mode_val when ext_fbk_cntr = "e0" else
e1_mode_val when ext_fbk_cntr = "e1" else
e2_mode_val when ext_fbk_cntr = "e2" else
e3_mode_val when ext_fbk_cntr = "e3" else
e0_mode_val;
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
m1 : stratixgx_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay,
ph => m_ph_val );
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
n1 : stratixgx_n_cntr
port map ( clk => clkin,
reset => areset_ipd,
cout => refclk,
modulus => n_val,
time_delay => n_time_delay_val);
inclk_l0 <= vco_out(l0_ph_val);
l0 : stratixgx_scale_cntr
port map ( clk => inclk_l0,
reset => areset_ena_sig,
cout => l0_clk,
initial => l0_initial_val,
high => l0_high_val,
low => l0_low_val,
mode => l0_mode_val,
time_delay => l0_time_delay_val,
ph_tap => l0_ph_val);
inclk_l1 <= vco_out(l1_ph_val);
l1 : stratixgx_scale_cntr
port map ( clk => inclk_l1,
reset => areset_ena_sig,
cout => l1_clk,
initial => l1_initial_val,
high => l1_high_val,
low => l1_low_val,
mode => l1_mode_val,
time_delay => l1_time_delay_val,
ph_tap => l1_ph_val);
inclk_g0 <= vco_out(g0_ph_val);
g0 : stratixgx_scale_cntr
port map ( clk => inclk_g0,
reset => areset_ena_sig,
cout => g0_clk,
initial => g0_initial_val,
high => g0_high_val,
low => g0_low_val,
mode => g0_mode_val,
time_delay => g0_time_delay_val,
ph_tap => g0_ph_val);
process(g0_clk, l0_clk, l1_clk)
begin
if (g0_clk'event and g0_clk = '1') then
dffa_out <= comparator_ipd;
end if;
if (l0_clk'event and l0_clk = '1' and enable0_counter = "l0") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
if (l1_clk'event and l1_clk = '1' and enable0_counter = "l1") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
end process;
nce_temp <= (not dffc_out) and dffb_out;
nce_l0 <= dffd_out when enable0_counter = "l0" else '0';
nce_l1 <= dffd_out when enable0_counter = "l1" else '0';
inclk_g1 <= vco_out(g1_ph_val);
g1 : stratixgx_scale_cntr
port map ( clk => inclk_g1,
reset => areset_ena_sig,
cout => g1_clk,
initial => g1_initial_val,
high => g1_high_val,
low => g1_low_val,
mode => g1_mode_val,
time_delay => g1_time_delay_val,
ph_tap => g1_ph_val);
inclk_g2 <= vco_out(g2_ph_val);
g2 : stratixgx_scale_cntr
port map ( clk => inclk_g2,
reset => areset_ena_sig,
cout => g2_clk,
initial => g2_initial_val,
high => g2_high_val,
low => g2_low_val,
mode => g2_mode_val,
time_delay => g2_time_delay_val,
ph_tap => g2_ph_val);
inclk_g3 <= vco_out(g3_ph_val);
g3 : stratixgx_scale_cntr
port map ( clk => inclk_g3,
reset => areset_ena_sig,
cout => g3_clk,
initial => g3_initial_val,
high => g3_high_val,
low => g3_low_val,
mode => g3_mode_val,
time_delay => g3_time_delay_val,
ph_tap => g3_ph_val);
inclk_e0 <= vco_out(e0_ph_val);
cntr_e0_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else e0_initial_val;
cntr_e0_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else
e0_time_delay_val;
e0 : stratixgx_scale_cntr
port map ( clk => inclk_e0,
reset => areset_ena_sig,
cout => e0_clk,
initial => cntr_e0_initial,
high => e0_high_val,
low => e0_low_val,
mode => e0_mode_val,
time_delay => cntr_e0_delay,
ph_tap => e0_ph_val);
inclk_e1 <= vco_out(e1_ph_val);
cntr_e1_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else e1_initial_val;
cntr_e1_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else
e1_time_delay_val;
e1 : stratixgx_scale_cntr
port map ( clk => inclk_e1,
reset => areset_ena_sig,
cout => e1_clk,
initial => cntr_e1_initial,
high => e1_high_val,
low => e1_low_val,
mode => e1_mode_val,
time_delay => cntr_e1_delay,
ph_tap => e1_ph_val);
inclk_e2 <= vco_out(e2_ph_val);
cntr_e2_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else e2_initial_val;
cntr_e2_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else
e2_time_delay_val;
e2 : stratixgx_scale_cntr
port map ( clk => inclk_e2,
reset => areset_ena_sig,
cout => e2_clk,
initial => cntr_e2_initial,
high => e2_high_val,
low => e2_low_val,
mode => e2_mode_val,
time_delay => cntr_e2_delay,
ph_tap => e2_ph_val);
inclk_e3 <= vco_out(e3_ph_val);
cntr_e3_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else e3_initial_val;
cntr_e3_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else
e3_time_delay_val;
e3 : stratixgx_scale_cntr
port map ( clk => inclk_e3,
reset => areset_ena_sig,
cout => e3_clk,
initial => cntr_e3_initial,
high => e3_high_val,
low => e3_low_val,
mode => e3_mode_val,
time_delay => cntr_e3_delay,
ph_tap => e3_ph_val);
inclk_l0_dly1 <= inclk_l0;
inclk_l0_dly2 <= inclk_l0_dly1;
inclk_l0_dly3 <= inclk_l0_dly2;
inclk_l0_dly4 <= inclk_l0_dly3;
inclk_l0_dly5 <= inclk_l0_dly4;
inclk_l0_dly6 <= inclk_l0_dly5;
inclk_l1_dly1 <= inclk_l1;
inclk_l1_dly2 <= inclk_l1_dly1;
inclk_l1_dly3 <= inclk_l1_dly2;
inclk_l1_dly4 <= inclk_l1_dly3;
inclk_l1_dly5 <= inclk_l1_dly4;
inclk_l1_dly6 <= inclk_l1_dly5;
process(inclk_l0_dly6, inclk_l1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable l0_got_first_rising_edge : boolean := false;
variable l0_count : integer := 1;
variable l0_tmp, l1_tmp : std_logic := '0';
variable l1_got_first_rising_edge : boolean := false;
variable l1_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
l0_count := 1;
l1_count := 1;
l0_got_first_rising_edge := false;
l1_got_first_rising_edge := false;
else
if (nce_l0 = '0') then
if (not l0_got_first_rising_edge) then
if (inclk_l0_dly6'event and inclk_l0_dly6 = '1') then
l0_got_first_rising_edge := true;
end if;
elsif (inclk_l0_dly6'event) then
l0_count := l0_count + 1;
if (l0_count = (l0_high_val + l0_low_val) * 2) then
l0_count := 1;
end if;
end if;
end if;
if (inclk_l0_dly6'event and inclk_l0_dly6 = '0') then
if (l0_count = 1) then
l0_tmp := '1';
l0_got_first_rising_edge := false;
else
l0_tmp := '0';
end if;
end if;
if (nce_l1 = '0') then
if (not l1_got_first_rising_edge) then
if (inclk_l1_dly6'event and inclk_l1_dly6 = '1') then
l1_got_first_rising_edge := true;
end if;
elsif (inclk_l1_dly6'event) then
l1_count := l1_count + 1;
if (l1_count = (l1_high_val + l1_low_val) * 2) then
l1_count := 1;
end if;
end if;
end if;
if (inclk_l1_dly6'event and inclk_l1_dly6 = '0') then
if (l1_count = 1) then
l1_tmp := '1';
l1_got_first_rising_edge := false;
else
l1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "l0") then
enable0_tmp <= l0_tmp;
elsif (enable0_counter = "l1") then
enable0_tmp <= l1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "l0") then
enable1_tmp <= l0_tmp;
elsif (enable1_counter = "l1") then
enable1_tmp <= l1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (count = gate_lock_counter) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (transfer)
variable init : boolean := true;
variable low, high : std_logic_vector(8 downto 0);
variable delay_chain : std_logic_vector(3 downto 0);
variable mn_delay_chain : std_logic_vector(0 to 3);
variable mode : string(1 to 6) := "bypass";
variable delay_val : integer := 0;
variable is_error : boolean := false;
variable buf : line;
-- user to advanced variables
variable i_m_initial : natural;
variable i_m : integer := 1;
variable i_n : natural := 1;
variable i_m2 : natural;
variable i_n2 : natural;
variable i_ss : natural;
variable i_l0_high : natural;
variable i_l1_high : natural;
variable i_g0_high : natural;
variable i_g1_high : natural;
variable i_g2_high : natural;
variable i_g3_high : natural;
variable i_e0_high : natural;
variable i_e1_high : natural;
variable i_e2_high : natural;
variable i_e3_high : natural;
variable i_l0_low : natural;
variable i_l1_low : natural;
variable i_g0_low : natural;
variable i_g1_low : natural;
variable i_g2_low : natural;
variable i_g3_low : natural;
variable i_e0_low : natural;
variable i_e1_low : natural;
variable i_e2_low : natural;
variable i_e3_low : natural;
variable i_l0_initial : natural;
variable i_l1_initial : natural;
variable i_g0_initial : natural;
variable i_g1_initial : natural;
variable i_g2_initial : natural;
variable i_g3_initial : natural;
variable i_e0_initial : natural;
variable i_e1_initial : natural;
variable i_e2_initial : natural;
variable i_e3_initial : natural;
variable i_l0_mode : string(1 to 6);
variable i_l1_mode : string(1 to 6);
variable i_g0_mode : string(1 to 6);
variable i_g1_mode : string(1 to 6);
variable i_g2_mode : string(1 to 6);
variable i_g3_mode : string(1 to 6);
variable i_e0_mode : string(1 to 6);
variable i_e1_mode : string(1 to 6);
variable i_e2_mode : string(1 to 6);
variable i_e3_mode : string(1 to 6);
variable max_neg_abs : integer := 0;
variable i_l0_time_delay : natural;
variable i_l1_time_delay : natural;
variable i_g0_time_delay : natural;
variable i_g1_time_delay : natural;
variable i_g2_time_delay : natural;
variable i_g3_time_delay : natural;
variable i_e0_time_delay : natural;
variable i_e1_time_delay : natural;
variable i_e2_time_delay : natural;
variable i_e3_time_delay : natural;
variable i_m_time_delay : natural;
variable i_n_time_delay : natural;
variable i_l0_ph : natural;
variable i_l1_ph : natural;
variable i_g0_ph : natural;
variable i_g1_ph : natural;
variable i_g2_ph : natural;
variable i_g3_ph : natural;
variable i_e0_ph : natural;
variable i_e1_ph : natural;
variable i_e2_ph : natural;
variable i_e3_ph : natural;
variable i_m_ph : natural;
variable output_count : natural;
variable new_divisor : natural;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_extclk0_mult_by : integer := 1;
variable i_extclk0_div_by : integer := 1;
variable i_extclk1_mult_by : integer := 1;
variable i_extclk1_div_by : integer := 1;
variable i_extclk2_mult_by : integer := 1;
variable i_extclk2_div_by : integer := 1;
variable i_extclk3_mult_by : integer := 1;
variable i_extclk3_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
begin
if (init) then
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
i_n := 1;
if (pll_type = "lvds") then
i_m := clk0_multiply_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
end if;
i_m_time_delay := maxnegabs ( str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay := mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (pll_type = "lvds") then
i_g0_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
else
i_g0_time_delay := counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,i_n_time_delay);
end if;
i_g1_time_delay := counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_g2_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_g3_time_delay := counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "lvds") then
i_l0_time_delay := i_g0_time_delay;
i_l1_time_delay := i_g0_time_delay;
else
i_l0_time_delay := counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay, i_n_time_delay);
i_l1_time_delay := counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay, i_n_time_delay);
end if;
i_e0_time_delay := counter_time_delay ( str2int(extclk0_time_delay),
i_m_time_delay, i_n_time_delay);
i_e1_time_delay := counter_time_delay ( str2int(extclk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_e2_time_delay := counter_time_delay ( str2int(extclk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_e3_time_delay := counter_time_delay ( str2int(extclk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
else
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_g1_ph := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g2_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_ph := i_g0_ph;
i_l1_ph := i_g0_ph;
else
i_l0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_l1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_e0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e2_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high := counter_high ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_high := counter_high ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high := counter_high ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_high := i_g0_high;
i_l1_high := i_g0_high;
else
i_l0_high := counter_high ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high := counter_high ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_high := counter_high ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high := counter_high ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high := counter_high ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high := counter_high ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (pll_type = "lvds") then
i_g0_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low := counter_low ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_low := counter_low ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low := counter_low ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_low := i_g0_low;
i_l1_low := i_g0_low;
else
i_l0_low := counter_low ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low := counter_low ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_low := counter_low ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low := counter_low ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low := counter_low ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low := counter_low ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
if (pll_type = "lvds") then
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
else
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_g1_initial := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g2_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_initial := i_g0_initial;
i_l1_initial := i_g0_initial;
else
i_l0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_l1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_e0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e2_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
end if;
i_g1_mode := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (pll_type = "lvds") then
i_l0_mode := "bypass";
i_l1_mode := "bypass";
else
i_l0_mode := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end if;
i_e0_mode := counter_mode(extclk0_duty_cycle, output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode := counter_mode(extclk1_duty_cycle, output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode := counter_mode(extclk2_duty_cycle, output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode := counter_mode(extclk3_duty_cycle, output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (feedback_source = "extclk0") then
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
elsif (feedback_source = "extclk1") then
if (i_e1_mode = "bypass") then
output_count := 1;
else
output_count := i_e1_high + i_e1_low;
end if;
elsif (feedback_source = "extclk2") then
if (i_e2_mode = "bypass") then
output_count := 1;
else
output_count := i_e2_high + i_e2_low;
end if;
elsif (feedback_source = "extclk3") then
if (i_e3_mode = "bypass") then
output_count := 1;
else
output_count := i_e3_high + i_e3_low;
end if;
else -- default to e0
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_time_delay := m_time_delay;
i_n_time_delay := n_time_delay;
i_l0_time_delay := l0_time_delay;
i_l1_time_delay := l1_time_delay;
i_g0_time_delay := g0_time_delay;
i_g1_time_delay := g1_time_delay;
i_g2_time_delay := g2_time_delay;
i_g3_time_delay := g3_time_delay;
i_e0_time_delay := e0_time_delay;
i_e1_time_delay := e1_time_delay;
i_e2_time_delay := e2_time_delay;
i_e3_time_delay := e3_time_delay;
i_m_ph := m_ph;
i_l0_ph := l0_ph;
i_l1_ph := l1_ph;
i_g0_ph := g0_ph;
i_g1_ph := g1_ph;
i_g2_ph := g2_ph;
i_g3_ph := g3_ph;
i_e0_ph := e0_ph;
i_e1_ph := e1_ph;
i_e2_ph := e2_ph;
i_e3_ph := e3_ph;
i_l0_high := l0_high;
i_l1_high := l1_high;
i_g0_high := g0_high;
i_g1_high := g1_high;
i_g2_high := g2_high;
i_g3_high := g3_high;
i_e0_high := e0_high;
i_e1_high := e1_high;
i_e2_high := e2_high;
i_e3_high := e3_high;
i_l0_low := l0_low;
i_l1_low := l1_low;
i_g0_low := g0_low;
i_g1_low := g1_low;
i_g2_low := g2_low;
i_g3_low := g3_low;
i_e0_low := e0_low;
i_e1_low := e1_low;
i_e2_low := e2_low;
i_e3_low := e3_low;
i_l0_initial := l0_initial;
i_l1_initial := l1_initial;
i_g0_initial := g0_initial;
i_g1_initial := g1_initial;
i_g2_initial := g2_initial;
i_g3_initial := g3_initial;
i_e0_initial := e0_initial;
i_e1_initial := e1_initial;
i_e2_initial := e2_initial;
i_e3_initial := e3_initial;
i_l0_mode := translate_string(l0_mode);
i_l1_mode := translate_string(l1_mode);
i_g0_mode := translate_string(g0_mode);
i_g1_mode := translate_string(g1_mode);
i_g2_mode := translate_string(g2_mode);
i_g3_mode := translate_string(g3_mode);
i_e0_mode := translate_string(e0_mode);
i_e1_mode := translate_string(e1_mode);
i_e2_mode := translate_string(e2_mode);
i_e3_mode := translate_string(e3_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val_tmp <= i_n;
m_val_tmp <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
end if;
-- NOTE: m_time_delay (vco time delay) not supported for external
-- feedback mode
-- in feedback mode, m_time_delay = delay of feedback loop tap
m_time_delay_val <= i_m_time_delay;
n_time_delay_val <= i_n_time_delay;
m_ph_val <= i_m_ph;
m2_val <= m2;
n2_val <= n2;
if (m2 = 1) then
m2_mode_val <= "bypass";
end if;
if (n2 = 1) then
n2_mode_val <= "bypass";
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
m_initial_val <= 1;
m_time_delay_val <= 0;
m_ph_val <= 0;
end if;
l0_ph_val <= i_l0_ph;
l1_ph_val <= i_l1_ph;
g0_ph_val <= i_g0_ph;
g1_ph_val <= i_g1_ph;
g2_ph_val <= i_g2_ph;
g3_ph_val <= i_g3_ph;
e0_ph_val <= i_e0_ph;
e1_ph_val <= i_e1_ph;
e2_ph_val <= i_e2_ph;
e3_ph_val <= i_e3_ph;
l0_initial_val <= i_l0_initial;
l0_high_val <= i_l0_high;
l0_low_val <= i_l0_low;
l0_mode_val <= i_l0_mode;
l0_time_delay_val <= i_l0_time_delay;
l1_initial_val <= i_l1_initial;
l1_high_val <= i_l1_high;
l1_low_val <= i_l1_low;
l1_mode_val <= i_l1_mode;
l1_time_delay_val <= i_l1_time_delay;
g0_initial_val <= i_g0_initial;
g0_high_val <= i_g0_high;
g0_low_val <= i_g0_low;
g0_mode_val <= i_g0_mode;
g0_time_delay_val <= i_g0_time_delay;
g1_initial_val <= i_g1_initial;
g1_high_val <= i_g1_high;
g1_low_val <= i_g1_low;
g1_mode_val <= i_g1_mode;
g1_time_delay_val <= i_g1_time_delay;
g2_initial_val <= i_g2_initial;
g2_high_val <= i_g2_high;
g2_low_val <= i_g2_low;
g2_mode_val <= i_g2_mode;
g2_time_delay_val <= i_g2_time_delay;
g3_initial_val <= i_g3_initial;
g3_high_val <= i_g3_high;
g3_low_val <= i_g3_low;
g3_mode_val <= i_g3_mode;
g3_time_delay_val <= i_g3_time_delay;
if (scan_chain = "long") then
e0_initial_val <= i_e0_initial;
e0_high_val <= i_e0_high;
e0_low_val <= i_e0_low;
e0_mode_val <= i_e0_mode;
e0_time_delay_val <= i_e0_time_delay;
e1_initial_val <= i_e1_initial;
e1_high_val <= i_e1_high;
e1_low_val <= i_e1_low;
e1_mode_val <= i_e1_mode;
e1_time_delay_val <= i_e1_time_delay;
e2_initial_val <= i_e2_initial;
e2_high_val <= i_e2_high;
e2_low_val <= i_e2_low;
e2_mode_val <= i_e2_mode;
e2_time_delay_val <= i_e2_time_delay;
e3_initial_val <= i_e3_initial;
e3_high_val <= i_e3_high;
e3_low_val <= i_e3_low;
e3_mode_val <= i_e3_mode;
e3_time_delay_val <= i_e3_time_delay;
scan_chain_length <= EGPP_SCAN_CHAIN;
end if;
init := false;
done_with_param_calc <= true;
elsif (transfer'event and transfer = '1') then
reconfig_err <= false;
ASSERT false REPORT "Reconfiguring PLL" severity note;
if (scan_chain = "long") then
-- cntr e3
delay_chain := scan_data(287 downto 284);
if (scan_data(273) = '1') then
e3_mode_val <= "bypass";
if (scan_data(283) = '1') then
e3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(283) = '1') then
e3_mode_val <= " odd";
else
e3_mode_val <= " even";
end if;
high := scan_data(272 downto 264);
low := scan_data(282 downto 274);
e3_low_val <= alt_conv_integer(low);
e3_high_val <= alt_conv_integer(high);
-- count value of 0 is actually 512
if (alt_conv_integer(high) = 0) then
e3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e3_time_delay_val <= delay_val;
-- cntr e2
delay_chain := scan_data(263 downto 260);
if (scan_data(249) = '1') then
e2_mode_val <= "bypass";
if (scan_data(259) = '1') then
e2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(259) = '1') then
e2_mode_val <= " odd";
else
e2_mode_val <= " even";
end if;
high := scan_data(248 downto 240);
low := scan_data(258 downto 250);
e2_low_val <= alt_conv_integer(low);
e2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e2_time_delay_val <= delay_val;
-- cntr e1
delay_chain := scan_data(239 downto 236);
if (scan_data(225) = '1') then
e1_mode_val <= "bypass";
if (scan_data(235) = '1') then
e1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(235) = '1') then
e1_mode_val <= " odd";
else
e1_mode_val <= " even";
end if;
high := scan_data(224 downto 216);
low := scan_data(234 downto 226);
e1_low_val <= alt_conv_integer(low);
e1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e1_time_delay_val <= delay_val;
-- cntr e0
delay_chain := scan_data(215 downto 212);
if (scan_data(201) = '1') then
e0_mode_val <= "bypass";
if (scan_data(211) = '1') then
e0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(211) = '1') then
e0_mode_val <= " odd";
else
e0_mode_val <= " even";
end if;
high := scan_data(200 downto 192);
low := scan_data(210 downto 202);
e0_low_val <= alt_conv_integer(low);
e0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e0_time_delay_val <= delay_val;
end if;
-- cntr l1
delay_chain := scan_data(191 downto 188);
if (scan_data(177) = '1') then
l1_mode_val <= "bypass";
if (scan_data(187) = '1') then
l1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(187) = '1') then
l1_mode_val <= " odd";
else
l1_mode_val <= " even";
end if;
high := scan_data(176 downto 168);
low := scan_data(186 downto 178);
l1_low_val <= alt_conv_integer(low);
l1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l1_time_delay_val <= delay_val;
-- cntr l0
delay_chain := scan_data(167 downto 164);
if (scan_data(153) = '1') then
l0_mode_val <= "bypass";
if (scan_data(163) = '1') then
l0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(163) = '1') then
l0_mode_val <= " odd";
else
l0_mode_val <= " even";
end if;
high := scan_data(152 downto 144);
low := scan_data(162 downto 154);
l0_low_val <= alt_conv_integer(low);
l0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l0_time_delay_val <= delay_val;
-- cntr g3
delay_chain := scan_data(143 downto 140);
if (scan_data(129) = '1') then
g3_mode_val <= "bypass";
if (scan_data(139) = '1') then
g3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(139) = '1') then
g3_mode_val <= " odd";
else
g3_mode_val <= " even";
end if;
high := scan_data(128 downto 120);
low := scan_data(138 downto 130);
g3_low_val <= alt_conv_integer(low);
g3_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g3_time_delay_val <= delay_val;
-- cntr g2
delay_chain := scan_data(119 downto 116);
if (scan_data(105) = '1') then
g2_mode_val <= "bypass";
if (scan_data(115) = '1') then
g2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(115) = '1') then
g2_mode_val <= " odd";
else
g2_mode_val <= " even";
end if;
high := scan_data(104 downto 96);
low := scan_data(114 downto 106);
g2_low_val <= alt_conv_integer(low);
g2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g2_time_delay_val <= delay_val;
-- cntr g1
delay_chain := scan_data(95 downto 92);
if (scan_data(81) = '1') then
g1_mode_val <= "bypass";
if (scan_data(91) = '1') then
g1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(91) = '1') then
g1_mode_val <= " odd";
else
g1_mode_val <= " even";
end if;
high := scan_data(80 downto 72);
low := scan_data(90 downto 82);
g1_low_val <= alt_conv_integer(low);
g1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g1_time_delay_val <= delay_val;
-- cntr g0
delay_chain := scan_data(71 downto 68);
if (scan_data(57) = '1') then
g0_mode_val <= "bypass";
if (scan_data(67) = '1') then
g0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(67) = '1') then
g0_mode_val <= " odd";
else
g0_mode_val <= " even";
end if;
high := scan_data(56 downto 48);
low := scan_data(66 downto 58);
g0_low_val <= alt_conv_integer(low);
g0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g0_time_delay_val <= delay_val;
-- cntr M
is_error := false;
-- 'low' contains modulus for m_cntr(spread_spectrum disabled)
low := scan_data(32 downto 24);
m_val_tmp <= alt_conv_integer(low);
if (scan_data(33) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m_val_tmp <= 512;
end if;
if (not is_error) then
if (m_mode_val = "bypass") then
ASSERT false REPORT "M counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m_mode_val <= " ";
end if;
elsif (scan_data(33) = '1') then
if (scan_data(24) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val /= "bypass") then
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M modulus = "));
write (buf, 1);
writeline (output, buf);
m_val_tmp <= 1;
m_mode_val <= "bypass";
end if;
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
ASSERT FALSE REPORT "VCO is bypassed, setting M modulus = 1, M time delay = 0" severity note;
end if;
-- cntr M2
if (ss > 0) then
is_error := false;
low := scan_data(42 downto 34);
m2_val <= alt_conv_integer(low);
if (scan_data(43) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M2 counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m2_val <= 512;
end if;
if (not is_error) then
if (m2_mode_val = "bypass") then
ASSERT false REPORT "M2 counter switched from BYPASS mode to enabled (M2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m2_mode_val <= " ";
end if;
elsif (scan_data(43) = '1') then
if (scan_data(34) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m2_mode_val /= "bypass") then
ASSERT false REPORT "M2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M2 modulus = "));
write (buf, 1);
writeline (output, buf);
m2_val <= 1;
m2_mode_val <= "bypass";
end if;
end if;
if (m_mode_val /= m2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for M1/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(47 downto 44);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
m_time_delay_val <= delay_val;
if (skip_vco = "on") then
m_time_delay_val <= 0;
delay_val := 0;
end if;
write (buf, string'(" M time delay = "));
write (buf, delay_val);
writeline (output, buf);
-- cntr N
is_error := false;
-- 'low' contains modulus for n_cntr(spread_spectrum disabled)
low := scan_data(8 downto 0);
n_val_tmp <= alt_conv_integer(low);
if (scan_data(9) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n_val_tmp <= 512;
write (buf, string'(" N modulus = "));
write (buf, 512);
writeline (output, buf);
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
if (not is_error) then
if (n_mode_val = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n_mode_val <= " ";
end if;
elsif (scan_data(9) = '1') then
if (scan_data(0) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val /= "bypass") then
ASSERT false REPORT "N counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N modulus = "));
write (buf, 1);
writeline (output, buf);
n_val_tmp <= 1;
n_mode_val <= "bypass";
end if;
end if;
-- cntr N2
if (ss > 0) then
is_error := false;
low := scan_data(18 downto 10);
n2_val <= alt_conv_integer(low);
if (scan_data(19) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N2 counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n2_val <= 512;
end if;
if (not is_error) then
if (n2_mode_val = "bypass") then
ASSERT false REPORT "N2 counter switched from BYPASS mode to enabled (N2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n2_mode_val <= " ";
end if;
elsif (scan_data(19) = '1') then
if (scan_data(10) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n2_mode_val /= "bypass") then
ASSERT false REPORT "N2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N2 modulus = "));
write (buf, 1);
writeline (output, buf);
n2_val <= 1;
n2_mode_val <= "bypass";
end if;
end if;
if (n_mode_val /= n2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for N1/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(23 downto 20);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
n_time_delay_val <= delay_val;
write (buf, string'(" N time delay = "));
write (buf, delay_val);
writeline (output, buf);
else
if (scan_chain = "long") then
write (buf, string'(" E3 high = "));
write (buf, e3_high_val);
write (buf, string'(" , E3 low = "));
write (buf, e3_low_val);
write (buf, string'(" , E3 mode = "));
write (buf, e3_mode_val);
write (buf, string'(" , E3 time delay = "));
write (buf, e3_time_delay_val);
writeline(output, buf);
write (buf, string'(" E2 high = "));
write (buf, e2_high_val);
write (buf, string'(" , E2 low = "));
write (buf, e2_low_val);
write (buf, string'(" , E2 mode = "));
write (buf, e2_mode_val);
write (buf, string'(" , E2 time delay = "));
write (buf, e2_time_delay_val);
writeline(output, buf);
write (buf, string'(" E1 high = "));
write (buf, e1_high_val);
write (buf, string'(" , E1 low = "));
write (buf, e1_low_val);
write (buf, string'(" , E1 mode = "));
write (buf, e1_mode_val);
write (buf, string'(" , E1 time delay = "));
write (buf, e1_time_delay_val);
writeline(output, buf);
write (buf, string'(" E0 high = "));
write (buf, e0_high_val);
write (buf, string'(" , E0 low = "));
write (buf, e0_low_val);
write (buf, string'(" , E0 mode = "));
write (buf, e0_mode_val);
write (buf, string'(" , E0 time delay = "));
write (buf, e0_time_delay_val);
writeline(output, buf);
end if;
write (buf, string'(" L1 high = "));
write (buf, l1_high_val);
write (buf, string'(" , L1 low = "));
write (buf, l1_low_val);
write (buf, string'(" , L1 mode = "));
write (buf, l1_mode_val);
write (buf, string'(" , L1 time delay = "));
write (buf, l1_time_delay_val);
writeline(output, buf);
write (buf, string'(" L0 high = "));
write (buf, l0_high_val);
write (buf, string'(" , L0 low = "));
write (buf, l0_low_val);
write (buf, string'(" , L0 mode = "));
write (buf, l0_mode_val);
write (buf, string'(" , L0 time delay = "));
write (buf, l0_time_delay_val);
writeline(output, buf);
write (buf, string'(" G3 high = "));
write (buf, g3_high_val);
write (buf, string'(" , G3 low = "));
write (buf, g3_low_val);
write (buf, string'(" , G3 mode = "));
write (buf, g3_mode_val);
write (buf, string'(" , G3 time delay = "));
write (buf, g3_time_delay_val);
writeline(output, buf);
write (buf, string'(" G2 high = "));
write (buf, g2_high_val);
write (buf, string'(" , G2 low = "));
write (buf, g2_low_val);
write (buf, string'(" , G2 mode = "));
write (buf, g2_mode_val);
write (buf, string'(" , G2 time delay = "));
write (buf, g2_time_delay_val);
writeline(output, buf);
write (buf, string'(" G1 high = "));
write (buf, g1_high_val);
write (buf, string'(" , G1 low = "));
write (buf, g1_low_val);
write (buf, string'(" , G1 mode = "));
write (buf, g1_mode_val);
write (buf, string'(" , G1 time delay = "));
write (buf, g1_time_delay_val);
writeline(output, buf);
write (buf, string'(" G0 high = "));
write (buf, g0_high_val);
write (buf, string'(" , G0 low = "));
write (buf, g0_low_val);
write (buf, string'(" , G0 mode = "));
write (buf, g0_mode_val);
write (buf, string'(" , G0 time delay = "));
write (buf, g0_time_delay_val);
writeline(output, buf);
end if;
end process;
process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, inclk0_ipd, inclk1_ipd, clkswitch_ipd, done_with_param_calc)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable primary_clock_frequency : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable schedule_offset : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_ext_fbk_cntr : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable init_clks : boolean := true;
variable ext_fbk_cntr_modulus : integer := 1;
variable pll_is_in_reset : boolean := false;
-- clkswitch variables
variable other_clock_value : std_logic := '0';
variable other_clock_last_value : std_logic;
variable current_clock : string(1 to 6) := primary_clock;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (init and done_with_param_calc) then
if (pll_type = "fast") then
locked_tmp := '1';
end if;
m_val <= m_val_tmp;
n_val <= n_val_tmp;
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
-- merged from separate process
if (now = 0 ps) then
if (current_clock = "inclk1") then
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
external_switch := true;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
if (current_clock /= "inclk0") then
other_clock_value := inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event) then
if (current_clock /= "inclk1") then
other_clock_value := inclk1_ipd;
end if;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
if (current_clock = "inclk0") then
current_clk_is_bad := false;
end if;
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = "inclk1") then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_ipd'event and inclk1_ipd = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
if (current_clock = "inclk1") then
current_clk_is_bad := false;
end if;
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = "inclk0") then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if ((primary_clock = "inclk0" and clk0_is_bad = '1') or (primary_clock = "inclk1" and clk1_is_bad = '1')) then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = "inclk0") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event and current_clock = "inclk1") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_ipd;
end if;
else
clkin <= transport inclk1_ipd;
end if;
end if;
if (inclk0_ipd'event or inclk1_ipd'event) then
if ( (other_clock_value = '1') and
(other_clock_value /= other_clock_last_value) and
(switch_over_on_lossclk = "on") and
(enable_switch_over_counter = "on") and
(primary_clk_is_bad) ) then
switch_over_count := switch_over_count + 1;
end if;
if ((other_clock_value = '0') and (other_clock_value /= other_clock_last_value)) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = "inclk0") then
current_clock := "inclk1";
else
current_clock := "inclk0";
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
other_clock_last_value := other_clock_value;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
-- end -- clkswitch
if (schedule_vco'event) then
if (init_clks) then
if (primary_clock = "inclk0") then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk0_input_frequency * 1 ps;
elsif (primary_clock = "inclk1") then
refclk_period := inclk1_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk1_input_frequency * 1 ps;
end if;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
end if;
-- areset deasserted
if (areset_ipd'event and areset_ipd = '0') then
if (scandataout_tmp = '1') then
sdataout_rst_trig <= transport not sdataout_rst_trig;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
end if;
if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
schedule_offset := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and (now > 0 ps)) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
loop_time_delay := m_time_delay_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * (ext_fbk_cntr_modulus));
loop_time_delay := m_time_delay_val + ext_fbk_cntr_delay;
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_ext_fbk_cntr := ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier)/1 ps + fbk_phase;
while (pull_back_ext_fbk_cntr > refclk_period/1 ps) loop
pull_back_ext_fbk_cntr := pull_back_ext_fbk_cntr - refclk_period/ 1 ps;
end loop;
pull_back_M := m_time_delay_val + (m_initial_val - 1) * (ext_fbk_cntr_modulus) * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_ext_fbk_cntr := 0;
pull_back_M := initial_delay/1 ps + m_time_delay_val + fbk_phase;
end if;
total_pull_back := pull_back_M + pull_back_ext_fbk_cntr;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
ext_fbk_delay <= transport (pull_back_ext_fbk_cntr - fbk_phase) after 1 ps;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- add offset
if (schedule_offset) then
sched_time := sched_time + offset;
schedule_offset := false;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
if (sched_time > 0 ps) then
schedule_vco <= transport not schedule_vco after sched_time;
end if;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
n_val <= n_val_tmp;
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ((vco_max /= 0 and vco_min /= 0 and skip_vco = "off" and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
-- unlock
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert false report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= transport m_val_tmp after 1 ps;
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ((now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert (quiet_period_violation) report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
if (pll_type = "fast") then
locked_tmp := '0';
end if;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert (quiet_period_violation) report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped; do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
locked_tmp := 'X';
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (quiet_period_violation or reconfig_err or scanclr_violation or scanclr_clk_violation) then
lock <= '0';
if (pll_type = "fast") then
lock <= '1';
end if;
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
sig_current_clock <= current_clock;
-- signals for debugging
sig_offset <= offset;
sig_refclk_time <= refclk_time;
sig_fbclk_time <= fbclk_time;
sig_fbclk_period <= fbclk_period;
sig_vco_period_was_phase_adjusted <= vco_period_was_phase_adjusted;
sig_phase_adjust_was_scheduled <= phase_adjust_was_scheduled;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
sig_m_times_vco_period <= m_times_vco_period;
sig_new_m_times_vco_period <= new_m_times_vco_period;
sig_got_refclk_posedge <= got_refclk_posedge;
sig_got_fbclk_posedge <= got_fbclk_posedge;
sig_got_second_refclk <= got_second_refclk;
end process;
process (scanclk_ipd, scanaclr_ipd, scan_data, transfer, sdataout_trig, sdataout_rst_trig)
variable j : integer := 0;
variable pll_in_quiet_period : boolean := false;
variable start_quiet_time : time := 0 ps;
variable quiet_time : time := 0 ps;
variable scanclr_rising_time : time := 0 ps;
variable scanclr_falling_time : time := 0 ps;
variable got_first_scanclk_after_scanclr_inactive_edge : boolean := false;
variable scan_chain_being_reset : boolean := false;
function slowest_clk ( L0 : integer; L0_mode : string(1 to 6);
L1 : integer; L1_mode : string(1 to 6);
G0 : integer; G0_mode : string(1 to 6);
G1 : integer; G1_mode : string(1 to 6);
G2 : integer; G2_mode : string(1 to 6);
G3 : integer; G3_mode : string(1 to 6);
E0 : integer; E0_mode : string(1 to 6);
E1 : integer; E1_mode : string(1 to 6);
E2 : integer; E2_mode : string(1 to 6);
E3 : integer; E3_mode : string(1 to 6);
scan_chain : string;
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (L0_mode /= "bypass" and L0_mode /= " off") then
max_modulus := L0;
end if;
if (L1 > max_modulus and L1_mode /= "bypass" and L1_mode /= " off") then
max_modulus := L1;
end if;
if (G0 > max_modulus and G0_mode /= "bypass" and G0_mode /= " off") then
max_modulus := G0;
end if;
if (G1 > max_modulus and G1_mode /= "bypass" and G1_mode /= " off") then
max_modulus := G1;
end if;
if (G2 > max_modulus and G2_mode /= "bypass" and G2_mode /= " off") then
max_modulus := G2;
end if;
if (G3 > max_modulus and G3_mode /= "bypass" and G3_mode /= " off") then
max_modulus := G3;
end if;
if (scan_chain = "long") then
if (E0 > max_modulus and E0_mode /= "bypass" and E0_mode /= " off") then
max_modulus := E0;
end if;
if (E1 > max_modulus and E1_mode /= "bypass" and E1_mode /= " off") then
max_modulus := E1;
end if;
if (E2 > max_modulus and E2_mode /= "bypass" and E2_mode /= " off") then
max_modulus := E2;
end if;
if (E3 > max_modulus and E3_mode /= "bypass" and E3_mode /= " off") then
max_modulus := E3;
end if;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := ((refclk_int/m_mod) * max_modulus) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
begin
if (transfer'event) then
if (transfer = '0') then
-- clear the chain
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
elsif (scanaclr_ipd'event and scanaclr_ipd = '1') then
-- scanaclr rising
scanclr_rising_time := now;
scan_chain_being_reset := true;
elsif (scanaclr_ipd'event and scanaclr_ipd = '0') then
-- scanaclr falling
scanclr_falling_time := now;
if (scan_chain_being_reset and (now - scanclr_rising_time < TRST)) then
scanclr_violation <= true;
ASSERT false REPORT "Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is "& int2str((now - scanclr_rising_time) / 1 ps) &". The PLL may not function correctly." severity warning;
else
scanclr_violation <= false;
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
scan_chain_being_reset := false;
got_first_scanclk_after_scanclr_inactive_edge := false;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and not got_first_scanclk_after_scanclr_inactive_edge and (now - scanclr_falling_time < TRSTCLK)) then
scanclr_clk_violation <= true;
got_first_scanclk_after_scanclr_inactive_edge := true;
ASSERT false REPORT "Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is "& int2str((now - scanclr_falling_time) / 1 ps) &". Reconfiguration may not work." severity warning;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
else
pll_in_quiet_period := false;
for j in scan_chain_length-1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
if (not got_first_scanclk_after_scanclr_inactive_edge) then
got_first_scanclk_after_scanclr_inactive_edge := true;
scanclr_clk_violation <= false;
end if;
elsif (scanclk_ipd'event and scanclk_ipd = '0' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
elsif (scan_data(scan_chain_length-1) = '1') then
-- reset violation flag only after another reconfig seq.
quiet_period_violation <= false;
-- initiate transfer
transfer <= '1';
transfer <= transport '0' after 1 ps;
scandataout_tmp <= '1';
pll_in_quiet_period := true;
start_quiet_time := now;
quiet_time := slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
scan_chain, sig_refclk_period, m_val);
sdataout_trig <= transport not sdataout_trig after quiet_time;
end if;
elsif (sdataout_trig'event) then
if (areset_ipd = '0') then
scandataout_tmp <= transport '0';
end if;
elsif (sdataout_rst_trig'event) then
scandataout_tmp <= transport '0' after quiet_time;
end if;
end process;
clk0_tmp <= l0_clk when i_clk0_counter = "l0" else
l1_clk when i_clk0_counter = "l1" else
g0_clk when i_clk0_counter = "g0" else
g1_clk when i_clk0_counter = "g1" else
g2_clk when i_clk0_counter = "g2" else
g3_clk when i_clk0_counter = "g3" else
'0';
not_clk0_tmp <= not clk0_tmp;
ena0_reg : stratixgx_dffe
port map ( D => clkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0_tmp,
Q => ena0 );
clk(0) <= ena0 and clk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena0 and 'X';
clk1_tmp <= l0_clk when i_clk1_counter = "l0" else
l1_clk when i_clk1_counter = "l1" else
g0_clk when i_clk1_counter = "g0" else
g1_clk when i_clk1_counter = "g1" else
g2_clk when i_clk1_counter = "g2" else
g3_clk when i_clk1_counter = "g3" else
'0';
not_clk1_tmp <= not clk1_tmp;
ena1_reg : stratixgx_dffe
port map ( D => clkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk1_tmp,
Q => ena1 );
clk(1) <= ena1 and clk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena1 and 'X';
clk2_tmp <= l0_clk when i_clk2_counter = "l0" else
l1_clk when i_clk2_counter = "l1" else
g0_clk when i_clk2_counter = "g0" else
g1_clk when i_clk2_counter = "g1" else
g2_clk when i_clk2_counter = "g2" else
g3_clk when i_clk2_counter = "g3" else
'0';
not_clk2_tmp <= not clk2_tmp;
ena2_reg : stratixgx_dffe
port map ( D => clkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk2_tmp,
Q => ena2 );
clk(2) <= ena2 and clk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena2 and 'X';
clk3_tmp <= l0_clk when i_clk3_counter = "l0" else
l1_clk when i_clk3_counter = "l1" else
g0_clk when i_clk3_counter = "g0" else
g1_clk when i_clk3_counter = "g1" else
g2_clk when i_clk3_counter = "g2" else
g3_clk when i_clk3_counter = "g3" else
'0';
not_clk3_tmp <= not clk3_tmp;
ena3_reg : stratixgx_dffe
port map ( D => clkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk3_tmp,
Q => ena3 );
clk(3) <= ena3 and clk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena3 and 'X';
clk4_tmp <= l0_clk when i_clk4_counter = "l0" else
l1_clk when i_clk4_counter = "l1" else
g0_clk when i_clk4_counter = "g0" else
g1_clk when i_clk4_counter = "g1" else
g2_clk when i_clk4_counter = "g2" else
g3_clk when i_clk4_counter = "g3" else
'0';
not_clk4_tmp <= not clk4_tmp;
ena4_reg : stratixgx_dffe
port map ( D => clkena(4),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk4_tmp,
Q => ena4 );
clk(4) <= ena4 and clk4_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena4 and 'X';
clk5_tmp <= l0_clk when i_clk5_counter = "l0" else
l1_clk when i_clk5_counter = "l1" else
g0_clk when i_clk5_counter = "g0" else
g1_clk when i_clk5_counter = "g1" else
g2_clk when i_clk5_counter = "g2" else
g3_clk when i_clk5_counter = "g3" else
'0';
not_clk5_tmp <= not clk5_tmp;
ena5_reg : stratixgx_dffe
port map ( D => clkena(5),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk5_tmp,
Q => ena5 );
clk(5) <= ena5 and clk5_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena5 and 'X';
extclk0_tmp <= e0_clk when i_extclk0_counter = "e0" else
e1_clk when i_extclk0_counter = "e1" else
e2_clk when i_extclk0_counter = "e2" else
e3_clk when i_extclk0_counter = "e3" else
g0_clk when i_extclk0_counter = "g0" else
'0';
not_extclk0_tmp <= not extclk0_tmp;
extena0_reg : stratixgx_dffe
port map ( D => extclkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk0_tmp,
Q => extena0 );
extclk(0) <= extena0 and extclk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena0 and 'X';
extclk1_tmp <= e0_clk when i_extclk1_counter = "e0" else
e1_clk when i_extclk1_counter = "e1" else
e2_clk when i_extclk1_counter = "e2" else
e3_clk when i_extclk1_counter = "e3" else
g0_clk when i_extclk1_counter = "g0" else
'0';
not_extclk1_tmp <= not extclk1_tmp;
extena1_reg : stratixgx_dffe
port map ( D => extclkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk1_tmp,
Q => extena1 );
extclk(1) <= extena1 and extclk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena1 and 'X';
extclk2_tmp <= e0_clk when i_extclk2_counter = "e0" else
e1_clk when i_extclk2_counter = "e1" else
e2_clk when i_extclk2_counter = "e2" else
e3_clk when i_extclk2_counter = "e3" else
g0_clk when i_extclk2_counter = "g0" else
'0';
not_extclk2_tmp <= not extclk2_tmp;
extena2_reg : stratixgx_dffe
port map ( D => extclkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk2_tmp,
Q => extena2 );
extclk(2) <= extena2 and extclk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena2 and 'X';
extclk3_tmp <= e0_clk when i_extclk3_counter = "e0" else
e1_clk when i_extclk3_counter = "e1" else
e2_clk when i_extclk3_counter = "e2" else
e3_clk when i_extclk3_counter = "e3" else
g0_clk when i_extclk3_counter = "g0" else
'0';
not_extclk3_tmp <= not extclk3_tmp;
extena3_reg : stratixgx_dffe
port map ( D => extclkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk3_tmp,
Q => extena3 );
extclk(3) <= extena3 and extclk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena3 and 'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
scandataout <= scandataout_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_dll
--
-- Description : Simulation model for the STRATIXGX DLL.
--
-- Outputs : Delayctrlout output (active high) indicates when the
-- DLL locks to the incoming clock
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_pllpack.all;
ENTITY stratixgx_dll is
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratixgx_dll";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END stratixgx_dll;
ARCHITECTURE vital_dll of stratixgx_dll is
signal clk_detect : std_logic := '0';
signal clk_ipd : std_logic;
begin
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
process (clk_ipd, clk_detect)
variable got_first_rising_edge : boolean := false;
variable got_first_falling_edge : boolean := false;
variable clk_ipd_last_rising_edge : time := 0 ps;
variable clk_ipd_last_falling_edge : time := 0 ps;
variable inclk_ps : time := 0 ps;
variable duty_cycle : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable clk_detect_count : integer := 0;
variable start_clk_detect : boolean := false;
variable half_cycles_to_lock : integer := 0;
variable half_cycles_to_keep_lock : integer := 0;
variable violation : boolean := false;
variable dll_is_locked : std_logic := '0';
variable init : boolean := true;
variable input_freq_warn : boolean := true;
variable duty_cycle_warn : boolean := true;
begin
if (init) then
-- convert the frequency in string form to integer
inclk_ps := dqs_str2int(input_frequency) * 1 ps;
duty_cycle := inclk_ps/2;
clk_per_tolerance := inclk_ps * 0.1;
-- if sim_valid_lock = 0, dll starts out locked
if (sim_valid_lock = 0) then
dll_is_locked := '1';
end if;
init := false;
end if;
if (clk_ipd'event and clk_ipd = '1') then
if (not got_first_rising_edge) then
got_first_rising_edge := true;
half_cycles_to_lock := half_cycles_to_lock + 1;
if (sim_valid_lock > 0 and half_cycles_to_lock >= sim_valid_lock and not violation) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
-- start the internal clock that will monitor
-- the input clock
if (not start_clk_detect) then
start_clk_detect := true;
clk_detect <= '1';
end if;
else
-- reset clk_event counter
clk_detect_count := 0;
-- check for clk period violation
if ( ((now - clk_ipd_last_rising_edge) < (inclk_ps - clk_per_tolerance)) or ((now - clk_ipd_last_rising_edge) > (inclk_ps + clk_per_tolerance)) ) then
violation := true;
if (input_freq_warn) then
assert false report "Input frequency violation." severity warning;
input_freq_warn := false;
end if;
elsif ( ((now - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (violation and dll_is_locked = '1') then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (violation) then
half_cycles_to_lock := 0;
elsif (not violation and dll_is_locked = '0') then
-- increment lock counter
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
else
half_cycles_to_keep_lock := 0;
end if;
end if;
clk_ipd_last_rising_edge := now;
elsif (clk_ipd'event and clk_ipd = '0') then
-- reset clk_event counter
clk_detect_count := 0;
got_first_falling_edge := true;
if (got_first_rising_edge) then
-- check for duty cycle violation
if ( ((now - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (dll_is_locked = '1' and violation) then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (dll_is_locked = '1') then
half_cycles_to_keep_lock := 0;
elsif (dll_is_locked = '0' and violation) then
half_cycles_to_lock := 0;
else
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
else
-- first clk edge is falling edge, do nothing
end if;
clk_ipd_last_falling_edge := now;
else
if (clk_ipd'event) then
-- illegal value
if (got_first_rising_edge or got_first_falling_edge) then
if (dll_is_locked = '1') then
dll_is_locked := '0';
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
else
-- clock started up, then went to 'X'
-- this is to weed out the 'X' at start of simulation.
assert false report "Illegal value detected on input clock." severity error;
-- reset lock counter
half_cycles_to_lock := 0;
end if;
end if;
end if;
end if;
-- ********************************************************************
-- The following block generates the internal clock that is used to
-- track loss of input clock. A counter counts events on this internal
-- clock, and is reset to 0 on event on input clock. If input clock
-- flatlines, the counter will exceed the limit and DLL will lose lock.
-- Events on internal clock are scheduled at the max. allowable input
-- clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
-- ********************************************************************
if (start_clk_detect) then
if (clk_detect'event and clk_detect /= clk_detect'last_value) then
-- increment clock event counter
clk_detect_count := clk_detect_count + 1;
if (dll_is_locked = '1') then
if (clk_detect_count > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to loss of input clock" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
clk_detect_count := 0;
start_clk_detect := false;
clk_detect <= transport '0' after inclk_ps/2;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
elsif (clk_detect_count > 10) then
assert false report "No input clock : DLL will not lock" severity warning;
clk_detect_count := 0;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
end if;
end if;
delayctrlout <= dll_is_locked;
end process;
end vital_dll;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- of STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_tx_parallel_register is
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixgx_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TX_OUT_BLOCK
--
-- Description : Timing simulation model for output block submodule
-- of STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_tx_parallel_register;
use work.stratixgx_dffe;
ENTITY stratixgx_lvds_tx_out_block is
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratixgx_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixgx_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TRANSMITTER
--
-- Description : Timing simulation model for STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_tx_out_block;
ENTITY stratixgx_lvds_transmitter is
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratixgx_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratixgx_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixgx_lvds_transmitter is
signal clk0_ipd : std_logic;
signal not_clk0 : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal txload1 : std_logic;
signal txload2 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly5 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
COMPONENT stratixgx_lvds_tx_parallel_register
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_tx_out_block
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01
);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
end block;
txload0_reg: stratixgx_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly2,
Q => txload0);
txload1_reg: stratixgx_dffe
PORT map(D => txload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly1,
Q => txload1);
not_clk0 <= not clk0_dly0;
txload2_reg: stratixgx_dffe
PORT map(D => txload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => txload2);
input_reg: stratixgx_lvds_tx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor);
output_module: stratixgx_lvds_tx_out_block
GENERIC map(bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT map(clk => clk0_dly2,
datain => shift_out,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly5 <= datain_dly4;
end process;
data_delay2: process (datain_dly5)
begin
datain_dly <= datain_dly5;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable i : integer := 0;
variable dataout_tmp : std_logic;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload2 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
end vital_transmitter_atom;
-------------------------------------------------------------------
--
-- Entity Name : stratixgx_jtag
--
-- Description : STRATIXGX JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_jtag is
generic (
lpm_type : string := "stratixgx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixgx_jtag;
architecture architecture_jtag of stratixgx_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixgx_crcblock
--
-- Description : STRATIXGX CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixgx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixgx_crcblock;
architecture architecture_crcblock of stratixgx_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixgx_rublock
--
-- Description : STRATIXGX RUBLOCK VHDL Simulation model
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixgx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratixgx_rublock;
architecture architecture_rublock of stratixgx_rublock is
signal update_reg : std_logic_vector(16 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(21 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is inverted output of shift-reg bit 0
regout <= not shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(16 downto 5) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(4) <= '1';
else
update_reg(4) <= '0';
end if;
-- PGM[] field
update_reg(3 downto 1) <= conv_std_logic_vector(sim_init_page_select, 3);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1]);
--report " -> Field User Watchdog is set to %s", update_reg[4] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 20 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(21) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and operation_mode = "remote") then
-- every bit in Update Reg gets updated
update_reg(16 downto 0) <= shift_reg(21 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[8:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[9] == 1) ? "Enableds" : (shift_reg[9] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[21:10];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
else
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1];
--report " -> Field User Watchdog is set to %s", (update_reg[4] == 1) ? "Enabled" : (update_reg[4] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
---------------------------------------------------------------------
--
-- Entity Name : stratixgx_routing_wire
--
-- Description : STRATIXGXII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_routing_wire : entity is TRUE;
end stratixgx_routing_wire;
ARCHITECTURE behave of stratixgx_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_deserializer
--
-- Description : Timing simulation model for deserializer submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_deserializer is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk0_pclk_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
clk0 : IN std_logic := '0';
coreclk : IN std_logic := '0';
datain : IN std_logic := '0';
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 downto 0);
pclk : OUT std_logic
);
end stratixgx_lvds_rx_deserializer;
ARCHITECTURE vital_stratixgx_lvds_rx_deserializer of stratixgx_lvds_rx_deserializer is
signal clk0_in : std_logic;
signal coreclk_in : std_logic;
signal coreclk_in_pre : std_logic;
signal datain_in : std_logic;
signal reset_in : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (coreclk_in_pre, coreclk, tipd_coreclk);
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (reset_in, reset, tipd_reset);
end block;
coreclk_delta : process (coreclk_in_pre)
begin
coreclk_in <= coreclk_in_pre;
end process;
vital : process (clk0_in, coreclk_in, reset_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable pclk_VitalGlitchData : VitalGlitchDataType;
variable datain_pos : std_logic;
variable datain_neg : std_logic;
variable sync_reset : std_logic;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable clkout_tmp : std_logic := '0';
variable deser_data_arr : std_logic_vector(channel_width - 1 downto 0);
variable clk_count : integer;
variable clk_count_neg : integer;
variable clk0_last_value : std_logic;
variable coreclk_last_value : std_logic;
variable clkout_last_value : std_logic;
variable i : integer;
VARIABLE CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
i := 0;
clk_count := channel_width;
clk_count_neg := 0;
clkout_last_value := '0';
coreclk_last_value := '0';
dataout_tmp := (OTHERS => '0');
datain_pos := '0';
datain_neg := '0';
sync_reset := '0';
for i in channel_width - 1 downto 0 loop
deser_data_arr(i) := '0';
end loop;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value /= clk0_in) then
if (clk_count = channel_width) then
clk_count := 0;
if (sync_reset = '0') then
clkout_tmp := NOT clkout_last_value;
end if;
else
if (clk_count = (channel_width + 1) / 2) then
if (sync_reset = '0') then
clkout_tmp := NOT clkout_last_value;
end if;
else
if (clk_count < channel_width) then
if (sync_reset = '0') then
clkout_tmp := clkout_last_value;
end if;
end if;
end if;
end if;
clk_count := clk_count + 1;
if (sync_reset = '1') then
dataout_tmp := (OTHERS => '0');
elsif (clk_count_neg = 2) then
dataout_tmp := deser_data_arr;
end if;
datain_pos := datain_neg;
for i in channel_width-1 downto 1 loop
deser_data_arr(i) := deser_data_arr(i - 1);
end loop;
deser_data_arr(0) := datain_pos;
end if;
if (clk0_in'event and (clk0_in = '0')) then
clk_count_neg := clk_count_neg + 1;
datain_neg := datain_in;
end if;
if (coreclk_in'event and (coreclk_in = '1')) then
if (reset_in = '1') then
sync_reset := '1';
else
sync_reset := '0';
clk_count_neg := 0;
end if;
end if;
if (clkout_tmp /= 'U') then
clkout_last_value := clkout_tmp;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => pclk,
OutsignalName => "PCLK",
OutTemp => clkout_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_pclk_posedge, TRUE)),
GlitchData => pclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
CQDelay := SelectDelay (
Paths => (
(0 => (clk0_in'LAST_EVENT,tpd_clk0_dataout_posedge, TRUE))
)
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_deserializer;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_RX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_parallel_register is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_lvds_rx_parallel_register;
ARCHITECTURE vital_stratixgx_lvds_rx_parallel_register of stratixgx_lvds_rx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, devpor, devclrn)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (reset = '1') then
dataout_tmp := (OTHERS => '0');
elsif (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_parallel_register;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_fifo_sync_ram
--
-- Description : Timing simulation model for FIFO SYNC RAM submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_fifo_sync_ram is
GENERIC (
ram_width : integer := 10
);
PORT (
clk : in std_logic := '0';
datain : in std_logic_vector(ram_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : in std_logic := '0';
waddr : in std_logic_vector(1 DOWNTO 0) := "00";
raddr : in std_logic_vector(1 DOWNTO 0) := "00";
we : in std_logic := '0';
dataout : out std_logic_vector(ram_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_stratixgx_lvds_rx_fifo_sync_ram OF stratixgx_lvds_rx_fifo_sync_ram IS
signal ram_d0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal dataout_tmp : std_logic_vector(ram_width - 1 DOWNTO 0);
begin
data_reg0 <= datain WHEN (waddr = "00") ELSE ram_q0 ;
data_reg1 <= datain WHEN (waddr = "01") ELSE ram_q1 ;
data_reg2 <= datain WHEN (waddr = "10") ELSE ram_q2 ;
data_reg3 <= datain WHEN (waddr = "11") ELSE ram_q3 ;
dataout <= dataout_tmp;
process (clk, reset)
begin
if (now = 0 ns) then
ram_q0 <= (OTHERS => '0');
ram_q1 <= (OTHERS => '0');
ram_q2 <= (OTHERS => '0');
ram_q3 <= (OTHERS => '0');
end if;
if (reset = '1') then
ram_q0 <= (OTHERS => '0');
ram_q1 <= (OTHERS => '0');
ram_q2 <= (OTHERS => '0');
ram_q3 <= (OTHERS => '0');
elsif (clk'event and clk = '1') then
ram_q0 <= ram_d0;
ram_q1 <= ram_d1;
ram_q2 <= ram_d2;
ram_q3 <= ram_d3;
end if;
end process;
process (we, data_reg0, data_reg1, data_reg2, data_reg3, ram_q0, ram_q1, ram_q2, ram_q3)
begin
if (we = '1') then
ram_d0 <= data_reg0;
ram_d1 <= data_reg1;
ram_d2 <= data_reg2;
ram_d3 <= data_reg3;
else
ram_d0 <= ram_q0;
ram_d1 <= ram_q1;
ram_d2 <= ram_q2;
ram_d3 <= ram_q3;
end if;
end process;
process (ram_q0, ram_q1, ram_q2, ram_q3, we, waddr, raddr)
begin
if (now = 0 ns) then
dataout_tmp <= (OTHERS => '0');
end if;
case raddr is
WHEN "00" =>
dataout_tmp <= ram_q0;
WHEN "01" =>
dataout_tmp <= ram_q1;
WHEN "10" =>
dataout_tmp <= ram_q2;
WHEN "11" =>
dataout_tmp <= ram_q3;
WHEN OTHERS =>
NULL;
end case;
end process;
END vital_stratixgx_lvds_rx_fifo_sync_ram;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_fifo
--
-- Description : Timing simulation model for RX FIFO submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_fifo_sync_ram;
ENTITY stratixgx_lvds_rx_fifo is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
reset : IN std_logic := '0';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_fifo;
ARCHITECTURE vital_stratixgx_lvds_rx_fifo of stratixgx_lvds_rx_fifo is
signal wclk_in : std_logic;
signal rclk_in : std_logic;
signal reset_in : std_logic;
signal datain_in : std_logic_vector(channel_width - 1 downto 0);
signal rdAddr : std_logic_vector(1 downto 0);
signal rdPtr : std_logic_vector(1 downto 0);
signal wrPtr : std_logic_vector(1 downto 0);
signal ram_datain : std_logic_vector(channel_width - 1 downto 0);
signal ram_dataout : std_logic_vector(channel_width - 1 downto 0);
signal ram_we : std_logic;
signal sync_reset : std_logic := '0';
COMPONENT stratixgx_lvds_rx_fifo_sync_ram
GENERIC (
ram_width : integer := 10
);
PORT (
clk : in std_logic := '0';
datain : in std_logic_vector(ram_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : in std_logic := '0';
waddr : in std_logic_vector(1 DOWNTO 0) := "00";
raddr : in std_logic_vector(1 DOWNTO 0) := "00";
we : in std_logic := '0';
dataout : out std_logic_vector(ram_width - 1 DOWNTO 0)
);
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (reset_in, reset, tipd_reset);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixgx_lvds_rx_fifo_sync_ram
GENERIC map (
ram_width => channel_width
)
PORT map (
clk => wclk_in,
datain => ram_datain,
reset => sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, sync_reset)
begin
if (now = 0 ns) then
wrPtr <= "00";
ram_datain <= (OTHERS => '0');
ram_we <= '0';
end if;
if (sync_reset = '1') then
wrPtr <= "00";
ram_we <= '0';
elsif (wclk_in'event and wclk_in = '1') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "00" => wrPtr <= "01";
when "01" => wrPtr <= "10";
when "10" => wrPtr <= "11";
when "11" => wrPtr <= "00";
when others => wrPtr <= "00";
end case;
end if;
end process;
process (rclk_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable dataout_tmp : std_logic_vector(channel_width - 1 DOWNTO 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
end if;
if (rclk_in'event and rclk_in = '1' and rclk_in'last_value = '0') then
if (reset_in = '1') then
sync_reset <= '1';
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
else
if (sync_reset = '1') then
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
else
dataout_tmp := ram_dataout;
case rdPtr is
when "00" => rdPtr <= "01";
when "01" => rdPtr <= "10";
when "10" => rdPtr <= "11";
when "11" => rdPtr <= "00";
when others => rdPtr <= "00";
end case;
end if;
sync_reset <= '0';
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_fifo;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_bitslip
--
-- Description : Timing simulation model for Bitslip submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_bitslip is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
coreclk : IN std_logic := '0';
bitslip : IN std_logic := '0';
rxpdat2 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpdat3 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_bitslip;
ARCHITECTURE vital_stratixgx_lvds_rx_bitslip of stratixgx_lvds_rx_bitslip is
signal bitslip_in : std_logic;
signal bitslip0 : std_logic;
signal bitslip1 : std_logic;
signal bitslip_cntl : std_logic;
signal coreclk_in : std_logic;
signal slip_count_sig : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (coreclk_in, coreclk, tipd_coreclk);
VitalWireDelay (bitslip_in, bitslip, tipd_bitslip);
end block;
vital : process (coreclk_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable slip_count : integer;
variable dataout_tmp : std_logic_vector(channel_width - 1 DOWNTO 0);
variable i : integer;
variable j : integer;
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
slip_count := 0;
bitslip0 <= '0';
bitslip1 <= '0';
dataout_tmp := (OTHERS => '0');
end if;
if (coreclk_in'event and coreclk_in = '1') then
if (reset = '1') then
slip_count := 0;
bitslip0 <= '0';
bitslip1 <= '0';
bitslip_cntl <= '0';
dataout_tmp := (OTHERS => '0');
else
bitslip_cntl <= bitslip1 AND (NOT bitslip0);
bitslip0 <= bitslip1;
bitslip1 <= bitslip_in;
if (bitslip_cntl = '1') then
slip_count := slip_count + 1;
if (slip_count = channel_width) then
slip_count := 0;
end if;
end if;
if (slip_count = 0) then
dataout_tmp := rxpdat3;
else
j := 0;
for i in (channel_width - slip_count) to (channel_width - 1) loop
dataout_tmp(j) := rxpdat2(i);
j := j + 1;
end loop;
for i in 0 to ((channel_width - slip_count) - 1) loop
dataout_tmp(j) := rxpdat3(i);
j := j + 1;
end loop;
end if;
end if;
end if;
slip_count_sig <= slip_count;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
Paths => (
(0 => (coreclk_in'LAST_EVENT,tpd_coreclk_dataout_posedge,TRUE))
)
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_bitslip;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_DPA_RECEIVER
--
-- Description : Timing simulation model for DPA_RECEIVER submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_deserializer;
use work.stratixgx_lvds_rx_parallel_register;
use work.stratixgx_lvds_rx_fifo;
use work.stratixgx_lvds_rx_bitslip;
ENTITY stratixgx_dpa_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end stratixgx_dpa_receiver;
ARCHITECTURE vital_stratixgx_dpa_receiver of stratixgx_dpa_receiver is
signal dpllreset_in : std_logic;
signal dpareset_in : std_logic;
-- internal reset signal
signal reset_int : std_logic;
-- output from rx_deserializer
signal deser_dataout : std_logic_vector(channel_width - 1 downto 0);
signal deser_pclk : std_logic;
-- input/output of FIFO
signal fifo_datain : std_logic_vector(channel_width - 1 downto 0);
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of RXPDAT2
signal rxpdat2_datain : std_logic_vector(channel_width - 1 downto 0);
signal rxpdat2_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of RXPDAT3
signal rxpdat3_datain : std_logic_vector(channel_width - 1 downto 0);
signal rxpdat3_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of bitslip
signal slip_pdat2 : std_logic_vector(channel_width - 1 downto 0);
signal slip_pdat3 : std_logic_vector(channel_width - 1 downto 0);
signal dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
signal dpalock_tmp : std_logic := '1';
signal vcc : std_logic := '1';
COMPONENT stratixgx_lvds_rx_deserializer
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk0_pclk_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
clk0 : IN std_logic := '0';
coreclk : IN std_logic := '0';
datain : IN std_logic := '0';
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 downto 0);
pclk : OUT std_logic
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_parallel_register
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_fifo
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
reset : IN std_logic := '0';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_bitslip
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
coreclk : IN std_logic := '0';
bitslip : IN std_logic := '0';
rxpdat2 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpdat3 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (dpareset_in, dpareset, tipd_dpareset);
VitalWireDelay (dpllreset_in, dpllreset, tipd_dpllreset);
end block;
reset_int <= (NOT devpor) OR (NOT devclrn) OR dpareset_in OR dpllreset_in ;
-- FIFO inputs
fifo_datain <= deser_dataout ;
fifo_wclk <= deser_pclk ;
fifo_rclk <= coreclk ;
-- RXPDAT2/3 inputs
rxpdat2_datain <= fifo_dataout WHEN (enable_fifo = "on") else deser_dataout ;
rxpdat3_datain <= rxpdat2_dataout ;
-- bitslip inputs
slip_pdat2 <= rxpdat2_dataout ;
slip_pdat3 <= rxpdat3_dataout ;
-- set output
dataout <= dataout_tmp;
dpalock <= dpalock_tmp;
-- sub modules
s_deserializer : stratixgx_lvds_rx_deserializer
GENERIC map (
channel_width => channel_width
)
PORT map (
clk0 => clk0,
coreclk => coreclk,
datain => datain,
reset => reset_int,
dataout => deser_dataout,
pclk => deser_pclk
);
s_fifo : stratixgx_lvds_rx_fifo
GENERIC map (
channel_width => channel_width
)
PORT map (
wclk => fifo_wclk,
rclk => fifo_rclk,
reset => reset_int,
datain => fifo_datain,
dataout => fifo_dataout
);
s_rxpdat2 : stratixgx_lvds_rx_parallel_register
GENERIC map (
channel_width => channel_width
)
PORT map (
clk => coreclk,
datain => rxpdat2_datain,
enable => vcc,
reset => reset_int,
devpor => vcc,
devclrn => vcc,
dataout => rxpdat2_dataout
);
s_rxpdat3 : stratixgx_lvds_rx_parallel_register
GENERIC map (
channel_width => channel_width
)
PORT map (
clk => coreclk,
datain => rxpdat3_datain,
enable => vcc,
reset => reset_int,
devpor => vcc,
devclrn => vcc,
dataout => rxpdat3_dataout
);
s_bitslip : stratixgx_lvds_rx_bitslip
GENERIC map (
channel_width => channel_width
)
PORT map (
coreclk => coreclk,
bitslip => bitslip,
rxpdat2 => slip_pdat2,
rxpdat3 => slip_pdat3,
reset => reset_int,
dataout => dataout_tmp
);
end vital_stratixgx_dpa_receiver;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_nondpa_lvds_receiver
--
-- Description : Timing simulation model for NONDPA_RECEIVER submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_parallel_register;
use work.stratixgx_dffe;
use work.stratixgx_and1;
ENTITY stratixgx_nondpa_lvds_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_nondpa_lvds_receiver;
ARCHITECTURE vital_receiver_atom of stratixgx_nondpa_lvds_receiver is
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal not_clk0 : std_logic;
signal txload_in : std_logic;
signal rxload0 : std_logic;
signal rxload1 : std_logic;
signal rxload2 : std_logic;
signal shift_data : std_logic_vector(channel_width - 1 downto 0);
signal load_data : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal gnd : std_logic := '0';
COMPONENT stratixgx_lvds_rx_parallel_register
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
COMPONENT stratixgx_and1
GENERIC (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
begin
clkdelaybuffer: stratixgx_and1
PORT map(IN1 => clk0,
Y => clk0_ipd);
dataindelaybuffer: stratixgx_and1
PORT map(IN1 => datain,
Y => datain_ipd);
rxload0_reg: stratixgx_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload0);
rxload1_reg: stratixgx_dffe
PORT map(D => rxload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload1);
not_clk0 <= not clk0;
rxload2_reg: stratixgx_dffe
PORT map(D => rxload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => rxload2);
txload_in <= enable1 when use_enable1 = "true" else
enable0;
load_reg: stratixgx_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => not_clk0,
enable => rxload2,
datain => shift_data,
reset => gnd,
dataout => load_data,
devclrn => devclrn,
devpor => devpor);
output_reg: stratixgx_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => clk0,
enable => txload_in,
datain => load_data,
reset => gnd,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
VITAL: process (clk0_ipd, devpor, devclrn)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable shift_out : std_logic;
begin
if (now = 0 ns) then
shift_data <= (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data <= (OTHERS => '0');
else
if (clk0_ipd'event and clk0_ipd = '0') then
for i in channel_width-1 downto 1 loop
shift_data(i) <= shift_data(i-1);
end loop;
shift_data(0) <= datain_ipd;
end if;
end if;
end process;
end vital_receiver_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_RECEIVER
--
-- Description : Timing simulation model for Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////--
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_nondpa_lvds_receiver;
use work.stratixgx_dpa_receiver;
ENTITY stratixgx_lvds_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end stratixgx_lvds_receiver;
ARCHITECTURE vital_stratixgx_lvds_receiver of stratixgx_lvds_receiver is
-- signals for DPA mode
signal dpa_clk0 : std_logic;
signal dpa_coreclk : std_logic;
signal dpa_datain : std_logic;
signal dpa_enable0 : std_logic;
signal dpa_enable1 : std_logic;
signal dpa_dpareset : std_logic;
signal dpa_dpllreset: std_logic;
signal dpa_bitslip : std_logic;
signal dpa_devclrn : std_logic;
signal dpa_devpor : std_logic;
signal dpa_dpalock : std_logic;
signal dpa_dataout : std_logic_vector(channel_width - 1 downto 0);
-- signals for NONDPA mode
signal nondpa_clk0 : std_logic;
signal nondpa_datain : std_logic;
signal nondpa_enable0 : std_logic;
signal nondpa_enable1 : std_logic;
signal nondpa_devclrn : std_logic;
signal nondpa_devpor : std_logic;
signal nondpa_dataout : std_logic_vector(channel_width - 1 downto 0);
signal gnd : std_logic := '0';
COMPONENT stratixgx_nondpa_lvds_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_dpa_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end COMPONENT;
begin
-- DPA mode inputs
dpa_clk0 <= clk0 WHEN (enable_dpa = "on") ELSE gnd;
dpa_coreclk <= coreclk WHEN (enable_dpa = "on") ELSE gnd;
dpa_datain <= datain WHEN (enable_dpa = "on") ELSE gnd;
dpa_enable0 <= gnd;
dpa_enable1 <= gnd;
dpa_dpareset <= dpareset WHEN (enable_dpa = "on") ELSE gnd;
dpa_dpllreset <= dpllreset WHEN (enable_dpa = "on") ELSE gnd;
dpa_bitslip <= bitslip WHEN (enable_dpa = "on") ELSE gnd;
dpa_devpor <= devpor WHEN (enable_dpa = "on") ELSE gnd;
dpa_devclrn <= devclrn WHEN (enable_dpa = "on") ELSE gnd;
-- NONDPA mode inputs
nondpa_clk0 <= clk0 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_datain <= datain WHEN (enable_dpa = "off") ELSE gnd;
nondpa_enable0 <= enable0 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_enable1 <= enable1 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_devpor <= devpor WHEN (enable_dpa = "off") ELSE gnd;
nondpa_devclrn <= devclrn WHEN (enable_dpa = "off") ELSE gnd;
-- sub modules
s_nondpa_receiver : stratixgx_nondpa_lvds_receiver
GENERIC map
(
channel_width => channel_width,
use_enable1 => use_enable1,
MsgOn => MsgOn,
XOn => XOn,
MsgOnChecks => MsgOnChecks,
XOnChecks => XOnChecks,
InstancePath => InstancePath,
tpd_clk0_dataout_posedge => tpd_clk0_dataout_posedge,
tipd_clk0 => tipd_clk0,
tipd_enable0 => tipd_enable0,
tipd_enable1 => tipd_enable1,
tipd_datain => tipd_datain
)
PORT map
(
clk0 => nondpa_clk0,
enable0 => nondpa_enable0,
enable1 => nondpa_enable1,
datain => nondpa_datain,
devclrn => nondpa_devclrn,
devpor => nondpa_devpor,
dataout => nondpa_dataout
);
s_dpa_receiver : stratixgx_dpa_receiver
GENERIC map
(
channel_width => channel_width,
use_enable1 => use_enable1,
enable_dpa => enable_dpa,
dpll_rawperror => dpll_rawperror,
dpll_lockwin => dpll_lockwin,
dpll_lockcnt => dpll_lockcnt,
enable_fifo => enable_fifo,
MsgOn => MsgOn,
XOn => XOn,
MsgOnChecks => MsgOnChecks,
XOnChecks => XOnChecks,
InstancePath => InstancePath,
tpd_clk0_dataout_posedge => tpd_clk0_dataout_posedge,
tipd_clk0 => tipd_clk0,
tipd_dpllreset => tipd_dpllreset,
tipd_dpareset => tipd_dpareset
)
PORT map
(
clk0 => clk0,
coreclk => coreclk,
enable0 => enable0,
enable1 => enable1,
datain => datain,
dpareset => dpareset,
dpllreset => dpllreset,
bitslip => bitslip,
devclrn => dpa_devclrn,
devpor => dpa_devpor,
dataout => dpa_dataout,
dpalock => dpa_dpalock
);
-- generate output
dataout <= dpa_dataout WHEN (enable_dpa = "on") ELSE nondpa_dataout;
dpalock <= dpa_dpalock WHEN (enable_dpa = "on") ELSE gnd;
end vital_stratixgx_lvds_receiver;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00020000";
constant x_DATA_BASE_ADDR : reg32 := x"00080000";
constant x_DATA_MEM_SZ : reg32 := x"00080000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"00000680"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000700"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_DMA_ADDR : integer := IO_BASE_ADDR + 13*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_signed( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
----------------------------------------------------------------------------------
-- Engineer: Brett Bourgeois
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity MUX2to1 is
generic (vectorSize : integer:= BITREG_16);
Port (
SEL : in STD_LOGIC; -- 2 bits
IN_1 : in STD_LOGIC_VECTOR (vectorSize-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (vectorSize-1 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (vectorSize-1 downto 0)
);
end MUX2to1;
architecture behavioral of MUX2to1 is
begin
OUTPUT<=IN_1 when SEL='0'
ELSE
IN_2;
end behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#00f3#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002B#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fffe#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: fifo_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY fifo_mem_tb IS
END ENTITY;
ARCHITECTURE fifo_mem_tb_ARCH OF fifo_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
fifo_mem_synth_inst:ENTITY work.fifo_mem_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: fifo_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY fifo_mem_tb IS
END ENTITY;
ARCHITECTURE fifo_mem_tb_ARCH OF fifo_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
fifo_mem_synth_inst:ENTITY work.fifo_mem_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_args_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_m2s_adapter;
use axis_accelerator_adapter_v2_1_6.xd_oarg_s2s_adapter;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
entity xd_output_args_module is
generic (
-- System generics:
C_FAMILY : string ; -- Xilinx FPGA family
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_MAX_ARG_DWIDTH : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_ARG_N_DIM : integer;
C_MAX_MB_DEPTH : integer;
C_MAX_N_OARGS : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MTBF_STAGES : integer;
C_N_OUTPUT_ARGS : integer;
C_M_AXIS_TDATA_WIDTH : integer;
C_M_AXIS_TUSER_WIDTH : integer;
C_M_AXIS_TID_WIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer;
C_AP_OARG_TYPE : std_logic_vector;
C_AP_OARG_DWIDTH : std_logic_vector; -- Interface width
C_AP_OARG_MB_DEPTH : std_logic_vector;
C_AP_OARG_WIDTH : std_logic_vector; -- Native width of data
C_AP_OARG_N_DIM : std_logic_vector;
C_AP_OARG_DIM : std_logic_vector;
C_AP_OARG_DIM_1 : std_logic_vector;
C_AP_OARG_DIM_2 : std_logic_vector;
C_AP_OARG_FORMAT_TYPE : std_logic_vector;
C_AP_OARG_FORMAT_FACTOR : std_logic_vector;
C_AP_OARG_FORMAT_DIM : std_logic_vector;
C_NONE : integer := 2);
port (
--- Slave AXI streams (output arguments)
M_AXIS_ACLK : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_ARESETN : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TVALID : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TREADY : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TDATA : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TLAST : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
---
oarg_sw_length : in std_logic_vector(31 downto 0);
oarg_sw_length_m2s : in std_logic_vector(31 downto 0);
oarg_sw_length_we : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_use_sw_length : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
host_oarg_tdest : in std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
---
dbg_stream_nwords : out std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_buffer_nwords : out std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_ap_done : in std_logic;
--- AP output arguments
ap_clk : in std_logic;
ap_rst_maclk : in std_logic;
ap_rst : in std_logic;
ap_oarg_rst : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_addr : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
ap_oarg_ce : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_we : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_oarg_dout : out std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_oarg_rdy : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_done : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_empty : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_full : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_used : out std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
ap_fifo_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_fifo_oarg_write : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_fifo_oarg_full_n : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_start : in std_logic;
ap_done : in std_logic);
end entity;
architecture rtl of xd_output_args_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant C_M_AXIS_TSTRB_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TKEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
alias C_AP_OARG_DIM_dw : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_N_DIM*32-1 downto 0) is C_AP_OARG_DIM;
-- Syncrhonizer Signals
signal oarg_use_sw_length_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_sw_length_we_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_aresetn : std_logic;
signal m_aclk : std_logic;
signal axis_rst : std_logic;
signal axis_rst1 : std_logic;
signal oarg_sw_length_sync_s2s : std_logic_vector(31 downto 0);
signal oarg_sw_length_sync_m2s : std_logic_vector(31 downto 0);
signal ap_rst_sync1_maclk : std_logic;
signal ap_rst_sync_maclk : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ap_rst_sync_maclk : SIGNAL IS "true";
ATTRIBUTE async_reg OF ap_rst_sync1_maclk : SIGNAL IS "true";
begin
-- undriven ports
dbg_stream_nwords <= (others => '0');
dbg_buffer_nwords <= (others => '0');
m_aresetn <= M_AXIS_ARESETN(0);
m_aclk <= M_AXIS_ACLK(0);
------------------------------------
--- aclk to m_axis_aclk Synchronizer
------------------------------------
-- EN_LITE_TO_STRM_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
-- begin
PROCESS (m_aclk, m_aresetn)
BEGIN
-- Register Stage #1
IF (m_aresetn = '0') THEN
axis_rst1 <= '1';
axis_rst <= '1';
ELSIF (m_aclk'event and m_aclk = '1') THEN
axis_rst1 <= '0';
axis_rst <= axis_rst1;
END IF;
END PROCESS;
-- prd1: PROCESS (m_aclk)
-- BEGIN
-- -- Register Stage #1
-- IF (m_aclk'event and m_aclk = '1') THEN
-- ap_rst_sync1_maclk <= ap_rst;
-- ap_rst_sync_maclk <= ap_rst_sync1_maclk;
-- END IF;
-- END PROCESS prd1;
SW_LENGTH_SYNC_M2S : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length_m2s,
scndry_aclk => m_aclk,
scndry_resetn => axis_rst,
scndry_out => open,
scndry_vect_out => oarg_sw_length_sync_m2s
);
SW_LENGTH_SYNC_S2S : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length,
scndry_aclk => m_aclk,
scndry_resetn => axis_rst,
scndry_out => open,
scndry_vect_out => oarg_sw_length_sync_s2s
);
XD_SW_LENGTH_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_use_sw_length,
scndry_aclk => m_aclk,
scndry_resetn => m_aresetn,
scndry_out => open,
scndry_vect_out => oarg_use_sw_length_sync
);
XD_SW_LENGTH_WE_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length_we,
scndry_aclk => m_aclk,
scndry_resetn => m_aresetn,
scndry_out => open,
scndry_vect_out => oarg_sw_length_we_sync
);
-- end generate EN_LITE_TO_STRM_SYNC_GEN;
------------------------------------
--- Clocks are synchronous
------------------------------------
-- NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
-- begin
--
--
-- oarg_use_sw_length_sync <= oarg_use_sw_length;
-- -- oarg_sw_length_we_sync <= oarg_sw_length_we;
--
-- process(m_aclk)
-- begin
-- if(m_aclk'event and m_aclk = '1') then
-- if(m_aresetn = '0') then
-- oarg_sw_length_we_sync <= (others=>'0');
-- else
-- oarg_sw_length_we_sync <= oarg_sw_length_we;
-- end if;
-- end if;
-- end process;
--
-- end generate NO_SYNC_GEN;
------------------------------------
--- Output Argument generation
------------------------------------
OARGS_GEN : if (C_N_OUTPUT_ARGS > 0) generate
begin
OUTPUT_ARGS_GEN : for i in 0 to C_N_OUTPUT_ARGS-1 generate
constant OARG_TYPE : integer := get_int_element(C_AP_OARG_TYPE, i);
constant OARG_DWIDTH : integer := get_int_element(C_AP_OARG_DWIDTH, i);
constant OARG_MB_DEPTH : integer := get_int_element(C_AP_OARG_MB_DEPTH, i);
constant OARG_WIDTH : integer := get_int_element(C_AP_OARG_WIDTH, i);
constant OARG_N_DIM : integer := get_int_element(C_AP_OARG_N_DIM, i);
constant OARG_DIM_1 : integer := get_int_element(C_AP_OARG_DIM_1, i);
constant OARG_DIM_2 : integer := get_int_element(C_AP_OARG_DIM_2, i);
constant OARG_FORMAT_TYPE : integer := get_int_element(C_AP_OARG_FORMAT_TYPE, i);
constant OARG_FORMAT_FACTOR : integer := get_int_element(C_AP_OARG_FORMAT_FACTOR, i);
constant OARG_FORMAT_DIM : integer := get_int_element(C_AP_OARG_FORMAT_DIM, i);
constant OARG_DIM : std_logic_vector := C_AP_OARG_DIM_dw(C_MAX_ARG_N_DIM*32*(i+1)-1 downto C_MAX_ARG_N_DIM*32*i);
constant OARG_DIMS : int_vector(C_MAX_ARG_N_DIM downto 1) := get_int_vector(C_AP_OARG_DIM, C_MAX_ARG_N_DIM*(i+1)-1, C_MAX_ARG_N_DIM*i);
function calc_arg_addr_width2 return integer is
variable addr_width : integer := 10;
variable N_elements : integer := 1;
begin
if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) then -- Memory map interface
for i in 1 to OARG_N_DIM loop
N_elements := N_elements * OARG_DIMS(i);
end loop;
case OARG_FORMAT_TYPE is
when FORMAT_TYPE_NONE =>
when FORMAT_TYPE_RESHAPE_BLOCK => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_RESHAPE_CYCLIC => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_RESHAPE_COMPLETE =>
when FORMAT_TYPE_PARTITION_BLOCK => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_PARTITION_CYCLIC => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_PARTITION_COMPLETE =>
when others =>
end case;
addr_width := log2(N_elements);
elsif (OARG_TYPE = AP_ARG_STREAM_TYPE) then -- FIFO interface
-- FIFO interface is considered a unidimentional array; taking the
-- number of elements from dimension 1
N_elements := OARG_DIMS(1);
addr_width := log2(N_elements);
end if;
return addr_width;
end function calc_arg_addr_width2;
signal dbg_arg_addr_width : integer := calc_arg_addr_width2;
function calc_arg_addr_width return integer is
variable addr_width : integer;
variable N_elements : integer;
begin
if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) then -- Memory map interface
if (OARG_N_DIM = 1) then
N_elements := OARG_DIM_1;
addr_width := log2(N_elements);
elsif (OARG_N_DIM = 2) then
if (OARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
N_elements := (OARG_DIM_1*OARG_DIM_2)/OARG_FORMAT_FACTOR;
else
N_elements := (OARG_DIM_1*OARG_DIM_2);
end if;
addr_width := log2(N_elements);
end if;
elsif (OARG_TYPE = AP_ARG_STREAM_TYPE) then -- FIFO interface
N_elements := OARG_DIM_1;
addr_width := log2(N_elements);
end if;
return addr_width;
end function calc_arg_addr_width;
constant OARG_AWIDTH : integer := calc_arg_addr_width;
signal test_dim : int_vector(0 to OARG_N_DIM-1) :=
get_int_vector(C_AP_OARG_DIM, OARG_N_DIM-1+C_MAX_ARG_N_DIM*i, C_MAX_ARG_N_DIM*i);
begin
-- BRAM Interface towards accelerator
M2S_GEN : if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) generate
begin
OARG_M2S_I : entity axis_accelerator_adapter_v2_1_6.xd_m2s_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => OARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => OARG_AWIDTH,
C_MULTIBUFFER_DEPTH => OARG_MB_DEPTH,
C_AP_ARG_WIDTH => OARG_WIDTH,
C_AP_ARG_N_DIM => OARG_N_DIM,
C_AP_ARG_DIMS => OARG_DIMS(OARG_N_DIM downto 1),
C_AP_ARG_DIM_1 => OARG_DIM_1,
C_AP_ARG_DIM_2 => OARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => OARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => OARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => OARG_FORMAT_DIM)
port map (
M_AXIS_ACLK => M_AXIS_ACLK(i),
M_AXIS_ARESETN => M_AXIS_ARESETN(i),
M_AXIS_TVALID => M_AXIS_TVALID(i),
M_AXIS_TREADY => M_AXIS_TREADY(i),
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i),
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i),
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i),
M_AXIS_TLAST => M_AXIS_TLAST(i),
M_AXIS_TID => M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i),
M_AXIS_TDEST => M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i),
---
sw_length => oarg_sw_length_sync_m2s,
sw_length_we => oarg_sw_length_we_sync(i),
use_sw_length => oarg_use_sw_length_sync(i),
host_oarg_tdest => host_oarg_tdest(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
---
ap_clk => ap_clk,
ap_rst_sync => ap_rst_maclk,
ap_rst => ap_rst,
ap_arg_addr => ap_oarg_addr(OARG_AWIDTH-1+C_MAX_ARG_AWIDTH*i downto C_MAX_ARG_AWIDTH*i),
ap_arg_ce => ap_oarg_ce(i),
ap_arg_we => ap_oarg_we(i),
ap_arg_din => ap_oarg_din(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_arg_dout => ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_arg_rqt => ap_oarg_rdy(i),
ap_arg_ack => ap_oarg_done(i),
-- Status info
ap_arg_empty => status_oarg_empty(i),
ap_arg_full => status_oarg_full(i),
ap_arg_used => status_oarg_used(4*(i+1)-1 downto 4*i));
-- Unused signals
ap_fifo_oarg_full_n(i) <= '0';
end generate M2S_GEN;
-- FIFO Interface towards accelerator
S2S_GEN : if (OARG_TYPE = AP_ARG_STREAM_TYPE) generate
begin
OARG_S2S_I : entity axis_accelerator_adapter_v2_1_6.xd_oarg_s2s_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => OARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => OARG_AWIDTH,
C_MULTIBUFFER_DEPTH => OARG_MB_DEPTH)
port map (
M_AXIS_ACLK => M_AXIS_ACLK(i),
M_AXIS_ARESETN => M_AXIS_ARESETN(i),
M_AXIS_TVALID => M_AXIS_TVALID(i),
M_AXIS_TREADY => M_AXIS_TREADY(i),
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i),
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i),
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i),
M_AXIS_TLAST => M_AXIS_TLAST(i),
M_AXIS_TID => M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i),
M_AXIS_TDEST => M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i),
---
sw_length => oarg_sw_length_sync_s2s,
sw_length_we => oarg_sw_length_we_sync(i),
use_sw_length => oarg_use_sw_length_sync(i),
host_oarg_tdest => host_oarg_tdest(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
---
ap_clk => ap_clk,
ap_rst_sync => ap_rst_maclk,
ap_rst => ap_rst,
ap_oarg_din => ap_fifo_oarg_din(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_oarg_we => ap_fifo_oarg_write(i),
ap_oarg_full_n => ap_fifo_oarg_full_n(i),
ap_arg_rqt => ap_oarg_rdy(i),
ap_arg_ack => ap_oarg_done(i),
ap_start => ap_start,
ap_done => ap_done);
-- Unused signals
ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
status_oarg_empty(i) <= '1';
status_oarg_full(i) <= '0';
status_oarg_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate S2S_GEN;
ap_oarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto OARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate OUTPUT_ARGS_GEN;
OARGS_DEFAULT_GEN : if (C_N_OUTPUT_ARGS < C_MAX_N_OARGS) generate
begin
OUTPUT_ARGS_HIGHER_GEN : for i in C_N_OUTPUT_ARGS to C_MAX_N_OARGS-1 generate
constant OARG_DWIDTH : integer := get_int_element(C_AP_OARG_DWIDTH, C_N_OUTPUT_ARGS-1);
begin
M_AXIS_TVALID(i) <= '0';
M_AXIS_TLAST(i) <= '0';
ap_oarg_rdy(i) <= '0';
ap_fifo_oarg_full_n(i) <= '0';
status_oarg_empty(i) <= '0';
status_oarg_full(i) <= '0';
status_oarg_used(4*(i+1)-1 downto 4*i) <= (others => '0');
M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i) <= (others => '0');
M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i) <= (others => '0');
M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i) <= (others => '0');
M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i) <= (others => '0');
M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i) <= (others => '0');
M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i) <= (others => '0');
ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
ap_oarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto OARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate OUTPUT_ARGS_HIGHER_GEN;
--ap_iarg_dout(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto C_MAX_ARG_DWIDTH*C_N_INPUT_ARGS) <= (others=>'0');
end generate OARGS_DEFAULT_GEN;
end generate OARGS_GEN;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of arithmetic is
constant N : integer := 15;
type solution is record
--The inputs
O: std_logic_vector(N-1 downto 0);
C: std_logic;
V: std_logic;
VALID: std_logic;
end record;
impure function do_operation(dummy:std_logic) return solution is
variable sol: solution;
subtype EXT_TYPE is signed(N-1 downto 0);
variable I1_EXT :EXT_TYPE := RESIZE(signed(I1),N);
variable I2_EXT :EXT_TYPE := RESIZE(signed(I2),N);
variable O_EXT :EXT_TYPE;
variable SIGNS : std_logic_vector(2 downto 0);
variable CARIES : std_logic_vector(1 downto 0); -- CIN, COUT
variable I1_SIGN : std_logic ;
variable I2_SIGN : std_logic ;
variable O_SIGN : std_logic ;
variable CF :std_logic;
variable VF :std_logic;
variable one :EXT_TYPE := (0=>'1',others=>'0');
begin
O_EXT := I1_EXT+I2_EXT;
I1_SIGN := I1_EXT(N-1);
I2_SIGN := I2_EXT(N-1);
O_SIGN := O_EXT(N-1);
SIGNS := (O_SIGN, I1_SIGN, I2_SIGN);
case SIGNS is
when "001" => CARIES := "11";
when "010" => CARIES := "11";
when "011" => CARIES := "10";
when "100" => CARIES := "01";
when "111" => CARIES := "11";
when others => CARIES := "00";
end case;
--ADD
CF := CARIES(1); --COUT
VF := CARIES(1) xor CARIES(0);--last two caries not same -> overflow
sol.O := std_logic_vector(O_EXT);
sol.C := CF;
sol.V := VF;
--comp2
sol.VALID := not VF;
return sol;
end do_operation;
begin
process (I1,I2)
variable solCalc : solution;
begin
solCalc:= do_operation('1');
O<=solCalc.O;
V<=solCalc.V;
C<=solCalc.C;
VALID<=solCalc.VALID;
end process;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of arithmetic is
constant N : integer := 15;
type solution is record
--The inputs
O: std_logic_vector(N-1 downto 0);
C: std_logic;
V: std_logic;
VALID: std_logic;
end record;
impure function do_operation(dummy:std_logic) return solution is
variable sol: solution;
subtype EXT_TYPE is signed(N-1 downto 0);
variable I1_EXT :EXT_TYPE := RESIZE(signed(I1),N);
variable I2_EXT :EXT_TYPE := RESIZE(signed(I2),N);
variable O_EXT :EXT_TYPE;
variable SIGNS : std_logic_vector(2 downto 0);
variable CARIES : std_logic_vector(1 downto 0); -- CIN, COUT
variable I1_SIGN : std_logic ;
variable I2_SIGN : std_logic ;
variable O_SIGN : std_logic ;
variable CF :std_logic;
variable VF :std_logic;
variable one :EXT_TYPE := (0=>'1',others=>'0');
begin
O_EXT := I1_EXT+I2_EXT;
I1_SIGN := I1_EXT(N-1);
I2_SIGN := I2_EXT(N-1);
O_SIGN := O_EXT(N-1);
SIGNS := (O_SIGN, I1_SIGN, I2_SIGN);
case SIGNS is
when "001" => CARIES := "11";
when "010" => CARIES := "11";
when "011" => CARIES := "10";
when "100" => CARIES := "01";
when "111" => CARIES := "11";
when others => CARIES := "00";
end case;
--ADD
CF := CARIES(1); --COUT
VF := CARIES(1) xor CARIES(0);--last two caries not same -> overflow
sol.O := std_logic_vector(O_EXT);
sol.C := CF;
sol.V := VF;
--comp2
sol.VALID := not VF;
return sol;
end do_operation;
begin
process (I1,I2)
variable solCalc : solution;
begin
solCalc:= do_operation('1');
O<=solCalc.O;
V<=solCalc.V;
C<=solCalc.C;
VALID<=solCalc.VALID;
end process;
end behavior;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_stub.vhdl
-- Design : scfifo_24in_24out_12kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scfifo_24in_24out_12kb is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end scfifo_24in_24out_12kb;
architecture stub of scfifo_24in_24out_12kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[23:0],wr_en,rd_en,dout[23:0],full,empty,data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_0_0,Vivado 2015.3";
begin
end;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_stub.vhdl
-- Design : scfifo_24in_24out_12kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scfifo_24in_24out_12kb is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end scfifo_24in_24out_12kb;
architecture stub of scfifo_24in_24out_12kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[23:0],wr_en,rd_en,dout[23:0],full,empty,data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_0_0,Vivado 2015.3";
begin
end;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(3 downto 0);
signal AsconInput : std_logic_vector(127 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput;
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "10000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00544ent IS
END c03s04b00x00p03n01i00544ent;
ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
type L is -- constrained array decl
array (1 to 1023, 31 downto 0) of Bit;
type M is -- record type decl
record
A: Integer;
B: L;
end record;
type O is -- file decl
file of M; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00544"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00544ent IS
END c03s04b00x00p03n01i00544ent;
ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
type L is -- constrained array decl
array (1 to 1023, 31 downto 0) of Bit;
type M is -- record type decl
record
A: Integer;
B: L;
end record;
type O is -- file decl
file of M; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00544"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00544ent IS
END c03s04b00x00p03n01i00544ent;
ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
type L is -- constrained array decl
array (1 to 1023, 31 downto 0) of Bit;
type M is -- record type decl
record
A: Integer;
B: L;
end record;
type O is -- file decl
file of M; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00544"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00544arch;
|
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
|
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
|
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of vgca_top_tb
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_top_tb-rtl-a.vhd,v 1.2 2004/08/18 10:46:57 wig Exp $
-- $Date: 2004/08/18 10:46:57 $
-- $Log: vgca_top_tb-rtl-a.vhd,v $
-- Revision 1.2 2004/08/18 10:46:57 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of vgca_top_tb
--
architecture rtl of vgca_top_tb is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component vgca_top --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for dut
dut: vgca_top
;
-- End of Generated Instance Port Map for dut
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT Command_FIFO_top IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm6 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm6;
architecture BEHAVIORAL of dcm6 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 33.33 = 32 * 25 / 24
CLKFX_DIVIDE => 24,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_regs is
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
---
comb_wave_l : in std_logic;
comb_wave_r : in std_logic;
---
voice_osc : in unsigned(3 downto 0);
voice_wave : in unsigned(3 downto 0);
voice_adsr : in unsigned(3 downto 0);
voice_mul : in unsigned(3 downto 0);
-- Oscillator parameters
freq : out unsigned(15 downto 0);
test : out std_logic;
sync : out std_logic;
-- Wave map parameters
comb_mode : out std_logic;
ring_mod : out std_logic;
wave_sel : out std_logic_vector(3 downto 0);
sq_width : out unsigned(11 downto 0);
-- ADSR parameters
gate : out std_logic;
attack : out std_logic_vector(3 downto 0);
decay : out std_logic_vector(3 downto 0);
sustain : out std_logic_vector(3 downto 0);
release : out std_logic_vector(3 downto 0);
-- mixer 1 parameters
filter_en : out std_logic;
-- globals
volume_l : out unsigned(3 downto 0) := (others => '0');
filter_co_l : out unsigned(10 downto 0) := (others => '0');
filter_res_l : out unsigned(3 downto 0) := (others => '0');
filter_ex_l : out std_logic := '0';
filter_hp_l : out std_logic := '0';
filter_bp_l : out std_logic := '0';
filter_lp_l : out std_logic := '0';
voice3_off_l : out std_logic := '0';
volume_r : out unsigned(3 downto 0) := (others => '0');
filter_co_r : out unsigned(10 downto 0) := (others => '0');
filter_res_r : out unsigned(3 downto 0) := (others => '0');
filter_ex_r : out std_logic := '0';
filter_hp_r : out std_logic := '0';
filter_bp_r : out std_logic := '0';
filter_lp_r : out std_logic := '0';
voice3_off_r : out std_logic := '0';
-- readback
osc3 : in std_logic_vector(7 downto 0);
env3 : in std_logic_vector(7 downto 0) );
attribute ramstyle : string;
end sid_regs;
architecture gideon of sid_regs is
attribute ramstyle of gideon : architecture is "logic";
type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0);
signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0'));
signal control : byte_array_t(0 to 15) := (others => (others => '0'));
signal att_dec : byte_array_t(0 to 15) := (others => (others => '0'));
signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0'));
signal do_write : std_logic;
signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0');
constant address_remap : byte_array_t(0 to 255) := (
X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1
X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2
X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3
X"08", X"09", X"0A", X"0B", -- 15
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19
X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4
X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5
X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6
X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7
X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8
X"0C", X"0D", X"0E", -- 43
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77
X"FF", X"FF", -- 7E
X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9
X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10
X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11
X"88", X"89", X"8A", X"8B", -- 95
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99
X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12
X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13
X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14
X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15
X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16
X"8C", X"8D", X"8E", -- C3
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7
X"FF", X"FF" ); -- FE
signal address : unsigned(7 downto 0);
begin
address <= unsigned(address_remap(to_integer(addr)));
process(clock)
begin
if rising_edge(clock) then
do_write <= wren;
if do_write='0' and wren='1' then
if address(3)='0' then -- Voice register
case address(2 downto 0) is
when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata;
when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata;
when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata;
when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata(3 downto 0);
when "100" => control(to_integer(address(7 downto 4))) <= wdata;
when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata;
when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata;
when others => null;
end case;
elsif address(7)='0' then -- Global register for left
case address(2 downto 0) is
when "000" => filter_co_l(2 downto 0) <= unsigned(wdata(2 downto 0));
when "001" => filter_co_l(10 downto 3) <= unsigned(wdata);
when "010" => filter_res_l <= unsigned(wdata(7 downto 4));
filter_ex_l <= wdata(3);
filt_en_i(2 downto 0) <= wdata(2 downto 0);
when "011" => voice3_off_l <= wdata(7);
filter_hp_l <= wdata(6);
filter_bp_l <= wdata(5);
filter_lp_l <= wdata(4);
volume_l <= unsigned(wdata(3 downto 0));
when "100" => filt_en_i(7 downto 0) <= wdata;
when others => null;
end case;
else -- Global register for right
case address(2 downto 0) is
when "000" => filter_co_r(2 downto 0) <= unsigned(wdata(2 downto 0));
when "001" => filter_co_r(10 downto 3) <= unsigned(wdata);
when "010" => filter_res_r <= unsigned(wdata(7 downto 4));
filter_ex_r <= wdata(3);
filt_en_i(10 downto 8) <= wdata(2 downto 0);
when "011" => voice3_off_r <= wdata(7);
filter_hp_r <= wdata(6);
filter_bp_r <= wdata(5);
filter_lp_r <= wdata(4);
volume_r <= unsigned(wdata(3 downto 0));
when "100" => filt_en_i(15 downto 8) <= wdata;
when others => null;
end case;
end if;
end if;
-- Readback (unmapped address)
case addr is
when "00011011" => rdata <= osc3;
when "00011100" => rdata <= env3;
when others => rdata <= (others => '0');
end case;
if reset='1' then
filt_en_i <= (others => '0');
voice3_off_l <= '0';
voice3_off_r <= '0';
volume_l <= X"0";
volume_r <= X"0";
end if;
end if;
end process;
freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc)));
test <= control(to_integer(voice_osc))(3);
sync <= control(to_integer(voice_osc))(1);
-- Wave map parameters
ring_mod <= control(to_integer(voice_wave))(2);
wave_sel <= control(to_integer(voice_wave))(7 downto 4);
sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave)));
comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l);
-- ADSR parameters
gate <= control(to_integer(voice_adsr))(0);
attack <= att_dec(to_integer(voice_adsr))(7 downto 4);
decay <= att_dec(to_integer(voice_adsr))(3 downto 0);
sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4);
release <= sust_rel(to_integer(voice_adsr))(3 downto 0);
-- Mixer 1 parameters
filter_en <= filt_en_i(to_integer(voice_mul));
end gideon;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity sync_recv_tb is
end entity;
architecture behavioural of sync_recv_tb is
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
-- Serial in
signal serClk : std_logic;
signal serData : std_logic;
-- Parallel out
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
-- Detect rising serClk edges
signal serClk_prev : std_logic;
signal serClkFE : std_logic;
begin
-- Instantiate sync_recv module for testing
uut: entity work.sync_recv
port map(
clk_in => sysClk,
-- Serial in
serClkFE_in => serClkFE,
serData_in => serData,
-- Parallel out
recvData_out => recvData,
recvValid_out => recvValid
);
-- Infer registers
process(sysClk)
begin
if ( rising_edge(sysClk) ) then
serClk_prev <= serClk;
end if;
end process;
-- Detect rising edges on serClk
serClkFE <=
'1' when serClk = '0' and serClk_prev = '1'
else '0';
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive serClk
process
begin
serClk <= '0';
loop
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
serClk <= not(serClk);
end loop;
end process;
-- Drive the sync serial signals
process
procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is
begin
serData <= '0'; -- start bit
wait until rising_edge(serClk); serData <= b(0); -- bit 0
wait until rising_edge(serClk); serData <= b(1); -- bit 1
wait until rising_edge(serClk); serData <= b(2); -- bit 2
wait until rising_edge(serClk); serData <= b(3); -- bit 3
wait until rising_edge(serClk); serData <= b(4); -- bit 4
wait until rising_edge(serClk); serData <= b(5); -- bit 5
wait until rising_edge(serClk); serData <= b(6); -- bit 6
wait until rising_edge(serClk); serData <= b(7); -- bit 7
wait until rising_edge(serClk); serData <= '1'; -- stop bit
wait until rising_edge(serClk);
end procedure;
procedure pause(constant n : in integer) is
variable i : integer;
begin
for i in 1 to n loop
wait until rising_edge(serClk);
end loop;
end procedure;
begin
serData <= '1';
pause(4);
sendByte(x"55");
sendByte(x"5B");
sendByte(x"5A");
serData <= 'Z'; -- tri-state data line after final send (AVR disables sender)
wait;
end process;
end architecture;
|
entity record13 is
end entity;
architecture test of record13 is
type rec is record
t : character; -- This struct must be packed
x, y : integer;
end record;
type rec_array is array (positive range <>) of rec;
function resolve(x : rec_array) return rec is
variable r : rec := ('0', 0, 0);
begin
assert x'left = 1;
assert x'right = x'length;
for i in x'range loop
report "x(" & integer'image(i) & ") = (" & integer'image(x(i).x)
& ", " & integer'image(x(i).y) & ")";
r.x := r.x + x(i).x;
r.y := r.y + x(i).y;
end loop;
return r;
end function;
subtype resolved_rec is resolve rec;
signal sig : resolved_rec := ('0', 0, 0);
begin
p1: process is
begin
sig <= ('a', 1, 2);
wait for 1 ns;
sig.x <= 5;
wait;
end process;
p2: process is
begin
sig <= ('b', 4, 5);
wait for 1 ns;
assert sig = ('0', 5, 7);
wait for 1 ns;
assert sig = ('0', 9, 7);
wait;
end process;
end architecture;
|
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and reference terminal for electrical systems
NATURE electrical IS
voltage ACROSS
current THROUGH ground reference;
FUNCTION always_positive (x:real) RETURN real;
-- a subnature that is compatible with electrical but has
-- different tolerance codes for across and through aspects
-- SUBNATURE high_voltage IS electrical
-- TOLERANCE "MV" ACROSS "A" THROUGH;
-- support for terminal arrays
-- NATURE electrical_vector IS ARRAY (integer RANGE <>) OF electrical;
-- Type quantity_vector IS ARRAY (integer RANGE <>) OF real;
-- Type Adresse is array (integer RANGE <>) of integer;
END PACKAGE electrical_system;
---------------------------------------------------------------------
PACKAGE BODY electrical_system IS
FUNCTION always_positive (x:real) RETURN real IS
BEGIN
IF (x < epsi) THEN
RETURN epsi;
ELSE
RETURN x;
END if;
END;
END package body;
|
entity stdenv2 is
end entity;
use std.env.all;
use std.textio.all;
architecture test of stdenv2 is
begin
p1: process is
variable open_status : dir_open_status;
variable create_status : dir_create_status;
file f : text;
begin
report dir_workingdir;
dir_createdir("tmp", false, create_status);
assert create_status = STATUS_OK;
assert dir_createdir("tmp") = STATUS_ITEM_EXISTS;
assert dir_workingdir("tmp") = STATUS_OK;
report dir_workingdir;
dir_workingdir("/not/here", open_status);
assert open_status = STATUS_NOT_FOUND;
assert dir_itemexists(".");
assert not dir_itemexists("file");
file_open(f, "file", write_mode);
file_close(f);
assert dir_itemexists("file");
assert dir_itemisfile("file");
assert not dir_itemisfile("not.here");
assert not dir_itemisfile(".");
assert not dir_itemisdir("file");
assert dir_itemisdir("..");
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:28:24 06/04/2015
-- Design Name:
-- Module Name: F:/WorkSpace/workspace_ise/Exp/CPU/cpu_test.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: module_CPU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cpu_test IS
END cpu_test;
ARCHITECTURE behavior OF cpu_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT module_CPU
PORT(
clk : IN std_logic;
nreset : IN std_logic;
io_input : IN std_logic_vector(7 downto 0);
io_output : OUT std_logic_vector(7 downto 0);
data_test : OUT std_logic_vector(7 downto 0);
ar_test : OUT std_logic_vector(6 downto 0);
cm_test : OUT std_logic_vector(47 downto 0);
addr_test : OUT std_logic_vector(11 downto 0);
ir_test : OUT std_logic_vector(7 downto 0);
pc_test : OUT std_logic_vector(11 downto 0);
c1_test : OUT std_logic;
c2_test : OUT std_logic;
n1_test : OUT std_logic;
n2_test : OUT std_logic;
w0_test : OUT std_logic;
w1_test : OUT std_logic;
w2_test : OUT std_logic;
w3_test : OUT std_logic;
ir_ctest : OUT std_logic;
rs_test : OUT std_logic;
rd_test : OUT std_logic;
pc_ntest : OUT std_logic;
nload_test : OUT std_logic;
x_test : OUT std_logic;
z_test : OUT std_logic;
count_test : OUT integer
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal nreset : std_logic := '0';
signal io_input : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal io_output : std_logic_vector(7 downto 0);
signal data_test : std_logic_vector(7 downto 0);
signal ar_test : std_logic_vector(6 downto 0);
signal cm_test : std_logic_vector(47 downto 0);
signal addr_test : std_logic_vector(11 downto 0);
signal ir_test : std_logic_vector(7 downto 0);
signal pc_test : std_logic_vector(11 downto 0);
signal c1_test : std_logic;
signal c2_test : std_logic;
signal n1_test : std_logic;
signal n2_test : std_logic;
signal w0_test : std_logic;
signal w1_test : std_logic;
signal w2_test : std_logic;
signal w3_test : std_logic;
signal ir_ctest : std_logic;
signal rs_test : std_logic;
signal rd_test : std_logic;
signal pc_ntest : std_logic;
signal nload_test : std_logic;
signal x_test : std_logic;
signal z_test : std_logic;
signal count_test : integer;
-- Clock period definitions
constant clk_period : time := 2 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: module_CPU PORT MAP (
clk => clk,
nreset => nreset,
io_input => io_input,
io_output => io_output,
data_test => data_test,
ar_test => ar_test,
cm_test => cm_test,
addr_test => addr_test,
ir_test => ir_test,
pc_test => pc_test,
c1_test => c1_test,
c2_test => c2_test,
n1_test => n1_test,
n2_test => n2_test,
w0_test => w0_test,
w1_test => w1_test,
w2_test => w2_test,
w3_test => w3_test,
ir_ctest => ir_ctest,
rs_test => rs_test,
rd_test => rd_test,
pc_ntest => pc_ntest,
nload_test => nload_test,
x_test => x_test,
z_test => z_test,
count_test => count_test
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
nreset <= '1';
io_input <= X"23";
wait for clk_period*100;
-- insert stimulus here
wait for clk_period*1000;
end process;
END;
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_tck is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jtag_state_rti : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tck : IN STD_LOGIC;
signal tdi : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal vs_cdr : IN STD_LOGIC;
signal vs_sdr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal ir_out : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal sr : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal st_ready_test_idle : OUT STD_LOGIC;
signal tdo : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_tck;
architecture europa of Video_System_CPU_jtag_debug_module_tck is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal DRsize : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal debugack_sync : STD_LOGIC;
signal internal_jrst_n1 : STD_LOGIC;
signal internal_sr : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal monitor_ready_sync : STD_LOGIC;
signal unxcomplemented_resetxx0 : STD_LOGIC;
signal unxcomplemented_resetxx1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of DRSize : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
attribute ALTERA_ATTRIBUTE of sr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
begin
process (tck)
begin
if tck'event and tck = '1' then
if std_logic'(vs_cdr) = '1' then
case ir_in is
when std_logic_vector'("00") =>
internal_sr(35) <= debugack_sync;
internal_sr(34) <= monitor_error;
internal_sr(33) <= resetlatch;
internal_sr(32 DOWNTO 1) <= MonDReg;
internal_sr(0) <= monitor_ready_sync;
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
internal_sr(35 DOWNTO 0) <= tracemem_trcdata;
internal_sr(37) <= tracemem_tw;
internal_sr(36) <= tracemem_on;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
internal_sr(37) <= trigger_state_1;
internal_sr(36) <= dbrk_hit3_latch;
internal_sr(35) <= dbrk_hit2_latch;
internal_sr(34) <= dbrk_hit1_latch;
internal_sr(33) <= dbrk_hit0_latch;
internal_sr(32 DOWNTO 1) <= break_readreg;
internal_sr(0) <= trigbrktype;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
internal_sr(15 DOWNTO 12) <= std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('0')));
internal_sr(11 DOWNTO 2) <= std_logic_vector'("000") & (trc_im_addr);
internal_sr(1) <= trc_wrap;
internal_sr(0) <= trc_on;
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
if std_logic'(vs_sdr) = '1' then
case DRsize is
when std_logic_vector'("000") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 9) & A_ToStdLogicVector(tdi) & internal_sr(7 DOWNTO 1));
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 17) & A_ToStdLogicVector(tdi) & internal_sr(15 DOWNTO 1));
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 33) & A_ToStdLogicVector(tdi) & internal_sr(31 DOWNTO 1));
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & A_ToStdLogicVector(internal_sr(37)) & A_ToStdLogicVector(tdi) & internal_sr(35 DOWNTO 1));
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 1));
-- when std_logic_vector'("101")
when others =>
internal_sr <= Std_Logic_Vector'(A_ToStdLogicVector(tdi) & internal_sr(37 DOWNTO 2) & A_ToStdLogicVector(tdi));
-- when others
end case; -- DRsize
end if;
if std_logic'(vs_uir) = '1' then
case ir_in is
when std_logic_vector'("00") =>
DRsize <= std_logic_vector'("100");
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
DRsize <= std_logic_vector'("101");
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
DRsize <= std_logic_vector'("010");
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- ir_in
end if;
end if;
end process;
tdo <= internal_sr(0);
st_ready_test_idle <= jtag_state_rti;
unxcomplemented_resetxx0 <= internal_jrst_n1;
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => debugack,
dout => debugack_sync,
reset_n => unxcomplemented_resetxx0
);
unxcomplemented_resetxx1 <= internal_jrst_n1;
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => tck,
din => monitor_ready,
dout => monitor_ready_sync,
reset_n => unxcomplemented_resetxx1
);
process (tck, internal_jrst_n1)
begin
if internal_jrst_n1 = '0' then
ir_out <= std_logic_vector'("00");
elsif tck'event and tck = '1' then
ir_out <= Std_Logic_Vector'(A_ToStdLogicVector(debugack_sync) & A_ToStdLogicVector(monitor_ready_sync));
end if;
end process;
--vhdl renameroo for output signals
jrst_n <= internal_jrst_n1;
--vhdl renameroo for output signals
sr <= internal_sr;
--synthesis translate_off
internal_jrst_n1 <= reset_n;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- internal_jrst_n1 <= std_logic'('1');
--synthesis read_comments_as_HDL off
end europa;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
sub_wire6 <= sub_wire0(4);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
c4 <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "6250",
clk2_divide_by => 5,
clk2_duty_cycle => 50,
clk2_multiply_by => 4,
clk2_phase_shift => "12500",
clk3_divide_by => 5,
clk3_duty_cycle => 50,
clk3_multiply_by => 4,
clk3_phase_shift => "18750",
clk4_divide_by => 5,
clk4_duty_cycle => 50,
clk4_multiply_by => 16,
clk4_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire8,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "160.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "160.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "270.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "6250"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "12500"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "18750"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
entity repro3 is
end;
architecture behav of repro3 is
component comp is
end component comp;
constant d : time := 1 comp;
begin
end behav;
|
architecture RTL of FIFO is
signal sig1, sig2 : std_logic_vector(3 downto 0);
constant c_cons1, c_const2 : integer := 200;
constant c_cons2 : integer := 200;
begin
U_RAM : RAM_ARRAY
generic map (
G_WIDTH => 512,
G_DEPTH => 2048,
G_SIZE => 32
)
port map (
I_DATA_A => data_a,
I_DATA_B => data_b
);
end architecture RTL;
|
--!
--! \file add.vhd
--!
--! Demo thread for partial reconfiguration
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 27.01.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end add;
architecture Behavioral of add is
-- OS synchronization state machine states
type t_state is (STATE_INIT, STATE_READ, STATE_WRITE, STATE_EXIT);
signal state : t_state := STATE_INIT;
-- address of data to process in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal result : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- calculate result in parallel
result <= data + 1 when C_SUB_NADD = 0 else data - 1;
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable next_state : t_state := STATE_INIT;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF00");
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read target address from init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
next_state := STATE_READ;
-- read data from target address
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, address, data);
next_state := STATE_WRITE;
-- write result to target address
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, address, result);
next_state := STATE_EXIT;
-- terminate
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, C_RECONOS_SUCCESS);
when others =>
next_state := STATE_INIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity testeverything_tb is
end testeverything_tb;
architecture Behavioral of testeverything_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
signal SDA, SCL, USER_RESET: std_logic;
begin
SDA <= 'H';
SCL <= 'H';
clock <= not clock after 7.57575757 ns;
i2cclient : entity work.ADS7830(RTL)
port map (
SDA => SDA,
SCL => SCL
);
united : entity work.unite(Behavioral)
port map (
LED => led,
CLK_66MHZ => clock,
SDA => SDA,
SCL => SCL,
USER_RESET => USER_RESET
);
stimuli : process
begin
USER_RESET <= '1';
wait for 10us;
USER_RESET <= '0';
wait for 1000ms;
wait;
end process;
end Behavioral;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: TargetCmdFIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity TargetCmdFIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end TargetCmdFIFO_top_wrapper;
architecture xilinx of TargetCmdFIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component TargetCmdFIFO_top is
PORT (
CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : TargetCmdFIFO_top
PORT MAP (
CLK => clk_i,
ALMOST_FULL => almost_full,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:16 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_rx.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: uart_rx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_rx IS
END tb_rx;
ARCHITECTURE behavior OF tb_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_rx
PORT(
clk : IN std_logic;
rx : IN std_logic;
rx_data : OUT std_logic_vector(7 downto 0);
rx_ready : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '1';
--Outputs
signal rx_data : std_logic_vector(7 downto 0);
signal rx_ready : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart_rx PORT MAP (
clk => clk,
rx => rx,
rx_data => rx_data,
rx_ready => rx_ready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity led_display_controller_tb is
end;
architecture led_display_controller_tb_func of led_display_controller_tb is
signal bcd0_in : std_logic_vector(3 downto 0);
signal bcd1_in : std_logic_vector(3 downto 0);
signal bcd2_in : std_logic_vector(3 downto 0);
signal bcd3_in : std_logic_vector(3 downto 0);
signal anode_out: std_logic_vector(3 downto 0);
signal led_out : std_logic_vector(7 downto 0);
signal clk_in: std_logic:='0';
component led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output : out std_logic_vector(7 downto 0)
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
bcd0_in <= b"1001";
bcd1_in <= b"0110";
bcd2_in <= b"0101";
bcd3_in <= b"1010";
led_display_controllerMap: led_display_controller
port map(
clk_in => clk_in,
bcd0 => bcd0_in,
bcd1 => bcd1_in,
bcd2 => bcd2_in,
bcd3 => bcd3_in,
anode_output => anode_out,
led_output => led_out
);
end architecture;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_nov;
architecture behaviour of ex1_nov is
constant s1: std_logic_vector(4 downto 0) := "01000";
constant s2: std_logic_vector(4 downto 0) := "10011";
constant s3: std_logic_vector(4 downto 0) := "00111";
constant s4: std_logic_vector(4 downto 0) := "00000";
constant s5: std_logic_vector(4 downto 0) := "10000";
constant s6: std_logic_vector(4 downto 0) := "11001";
constant s7: std_logic_vector(4 downto 0) := "01111";
constant s8: std_logic_vector(4 downto 0) := "10001";
constant s9: std_logic_vector(4 downto 0) := "11010";
constant s10: std_logic_vector(4 downto 0) := "11011";
constant s11: std_logic_vector(4 downto 0) := "11100";
constant s12: std_logic_vector(4 downto 0) := "11101";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s14: std_logic_vector(4 downto 0) := "11110";
constant s15: std_logic_vector(4 downto 0) := "10100";
constant s16: std_logic_vector(4 downto 0) := "11111";
constant s17: std_logic_vector(4 downto 0) := "10101";
constant s18: std_logic_vector(4 downto 0) := "10110";
constant s19: std_logic_vector(4 downto 0) := "10111";
constant s20: std_logic_vector(4 downto 0) := "10010";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: ROM_Seno.vhd
-- Megafunction Name(s):
-- lpm_rom
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY ROM_Seno IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ROM_Seno;
ARCHITECTURE SYN OF rom_seno IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_rom
GENERIC (
intended_device_family : STRING;
lpm_address_control : STRING;
lpm_file : STRING;
lpm_outdata : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthad : NATURAL
);
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
lpm_rom_component : lpm_rom
GENERIC MAP (
intended_device_family => "FLEX10K",
lpm_address_control => "REGISTERED",
lpm_file => "seno.mif",
lpm_outdata => "UNREGISTERED",
lpm_type => "LPM_ROM",
lpm_width => 8,
lpm_widthad => 8
)
PORT MAP (
address => address,
inclock => inclock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "FLEX10K"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "seno.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: OutputRegistered NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAdd NUMERIC "1"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "FLEX10K"
-- Retrieval info: CONSTANT: LPM_ADDRESS_CONTROL STRING "REGISTERED"
-- Retrieval info: CONSTANT: LPM_FILE STRING "seno.mif"
-- Retrieval info: CONSTANT: LPM_OUTDATA STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ROM"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "8"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: CONNECT: @address 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01450ent IS
END c08s07b00x00p01n01i01450ent;
ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
begin
p: process
variable j : integer := 1;
variable i : integer := 0;
variable k : integer := 0;
variable m : integer := 0;
begin
if j = 1 then
i := 1;
elsif j = 2 then
k := 1;
else
m := 1;
end if;
assert (i = 0) and (k = 1) and (m = 1)
report "***PASSED TEST: c08s07b00x00p01n01i01450"
severity NOTE;
assert NOT((i = 0) and (k = 1) and (m = 1))
report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01450arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01450ent IS
END c08s07b00x00p01n01i01450ent;
ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
begin
p: process
variable j : integer := 1;
variable i : integer := 0;
variable k : integer := 0;
variable m : integer := 0;
begin
if j = 1 then
i := 1;
elsif j = 2 then
k := 1;
else
m := 1;
end if;
assert (i = 0) and (k = 1) and (m = 1)
report "***PASSED TEST: c08s07b00x00p01n01i01450"
severity NOTE;
assert NOT((i = 0) and (k = 1) and (m = 1))
report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01450arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01450ent IS
END c08s07b00x00p01n01i01450ent;
ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
begin
p: process
variable j : integer := 1;
variable i : integer := 0;
variable k : integer := 0;
variable m : integer := 0;
begin
if j = 1 then
i := 1;
elsif j = 2 then
k := 1;
else
m := 1;
end if;
assert (i = 0) and (k = 1) and (m = 1)
report "***PASSED TEST: c08s07b00x00p01n01i01450"
severity NOTE;
assert NOT((i = 0) and (k = 1) and (m = 1))
report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01450arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output: out std_logic_vector(7 downto 0)
);
end;
architecture led_display_controller_arq of led_display_controller is
signal counter_enabler: std_logic:= '1';
signal counter_output: std_logic_vector(1 downto 0);
signal multiplex_output: std_logic_vector(3 downto 0);
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
component generic_enabler is
generic(PERIOD:natural := 1000000 );
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
component bcd_mux IS
port(
bcd0_i : IN std_logic_vector(3 DOWNTO 0);
bcd1_i : IN std_logic_vector(3 DOWNTO 0);
bcd2_i : IN std_logic_vector(3 DOWNTO 0);
bcd3_i : IN std_logic_vector(3 DOWNTO 0);
m_sel : IN std_logic_vector(1 DOWNTO 0);
m_out : OUT std_logic_vector(3 DOWNTO 0));
end component;
component anode_sel IS
PORT(
sel_in : IN std_logic_vector(1 DOWNTO 0);
sel_out : OUT std_logic_vector(3 DOWNTO 0));
END component;
component led_enabler IS
PORT(
ena_in : IN std_logic_vector(3 DOWNTO 0);
ena_out : OUT std_logic_vector(7 DOWNTO 0));
END component;
begin
genericCounterMap: generic_counter generic map (2,4)
port map(
clk => clk_in,
rst => '0',
ena => counter_enabler,
count => counter_output
);
generic_enabler_map: generic_enabler generic map (100000)
port map(
clk => clk_in,
rst => '0',
ena_out => counter_enabler
);
bcd_muxMap: bcd_mux port map(
bcd0_i => bcd0,
bcd1_i => bcd1,
bcd2_i => bcd2,
bcd3_i => bcd3,
m_sel => counter_output,
m_out => multiplex_output
);
anode_selMap: anode_sel port map(
sel_in => counter_output,
sel_out => anode_output
);
led_enablerMap: led_enabler port map(
ena_in => multiplex_output,
ena_out => led_output
);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpio
-- File: grgpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0;
iflagreg : integer range 0 to 1 := 0;
bpmode : integer range 0 to 1 := 0;
inpen : integer range 0 to 1 := 0;
doutresv : integer := 0;
dirresv : integer := 0;
bpresv : integer := 0;
inpresv : integer := 0;
pulse : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 3;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant DOUT_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(doutresv, 32);
constant DIR_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(dirresv, 32);
constant BP_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpresv, 32);
constant INPEN_RESVAL : std_logic_vector(31 downto 0) := conv_std_logic_vector(inpresv, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- Prevent tools from issuing index errors for unused code
function calc_nirqmux return integer is
begin
if irqgen = 0 then return 1; end if;
return irqgen;
end;
constant NIRQMUX : integer := calc_nirqmux;
subtype irqmap_type is std_logic_vector(log2x(NIRQMUX)-1 downto 0);
type irqmap_array_type is array (natural range <>) of irqmap_type;
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
irqmap : irqmap_array_type(nbits-1 downto 0);
iflag : std_logic_vector(nbits-1 downto 0);
inpen : std_logic_vector(nbits-1 downto 0);
pulse : std_logic_vector(nbits-1 downto 0);
end record;
constant nbitszero : std_logic_vector(nbits-1 downto 0) := (others => '0');
constant irqmapzero : irqmap_array_type(nbits-1 downto 0) := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : registers := (
din1 => nbitszero, din2 => nbitszero, -- Sync. regs, not reset
dout => DOUT_RESVAL(nbits-1 downto 0), imask => nbitszero, level => nbitszero, edge => nbitszero,
ilat => nbitszero, dir => DIR_RESVAL(nbits-1 downto 0), bypass => BP_RESVAL(nbits-1 downto 0), irqmap => irqmapzero,
iflag => nbitszero, inpen => INPEN_RESVAL(nbits-1 downto 0),
pulse => nbitszero);
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
if inpen /= 0 then
din(nbits-1 downto 0) := din(nbits-1 downto 0) and r.inpen;
end if;
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
dir(nbits-1 downto 0) := DIR_RESVAL(nbits-1 downto 0);
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(nbits-1 downto 0) := r.din2;
when "00001" | "10101" | "11001" | "11101" =>
readdata(nbits-1 downto 0) := r.dout;
when "00010" | "10110" | "11010" | "11110" =>
readdata(nbits-1 downto 0) := r.dir;
when "00011" | "10111" | "11011" | "11111"=>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "00111" =>
readdata(18) := conv_std_logic(pulse /= 0);
readdata(17) := conv_std_logic(inpen /= 0);
readdata(16) := conv_std_logic(iflagreg /= 0);
readdata(12 downto 8) := conv_std_logic_vector(irqgen, 5);
readdata(4 downto 0) := conv_std_logic_vector(nbits-1, 5);
when "10000" =>
if (iflagreg /= 0) then
readdata(nbits-1 downto 0) := PIMASK(nbits-1 downto 0);
end if;
when "10001" =>
if (iflagreg) /= 0 then
readdata(nbits-1 downto 0) := r.iflag and PIMASK(nbits-1 downto 0);
end if;
when "10010" | "10100" | "11000" | "11100" =>
if (inpen /= 0) then
readdata(nbits-1 downto 0) := r.inpen;
end if;
when "10011" =>
if (pulse /= 0) then
readdata(nbits-1 downto 0) := r.pulse;
end if;
when others => --when "01000" to "01111" =>
if (irqgen > 1) then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
readdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8)) := r.irqmap(i*4+j);
end loop;
end if;
end loop;
end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => null;
when "00001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "00010" => v.dir := apbi.pwdata(nbits-1 downto 0);
when "00011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "00110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "00111" =>
null;
when "10000" =>
null;
when "10001" =>
if (iflagreg /= 0) then
v.iflag := (r.iflag and not apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "10010" =>
if (inpen /= 0) then
v.inpen := apbi.pwdata(nbits-1 downto 0);
end if;
when "10011" =>
if (pulse /= 0) then
v.pulse := apbi.pwdata(nbits-1 downto 0);
end if;
when "10100" =>
if (inpen /= 0) then
v.inpen := r.inpen or apbi.pwdata(nbits-1 downto 0);
end if;
when "10101" => v.dout := r.dout or apbi.pwdata(nbits-1 downto 0);
when "10110" => v.dir := r.dir or apbi.pwdata(nbits-1 downto 0);
when "10111" =>
if (imask /= 0) then
v.imask := (r.imask or apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "11000" =>
if (inpen /= 0) then
v.inpen := r.inpen and apbi.pwdata(nbits-1 downto 0);
end if;
when "11001" => v.dout := r.dout and apbi.pwdata(nbits-1 downto 0);
when "11010" => v.dir := r.dir and apbi.pwdata(nbits-1 downto 0);
when "11011" =>
if (imask /= 0) then
v.imask := (r.imask and apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when "11100" =>
if (inpen /= 0) then
v.inpen := r.inpen xor apbi.pwdata(nbits-1 downto 0);
end if;
when "11101" => v.dout := r.dout xor apbi.pwdata(nbits-1 downto 0);
when "11110" => v.dir := r.dir xor apbi.pwdata(nbits-1 downto 0);
when "11111" =>
if (imask /= 0) then
v.imask := (r.imask xor apbi.pwdata(nbits-1 downto 0)) and PIMASK(nbits-1 downto 0);
end if;
when others => --when "01000" to "01111" =>
if (irqgen > 1) then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
v.irqmap(i*4+j) := apbi.pwdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8));
end loop;
end if;
end loop;
end if;
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if irqgen = 0 then
-- IRQ for line i = i + pirq
if (i+pirq) > NAHBIRQ-1 then
exit;
end if;
xirq(i+pirq) := tmp2(i);
else
-- IRQ for line i determined by irq select register i
for j in 0 to NIRQMUX-1 loop
if (j+pirq) > NAHBIRQ-1 then
exit;
end if;
if (irqgen = 1) or (j = conv_integer(r.irqmap(i))) then
xirq(j+pirq) := xirq(j+pirq) or tmp2(i);
end if;
end loop;
end if;
end loop;
if iflagreg /= 0 then
v.iflag := tmp2(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
end if;
-- toggle dout based on gpioi.sig_in pulse
if pulse /= 0 then
for i in 0 to nbits-1 loop
if r.pulse(i) = '1' and gpioi.sig_in(i) = '1' then
v.dout(i) := not r.dout(i);
end if;
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if ((BPDIRM(i) = '1') and
((gpioi.sig_en(i) = '1' and bpmode = 0) or
(r.bypass(i) = '1' and bpmode = 1))) then
dout(i) := gpioi.sig_in(i);
if bpmode = 0 then
dir(i) := '1';
else
dir(i) := gpioi.sig_en(i);
end if;
end if;
end loop;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.imask := RES.imask; v.bypass := RES.bypass;
v.dir := RES.dir; v.dout := RES.dout;
v.irqmap := RES.irqmap;
if iflagreg /= 0 then
v.iflag := RES.iflag;
end if;
if inpen /= 0 then
v.inpen := RES.inpen;
end if;
if pulse /= 0 then
v.pulse := RES.pulse;
end if;
end if;
if irqgen < 2 then v.irqmap := (others => (others => '0')); end if;
if iflagreg = 0 then v.iflag := (others => '0'); end if;
if inpen = 0 then v.inpen := (others => '0'); end if;
if pulse = 0 then v.pulse := (others => '0'); end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
if (scantest = 1) and (apbi.testen = '1') then
dir := (others => apbi.testoen);
if oepol = 0 then dir := not dir; end if;
elsif (syncrst = 1 ) and (rst = '0') then
dir := (others => '0');
end if;
gpioo.dout <= dout;
gpioo.oen <= dir;
if oepol = 0 then gpioo.oen <= not dir; end if;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers din1 and din2 not reset
r.din1 <= rin.din1;
r.din2 <= rin.din2;
end if;
end if;
if (syncrst = 0 ) and (arst = '0') then
r.dir <= DIR_RESVAL(nbits-1 downto 0);
r.dout <= DOUT_RESVAL(nbits-1 downto 0);
if bypass /= 0 then
r.bypass <= BP_RESVAL(nbits-1 downto 0);
end if;
if inpen /= 0 then
r.inpen <= INPEN_RESVAL(nbits-1 downto 0);
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.slot_bus_pkg.all;
package slot_bus_master_bfm_pkg is
type t_slot_bus_master_bfm_object;
type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object;
type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read,
e_slot_io_write, e_slot_bus_write );
type t_slot_bus_master_bfm_object is record
next_bfm : p_slot_bus_master_bfm_object;
name : string(1 to 256);
command : t_slot_bus_bfm_command;
poll_time : time;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
irq_pending : boolean;
end record;
------------------------------------------------------------------------------------
shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object);
end slot_bus_master_bfm_pkg;
package body slot_bus_master_bfm_pkg is
procedure register_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_slot_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if slot_bus_master_bfms = null then -- first entry
slot_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := slot_bus_master_bfms;
slot_bus_master_bfms := pntr;
end if;
pntr.irq_pending := false;
pntr.poll_time := 10 ns;
end register_slot_bus_master_bfm;
procedure bind_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
variable p : p_slot_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := slot_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_slot_bus_master_bfm;
------------------------------------------------------------------------------
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is
begin
while not m.irq_pending loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
|
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