content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
architecture rtl of fifo is
begin
GEN_LABEL : for x in range (3 downto 0) generate
end generate;
GEN_LABEL : for x in range (3 downto 0) generate
end GENERATE;
end architecture;
|
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
----------------------------------------------------------------------------------
-- Engineer: Brett Bourgeois
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity MUX2to1 is
generic (vectorSize : i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_args_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of arithmetic is
constant N : integer := 15;
type solution is record
--The inputs
O: std_logic_vector(N-1 downto 0);
C: std_logic;
V: std_logic;
VALID: std_logic;
end record... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of arithmetic is
constant N : integer := 15;
type solution is record
--The inputs
O: std_logic_vector(N-1 downto 0);
C: std_logic;
V: std_logic;
VALID: std_logic;
end record... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer... |
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer... |
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of vgca_top_tb
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm6 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm6;
architecture BEHAVIORAL of dcm... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
entity record13 is
end entity;
architecture test of record13 is
type rec is record
t : character; -- This struct must be packed
x, y : integer;
end record;
type rec_array is array (positive range <>) of rec;
function resolve(x : rec_array) return rec is
varia... |
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
PACKAGE electrical_system IS
CONSTANT epsi : real := 1.0e-18;
-- declare subtypes for voltage and current
SUBTYPE voltage IS real; -- TOLERANCE "default_voltage";
SUBTYPE current IS real; -- TOLERANCE "default_current";
SUBTYPE charge IS real; -- TOLERANCE "default_charge";
-- basic nature and ref... |
entity stdenv2 is
end entity;
use std.env.all;
use std.textio.all;
architecture test of stdenv2 is
begin
p1: process is
variable open_status : dir_open_status;
variable create_status : dir_create_status;
file f : text;
begin
report dir_workingdir;
dir_createdir("tmp", ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:28:24 06/04/2015
-- Design Name:
-- Module Name: F:/WorkSpace/workspace_ise/Exp/CPU/cpu_test.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
--... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===============================================... |
entity repro3 is
end;
architecture behav of repro3 is
component comp is
end component comp;
constant d : time := 1 comp;
begin
end behav;
|
architecture RTL of FIFO is
signal sig1, sig2 : std_logic_vector(3 downto 0);
constant c_cons1, c_const2 : integer := 200;
constant c_cons2 : integer := 200;
begin
U_RAM : RAM_ARRAY
generic map (
G_WIDTH => 512,
G_DEPTH => 2048,
G_SIZE => 32
)
port map (
I_DATA_A => data_... |
--!
--! \file add.vhd
--!
--! Demo thread for partial reconfiguration
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-------------------... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vec... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vec... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vec... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vec... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vec... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity testeverything_tb is
end testeverything_tb;
architecture Behavioral of testeverything_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
signal SDA, SCL, USER_RESET: std_logic;
begin
SDA <= 'H';
SCL <= 'H... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:16 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_rx.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Descri... |
library ieee;
use ieee.std_logic_1164.all;
entity led_display_controller_tb is
end;
architecture led_display_controller_tb_func of led_display_controller_tb is
signal bcd0_in : std_logic_vector(3 downto 0);
signal bcd1_in : std_logic_vector(3 downto 0);
signal bcd2_in : std_logic_vector(3 downto 0);... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_nov;
architecture behaviour of ex1_nov is
constant s1: std_logic_vector(4 downto 0) := "010... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: ROM_Seno.vhd
-- Megafunction Name(s):
-- lpm_rom
--
-- Simulation Library Files(s):
-- lpm
-- =========================================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.slot_bus_pkg.all;
package slot_bus_master_bfm_pkg is
type t_slot_bus_master_bfm_object;
type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object;
... |
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