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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:52 11/09/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/EX_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY EX_TB IS
END EX_TB;
ARCHITECTURE behavior OF EX_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EX
PORT(
clock : IN std_logic;
reset : IN std_logic;
ALUA_from_ID : IN std_logic_vector(31 downto 0);
ALUB_from_ID : IN std_logic_vector(31 downto 0);
cntl_from_ID : IN std_logic_vector(11 downto 0);
p_flag_from_MEM : IN std_logic;
ALUR_to_MEM : OUT std_logic_vector(31 downto 0);
dest_reg_addr_to_ID : OUT std_logic_vector(4 downto 0);
cond_bit_to_IF : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal ALUA_from_ID : std_logic_vector(31 downto 0) := (others => '0');
signal ALUB_from_ID : std_logic_vector(31 downto 0) := (others => '0');
signal cntl_from_ID : std_logic_vector(11 downto 0) := (others => '0');
signal p_flag_from_MEM : std_logic := '0';
--Outputs
signal ALUR_to_MEM : std_logic_vector(31 downto 0);
signal dest_reg_addr_to_ID : std_logic_vector(4 downto 0);
signal cond_bit_to_IF : std_logic;
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EX PORT MAP (
clock => clock,
reset => reset,
ALUA_from_ID => ALUA_from_ID,
ALUB_from_ID => ALUB_from_ID,
cntl_from_ID => cntl_from_ID,
p_flag_from_MEM => p_flag_from_MEM,
ALUR_to_MEM => ALUR_to_MEM,
dest_reg_addr_to_ID => dest_reg_addr_to_ID,
cond_bit_to_IF => cond_bit_to_IF
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
ALUA_from_ID <= x"00000001";
ALUB_from_ID <= x"00000001";
cntl_from_ID <= b"00001_000_0000";
p_flag_from_MEM <= '0';
wait for 20 ns;
reset <= '0';
ALUA_from_ID <= x"00000002";
ALUB_from_ID <= x"00000001";
cntl_from_ID <= b"00001_011_0000";
p_flag_from_MEM <= '0';
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.vhdl
-- Design : bram_1024_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_1024_3_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000001000000001C0000001800000014000000100000000C0000000800000004",
INIT_01 => X"000002000000011C0000011800000114000001100000010C0000010800000104",
INIT_02 => X"000003000000021C0000021800000214000002100000020C0000020800000204",
INIT_03 => X"000004000000031C0000031800000314000003100000030C0000030800000304",
INIT_04 => X"000005000000041C0000041800000414000004100000040C0000040800000404",
INIT_05 => X"000006000000051C0000051800000514000005100000050C0000050800000504",
INIT_06 => X"000007000000061C0000061800000614000006100000060C0000060800000604",
INIT_07 => X"000008000000071C0000071800000714000007100000070C0000070800000704",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_1024_3_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_1024_3_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_1024_3_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_1024_3_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_1024_3_blk_mem_gen_top;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_1024_3_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_1024_3_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_3_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_1024_3_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_1024_3_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_1024_3 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_1024_3 : entity is "bram_1024_3,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_3 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_1024_3 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_1024_3;
architecture STRUCTURE of bram_1024_3 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_1024_3_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:47 04/04/2013
-- Design Name:
-- Module Name: encoder8x3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder8x3 is
Port ( i : in std_logic_VECTOR (7 downto 0);
o : out std_logic_VECTOR (2 downto 0));
end encoder8x3;
architecture Behavioral of encoder8x3 is
begin
process(i)
begin
case i is
when "00000001" => o <= "000";
when "00000010" => o <= "001";
when "00000100" => o <= "010";
when "00001000" => o <= "011";
when "00010000" => o <= "100";
when "00100000" => o <= "101";
when "01000000" => o <= "110";
when "10000000" => o <= "111";
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_rx.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity pci_exp_usrapp_rx is
generic (
TRN_RX_TIMEOUT : INTEGER :=10000
);
port (
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
trn_rd : in std_logic_vector ((64 - 1) downto 0 );
trn_rrem_n : in std_logic_vector ((8 - 1) downto 0 );
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector ((7 - 1) downto 0 );
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
--sim_time : in TIME;
rx_tx_read_data : out std_logic_vector(31 downto 0);
rx_tx_read_data_valid : out std_logic;
tx_rx_read_data_valid : in std_logic
);
end pci_exp_usrapp_rx;
architecture rtl of pci_exp_usrapp_rx is
type BYTE_ARRAY is array (999 downto 0) of std_logic_vector(7 downto 0);
constant TRN_RX_RESET : std_logic_vector(4 downto 0) := "00001";
constant TRN_RX_DOWN : std_logic_vector(4 downto 0) := "00010";
constant TRN_RX_IDLE : std_logic_vector(4 downto 0) := "00100";
constant TRN_RX_ACTIVE : std_logic_vector(4 downto 0) := "01000";
constant TRN_RX_SRC_DSC : std_logic_vector(4 downto 0) := "10000";
constant PCI_EXP_MEM_READ32 : std_logic_vector(6 downto 0) := "0000000";
constant PCI_EXP_IO_READ : std_logic_vector(6 downto 0) := "0000010";
constant PCI_EXP_CFG_READ0 : std_logic_vector(6 downto 0) := "0000100";
constant PCI_EXP_COMPLETION_WO_DATA : std_logic_vector(6 downto 0) := "0001010";
constant PCI_EXP_MEM_READ64 : std_logic_vector(6 downto 0) := "0100000";
constant PCI_EXP_MSG_NODATA : std_logic_vector(6 downto 3) := "0110";
constant PCI_EXP_MEM_WRITE32 : std_logic_vector(6 downto 0) := "1000000";
constant PCI_EXP_IO_WRITE : std_logic_vector(6 downto 0) := "1000010";
constant PCI_EXP_CFG_WRITE0 : std_logic_vector(6 downto 0) := "1000100";
constant PCI_EXP_COMPLETION_DATA : std_logic_vector(6 downto 0) := "1001010";
constant PCI_EXP_MEM_WRITE64 : std_logic_vector(6 downto 0) := "1100000";
constant PCI_EXP_MSG_DATA : std_logic_vector(6 downto 3) := "1110";
constant COMPLETER_ID_CFG : std_logic_vector(15 downto 0) := X"01A0";
-- Global variables
shared variable frame_store_rx : BYTE_ARRAY;
shared variable frame_store_rx_idx : INTEGER;
shared variable next_trn_rx_timeout : INTEGER;
signal trn_rdst_rdy_n_c : std_logic;
signal trn_rnp_ok_n_c : std_logic;
signal read_data_valid_int : std_logic;
signal read_data_valid_int_d : std_logic; -- added to prevent race condition
signal trn_rx_state : std_logic_vector(4 downto 0);
file RX_file : TEXT open write_mode is "rx.dat";
--************************************************************
-- Proc : writeNowToRx
-- Inputs : Text String
-- Outputs : None
-- Description : Displays text string to Rx file pre-appended with
-- current simulation time..
-- *************************************************************/
procedure writeNowToRx (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (rx_file, L);
end writeNowToRx;
--************************************************************
-- Proc : writeNowToScreen
-- Inputs : Text String
-- Outputs : None
-- Description : Displays current simulation time and text string to
-- standard output.
-- *************************************************************
procedure writeNowToScreen (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (output, L);
end writeNowToScreen;
--************************************************************
-- Proc : writeHexToRx
-- Inputs : hex value with bit width that is multiple of 4
-- Outputs : None
-- Description : Displays nibble aligned hex value to Rx file
--
-- *************************************************************
procedure writeHexToRx (
text_string : in string;
hexValue : in std_logic_vector
) is
variable L : line;
begin
write (L, text_string);
hwrite(L, hexValue);
writeline (rx_file, L);
end writeHexToRx;
--************************************************************
-- Proc : PROC_READ_DATA
-- Inputs : None
-- Outputs : None
-- Description : Consume clocks.
-- *************************************************************/
procedure PROC_READ_DATA (
last : in INTEGER;
trn_d : in std_logic_vector (63 downto 0);
trn_rem : in std_logic_vector (7 downto 0)
) is
variable i : INTEGER;
variable data_byte : std_logic_vector (7 downto 0);
variable remain : INTEGER;
variable hi_index : INTEGER;
variable low_index : INTEGER;
variable my_line : line;
begin
hi_index := 63;
low_index := 56;
if (last = 1) then
if (trn_rem = X"0F") then
remain := 4;
else
remain := 8;
end if;
else
remain := 8;
end if;
for i in 0 to (remain - 1) loop
data_byte := trn_d( hi_index downto low_index);
hi_index := hi_index - 8;
low_index := low_index - 8;
frame_store_rx(frame_store_rx_idx) := data_byte;
frame_store_rx_idx := frame_store_rx_idx + 1;
end loop;
end PROC_READ_DATA;
--************************************************************
-- Proc : PROC_DECIPHER_FRAME
-- Inputs : None
-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
-- Description : Deciphers frame
-- *************************************************************/
procedure PROC_DECIPHER_FRAME (
fmt : out std_logic_vector (1 downto 0);
tlp_type : out std_logic_vector (4 downto 0);
traffic_class : out std_logic_vector (2 downto 0);
td : out std_logic;
ep : out std_logic;
attr : out std_logic_vector (1 downto 0);
length : out std_logic_vector (9 downto 0)
) is
begin
fmt := frame_store_rx(0)(6 downto 5);
tlp_type := frame_store_rx(0)(4 downto 0);
traffic_class := frame_store_rx(1)(6 downto 4);
td := frame_store_rx(2)(7);
ep := frame_store_rx(2)(6);
attr := frame_store_rx(2)(5 downto 4);
length(9 downto 8) := frame_store_rx(2)(1 downto 0);
length(7 downto 0) := frame_store_rx(3);
end PROC_DECIPHER_FRAME;
-- ************************************************************
-- Proc : PROC_3DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length,
-- payload,
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_3DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER;
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
signal read_data_valid_int : out std_logic
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable completer_id : std_logic_vector (15 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
writeHexToRx (String'(" Length: 0x"), "00" & length);
fmt_type := fmt & tlp_type;
case (fmt_type) is
when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
completer_id := frame_store_rx(8) & frame_store_rx(9);
register_address(9 downto 8) := frame_store_rx(10)(1 downto 0);
register_address(7 downto 0) := frame_store_rx(11);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
writeHexToRx (String'(" Register Address: 0x"), "00" & register_address);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
completer_id := frame_store_rx(4) & frame_store_rx(5);
completion_status(2 downto 0) := frame_store_rx(6)(7 downto 5);
requester_id := frame_store_rx(8) & frame_store_rx(9);
tag := frame_store_rx(10);
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
writeHexToRx ( String'(" Completion Status: 0x"), '0' & completion_status);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
rx_tx_read_data <= frame_store_rx(15) & frame_store_rx(14) &
frame_store_rx(13) & frame_store_rx(12);
read_data_valid_int <= '1';
end if;
write (L, String'("")); writeline(rx_file, L);
when others =>
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
address_low(31 downto 24) := frame_store_rx(8);
address_low(23 downto 16) := frame_store_rx(9);
address_low(15 downto 8) := frame_store_rx(10);
address_low( 7 downto 0) := frame_store_rx(11);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
end case;
end PROC_3DW;
-- ************************************************************
-- Proc : PROC_4DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length
-- payload
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_4DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable message_code : std_logic_vector (7 downto 0);
variable address_high : std_logic_vector (31 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable msg_type : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
writeHexToRx (String'(" Length: 0x"), "00" & length);
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
message_code := frame_store_rx(7);
address_high(31 downto 24) := frame_store_rx(8);
address_high(23 downto 16) := frame_store_rx(9) ;
address_high(15 downto 8) := frame_store_rx(10);
address_high(7 downto 0) := frame_store_rx(11);
address_low(31 downto 24) := frame_store_rx(12);
address_low(23 downto 16) := frame_store_rx(13);
address_low(15 downto 8) := frame_store_rx(14) ;
address_low(7 downto 0) := frame_store_rx(15);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
fmt_type := fmt & tlp_type;
if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
msg_type := tlp_type(2 downto 0);
writeHexToRx ( String'(" Message Type: 0x"), '0' & msg_type);
writeHexToRx ( String'(" Message Code: 0x"), message_code);
writeHexToRx ( String'(" Address High: 0x"), address_high);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 16 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
else
case (fmt_type) is
when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Address High: 0x"), address_high);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 16 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
when others =>
write (L, String'(": Not a vaild frame")); writeline (rx_file, L); write (L, String'("")); writeline(rx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case;
end if;
end PROC_4DW;
--************************************************************
-- Proc : PROC_PARSE_FRAME
-- Inputs : None
-- Outputs : None
-- Description : Parse frame data
-- *************************************************************/
procedure PROC_PARSE_FRAME (
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
signal read_data_valid_int : out std_logic
) is
variable fmt : std_logic_vector (1 downto 0);
variable tlp_type : std_logic_vector (4 downto 0);
variable traffic_class : std_logic_vector (2 downto 0);
variable td : std_logic;
variable ep : std_logic;
variable attr : std_logic_vector (1 downto 0);
variable length : std_logic_vector (9 downto 0);
variable payload : INTEGER;
variable reqester_id : std_logic_vector(15 downto 0);
variable completer_id : std_logic_vector(15 downto 0);
variable tag : std_logic_vector(7 downto 0);
variable byte_enables : std_logic_vector(7 downto 0);
variable message_code : std_logic_vector(7 downto 0);
variable address_low : std_logic_vector(31 downto 0);
variable address_high : std_logic_vector(31 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable log_file_ptr : std_logic_vector (31 downto 0);
variable frame_store_idx : INTEGER;
variable fmt_type : std_logic_vector (6 downto 0);
variable L : line;
begin
writeNowToScreen ( String'("PROC_PARSE_FRAME on Receive"));
PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
-- decode the packets received based on fmt and type
fmt_type := fmt & tlp_type;
if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
writeNowToRx("Message With No Data Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
writeNowToRx("Message With Data Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
else
case (fmt_type) is
when PCI_EXP_MEM_READ32 =>
writeNowToRx("Memory Read-32 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_IO_READ =>
writeNowToRx("IO Read Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_CFG_READ0 =>
writeNowToRx("Config Read Type 0 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_COMPLETION_WO_DATA =>
writeNowToRx("Completion Without Data Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_MEM_READ64 =>
writeNowToRx("Memory Read-64 Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload); --, rx_tx_read_data, rx_tx_read_data_valid );
when PCI_EXP_MEM_WRITE32 =>
writeNowToRx("Memory Write-32 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_IO_WRITE =>
writeNowToRx("IO Write Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_CFG_WRITE0 =>
writeNowToRx("Config Write Type 0 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_COMPLETION_DATA =>
writeNowToRx("Completion With Data Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_MEM_WRITE64 =>
writeNowToRx("Memory Write-64 Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when others =>
writeNowToRx("Not a vaild frame. fmt_type = ");
write (L, fmt_type);
writeline (rx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case;
end if;
frame_store_rx_idx := 0; -- reset frame pointer
end PROC_PARSE_FRAME;
begin
trn_rdst_rdy_n <= trn_rdst_rdy_n_c;
trn_rnp_ok_n <= '0';
trn_rdst_rdy_n_c <= '0';
-- Transaction Receive User Interface State Machine
process (trn_clk, trn_reset_n)
begin
if (trn_reset_n = '0' ) then
trn_rx_state <= TRN_RX_RESET;
frame_store_rx_idx := 0;
rx_tx_read_data <= X"FFFFFFFF";
read_data_valid_int <= '0';
else
if (trn_clk'event and trn_clk = '1') then
case (trn_rx_state) is
when TRN_RX_RESET =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
else
trn_rx_state <= TRN_RX_DOWN;
end if;
when TRN_RX_DOWN =>
if (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when TRN_RX_IDLE =>
read_data_valid_int <= '0';
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
elsif ((trn_rsof_n = '0') and (trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
trn_rx_state <= TRN_RX_ACTIVE;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when TRN_RX_ACTIVE =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int);
trn_rx_state <= TRN_RX_IDLE;
elsif ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
trn_rx_state <= TRN_RX_ACTIVE;
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rsrc_dsc_n = '0')) then
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int);
trn_rx_state <= TRN_RX_SRC_DSC;
else
trn_rx_state <= TRN_RX_ACTIVE;
end if;
when TRN_RX_SRC_DSC =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when others =>
trn_rx_state <= TRN_RX_RESET;
end case;
end if;
end if;
end process;
process (trn_clk, trn_reset_n)
begin
if (trn_reset_n = '0' ) then
next_trn_rx_timeout := TRN_RX_TIMEOUT;
else
if (trn_clk'event and trn_clk = '1') then
if (next_trn_rx_timeout = 0) then
assert (false)
report "RX Simulation Timeout."
severity failure;
elsif (trn_lnk_up_n = '0') then
next_trn_rx_timeout := next_trn_rx_timeout - 1;
end if;
end if;
end if;
end process;
-- Following is used to allow rx to tx communication to occur over two trn clocks - avoiding race conditions
process (trn_clk)
begin
if (trn_clk'event and trn_clk = '1') then
read_data_valid_int_d <= read_data_valid_int;
end if;
end process;
process (trn_clk)
begin
if (trn_clk'event and trn_clk = '1') then
if (trn_lnk_up_n = '0') then
if ((tx_rx_read_data_valid = '1' ) and ((read_data_valid_int = '1') or (read_data_valid_int_d = '1'))) then
rx_tx_read_data_valid <= '1';
else
rx_tx_read_data_valid <= '0';
end if;
end if;
end if;
end process;
end; -- pci_exp_usrapp_rx
|
-- wasca.vhd
-- Generated using ACDS version 15.1 193
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- .interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata
abus_slave_0_abus_direction : out std_logic; -- .direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing
abus_slave_0_abus_disableout : out std_logic; -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
leds_conn_export : out std_logic_vector(3 downto 0); -- leds_conn.export
sdram_clkout_clk : out std_logic; -- sdram_clkout.clk
switches_conn_export : in std_logic_vector(2 downto 0) := (others => '0'); -- switches_conn.export
uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd
uart_0_external_connection_txd : out std_logic -- .txd
);
end entity wasca;
architecture rtl of wasca is
component abus_demux is
port (
clock : in std_logic := 'X'; -- clk
abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_read : in std_logic := 'X'; -- read
abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_waitrequest : out std_logic; -- waitrequest
abus_interrupt : out std_logic; -- interrupt
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_direction : out std_logic; -- direction
abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_disable_out : out std_logic; -- disableout
reset : in std_logic := 'X'; -- reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X'; -- burstcount
demux_writeaddress : out std_logic_vector(27 downto 0); -- writeaddress
demux_writedata : out std_logic_vector(15 downto 0); -- data
demux_writepulse : out std_logic; -- writepulse
demux_write_byteenable : out std_logic_vector(1 downto 0); -- write_byteenable
demux_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
demux_readpulse : out std_logic; -- readpulse
demux_readdatavalid : in std_logic := 'X'; -- readdatavalid
demux_readaddress : out std_logic_vector(27 downto 0); -- readaddress
saturn_reset : in std_logic := 'X' -- saturn_reset
);
end component abus_demux;
component abus_slave is
port (
clock : in std_logic := 'X'; -- clk
avalon_read : out std_logic; -- read
avalon_write : out std_logic; -- write
avalon_waitrequest : in std_logic := 'X'; -- waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- writedata
avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon_burstcount : out std_logic; -- burstcount
reset : in std_logic := 'X'; -- reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X'; -- burstcount
demux_writeaddress : in std_logic_vector(27 downto 0) := (others => 'X'); -- writeaddress
demux_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
demux_writepulse : in std_logic := 'X'; -- writepulse
demux_write_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- write_byteenable
demux_readdata : out std_logic_vector(15 downto 0); -- readdata
demux_readpulse : in std_logic := 'X'; -- readpulse
demux_readdatavalid : out std_logic; -- readdatavalid
demux_readaddress : in std_logic_vector(27 downto 0) := (others => 'X') -- readaddress
);
end component abus_slave;
component wasca_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component wasca_altpll_0;
component wasca_external_sdram_controller is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component wasca_external_sdram_controller;
component wasca_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(3 downto 0) -- export
);
end component wasca_leds;
component wasca_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component wasca_nios2_gen2_0;
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
component wasca_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_0;
component wasca_onchip_memory2_1 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_1;
component wasca_performance_counter_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X') -- writedata
);
end component wasca_performance_counter_0;
component wasca_switches is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(2 downto 0) := (others => 'X') -- export
);
end component wasca_switches;
component wasca_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component wasca_uart_0;
component wasca_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address
abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest
abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read
abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata
abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write
abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
abus_demux_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
abus_demux_0_avalon_nios_write : out std_logic; -- write
abus_demux_0_avalon_nios_read : out std_logic; -- read
abus_demux_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
abus_demux_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
abus_demux_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
abus_demux_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
abus_demux_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
abus_slave_0_avalon_nios_write : out std_logic; -- write
abus_slave_0_avalon_nios_read : out std_logic; -- read
abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address
external_sdram_controller_s1_write : out std_logic; -- write
external_sdram_controller_s1_read : out std_logic; -- read
external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest
external_sdram_controller_s1_chipselect : out std_logic; -- chipselect
leds_s1_address : out std_logic_vector(1 downto 0); -- address
leds_s1_write : out std_logic; -- write
leds_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
leds_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
leds_s1_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_flash_0_csr_address : out std_logic_vector(0 downto 0); -- address
onchip_flash_0_csr_write : out std_logic; -- write
onchip_flash_0_csr_read : out std_logic; -- read
onchip_flash_0_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address
onchip_flash_0_data_write : out std_logic; -- write
onchip_flash_0_data_read : out std_logic; -- read
onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_data_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount
onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid
onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest
onchip_memory2_0_s1_address : out std_logic_vector(12 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
onchip_memory2_1_s1_address : out std_logic_vector(9 downto 0); -- address
onchip_memory2_1_s1_write : out std_logic; -- write
onchip_memory2_1_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_1_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_1_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_1_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_1_s1_clken : out std_logic; -- clken
performance_counter_0_control_slave_address : out std_logic_vector(2 downto 0); -- address
performance_counter_0_control_slave_write : out std_logic; -- write
performance_counter_0_control_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
performance_counter_0_control_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
performance_counter_0_control_slave_begintransfer : out std_logic; -- begintransfer
switches_s1_address : out std_logic_vector(1 downto 0); -- address
switches_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component wasca_mm_interconnect_0;
component wasca_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component wasca_irq_mapper;
component wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller;
component wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, abus_demux_0:clock, abus_slave_0:clock, external_sdram_controller:clk, irq_mapper:clk, leds:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, onchip_memory2_1:clk, performance_counter_0:clk, rst_controller:clk, rst_controller_002:clk, switches:clk, uart_0:clk]
signal abus_slave_0_demux_readdata : std_logic_vector(15 downto 0); -- abus_slave_0:demux_readdata -> abus_demux_0:demux_readdata
signal abus_demux_0_demux_readpulse : std_logic; -- abus_demux_0:demux_readpulse -> abus_slave_0:demux_readpulse
signal abus_demux_0_demux_readaddress : std_logic_vector(27 downto 0); -- abus_demux_0:demux_readaddress -> abus_slave_0:demux_readaddress
signal abus_demux_0_demux_data : std_logic_vector(15 downto 0); -- abus_demux_0:demux_writedata -> abus_slave_0:demux_writedata
signal abus_slave_0_demux_readdatavalid : std_logic; -- abus_slave_0:demux_readdatavalid -> abus_demux_0:demux_readdatavalid
signal abus_demux_0_demux_write_byteenable : std_logic_vector(1 downto 0); -- abus_demux_0:demux_write_byteenable -> abus_slave_0:demux_write_byteenable
signal abus_demux_0_demux_writeaddress : std_logic_vector(27 downto 0); -- abus_demux_0:demux_writeaddress -> abus_slave_0:demux_writeaddress
signal abus_demux_0_demux_writepulse : std_logic; -- abus_demux_0:demux_writepulse -> abus_slave_0:demux_writepulse
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_master_waitrequest -> abus_slave_0:avalon_waitrequest
signal abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_master_readdata -> abus_slave_0:avalon_readdata
signal abus_slave_0_avalon_master_read : std_logic; -- abus_slave_0:avalon_read -> mm_interconnect_0:abus_slave_0_avalon_master_read
signal abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- abus_slave_0:avalon_address -> mm_interconnect_0:abus_slave_0_avalon_master_address
signal abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_master_readdatavalid -> abus_slave_0:avalon_readdatavalid
signal abus_slave_0_avalon_master_write : std_logic; -- abus_slave_0:avalon_write -> mm_interconnect_0:abus_slave_0_avalon_master_write
signal abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- abus_slave_0:avalon_writedata -> mm_interconnect_0:abus_slave_0_avalon_master_writedata
signal abus_slave_0_avalon_master_burstcount : std_logic; -- abus_slave_0:avalon_burstcount -> mm_interconnect_0:abus_slave_0_avalon_master_burstcount
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs
signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata
signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest
signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr
signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in
signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in
signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid
signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in
signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data
signal mm_interconnect_0_onchip_memory2_1_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_chipselect -> onchip_memory2_1:chipselect
signal mm_interconnect_0_onchip_memory2_1_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_1:readdata -> mm_interconnect_0:onchip_memory2_1_s1_readdata
signal mm_interconnect_0_onchip_memory2_1_s1_address : std_logic_vector(9 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_address -> onchip_memory2_1:address
signal mm_interconnect_0_onchip_memory2_1_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_byteenable -> onchip_memory2_1:byteenable
signal mm_interconnect_0_onchip_memory2_1_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_write -> onchip_memory2_1:write
signal mm_interconnect_0_onchip_memory2_1_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_writedata -> onchip_memory2_1:writedata
signal mm_interconnect_0_onchip_memory2_1_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_clken -> onchip_memory2_1:clken
signal mm_interconnect_0_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:abus_slave_0_avalon_nios_readdata
signal mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest : std_logic; -- abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:abus_slave_0_avalon_nios_waitrequest
signal mm_interconnect_0_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_address -> abus_slave_0:avalon_nios_address
signal mm_interconnect_0_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_nios_read -> abus_slave_0:avalon_nios_read
signal mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:abus_slave_0_avalon_nios_readdatavalid
signal mm_interconnect_0_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_nios_write -> abus_slave_0:avalon_nios_write
signal mm_interconnect_0_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_writedata -> abus_slave_0:avalon_nios_writedata
signal mm_interconnect_0_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_burstcount -> abus_slave_0:avalon_nios_burstcount
signal mm_interconnect_0_abus_demux_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- abus_demux_0:avalon_nios_readdata -> mm_interconnect_0:abus_demux_0_avalon_nios_readdata
signal mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest : std_logic; -- abus_demux_0:avalon_nios_waitrequest -> mm_interconnect_0:abus_demux_0_avalon_nios_waitrequest
signal mm_interconnect_0_abus_demux_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_address -> abus_demux_0:avalon_nios_address
signal mm_interconnect_0_abus_demux_0_avalon_nios_read : std_logic; -- mm_interconnect_0:abus_demux_0_avalon_nios_read -> abus_demux_0:avalon_nios_read
signal mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid : std_logic; -- abus_demux_0:avalon_nios_readdatavalid -> mm_interconnect_0:abus_demux_0_avalon_nios_readdatavalid
signal mm_interconnect_0_abus_demux_0_avalon_nios_write : std_logic; -- mm_interconnect_0:abus_demux_0_avalon_nios_write -> abus_demux_0:avalon_nios_write
signal mm_interconnect_0_abus_demux_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_writedata -> abus_demux_0:avalon_nios_writedata
signal mm_interconnect_0_abus_demux_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_burstcount -> abus_demux_0:avalon_nios_burstcount
signal mm_interconnect_0_onchip_flash_0_csr_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_csr_readdata -> mm_interconnect_0:onchip_flash_0_csr_readdata
signal mm_interconnect_0_onchip_flash_0_csr_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:onchip_flash_0_csr_address -> onchip_flash_0:avmm_csr_addr
signal mm_interconnect_0_onchip_flash_0_csr_read : std_logic; -- mm_interconnect_0:onchip_flash_0_csr_read -> onchip_flash_0:avmm_csr_read
signal mm_interconnect_0_onchip_flash_0_csr_write : std_logic; -- mm_interconnect_0:onchip_flash_0_csr_write -> onchip_flash_0:avmm_csr_write
signal mm_interconnect_0_onchip_flash_0_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_flash_0_csr_writedata -> onchip_flash_0:avmm_csr_writedata
signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
signal mm_interconnect_0_onchip_flash_0_data_write : std_logic; -- mm_interconnect_0:onchip_flash_0_data_write -> onchip_flash_0:avmm_data_write
signal mm_interconnect_0_onchip_flash_0_data_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_flash_0_data_writedata -> onchip_flash_0:avmm_data_writedata
signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(12 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_performance_counter_0_control_slave_readdata : std_logic_vector(31 downto 0); -- performance_counter_0:readdata -> mm_interconnect_0:performance_counter_0_control_slave_readdata
signal mm_interconnect_0_performance_counter_0_control_slave_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:performance_counter_0_control_slave_address -> performance_counter_0:address
signal mm_interconnect_0_performance_counter_0_control_slave_begintransfer : std_logic; -- mm_interconnect_0:performance_counter_0_control_slave_begintransfer -> performance_counter_0:begintransfer
signal mm_interconnect_0_performance_counter_0_control_slave_write : std_logic; -- mm_interconnect_0:performance_counter_0_control_slave_write -> performance_counter_0:write
signal mm_interconnect_0_performance_counter_0_control_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:performance_counter_0_control_slave_writedata -> performance_counter_0:writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_switches_s1_readdata : std_logic_vector(31 downto 0); -- switches:readdata -> mm_interconnect_0:switches_s1_readdata
signal mm_interconnect_0_switches_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:switches_s1_address -> switches:address
signal mm_interconnect_0_leds_s1_chipselect : std_logic; -- mm_interconnect_0:leds_s1_chipselect -> leds:chipselect
signal mm_interconnect_0_leds_s1_readdata : std_logic_vector(31 downto 0); -- leds:readdata -> mm_interconnect_0:leds_s1_readdata
signal mm_interconnect_0_leds_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:leds_s1_address -> leds:address
signal mm_interconnect_0_leds_s1_write : std_logic; -- mm_interconnect_0:leds_s1_write -> mm_interconnect_0_leds_s1_write:in
signal mm_interconnect_0_leds_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:leds_s1_writedata -> leds:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [abus_demux_0:reset, abus_slave_0:reset, irq_mapper:reset, mm_interconnect_0:abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, onchip_memory2_1:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [onchip_memory2_0:reset_req, onchip_memory2_1:reset_req, rst_translator:reset_req_in]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n
signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n
signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n
signal mm_interconnect_0_leds_s1_write_ports_inv : std_logic; -- mm_interconnect_0_leds_s1_write:inv -> leds:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [external_sdram_controller:reset_n, leds:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, performance_counter_0:reset_n, switches:reset_n, uart_0:reset_n]
begin
abus_demux_0 : component abus_demux
port map (
clock => altpll_0_c0_clk, -- clock.clk
abus_address => abus_slave_0_abus_address, -- abus.address
abus_chipselect => abus_slave_0_abus_chipselect, -- .chipselect
abus_read => abus_slave_0_abus_read, -- .read
abus_write => abus_slave_0_abus_write, -- .write
abus_waitrequest => abus_slave_0_abus_waitrequest, -- .waitrequest
abus_interrupt => abus_slave_0_abus_interrupt, -- .interrupt
abus_addressdata => abus_slave_0_abus_addressdata, -- .addressdata
abus_direction => abus_slave_0_abus_direction, -- .direction
abus_muxing => abus_slave_0_abus_muxing, -- .muxing
abus_disable_out => abus_slave_0_abus_disableout, -- .disableout
reset => rst_controller_reset_out_reset, -- reset.reset
avalon_nios_read => mm_interconnect_0_abus_demux_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_abus_demux_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_abus_demux_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_abus_demux_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_abus_demux_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_abus_demux_0_avalon_nios_burstcount(0), -- .burstcount
demux_writeaddress => abus_demux_0_demux_writeaddress, -- demux.writeaddress
demux_writedata => abus_demux_0_demux_data, -- .data
demux_writepulse => abus_demux_0_demux_writepulse, -- .writepulse
demux_write_byteenable => abus_demux_0_demux_write_byteenable, -- .write_byteenable
demux_readdata => abus_slave_0_demux_readdata, -- .readdata
demux_readpulse => abus_demux_0_demux_readpulse, -- .readpulse
demux_readdatavalid => abus_slave_0_demux_readdatavalid, -- .readdatavalid
demux_readaddress => abus_demux_0_demux_readaddress, -- .readaddress
saturn_reset => abus_slave_0_conduit_saturn_reset_saturn_reset -- conduit_saturn_reset.saturn_reset
);
abus_slave_0 : component abus_slave
port map (
clock => altpll_0_c0_clk, -- clock.clk
avalon_read => abus_slave_0_avalon_master_read, -- avalon_master.read
avalon_write => abus_slave_0_avalon_master_write, -- .write
avalon_waitrequest => abus_slave_0_avalon_master_waitrequest, -- .waitrequest
avalon_address => abus_slave_0_avalon_master_address, -- .address
avalon_readdata => abus_slave_0_avalon_master_readdata, -- .readdata
avalon_writedata => abus_slave_0_avalon_master_writedata, -- .writedata
avalon_readdatavalid => abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
avalon_burstcount => abus_slave_0_avalon_master_burstcount, -- .burstcount
reset => rst_controller_reset_out_reset, -- reset.reset
avalon_nios_read => mm_interconnect_0_abus_slave_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_abus_slave_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_abus_slave_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_abus_slave_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_abus_slave_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_abus_slave_0_avalon_nios_burstcount(0), -- .burstcount
demux_writeaddress => abus_demux_0_demux_writeaddress, -- demux.writeaddress
demux_writedata => abus_demux_0_demux_data, -- .data
demux_writepulse => abus_demux_0_demux_writepulse, -- .writepulse
demux_write_byteenable => abus_demux_0_demux_write_byteenable, -- .write_byteenable
demux_readdata => abus_slave_0_demux_readdata, -- .readdata
demux_readpulse => abus_demux_0_demux_readpulse, -- .readpulse
demux_readdatavalid => abus_slave_0_demux_readdatavalid, -- .readdatavalid
demux_readaddress => abus_demux_0_demux_readaddress -- .readaddress
);
altpll_0 : component wasca_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => sdram_clkout_clk, -- c1.clk
areset => altpll_0_areset_conduit_export, -- areset_conduit.export
locked => altpll_0_locked_conduit_export, -- locked_conduit.export
phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export
);
external_sdram_controller : component wasca_external_sdram_controller
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address
az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
zs_addr => external_sdram_controller_wire_addr, -- wire.export
zs_ba => external_sdram_controller_wire_ba, -- .export
zs_cas_n => external_sdram_controller_wire_cas_n, -- .export
zs_cke => external_sdram_controller_wire_cke, -- .export
zs_cs_n => external_sdram_controller_wire_cs_n, -- .export
zs_dq => external_sdram_controller_wire_dq, -- .export
zs_dqm => external_sdram_controller_wire_dqm, -- .export
zs_ras_n => external_sdram_controller_wire_ras_n, -- .export
zs_we_n => external_sdram_controller_wire_we_n -- .export
);
leds : component wasca_leds
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_leds_s1_address, -- s1.address
write_n => mm_interconnect_0_leds_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_leds_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_leds_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_leds_s1_readdata, -- .readdata
out_port => leds_conn_export -- external_connection.export
);
nios2_gen2_0 : component wasca_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "",
INIT_FILENAME_SIM => "",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M08SCE144C8G",
DEVICE_ID => "08",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 4096,
SECTOR2_END_ADDR => 8191,
SECTOR3_START_ADDR => 8192,
SECTOR3_END_ADDR => 23039,
SECTOR4_START_ADDR => 23040,
SECTOR4_END_ADDR => 58879,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 58879,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 8191,
SECTOR1_MAP => 1,
SECTOR2_MAP => 2,
SECTOR3_MAP => 4,
SECTOR4_MAP => 5,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 8191,
ADDR_RANGE1_OFFSET => 512,
ADDR_RANGE2_OFFSET => 21504,
AVMM_DATA_ADDR_WIDTH => 16,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 16,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 4,
FLASH_RESET_CYCLE_MAX_INDEX => 28,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 135,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 39516766,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 34436,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => true,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "False"
)
port map (
clock => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- nreset.reset_n
avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address
avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
avmm_data_writedata => mm_interconnect_0_onchip_flash_0_data_writedata, -- .writedata
avmm_data_write => mm_interconnect_0_onchip_flash_0_data_write, -- .write
avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
avmm_csr_addr => mm_interconnect_0_onchip_flash_0_csr_address(0), -- csr.address
avmm_csr_read => mm_interconnect_0_onchip_flash_0_csr_read, -- .read
avmm_csr_writedata => mm_interconnect_0_onchip_flash_0_csr_writedata, -- .writedata
avmm_csr_write => mm_interconnect_0_onchip_flash_0_csr_write, -- .write
avmm_csr_readdata => mm_interconnect_0_onchip_flash_0_csr_readdata -- .readdata
);
onchip_memory2_0 : component wasca_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
onchip_memory2_1 : component wasca_onchip_memory2_1
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_1_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_1_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_1_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_1_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_1_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_1_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_1_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
performance_counter_0 : component wasca_performance_counter_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_performance_counter_0_control_slave_address, -- control_slave.address
begintransfer => mm_interconnect_0_performance_counter_0_control_slave_begintransfer, -- .begintransfer
readdata => mm_interconnect_0_performance_counter_0_control_slave_readdata, -- .readdata
write => mm_interconnect_0_performance_counter_0_control_slave_write, -- .write
writedata => mm_interconnect_0_performance_counter_0_control_slave_writedata -- .writedata
);
switches : component wasca_switches
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_switches_s1_address, -- s1.address
readdata => mm_interconnect_0_switches_s1_readdata, -- .readdata
in_port => switches_conn_export -- external_connection.export
);
uart_0 : component wasca_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_external_connection_rxd, -- external_connection.export
txd => uart_0_external_connection_txd, -- .export
irq => irq_mapper_receiver0_irq -- irq.irq
);
mm_interconnect_0 : component wasca_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- abus_slave_0_reset_reset_bridge_in_reset.reset
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
abus_slave_0_avalon_master_address => abus_slave_0_avalon_master_address, -- abus_slave_0_avalon_master.address
abus_slave_0_avalon_master_waitrequest => abus_slave_0_avalon_master_waitrequest, -- .waitrequest
abus_slave_0_avalon_master_burstcount(0) => abus_slave_0_avalon_master_burstcount, -- .burstcount
abus_slave_0_avalon_master_read => abus_slave_0_avalon_master_read, -- .read
abus_slave_0_avalon_master_readdata => abus_slave_0_avalon_master_readdata, -- .readdata
abus_slave_0_avalon_master_readdatavalid => abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
abus_slave_0_avalon_master_write => abus_slave_0_avalon_master_write, -- .write
abus_slave_0_avalon_master_writedata => abus_slave_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
abus_demux_0_avalon_nios_address => mm_interconnect_0_abus_demux_0_avalon_nios_address, -- abus_demux_0_avalon_nios.address
abus_demux_0_avalon_nios_write => mm_interconnect_0_abus_demux_0_avalon_nios_write, -- .write
abus_demux_0_avalon_nios_read => mm_interconnect_0_abus_demux_0_avalon_nios_read, -- .read
abus_demux_0_avalon_nios_readdata => mm_interconnect_0_abus_demux_0_avalon_nios_readdata, -- .readdata
abus_demux_0_avalon_nios_writedata => mm_interconnect_0_abus_demux_0_avalon_nios_writedata, -- .writedata
abus_demux_0_avalon_nios_burstcount => mm_interconnect_0_abus_demux_0_avalon_nios_burstcount, -- .burstcount
abus_demux_0_avalon_nios_readdatavalid => mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid, -- .readdatavalid
abus_demux_0_avalon_nios_waitrequest => mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest, -- .waitrequest
abus_slave_0_avalon_nios_address => mm_interconnect_0_abus_slave_0_avalon_nios_address, -- abus_slave_0_avalon_nios.address
abus_slave_0_avalon_nios_write => mm_interconnect_0_abus_slave_0_avalon_nios_write, -- .write
abus_slave_0_avalon_nios_read => mm_interconnect_0_abus_slave_0_avalon_nios_read, -- .read
abus_slave_0_avalon_nios_readdata => mm_interconnect_0_abus_slave_0_avalon_nios_readdata, -- .readdata
abus_slave_0_avalon_nios_writedata => mm_interconnect_0_abus_slave_0_avalon_nios_writedata, -- .writedata
abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_abus_slave_0_avalon_nios_burstcount, -- .burstcount
abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address
external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write
external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read
external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable
external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
leds_s1_address => mm_interconnect_0_leds_s1_address, -- leds_s1.address
leds_s1_write => mm_interconnect_0_leds_s1_write, -- .write
leds_s1_readdata => mm_interconnect_0_leds_s1_readdata, -- .readdata
leds_s1_writedata => mm_interconnect_0_leds_s1_writedata, -- .writedata
leds_s1_chipselect => mm_interconnect_0_leds_s1_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_flash_0_csr_address => mm_interconnect_0_onchip_flash_0_csr_address, -- onchip_flash_0_csr.address
onchip_flash_0_csr_write => mm_interconnect_0_onchip_flash_0_csr_write, -- .write
onchip_flash_0_csr_read => mm_interconnect_0_onchip_flash_0_csr_read, -- .read
onchip_flash_0_csr_readdata => mm_interconnect_0_onchip_flash_0_csr_readdata, -- .readdata
onchip_flash_0_csr_writedata => mm_interconnect_0_onchip_flash_0_csr_writedata, -- .writedata
onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address
onchip_flash_0_data_write => mm_interconnect_0_onchip_flash_0_data_write, -- .write
onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
onchip_flash_0_data_writedata => mm_interconnect_0_onchip_flash_0_data_writedata, -- .writedata
onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
onchip_memory2_1_s1_address => mm_interconnect_0_onchip_memory2_1_s1_address, -- onchip_memory2_1_s1.address
onchip_memory2_1_s1_write => mm_interconnect_0_onchip_memory2_1_s1_write, -- .write
onchip_memory2_1_s1_readdata => mm_interconnect_0_onchip_memory2_1_s1_readdata, -- .readdata
onchip_memory2_1_s1_writedata => mm_interconnect_0_onchip_memory2_1_s1_writedata, -- .writedata
onchip_memory2_1_s1_byteenable => mm_interconnect_0_onchip_memory2_1_s1_byteenable, -- .byteenable
onchip_memory2_1_s1_chipselect => mm_interconnect_0_onchip_memory2_1_s1_chipselect, -- .chipselect
onchip_memory2_1_s1_clken => mm_interconnect_0_onchip_memory2_1_s1_clken, -- .clken
performance_counter_0_control_slave_address => mm_interconnect_0_performance_counter_0_control_slave_address, -- performance_counter_0_control_slave.address
performance_counter_0_control_slave_write => mm_interconnect_0_performance_counter_0_control_slave_write, -- .write
performance_counter_0_control_slave_readdata => mm_interconnect_0_performance_counter_0_control_slave_readdata, -- .readdata
performance_counter_0_control_slave_writedata => mm_interconnect_0_performance_counter_0_control_slave_writedata, -- .writedata
performance_counter_0_control_slave_begintransfer => mm_interconnect_0_performance_counter_0_control_slave_begintransfer, -- .begintransfer
switches_s1_address => mm_interconnect_0_switches_s1_address, -- switches_s1.address
switches_s1_readdata => mm_interconnect_0_switches_s1_readdata, -- .readdata
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component wasca_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component wasca_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "both",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => open, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read;
mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable;
mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write;
mm_interconnect_0_leds_s1_write_ports_inv <= not mm_interconnect_0_leds_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
clock_116_mhz_clk <= altpll_0_c0_clk;
end architecture rtl; -- of wasca
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.monitor_cmd_pkg.all;
use work.vvc_cmd_pkg.all;
use work.vvc_methods_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity uart_monitor is
generic (
GC_INSTANCE_IDX : natural := 1;
GC_MONITOR_CONFIG : t_uart_monitor_config
);
port(
uart_dut_rx : in std_logic;
uart_dut_tx : in std_logic
);
end entity uart_monitor;
--=================================================================================================
--=================================================================================================
architecture behave of uart_monitor is
alias tx_transaction_info : t_base_transaction is shared_uart_monitor_transaction_info(TX, GC_INSTANCE_IDX).bt;
alias rx_transaction_info : t_base_transaction is shared_uart_monitor_transaction_info(RX, GC_INSTANCE_IDX).bt;
alias tx_transaction_trigger : std_logic is global_uart_monitor_transaction_trigger(TX, GC_INSTANCE_IDX);
alias rx_transaction_trigger : std_logic is global_uart_monitor_transaction_trigger(RX, GC_INSTANCE_IDX);
signal tx_i : std_logic;
signal rx_i : std_logic;
procedure monitor_uart_line(
constant operation : in t_operation;
constant C_LOG_PREFIX : in string;
signal transaction_trigger : inout std_logic;
variable transaction_info : inout t_base_transaction;
signal uart_line : in std_logic;
variable monitor_config : in t_uart_monitor_config
) is
alias interface_config : t_uart_interface_config is monitor_config.interface_config;
variable v_data : std_logic_vector(C_MAX_BITS_IN_DATA-1 downto 0) := (others => '0');
variable v_parity_error : boolean;
variable v_stop_bit_error : boolean_vector(0 to 1);
variable v_legal_transaction : boolean;
variable v_time_stamp : time;
variable v_timeout : time;
begin
-- Give constructor some time to set values
wait for 0 ns;
wait for 0 ns;
transaction_info.operation := NO_OPERATION;
transaction_info.transaction_status := INACTIVE;
-- Await idle state
if uart_line /= '1' then
wait until uart_line = '1';
end if;
loop
-- Reset meta data
v_parity_error := false;
v_stop_bit_error := (others => false);
if uart_line /= '0' then
-- Await start bit
-- If transaction_display_time > 0 then change operation after specified time
if monitor_config.transaction_display_time > 0 ns then
wait until falling_edge(uart_line) for monitor_config.transaction_display_time;
transaction_info.operation := NO_OPERATION;
transaction_info.transaction_status := INACTIVE;
end if;
if uart_line /= '0' then
wait until falling_edge(uart_line);
end if;
-- Start bit registered and transaction is active
log(ID_FRAME_INITIATE, C_LOG_PREFIX & "Start bit detected", monitor_config.scope_name, monitor_config.msg_id_panel);
transaction_info.transaction_status := IN_PROGRESS;
-- Align sampling point to middle of bit period
wait for interface_config.bit_time + (interface_config.bit_time/2);
else
-- Second stop bit interpreted as start bit transaction is active
log(ID_FRAME_INITIATE, C_LOG_PREFIX & "Second stop bit interpreted as start bit.", monitor_config.scope_name, monitor_config.msg_id_panel);
transaction_info.transaction_status := IN_PROGRESS;
-- Align sampling to middle of bit
if (interface_config.bit_time/2) > uart_line'last_event then
wait for (interface_config.bit_time/2) - uart_line'last_event + interface_config.bit_time;
else
wait for interface_config.bit_time - uart_line'last_event + (interface_config.bit_time/2);
end if;
end if;
-- Data bits
for i in 0 to interface_config.num_data_bits-1 loop
v_data(i) := uart_line;
wait for interface_config.bit_time;
end loop;
-- Parity bit
if interface_config.parity = PARITY_ODD then
v_parity_error := xor(v_data & uart_line) = '0';
elsif interface_config.parity = PARITY_EVEN then
v_parity_error := xor(v_data & uart_line) = '1';
end if;
-- First stop bit
wait for interface_config.bit_time;
if uart_line /= '1' then
v_stop_bit_error(0) := true;
end if;
-- If two or one and a half stop bit
if interface_config.num_stop_bits = STOP_BITS_TWO then
wait for interface_config.bit_time;
if uart_line /= '1' then
v_stop_bit_error(1) := true;
end if;
elsif interface_config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for interface_config.bit_time/2 + interface_config.bit_time/4; -- Middle of half bit period
if uart_line /= '1' then
v_stop_bit_error(1) := true;
end if;
end if;
-- Determine legal transaction
if v_parity_error or or(v_stop_bit_error) then
log(ID_MONITOR, C_LOG_PREFIX & "Non-legal transaction detected: parity_error: " & to_string(v_parity_error) & "; stop_bit_error: " &
to_string(or(v_stop_bit_error)) & ".", monitor_config.scope_name, monitor_config.msg_id_panel);
else
log(ID_MONITOR, C_LOG_PREFIX & "Legal transaction completed.", monitor_config.scope_name, monitor_config.msg_id_panel);
end if;
-- Update transaction
transaction_info.operation := operation;
transaction_info.data := v_data;
transaction_info.error_info := (parity_bit_error => v_parity_error,
stop_bit_error => or(v_stop_bit_error));
if v_parity_error or or(v_stop_bit_error) then
transaction_info.transaction_status := FAILED;
else
transaction_info.transaction_status := SUCCEEDED;
end if;
-- Pulse transaction info trigger signal for updated transaction information
gen_pulse(transaction_trigger, 0 ns, BLOCKING, "pulsing monitor transaction info trigger");
-- Await non-active line if no stop bit has been detected
if (and(v_stop_bit_error) or (interface_config.num_stop_bits = STOP_BITS_ONE and v_stop_bit_error(0))) and uart_line /= '1' then
wait until uart_line = '1';
end if;
end loop;
end procedure;
begin
p_tx_monitor_constructor : monitor_constructor(GC_MONITOR_CONFIG, shared_uart_monitor_config(TX, GC_INSTANCE_IDX));
p_rx_monitor_constructor : monitor_constructor(GC_MONITOR_CONFIG, shared_uart_monitor_config(RX, GC_INSTANCE_IDX));
-- Strength reduction functions to handle H/L
p_tx_i : tx_i <= to_ux01(uart_dut_tx);
p_rx_i : rx_i <= to_ux01(uart_dut_rx);
p_tx_monitor : monitor_uart_line(TRANSMIT, "TX: ", tx_transaction_trigger, tx_transaction_info, tx_i, shared_uart_monitor_config(TX, GC_INSTANCE_IDX));
p_rx_monitor : monitor_uart_line(RECEIVE, "RX: ", rx_transaction_trigger, rx_transaction_info, rx_i, shared_uart_monitor_config(RX, GC_INSTANCE_IDX));
end architecture behave; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02396ent IS
END c07s03b02x00p07n01i02396ent;
ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV : BYTE;
BEGIN
BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
2 => '1', 0 => '1', 5 => '0',
3 => '0', 1 => '0' );
assert( BYTEV( 1 ) = '0' );
assert( BYTEV( 3 ) = '0' );
assert( BYTEV( 5 ) = '0' );
assert( BYTEV( 7 ) = '0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 6 ) = '1' );
wait for 1 ns;
assert NOT( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n01i02396"
severity NOTE;
assert ( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02396arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02396ent IS
END c07s03b02x00p07n01i02396ent;
ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV : BYTE;
BEGIN
BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
2 => '1', 0 => '1', 5 => '0',
3 => '0', 1 => '0' );
assert( BYTEV( 1 ) = '0' );
assert( BYTEV( 3 ) = '0' );
assert( BYTEV( 5 ) = '0' );
assert( BYTEV( 7 ) = '0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 6 ) = '1' );
wait for 1 ns;
assert NOT( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n01i02396"
severity NOTE;
assert ( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02396arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02396ent IS
END c07s03b02x00p07n01i02396ent;
ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV : BYTE;
BEGIN
BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
2 => '1', 0 => '1', 5 => '0',
3 => '0', 1 => '0' );
assert( BYTEV( 1 ) = '0' );
assert( BYTEV( 3 ) = '0' );
assert( BYTEV( 5 ) = '0' );
assert( BYTEV( 7 ) = '0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 6 ) = '1' );
wait for 1 ns;
assert NOT( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n01i02396"
severity NOTE;
assert ( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02396arch;
|
-- $Id: artylib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: artylib
-- Description: Digilent Arty components
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-29 1063 1.2 add arty_dram_aif
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package artylib is
component arty_aif is -- ARTY, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end component;
component arty_dram_aif is -- ARTY, abstract iface, base+dram
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end component;
end package artylib;
|
-- This block makes double accumulator linear FM chirp generator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity chirp_gen is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end chirp_gen;
architecture rtl of chirp_gen is
constant chirp_rate : unsigned(31 downto 0) := B"00000000_00010000_00000000_00000000";
signal phase, freq : unsigned(31 downto 0);
signal s_axis_phase_tdata : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal m_axis_data_tdata : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- The double accumulator phase generator.
regs_proc:process
begin
wait until rising_edge(clk);
if reset = '1' then
freq <= (others=>'0');
phase <= (others=>'0');
else
freq <= freq + chirp_rate;
phase <= phase + freq;
end if;
end process;
-- Pack the 12 phase bits into the silly axis bus.
s_axis_phase_tdata(11 downto 0) <= std_logic_vector(phase(phase'left downto phase'left-11));
-- The sine rom IP core.
sine_rom_inst : entity work.sine_rom
PORT MAP (
aclk => clk,
s_axis_phase_tvalid => '1',
s_axis_phase_tdata => s_axis_phase_tdata,
m_axis_data_tvalid => open,
m_axis_data_tdata => m_axis_data_tdata);
-- Rip the sine and cosine out of the silly axis bus.
sin <= m_axis_data_tdata(15 downto 8);
cos <= m_axis_data_tdata( 7 downto 0);
end rtl;
|
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'ascending;
assert x = "hello";
end procedure;
procedure proc2(x : in string) is
begin
proc1(x(x'range));
end procedure;
begin
process is
variable s : string(1 to 5) := "hello";
begin
proc2(s);
wait;
end process;
end architecture;
|
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'ascending;
assert x = "hello";
end procedure;
procedure proc2(x : in string) is
begin
proc1(x(x'range));
end procedure;
begin
process is
variable s : string(1 to 5) := "hello";
begin
proc2(s);
wait;
end process;
end architecture;
|
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'ascending;
assert x = "hello";
end procedure;
procedure proc2(x : in string) is
begin
proc1(x(x'range));
end procedure;
begin
process is
variable s : string(1 to 5) := "hello";
begin
proc2(s);
wait;
end process;
end architecture;
|
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'ascending;
assert x = "hello";
end procedure;
procedure proc2(x : in string) is
begin
proc1(x(x'range));
end procedure;
begin
process is
variable s : string(1 to 5) := "hello";
begin
proc2(s);
wait;
end process;
end architecture;
|
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'ascending;
assert x = "hello";
end procedure;
procedure proc2(x : in string) is
begin
proc1(x(x'range));
end procedure;
begin
process is
variable s : string(1 to 5) := "hello";
begin
proc2(s);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler, Konrad Eisele - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of mmu_dcache is
constant DSNOOP2 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(3,3));
constant DSNOOP4 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(4,3));
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant lram : integer range 0 to 1 := 0;
constant lramsize : integer range 1 to 64 := 1;
constant lramstart : integer range 0 to 255 := 16#00#;
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DCLOCK_BIT : integer := dsetlock;
constant M_EN : boolean := true;
constant DCREPLACE : integer range 0 to 2 := drepl;
constant DLINE_SIZE : integer := dlinesize;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory, sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag,dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : dstatetype; -- FSM
hit : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_logic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_logic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_logic;
lramrd : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
su : std_logic;
dblwdata : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_logic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr, dparerr : std_logic_vector(0 to DSETS-1);
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to MAXSETS-1);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoopset2, rdsuset : integer range 0 to DSETS-1;
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_logic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable ctx : ctxdatatype;
variable miscdata : std_logic_vector(31 downto 0);
variable mmudiagaddr : std_logic_vector(2 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuwdata : std_logic_vector(31 downto 0);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable mmuregw, su : std_logic;
variable mmuisdis : std_logic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; v.cctrlwr := '0'; v.mmctrl1wr := '0';
v.flush2 := r.flush; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
tparerr := (others => '0'); dparerr := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0'; rdsuset := 0;
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
mmudiagaddr := (others => '0'); mmuregw := '0'; mmuwdata := (others => '0');
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
ctx := (others => (others => '0')); vs.readbpx := (others => '0'); rbphit := '0';
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
if (not M_EN) or (r.mmctrl1.e = '0') then v.cache := '1'; end if;
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if DCLOCK_BIT = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if DSNOOP2 /= 0 then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;-- and not r.mmctrl1.e;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (paddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP2 = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP2 /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); --signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read;
else
maddress := dci.maddress(31 downto 0); --signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0;
snoophit := (others => '0'); snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP2 = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and (not r.flush2);
-- cache hit disabled if mmu-enabled but off or BYPASS
if (M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP) then -- or (r.mmctrl1.e = '0')
hit := '0';
end if;
validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if hitv(i) = '1' then
vset := vset or conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
--v.signed := dci.signed;
v.su := dci.msu;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
if (dsu = 1) and (dci.dsuen = '1') then
mmuwdata := dci.maddress;
else
mmuwdata := dci.edata;
end if;
mmudiagaddr := dci.maddress(CNR_U downto CNR_D);
if r.mmctrl1wr = '1' then
mmudiagaddr := r.xaddress(CNR_U downto CNR_D); -- defer match sram out
if (dci.read = '0') then
mmuwdata := dci.maddress;
mmuregw := '1';
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
v.nomds := r.nomds and not eholdn; --v.valid := dcramov.dtramout(set).valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and (M_TLB_FASTWRITE /= 0) ) then
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => rdatasel := dctx;
when ASI_MMUREGS => rdatasel := misc;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_MMUREGS =>
if (dsu = 0) or dci.dsuen = '0' then
if M_EN then
-- rdatasel := misc;
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
else
mmuregw := '1';
end if;
end if;
else
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := '0'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if M_EN then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
--if (not ((mcdo.dcs(0) = '1')
if (not ((r.cctrl.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := '1';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0'))
then
-- cache disabled if mmu-enabled but off or BYPASS
if (M_EN) then v.cache := '0'; end if;
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
end if;
else -- write access
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0';
end if;
else
-- ## mmu case > false and
--if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (dci.size /= "11") and (M_TLB_FASTWRITE /= 0)
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (M_TLB_FASTWRITE /= 0)
then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
v.dblwdata := dci.size(0) or dci.size(1); -- "11"
-- ## < mmu case
end if;
end if;
-- note: cache hit disabled if BYPASS
if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not dparerr(set)) and (not r.flush)) = '1' then
case DCREPLACE is
when rnd =>
if DCLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if DCLOCK_BIT = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (DCLOCK_BIT = 1) then
if (hit and (not dparerr(set)) and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
--v.xaddress := mmudco.data;
v.paddress := mmudco.transdata.data;
if v.wbinit = '1' then
v.wb.addr := mmudco.transdata.data;
v.req := '1';
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 1 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit and r.cache; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))) and r.cache; twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
tpwrite := twrite;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
if DSNOOP2 /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := idle;
when dblwrite => -- second part of double store cycle
v.dstate := idle; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when asi_idtag => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; mds := not r.read;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
-- fetch dblwrite data 2, does the same as state dblwrite,
-- except that init of data2 is omitted to end of translation or in wwrite
if ((r.dblwdata) = '1') and ((r.size) = "11") then
v.dblwdata := '0';
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.cctrl.dcs(0) and r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
v.req := '1'; v.stpend := '1';
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
--if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := '1';
end if;
end if;
end if;
else
-- mmudci_trans_op := '1'; -- start translation
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (v.ready or (mcdo.ready and not r.req)) = '1' then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := idle;
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
--mmudiagaddr := dci.maddress(CNR_U downto CNR_D); mmuwdata := dci.edata;
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if M_EN then
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag;
end if;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_MMUREGS =>
mmuregw := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := misc;
when others =>
end case;
end if;
-- note: mmudiagaddr is (10 downto 8) (000,001, ...)
-- read
case mmudiagaddr is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0000";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(17) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
set := 0;
rdatav(0) := miscdata;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, lram, lramsize, lramstart, 1);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = idle then
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
v.valid := vmask;
if (DSETS>1) and (DCREPLACE = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (DCREPLACE = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if mmuregw = '1' then
case mmudiagaddr is
when CNR_CTRL =>
v.mmctrl1.e := mmuwdata(MMCTRL_E);
v.mmctrl1.nf := mmuwdata(MMCTRL_NF);
v.mmctrl1.pso := mmuwdata(MMCTRL_PSO);
v.mmctrl1.tlbdis := mmuwdata(MMCTRL_TLBDIS);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := mmuwdata(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := mmuwdata(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
--if (dci.flush or flush or mcdo.dflush) = '1' then
if (dci.flush or flush ) = '1' then
v.flush := '1'; v.faddr := (others => '0'); v.pflush := pflush;
v.pflushr := '1';
v.pflushaddr := pflushaddr;
v.pflushtyp := pflushtyp;
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others=>(others => '0')); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0'); v.lrr := '0';
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP2 = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP2 /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP2 = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= idle) then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = wread) and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if M_EN then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if M_EN then
ctpwrite := (others => '1');
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if false then --
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
for i in DSETS-1 downto 0 loop
wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS);
wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS);
end loop;
if r.pflushr = '0' then
for i in DSETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := dcramov.tag(i)(TAG_HIGH downto TAG_LOW);
if ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
(r.pflushtyp = '1')) then
ctwrite(i) := '1';
wlrr(i) := '0';
wlock(i) := '0';
end if;
end loop;
else
v.faddr := r.faddr;
end if;
v.pflushr := not r.pflushr;
end if;
end if;
end if;
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0');
v.lrr := '0'; v.lock := '0'; v.flush2 := '1';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.bar := (others => '0');
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag;
dcrami.ptag <= ptag;
dcrami.ctx <= ctx;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.tpwrite <= ctpwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable; --vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs);
--mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;-- or mcdo.iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= (not r.asi(0));-- and (not r.asi(4));
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk ) then r <= c; end if; end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP2 = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
sn3no : if DSNOOP2 /= 2 generate
rh.hit <= (others => (others => '0'));
rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (DCREPLACE = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (DCREPLACE = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler, Konrad Eisele - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of mmu_dcache is
constant DSNOOP2 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(3,3));
constant DSNOOP4 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(4,3));
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant lram : integer range 0 to 1 := 0;
constant lramsize : integer range 1 to 64 := 1;
constant lramstart : integer range 0 to 255 := 16#00#;
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DCLOCK_BIT : integer := dsetlock;
constant M_EN : boolean := true;
constant DCREPLACE : integer range 0 to 2 := drepl;
constant DLINE_SIZE : integer := dlinesize;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory, sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag,dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : dstatetype; -- FSM
hit : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_logic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_logic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_logic;
lramrd : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
su : std_logic;
dblwdata : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_logic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr, dparerr : std_logic_vector(0 to DSETS-1);
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to MAXSETS-1);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoopset2, rdsuset : integer range 0 to DSETS-1;
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_logic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable ctx : ctxdatatype;
variable miscdata : std_logic_vector(31 downto 0);
variable mmudiagaddr : std_logic_vector(2 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuwdata : std_logic_vector(31 downto 0);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable mmuregw, su : std_logic;
variable mmuisdis : std_logic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; v.cctrlwr := '0'; v.mmctrl1wr := '0';
v.flush2 := r.flush; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
tparerr := (others => '0'); dparerr := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0'; rdsuset := 0;
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
mmudiagaddr := (others => '0'); mmuregw := '0'; mmuwdata := (others => '0');
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
ctx := (others => (others => '0')); vs.readbpx := (others => '0'); rbphit := '0';
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
if (not M_EN) or (r.mmctrl1.e = '0') then v.cache := '1'; end if;
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if DCLOCK_BIT = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if DSNOOP2 /= 0 then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;-- and not r.mmctrl1.e;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (paddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP2 = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP2 /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); --signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read;
else
maddress := dci.maddress(31 downto 0); --signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0;
snoophit := (others => '0'); snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP2 = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and (not r.flush2);
-- cache hit disabled if mmu-enabled but off or BYPASS
if (M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP) then -- or (r.mmctrl1.e = '0')
hit := '0';
end if;
validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if hitv(i) = '1' then
vset := vset or conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
--v.signed := dci.signed;
v.su := dci.msu;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
if (dsu = 1) and (dci.dsuen = '1') then
mmuwdata := dci.maddress;
else
mmuwdata := dci.edata;
end if;
mmudiagaddr := dci.maddress(CNR_U downto CNR_D);
if r.mmctrl1wr = '1' then
mmudiagaddr := r.xaddress(CNR_U downto CNR_D); -- defer match sram out
if (dci.read = '0') then
mmuwdata := dci.maddress;
mmuregw := '1';
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
v.nomds := r.nomds and not eholdn; --v.valid := dcramov.dtramout(set).valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and (M_TLB_FASTWRITE /= 0) ) then
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => rdatasel := dctx;
when ASI_MMUREGS => rdatasel := misc;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_MMUREGS =>
if (dsu = 0) or dci.dsuen = '0' then
if M_EN then
-- rdatasel := misc;
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
else
mmuregw := '1';
end if;
end if;
else
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := '0'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if M_EN then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
--if (not ((mcdo.dcs(0) = '1')
if (not ((r.cctrl.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := '1';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0'))
then
-- cache disabled if mmu-enabled but off or BYPASS
if (M_EN) then v.cache := '0'; end if;
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
end if;
else -- write access
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0';
end if;
else
-- ## mmu case > false and
--if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (dci.size /= "11") and (M_TLB_FASTWRITE /= 0)
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (M_TLB_FASTWRITE /= 0)
then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
v.dblwdata := dci.size(0) or dci.size(1); -- "11"
-- ## < mmu case
end if;
end if;
-- note: cache hit disabled if BYPASS
if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not dparerr(set)) and (not r.flush)) = '1' then
case DCREPLACE is
when rnd =>
if DCLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if DCLOCK_BIT = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (DCLOCK_BIT = 1) then
if (hit and (not dparerr(set)) and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
--v.xaddress := mmudco.data;
v.paddress := mmudco.transdata.data;
if v.wbinit = '1' then
v.wb.addr := mmudco.transdata.data;
v.req := '1';
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 1 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit and r.cache; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))) and r.cache; twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
tpwrite := twrite;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
if DSNOOP2 /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := idle;
when dblwrite => -- second part of double store cycle
v.dstate := idle; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when asi_idtag => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; mds := not r.read;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
-- fetch dblwrite data 2, does the same as state dblwrite,
-- except that init of data2 is omitted to end of translation or in wwrite
if ((r.dblwdata) = '1') and ((r.size) = "11") then
v.dblwdata := '0';
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.cctrl.dcs(0) and r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
v.req := '1'; v.stpend := '1';
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
--if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := '1';
end if;
end if;
end if;
else
-- mmudci_trans_op := '1'; -- start translation
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (v.ready or (mcdo.ready and not r.req)) = '1' then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := idle;
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
--mmudiagaddr := dci.maddress(CNR_U downto CNR_D); mmuwdata := dci.edata;
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if M_EN then
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag;
end if;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_MMUREGS =>
mmuregw := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := misc;
when others =>
end case;
end if;
-- note: mmudiagaddr is (10 downto 8) (000,001, ...)
-- read
case mmudiagaddr is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0000";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(17) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
set := 0;
rdatav(0) := miscdata;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, lram, lramsize, lramstart, 1);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = idle then
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
v.valid := vmask;
if (DSETS>1) and (DCREPLACE = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (DCREPLACE = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if mmuregw = '1' then
case mmudiagaddr is
when CNR_CTRL =>
v.mmctrl1.e := mmuwdata(MMCTRL_E);
v.mmctrl1.nf := mmuwdata(MMCTRL_NF);
v.mmctrl1.pso := mmuwdata(MMCTRL_PSO);
v.mmctrl1.tlbdis := mmuwdata(MMCTRL_TLBDIS);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := mmuwdata(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := mmuwdata(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
--if (dci.flush or flush or mcdo.dflush) = '1' then
if (dci.flush or flush ) = '1' then
v.flush := '1'; v.faddr := (others => '0'); v.pflush := pflush;
v.pflushr := '1';
v.pflushaddr := pflushaddr;
v.pflushtyp := pflushtyp;
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others=>(others => '0')); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0'); v.lrr := '0';
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP2 = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP2 /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP2 = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= idle) then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = wread) and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if M_EN then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if M_EN then
ctpwrite := (others => '1');
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if false then --
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
for i in DSETS-1 downto 0 loop
wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS);
wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS);
end loop;
if r.pflushr = '0' then
for i in DSETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := dcramov.tag(i)(TAG_HIGH downto TAG_LOW);
if ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
(r.pflushtyp = '1')) then
ctwrite(i) := '1';
wlrr(i) := '0';
wlock(i) := '0';
end if;
end loop;
else
v.faddr := r.faddr;
end if;
v.pflushr := not r.pflushr;
end if;
end if;
end if;
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0');
v.lrr := '0'; v.lock := '0'; v.flush2 := '1';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.bar := (others => '0');
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag;
dcrami.ptag <= ptag;
dcrami.ctx <= ctx;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.tpwrite <= ctpwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable; --vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs);
--mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;-- or mcdo.iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= (not r.asi(0));-- and (not r.asi(4));
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk ) then r <= c; end if; end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP2 = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
sn3no : if DSNOOP2 /= 2 generate
rh.hit <= (others => (others => '0'));
rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (DCREPLACE = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (DCREPLACE = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Instruction_ROM.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Instruction_ROM
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Instruction ROM
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.CPU_Subsystem_8_bit_pkg.ALL;
ENTITY Instruction_ROM IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
read : IN std_logic; -- ufix1
instr_out : OUT std_logic_vector(11 DOWNTO 0) -- ufix12
);
END Instruction_ROM;
ARCHITECTURE rtl OF Instruction_ROM IS
-- Signals
SIGNAL addr_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL instr_out_tmp : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL data : vector_of_unsigned12(0 TO 255); -- ufix12 [256]
SIGNAL data_next : vector_of_unsigned12(0 TO 255); -- ufix12 [256]
BEGIN
addr_unsigned <= unsigned(addr);
Instruction_ROM_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
data <= (OTHERS => to_unsigned(2#000000000000#, 12));
ELSIF enb = '1' THEN
data <= data_next;
END IF;
END IF;
END PROCESS Instruction_ROM_1_process;
Instruction_ROM_1_output : PROCESS (addr_unsigned, read, data)
VARIABLE data_temp : vector_of_unsigned12(0 TO 255);
VARIABLE add_temp : unsigned(8 DOWNTO 0);
VARIABLE sub_cast : unsigned(7 DOWNTO 0);
VARIABLE sub_cast_0 : signed(31 DOWNTO 0);
BEGIN
data_temp := data;
--MATLAB Function 'CPU_Subsystem_8_bit/Instruction ROM': '<S7>:1'
--% Instruction Memory
-- read == 1 => read from IM
-- HDL specific fimath
-- ASSEMBLED CODE from sort1.in
--'<S7>:1:21'
data_temp(0) := to_unsigned(2#100100001010#, 12);
-- LI 10
--'<S7>:1:22'
data_temp(1) := to_unsigned(2#101000000000#, 12);
-- STA 0
--'<S7>:1:23'
data_temp(2) := to_unsigned(2#100100001100#, 12);
-- LI 12
--'<S7>:1:24'
data_temp(3) := to_unsigned(2#101000000001#, 12);
-- STA 1
--'<S7>:1:25'
data_temp(4) := to_unsigned(2#100100010010#, 12);
-- LI 18
--'<S7>:1:26'
data_temp(5) := to_unsigned(2#101000001100#, 12);
-- STA 12
--'<S7>:1:27'
data_temp(6) := to_unsigned(2#100100000110#, 12);
-- LI 6
--'<S7>:1:28'
data_temp(7) := to_unsigned(2#101000001101#, 12);
-- STA 13
--'<S7>:1:29'
data_temp(8) := to_unsigned(2#100100010011#, 12);
-- LI 19
--'<S7>:1:30'
data_temp(9) := to_unsigned(2#101000001110#, 12);
-- STA 14
--'<S7>:1:31'
data_temp(10) := to_unsigned(2#100111111011#, 12);
-- LI 251
--'<S7>:1:32'
data_temp(11) := to_unsigned(2#101000001111#, 12);
-- STA 15
--'<S7>:1:33'
data_temp(12) := to_unsigned(2#100100001111#, 12);
-- LI 15
--'<S7>:1:34'
data_temp(13) := to_unsigned(2#101000010000#, 12);
-- STA 16
--'<S7>:1:35'
data_temp(14) := to_unsigned(2#100111111110#, 12);
-- LI 254
--'<S7>:1:36'
data_temp(15) := to_unsigned(2#101000010001#, 12);
-- STA 17
--'<S7>:1:37'
data_temp(16) := to_unsigned(2#100100000010#, 12);
-- LI 2
--'<S7>:1:38'
data_temp(17) := to_unsigned(2#101000010010#, 12);
-- STA 18
--'<S7>:1:39'
data_temp(18) := to_unsigned(2#100100001011#, 12);
-- LI 11
--'<S7>:1:40'
data_temp(19) := to_unsigned(2#101000010011#, 12);
-- STA 19
--'<S7>:1:41'
data_temp(20) := to_unsigned(2#100100010100#, 12);
-- LI 20
--'<S7>:1:42'
data_temp(21) := to_unsigned(2#101000010100#, 12);
-- STA 20
--'<S7>:1:43'
data_temp(22) := to_unsigned(2#100100001010#, 12);
-- LI 10
--'<S7>:1:44'
data_temp(23) := to_unsigned(2#101000010101#, 12);
-- STA 21
--'<S7>:1:45'
data_temp(24) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:46'
data_temp(25) := to_unsigned(2#101000000010#, 12);
-- STA 2
--'<S7>:1:47'
data_temp(26) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:48'
data_temp(27) := to_unsigned(2#101000000011#, 12);
-- STA 3
--'<S7>:1:49'
data_temp(28) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:50'
data_temp(29) := to_unsigned(2#101000000100#, 12);
-- STA 4
--'<S7>:1:51'
data_temp(30) := to_unsigned(2#000000000010#, 12);
-- LDA 2
--'<S7>:1:52'
data_temp(31) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:53'
data_temp(32) := to_unsigned(2#011000000100#, 12);
-- SUB 4
--'<S7>:1:54'
data_temp(33) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:55'
data_temp(34) := to_unsigned(2#010000000001#, 12);
-- ADD 1
--'<S7>:1:56'
data_temp(35) := to_unsigned(2#101000000101#, 12);
-- STA 5
--'<S7>:1:57'
data_temp(36) := to_unsigned(2#000100000101#, 12);
-- LDAI 5
--'<S7>:1:58'
data_temp(37) := to_unsigned(2#101000000110#, 12);
-- STA 6
--'<S7>:1:59'
data_temp(38) := to_unsigned(2#000000000010#, 12);
-- LDA 2
--'<S7>:1:60'
data_temp(39) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:61'
data_temp(40) := to_unsigned(2#010000000001#, 12);
-- ADD 1
--'<S7>:1:62'
data_temp(41) := to_unsigned(2#101000000111#, 12);
-- STA 7
--'<S7>:1:63'
data_temp(42) := to_unsigned(2#000100000111#, 12);
-- LDAI 7
--'<S7>:1:64'
data_temp(43) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:65'
data_temp(44) := to_unsigned(2#011000000110#, 12);
-- SUB 6
--'<S7>:1:66'
data_temp(45) := to_unsigned(2#110100000010#, 12);
-- BRA_N 2
--'<S7>:1:67'
data_temp(46) := to_unsigned(2#100000000111#, 12);
-- JMP 7
--'<S7>:1:68'
data_temp(47) := to_unsigned(2#100100000000#, 12);
-- LI 0
--'<S7>:1:69'
data_temp(48) := to_unsigned(2#101000000011#, 12);
-- STA 3
--'<S7>:1:70'
data_temp(49) := to_unsigned(2#000100000111#, 12);
-- LDAI 7
--'<S7>:1:71'
data_temp(50) := to_unsigned(2#101100000101#, 12);
-- STAI 5
--'<S7>:1:72'
data_temp(51) := to_unsigned(2#000000000110#, 12);
-- LDA 6
--'<S7>:1:73'
data_temp(52) := to_unsigned(2#101100000111#, 12);
-- STAI 7
--'<S7>:1:74'
data_temp(53) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:75'
data_temp(54) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:76'
data_temp(55) := to_unsigned(2#010000000010#, 12);
-- ADD 2
--'<S7>:1:77'
data_temp(56) := to_unsigned(2#101000000010#, 12);
-- STA 2
--'<S7>:1:78'
data_temp(57) := to_unsigned(2#000000000000#, 12);
-- LDA 0
--'<S7>:1:79'
data_temp(58) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:80'
data_temp(59) := to_unsigned(2#011000000010#, 12);
-- SUB 2
--'<S7>:1:81'
data_temp(60) := to_unsigned(2#111100000010#, 12);
-- BRA_Z 2
--'<S7>:1:82'
data_temp(61) := to_unsigned(2#100011011111#, 12);
-- JMP -33
--'<S7>:1:83'
data_temp(62) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:84'
data_temp(63) := to_unsigned(2#101000000100#, 12);
-- STA 4
--'<S7>:1:85'
data_temp(64) := to_unsigned(2#000000000011#, 12);
-- LDA 3
--'<S7>:1:86'
data_temp(65) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:87'
data_temp(66) := to_unsigned(2#011000000100#, 12);
-- SUB 4
--'<S7>:1:88'
data_temp(67) := to_unsigned(2#111100000010#, 12);
-- BRA_Z 2
--'<S7>:1:89'
data_temp(68) := to_unsigned(2#100011010100#, 12);
-- JMP -44
--'<S7>:1:90'
data_temp(69) := to_unsigned(2#100100000000#, 12);
-- LI 0
--'<S7>:1:91'
data_temp(70) := to_unsigned(2#101000000010#, 12);
-- STA 2
--'<S7>:1:92'
data_temp(71) := to_unsigned(2#000100000001#, 12);
-- LDAI 1
--'<S7>:1:93'
data_temp(72) := to_unsigned(2#101011111111#, 12);
-- STA 255
--'<S7>:1:94'
data_temp(73) := to_unsigned(2#111001110000#, 12);
-- PRINT
--'<S7>:1:95'
data_temp(74) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:96'
data_temp(75) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:97'
data_temp(76) := to_unsigned(2#010000000001#, 12);
-- ADD 1
--'<S7>:1:98'
data_temp(77) := to_unsigned(2#101000000001#, 12);
-- STA 1
--'<S7>:1:99'
data_temp(78) := to_unsigned(2#100100000001#, 12);
-- LI 1
--'<S7>:1:100'
data_temp(79) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:101'
data_temp(80) := to_unsigned(2#010000000010#, 12);
-- ADD 2
--'<S7>:1:102'
data_temp(81) := to_unsigned(2#101000000010#, 12);
-- STA 2
--'<S7>:1:103'
data_temp(82) := to_unsigned(2#000000000000#, 12);
-- LDA 0
--'<S7>:1:104'
data_temp(83) := to_unsigned(2#111001111000#, 12);
-- CLC
--'<S7>:1:105'
data_temp(84) := to_unsigned(2#011000000010#, 12);
-- SUB 2
--'<S7>:1:106'
data_temp(85) := to_unsigned(2#111100000010#, 12);
-- BRA_Z 2
--'<S7>:1:107'
data_temp(86) := to_unsigned(2#100011110001#, 12);
-- JMP -15
--'<S7>:1:108'
data_temp(87) := to_unsigned(2#111001000000#, 12);
-- HLT
-- Loading from memory
IF read = '1' THEN
--'<S7>:1:113'
add_temp := resize(addr_unsigned, 9) + 1;
IF add_temp(8) /= '0' THEN
sub_cast := "11111111";
ELSE
sub_cast := add_temp(7 DOWNTO 0);
END IF;
sub_cast_0 := signed(resize(sub_cast, 32));
instr_out_tmp <= data_temp(to_integer(sub_cast_0 - 1));
ELSE
--'<S7>:1:115'
instr_out_tmp <= to_unsigned(2#000000000000#, 12);
END IF;
data_next <= data_temp;
END PROCESS Instruction_ROM_1_output;
instr_out <= std_logic_vector(instr_out_tmp);
END rtl;
|
-- ======================================================================
-- CBC-MAC-DES testbench
-- Copyright (C) 2015 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_cbcmac_des is
end entity tb_cbcmac_des;
architecture sim of tb_cbcmac_des is
type t_array is array (natural range <>) of std_logic_vector(0 to 63);
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_key : std_logic_vector(0 to 63) := (others => '0');
signal s_datain : std_logic_vector(0 to 63) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptout : std_logic;
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic;
signal s_acceptin : std_logic;
component cbcmac_des is
port (
reset_i : in std_logic;
clk_i : in std_logic;
start_i : in std_logic;
key_i : in std_logic_vector(0 to 63);
data_i : in std_logic_vector(0 to 63);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63);
valid_o : out std_logic;
accept_i : in std_logic
);
end component cbcmac_des;
-- key, plain & crypto stimuli values
-- taken from NIST website:
-- http://csrc.nist.gov/publications/fips/fips113/fips113.html
constant C_KEY : std_logic_vector(0 to 63) := x"0123456789abcdef";
constant C_PLAIN : t_array := (
x"3736353433323120", x"4e6f772069732074",
x"68652074696d6520", x"666f722000000000");
constant C_CRYPT : t_array := (
x"21fb193693a16c28", x"6c463f0cb7167a6f",
x"956ee891e889d91e", x"f1d30f6849312ca4");
begin
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
StimuliP : process is
begin
s_start <= '0';
s_key <= (others => '0');
s_datain <= (others => '0');
s_validin <= '0';
wait until s_reset = '1';
s_start <= '1';
for i in C_PLAIN'range loop
wait until rising_edge(s_clk);
s_validin <= '1';
s_key <= C_KEY;
s_datain <= C_PLAIN(i);
wait until rising_edge(s_clk) and s_acceptout = '1';
s_start <= '0';
s_validin <= '0';
end loop;
wait;
end process StimuliP;
CheckerP : process is
begin
s_acceptin <= '0';
wait until s_reset = '1';
for i in C_CRYPT'range loop
wait until rising_edge(s_clk);
s_acceptin <= '1';
wait until rising_edge(s_clk) and s_validout = '1';
assert s_dataout = C_CRYPT(i)
report "Encryption error"
severity failure;
s_acceptin <= '0';
end loop;
report "CBCMAC test successful :)";
wait;
end process CheckerP;
i_cbcmac_des : cbcmac_des
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptout,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptin
);
end architecture sim;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
--
-- 4th July 2012 - ** SPECIAL VERSION **
--
-- Only use this version if problems are encountered during MAP and all
-- other workarounds described in the 'READ_ME_FIRST.txt' file have been
-- considered.
--
-- In this version all the Slice packing attributes have been commented out
-- and it should be expected that the implementation will be larger than the
-- 26-30 Slices normally achieved. Lower performance may also result.
--
-- Version 1.3 - 21st May 2014.
-- Addition of WebTalk information.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
-- attribute hblknm : string;
-- attribute hblknm of reset_lut : label is "kcpsm6_control";
-- attribute hblknm of run_flop : label is "kcpsm6_control";
-- attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state_lut : label is "kcpsm6_control";
-- attribute hblknm of t_state1_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state2_flop : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
-- attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
-- attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
-- attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
-- attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
-- attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
-- attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
-- attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
-- attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
-- attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
-- attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
-- attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
-- attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_flop : label is "kcpsm6_stack1";
-- attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
-- attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
-- attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
-- attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
-- attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
-- attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
-- attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
--
-- 4th July 2012 - ** SPECIAL VERSION **
--
-- Only use this version if problems are encountered during MAP and all
-- other workarounds described in the 'READ_ME_FIRST.txt' file have been
-- considered.
--
-- In this version all the Slice packing attributes have been commented out
-- and it should be expected that the implementation will be larger than the
-- 26-30 Slices normally achieved. Lower performance may also result.
--
-- Version 1.3 - 21st May 2014.
-- Addition of WebTalk information.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
-- attribute hblknm : string;
-- attribute hblknm of reset_lut : label is "kcpsm6_control";
-- attribute hblknm of run_flop : label is "kcpsm6_control";
-- attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state_lut : label is "kcpsm6_control";
-- attribute hblknm of t_state1_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state2_flop : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
-- attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
-- attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
-- attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
-- attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
-- attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
-- attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
-- attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
-- attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
-- attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
-- attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
-- attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
-- attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_flop : label is "kcpsm6_stack1";
-- attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
-- attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
-- attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
-- attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
-- attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
-- attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
-- attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_mmu_data_types_pkg.all;
use work.cpu_types_pkg.all;
package cpu_mmu_data_pass_pkg is
type cpu_mmu_data_pass_ctrl_in_type is record
request : std_ulogic;
mmuen : std_ulogic;
end record;
type cpu_mmu_data_pass_ctrl_out_type is record
ready : std_ulogic;
result : cpu_mmu_data_result_code_type;
end record;
type cpu_mmu_data_pass_dp_in_type is record
vpn : cpu_vpn_type;
end record;
type cpu_mmu_data_pass_dp_out_type is record
ppn : cpu_ppn_type;
end record;
end package;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block4
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block4 IS
-- Signals
SIGNAL dout_10_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_11_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_11_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_10_re_signed <= signed(dout_10_re);
dout_10_im_signed <= signed(dout_10_im);
dout_12_re_signed <= signed(dout_12_re);
dout_12_im_signed <= signed(dout_12_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_10_re_signed, dout_10_im_signed,
dout_12_re_signed, dout_12_im_signed, dout_1_vld, rotate_11)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_11 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_10_re_signed, 17);
add_cast_2 := resize(dout_12_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_10_re_signed, 17);
sub_cast_2 := resize(dout_12_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_10_im_signed, 17);
add_cast_6 := resize(dout_12_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_10_im_signed, 17);
sub_cast_6 := resize(dout_12_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_10_re_signed, 17);
add_cast_0 := resize(dout_12_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_10_re_signed, 17);
sub_cast_0 := resize(dout_12_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_10_im_signed, 17);
add_cast_4 := resize(dout_12_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_10_im_signed, 17);
sub_cast_4 := resize(dout_12_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_11_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_11_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_12_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_12_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re_1 <= std_logic_vector(dout_12_re_tmp);
dout_12_im_1 <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_dma.vhd
-- |- axi_dma_pkg.vhd
-- |- axi_dma_rst_module.vhd
-- |- axi_dma_reg_module.vhd
-- | |- axi_dma_lite_if.vhd
-- | |- axi_dma_register.vhd (mm2s)
-- | |- axi_dma_register.vhd (s2mm)
-- |- axi_dma_mm2s_mngr.vhd
-- | |- axi_dma_mm2s_sg_if.vhd
-- | |- axi_dma_mm2s_sm.vhd
-- | |- axi_dma_mm2s_cmdsts_if.vhd
-- | |- axi_dma_mm2s_cntrl_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- | |- axi_dma_strm_rst.vhd
-- |- axi_dma_s2mm_mngr.vhd
-- | |- axi_dma_s2mm_sg_if.vhd
-- | |- axi_dma_s2mm_sm.vhd
-- | |- axi_dma_s2mm_cmdsts_if.vhd
-- | |- axi_dma_s2mm_sts_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- |- axi_datamover_v2_00_a.axi_data_mover.vhd (FULL)
-- |- axi_dma_strm_rst.vhd
-- |- axi_dma_skid_buf.vhd
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 9/03/10 v2_00_a
-- ^^^^^^
-- - Updated libraries to v2_00_a
-- ~~~~~~
-- GAB 9/30/10 v2_00_a
-- ^^^^^^
-- CR576999 - Modified to assert back to back read/write address requests, i.e.
-- requests where arvalid or awvalid do not de-assert between requests
-- and back to back write data valid.
-- ~~~~~~
-- GAB 10/15/10 v3_00_a
-- ^^^^^^
-- - Updated libraries to v3_00_a
-- - Added asynchronous mode
-- ~~~~~~
-- GAB 2/15/11 v4_00_a
-- ^^^^^^
-- Updated libraries to v4_00_a
-- ~~~~~~
-- GAB 4/12/11 v4_00_a
-- ^^^^^^
-- CR605883 (CDC) need to provide pure register output to synchronizers
-- ~~~~~~
-- GAB 4/14/11 v4_00_a
-- ^^^^^^
-- CR606122 - Align awvalid_re pulse and wvalid_re pulse for proper async writes
-- ~~~~~~
-- GAB 4/14/11 v4_00_a
-- ^^^^^^
-- CR607165 - asynch operation allowed acceptance of 2nd read address prior
-- to completion of the previous reads. CR Fixed.
-- ~~~~~~
-- GAB 6/21/11 v5_00_a
-- ^^^^^^
-- Updated to axi_dma
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_RSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Right Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5;
ARCHITECTURE rtl OF dp_rsft64x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
|
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram for openMAC Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--!
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamOpenmac is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8,
read_during_write_mode_mixed_ports => "OLD_DATA"
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
|
-------------------------------------------------------------------------------
--! @file nf_top_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief NanoFIP FPGA package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of nf_top_pkg
--! @details
--! This provides types and constants for the NanoFIP FPGA.
package nf_top_pkg is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
--! NanoFIP FPGA version number
constant NF_VERSION_c : std_ulogic_vector(3 downto 0) := "0001";
end package nf_top_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
entity ddr4_dimm_u200_wrapper is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(17 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(17 downto 0)
);
end;
architecture arch of ddr4_dimm_u200_wrapper is
component ddr4_dimm_u200 is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(17 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(17 downto 0)
);
end component;
begin
I1 : ddr4_dimm_u200 port map (
sys_reset ,
c0_ddr4_act_n ,
c0_ddr4_adr ,
c0_ddr4_ba ,
c0_ddr4_bg ,
c0_ddr4_cke ,
c0_ddr4_odt ,
c0_ddr4_cs_n ,
c0_ddr4_ck_t ,
c0_ddr4_ck_c ,
c0_ddr4_reset_n ,
c0_ddr4_dq ,
c0_ddr4_dqs_t ,
c0_ddr4_dqs_c );
end;
|
entity tb_sram03 is
end tb_sram03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram03 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram03
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"03";
wen <= '1';
pulse;
wdat <= x"41";
pulse;
assert rdat = x"03" severity failure;
addr <= "0100";
wdat <= x"07";
wait for 1 ns;
pulse;
pulse;
assert rdat = x"07" severity failure;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"41" severity failure;
wait;
end process;
end behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk is
generic ( fc : real := 1.0e6; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequencies
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk;
----------------------------------------------------------------
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
break on d_in;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk is
generic ( fc : real := 1.0e6; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequencies
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk;
----------------------------------------------------------------
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
break on d_in;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk is
generic ( fc : real := 1.0e6; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequencies
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk;
----------------------------------------------------------------
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
break on d_in;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity accumulator_reg is
port ( clk : in std_ulogic;
clr : in std_ulogic;
d : in std_ulogic_vector(21 downto 0);
q : out std_ulogic_vector(21 downto 0) );
end entity accumulator_reg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity accumulator_reg is
port ( clk : in std_ulogic;
clr : in std_ulogic;
d : in std_ulogic_vector(21 downto 0);
q : out std_ulogic_vector(21 downto 0) );
end entity accumulator_reg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity accumulator_reg is
port ( clk : in std_ulogic;
clr : in std_ulogic;
d : in std_ulogic_vector(21 downto 0);
q : out std_ulogic_vector(21 downto 0) );
end entity accumulator_reg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7410_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
i2c_addr_i : in std_logic_vector(1 downto 0);
int_o : out std_logic;
ct_o : out std_logic;
temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic;
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_e : std_logic; -- directly from inside I2C_FSM
signal CpuIntr_e : std_logic; -- directly from inside SPI_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- SlowADT7410 component ports
signal I2C_SDA_i : std_logic;
signal I2C_SDA_o : std_logic;
signal I2C_SDA_s : std_logic;
signal I2C_SCL_o : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
signal TempBin_s : std_logic_vector(15 downto 0);
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2C_SCL_o,
I2CSDA_i => I2C_SDA_i,
I2CSDA_o => I2C_SDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
TempBin_s <= std_logic_vector(to_unsigned(integer(Temp_s*128.0),16));
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
I2CFSM_Done_d <= I2CFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
I2C_SDA_s <= 'H'; -- weak 1 -> simulate pull-up
I2C_SDA_s <= '0' when I2C_SDA_o = '0' else 'Z';
I2C_SDA_i <= to_X01(I2C_SDA_s) after 0.2 us;
adt7410_1: adt7410_model
port map (
scl_i => I2C_SCL_o,
sda_io => I2C_SDA_s,
i2c_addr_i => "00",
INT_o => INT_n_s,
CT_o => CT_n_s,
temp_i => TempBin_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
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-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
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-- ** expressly prohibited. **
-- ** **
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-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
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-- ** indirectly, the original core source). **
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-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v3_00_a.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v3_00_a.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-- file: my_dcm_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity my_dcm_tb is
end my_dcm_tb;
architecture test of my_dcm_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component my_dcm_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : my_dcm_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_shiftreg is end;
architecture test_shiftreg of test_shiftreg is
component shift_reg
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
control:in std_logic_vector(1 downto 0);
Clear :in std_logic; clock : in std_logic;
Output : out std_logic_vector((width - 1) downto 0));
end component;
for all : shift_reg use entity work.shift_reg(behavior);
signal INPUT : std_logic_vector(3 downto 0);
signal control : std_logic_vector(1 downto 0);
signal CLEAR : std_logic ;
SIGNAL clock : std_logic;
signal OUTPUT : std_logic_vector(3 downto 0);
begin
Latch1 : shift_reg generic map(4)
port map( input, control, clear, clock , output);
test_process : process
begin
----------- check clear ----------------
CLEAR <= '1';
control <= "01" ;
clock <= '1';
control <= "01";
input <= "1101";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
CLEAR <= '1';
control <= "01" ;
clock <= '1';
control <= "01";
input <= "0111";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
----------- check Control ---------------
CLEAR <= '0';
control <= "01";
clock <= '1';
input <= "0100";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "10";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "01";
wait for 10 ns;
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "11";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
CLEAR <= '1';
control <= "11";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
wait;
end process test_process ;
end test_shiftreg;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
|
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end RAMDataReg;
architecture RTL of RAMDataReg is
begin
RAMDataReg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RAMDataOut <= (others => '0');
elsif cp2='1' and cp2'event then -- Clock
if cpuwait='0' then -- Clock enable
RAMDataOut <= RAMDataIn;
end if;
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end RAMDataReg;
architecture RTL of RAMDataReg is
begin
RAMDataReg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RAMDataOut <= (others => '0');
elsif cp2='1' and cp2'event then -- Clock
if cpuwait='0' then -- Clock enable
RAMDataOut <= RAMDataIn;
end if;
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end RAMDataReg;
architecture RTL of RAMDataReg is
begin
RAMDataReg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RAMDataOut <= (others => '0');
elsif cp2='1' and cp2'event then -- Clock
if cpuwait='0' then -- Clock enable
RAMDataOut <= RAMDataIn;
end if;
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end RAMDataReg;
architecture RTL of RAMDataReg is
begin
RAMDataReg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RAMDataOut <= (others => '0');
elsif cp2='1' and cp2'event then -- Clock
if cpuwait='0' then -- Clock enable
RAMDataOut <= RAMDataIn;
end if;
end if;
end process;
end RTL;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "InputSwitchingMatrix"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.tbfuncs.all;
use work.trfsmparts.all;
-------------------------------------------------------------------------------
entity tb_InputSwitchingMatrix is
end tb_InputSwitchingMatrix;
-------------------------------------------------------------------------------
architecture behavior of tb_InputSwitchingMatrix is
constant InputWidth : integer := 10;
constant OutputWidth : integer := 4;
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n : std_logic;
signal Input : std_logic_vector(InputWidth-1 downto 0);
signal Output : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode : std_logic;
signal CfgClk : std_logic;
signal CfgShift : std_logic;
signal CfgDataIn : std_logic;
signal CfgDataOut : std_logic;
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
procedure Configure (
constant ConfigBitStream : in std_logic_vector;
signal CfgMode : out std_logic;
signal CfgClk : out std_logic;
signal CfgShift : out std_logic;
signal CfgDataIn : out std_logic;
signal CfgDataOut : in std_logic
) is
begin -- Configure
CfgMode <= '1';
CfgShift <= '1';
for i in 0 to ConfigBitStream'length-1 loop
CfgDataIn <= ConfigBitStream(i);
wait for SetupNextInputDelay;
CfgClk <= '1';
wait for CfgClkHalfPeriode;
CfgClk <= '0';
wait for CfgClkHalfPeriode-SetupNextInputDelay;
end loop; -- i
CfgMode <= '0';
CfgShift <= '0';
end Configure;
procedure CheckISM (
constant Config : in std_logic_vector(InputWidth-1 downto 0);
signal Input : out std_logic_vector(InputWidth-1 downto 0);
signal Output : in std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode : out std_logic;
signal CfgClk : out std_logic;
signal CfgShift : out std_logic;
signal CfgDataIn : out std_logic;
signal CfgDataOut : in std_logic
) is
variable Input_v : std_logic_vector(InputWidth -1 downto 0);
variable Output_v : std_logic_vector(OutputWidth-1 downto 0);
variable OutPos : integer;
variable Errors : integer;
begin -- CheckISM
Configure(Config,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
Errors := 0;
for i in 0 to 2**InputWidth-1 loop
Input_v := conv_std_logic_vector(i,InputWidth);
-- construct right value of output
Output_v := (others => '0');
OutPos := OutputWidth-1;
for Pos in InputWidth-1 downto 0 loop
if (Pos < OutputWidth-1) and (Pos < OutPos) then
OutPos := Pos;
end if;
if Config(Pos) = '1' then
Output_v(OutPos) := Input_v(Pos);
OutPos := OutPos - 1;
end if;
end loop; -- Pos
-- setup input
Input <= Input_v;
wait for CheckOutputDelay;
-- check output
if Output /= Output_v then
assert false
report "Wrong Output " & Vector2String(Output) & " for Input " & Vector2String(Input_v) & ", should be " & Vector2String(Output_v)
severity error;
Errors := Errors + 1;
end if;
wait for SetupNextInputDelay;
end loop; -- i
assert false report "ISM with config pattern " & Vector2String(Config) & " had " & integer'image(Errors) & " errors" severity note;
end CheckISM;
begin -- behavior
InputSwitchingMatrix_1: InputSwitchingMatrix
generic map (
InputWidth => InputWidth,
OutputWidth => OutputWidth)
port map (
Reset_n_i => Reset_n,
Input_i => Input,
Output_o => Output,
CfgMode_i => CfgMode,
CfgClk_i => CfgClk,
CfgShift_i => CfgShift,
CfgDataIn_i => CfgDataIn,
CfgDataOut_o => CfgDataOut);
TestProc: process
begin -- process TestProc
Input <= (others => '0');
CfgMode <= '0';
CfgClk <= '0';
CfgShift <= '0';
CfgDataIn <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n <= '0';
wait for 1 us;
Reset_n <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
CheckISM("1111000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000001111",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1010101000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0001010101",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1100000011",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0001111000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1000000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1100000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1110000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0100000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0010000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0001000000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000100000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000010000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000001000",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000000100",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000000010",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000000001",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000000011",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("0000000111",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1000000001",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
CheckISM("1000100010",Input,Output,CfgMode,CfgClk,CfgShift,CfgDataIn,CfgDataOut);
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process TestProc;
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc271.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p06n01i00271ent IS
END c03s01b03x00p06n01i00271ent;
ARCHITECTURE c03s01b03x00p06n01i00271arch OF c03s01b03x00p06n01i00271ent IS
type GLORIA is range 1 to 6
units
PRIM;
SEC1 = 6 PRIM;
SEC2 = 36 SEC1; -- Failure_here
-- ERROR - SEMANTICS ERROR: Position Number of sec2 exceeds
-- range of physical type
end units;
BEGIN
TESTING: PROCESS
variable temp : GLORIA := 10 PRIM;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p06n01i00271 - Position number exceeds range of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p06n01i00271arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc271.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p06n01i00271ent IS
END c03s01b03x00p06n01i00271ent;
ARCHITECTURE c03s01b03x00p06n01i00271arch OF c03s01b03x00p06n01i00271ent IS
type GLORIA is range 1 to 6
units
PRIM;
SEC1 = 6 PRIM;
SEC2 = 36 SEC1; -- Failure_here
-- ERROR - SEMANTICS ERROR: Position Number of sec2 exceeds
-- range of physical type
end units;
BEGIN
TESTING: PROCESS
variable temp : GLORIA := 10 PRIM;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p06n01i00271 - Position number exceeds range of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p06n01i00271arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc271.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p06n01i00271ent IS
END c03s01b03x00p06n01i00271ent;
ARCHITECTURE c03s01b03x00p06n01i00271arch OF c03s01b03x00p06n01i00271ent IS
type GLORIA is range 1 to 6
units
PRIM;
SEC1 = 6 PRIM;
SEC2 = 36 SEC1; -- Failure_here
-- ERROR - SEMANTICS ERROR: Position Number of sec2 exceeds
-- range of physical type
end units;
BEGIN
TESTING: PROCESS
variable temp : GLORIA := 10 PRIM;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p06n01i00271 - Position number exceeds range of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p06n01i00271arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
port
(
alu_input1: in std_logic_vector(15 downto 0);
alu_input2: in std_logic_vector(15 downto 0);
alu_output: out std_logic_vector(15 downto 0);
alu_operator: in std_logic_vector(2 downto 0)
);
end alu;
architecture Behavioral of alu is
begin
process(alu_operator, alu_input1, alu_input2)
variable a :std_logic_vector(15 downto 0);
begin
case alu_operator is
when "000" =>
alu_output <= alu_input1 + alu_input2;
when "001" =>
alu_output <= alu_input1 - alu_input2;
when "010" =>
alu_output <= alu_input1 and alu_input2;
when "011" =>
alu_output <= alu_input1 or alu_input2;
when "100" =>
a := alu_input1 xor alu_input2;
if(a="0000000000000000")then
alu_output<="0000000000000000";
else
alu_output<="0000000000000001";
end if;
when "101" =>
alu_output <= to_stdlogicvector(to_bitvector(alu_input1) sll conv_integer(alu_input2));
when "110" =>
alu_output <= to_stdlogicvector(to_bitvector(alu_input1) sra conv_integer(alu_input2));
when others =>
alu_output <= "0000000000000000";
end case;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SWandHW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SWandHW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SWandHW_standalone_axi_gpio_0_0_arch OF design_SWandHW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SWandHW_standalone_axi_gpio_0_0_arch;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_send_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_data_send_fifo_top;
architecture xilinx of pcie_data_send_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_send_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_data_send_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
-- All Rights Reserved.
--
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Table driven, cycle exact 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture rtl of cpu_65xx is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processNmi : std_logic := '0';
signal processIrq : std_logic := '0';
signal processInt : std_logic := '0';
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal so_reg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInE : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- E = Accu | 0xEE (for ANE, LXA)
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInE : unsigned(0 to 7) := "01000000";
constant aluInEXT : unsigned(0 to 7) := "01100100";
constant aluInET : unsigned(0 to 7) := "01000100";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInXH : unsigned(0 to 7) := "00100010";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInYH : unsigned(0 to 7) := "00010010";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInAX : unsigned(0 to 7) := "10100000";
constant aluInAXH : unsigned(0 to 7) := "10100010";
constant aluInAT : unsigned(0 to 7) := "10000100";
constant aluInXT : unsigned(0 to 7) := "00100100";
constant aluInST : unsigned(0 to 7) := "00001100";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
-- 1100
-- 1101
-- 1110
constant aluModeAnc : aluMode1 := "1111";
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeArr : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---";
constant aluSre : aluMode := aluModeLsr & aluModeEor & "---";
constant aluRra : aluMode := aluModeRor & aluModeAdc & "---";
constant aluRla : aluMode := aluModeRol & aluModeAnd & "---";
constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100";
constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---";
constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---";
constant aluArr : aluMode := aluModeRor & aluModeArr & "---";
constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x)
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu
"1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM ***
"1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
"0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x)
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM ***
"0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
"0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
"0000" & "000000" & writeAbsY & aluInAX & aluInp, -- 9F iAHX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x)
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"1100" & "100010" & immediate & aluInET & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM ***
"1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
"0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM ***
"0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied
"0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
"1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc)
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal Creg: std_logic; -- Carry
signal Zreg: std_logic; -- Zero flag
signal Ireg: std_logic; -- Interrupt flag
signal Dreg: std_logic; -- Decimal mode
signal Vreg: std_logic; -- Overflow
signal Nreg: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Pipeline registers
signal aluInputReg : unsigned(7 downto 0);
signal aluCmpInputReg : unsigned(7 downto 0);
signal aluRmwReg : unsigned(7 downto 0);
signal aluNineReg : unsigned(7 downto 0);
signal aluCReg : std_logic;
signal aluZReg : std_logic;
signal aluVReg : std_logic;
signal aluNReg : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInE) = '1' then
temp := temp and (A or X"EE");
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
if rising_edge(clk) then
aluInputReg <= temp;
end if;
aluInput <= temp;
if pipelineAluMux then
aluInput <= aluInputReg;
end if;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
if rising_edge(clk) then
aluCmpInputReg <= temp;
end if;
aluCmpInput <= temp;
if pipelineAluMux then
aluCmpInput <= aluCmpInputReg;
end if;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
varV := aluInput(6); -- Default for BIT / PLP / RTI
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp =>
rmwBits := Creg & aluInput;
when aluModeP =>
rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
when aluModeInc =>
rmwBits := Creg & (aluInput + 1);
when aluModeDec =>
rmwBits := Creg & (aluInput - 1);
when aluModeAsl =>
rmwBits := aluInput & "0";
when aluModeFlg =>
rmwBits := aluInput(0) & aluInput;
when aluModeLsr =>
rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol =>
rmwBits := aluInput & Creg;
when aluModeRoR =>
rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
when aluModeAnc =>
rmwBits := (aluInput(7) and A(7)) & aluInput;
when others =>
rmwBits := Creg & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp =>
ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd =>
ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor =>
ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra =>
ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when others =>
ninebits := rmwBits;
end case;
if (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeFlg) then
varZ := rmwBits(1);
elsif to_01(ninebits(7 downto 0)) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if Dreg = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
if (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeBit)
or (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
if to_01(opcInfo(aluMode2From to aluMode2To)) = aluModeArr then
varC := aluInput(7);
varV := aluInput(7) xor aluInput(6);
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if Dreg = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if Dreg = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when aluModeArr =>
if Dreg = '1' then
if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
end if;
if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
else
varC := '0';
end if;
end if;
when others =>
null;
end case;
if rising_edge(clk) then
aluRmwReg <= rmwBits(7 downto 0);
aluNineReg <= ninebits(7 downto 0);
aluCReg <= varC;
aluZReg <= varZ;
aluVReg <= varV;
aluNReg <= varN;
end if;
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
if pipelineAluOut then
aluRmwOut <= aluRmwReg;
aluRegisterOut <= aluNineReg;
aluC <= aluCReg;
aluZ <= aluZReg;
aluV <= aluVReg;
aluN <= aluNReg;
end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') then -- and (halt = '0') then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
if theCpuCycle = cycleStack4 -- MWW
or reset = '1' then
nmiReg <= '1';
end if;
if halt = '0' then
if theCpuCycle /= cycleBranchTaken then
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processNmi <= not (nmiReg or opcInfo(opcIRQ));
processIrq <= not (irqReg or opcInfo(opcIRQ));
end if;
end if;
end if;
processInt <= processNmi or (processIrq and (not Ireg));
end if;
end process;
calcNextOpcode: process(clk, d, reset, processInt)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := d;
if reset = '1' then
myNextOpcode := X"4C";
elsif processInt = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(to_01(nextOpcode, '0')));
process(clk)
begin
if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
end if;
end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
if (reset = '1') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
if pipelineOpcode then
opcInfo <= nextOpcInfoReg;
end if;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processInt = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, halt, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if (enable = '1') and (halt = '0') then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
debugOpcode <= theOpcode;
process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '1' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
nextCpuCycle <= cycle2;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
-- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1'
and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
-- Page boundary crossing during branch.
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
-- Page boundary crossing while indexed addressing.
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1'
or opcInfo(indexY) = '1' then
-- 6510 needs extra cycle for indexed addressing
-- combined with RMW indexing
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0'
and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0'
or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
-- Insert extra cycle
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
case theCpuCycle is
when cycle2 =>
T <= d;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
-- Read from stack
T <= d;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= d;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
Creg <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Zreg <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
Ireg <= aluInput(2);
end if;
end if;
-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
if (theOpcode = X"58") then
Ireg <= '0';
end if;
if (theOpcode = X"78") then
Ireg <= '1';
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
Dreg <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
Vreg <= aluV;
end if;
end if;
if so_reg = '1' and so_n = '0' then
Vreg <= '1';
end if;
so_reg <= so_n;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
Nreg <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if (enable = '1') and (halt = '0') then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1')
or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
calcDo: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
doReg <= aluRmwOut;
if opcInfo(opcInH) = '1' then
-- For illegal opcodes SHA, SHX, SHY, SHS
doReg <= aluRmwOut and myAddrIncrH;
end if;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1'
and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
-- q <= T; -- Read-modify-write write old value first.
doReg <= d; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
q <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
theWe <= '0';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0'
and ((opcInfo(opcStackAddr) = '0')
or (opcInfo(opcStackData) = '1')) then
theWe <= '1';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '1';
end if;
when cycleRmw =>
theWe <= '1';
when cycleWrite =>
theWe <= '1';
when others =>
null;
end case;
if reset = '1' then
theWe <= '0';
end if;
end if;
end if;
end process;
we <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
debugPc <= PC;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when opcodeFetch =>
if processInt = '1' then
nextAddr <= nextAddrHold;
end if;
when cycle2 =>
if opcInfo(opcStackAddr) = '1'
or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '1' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') then
halt_dly <= halt;
end if;
if (enable = '1') and (halt = '0') then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
-- when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= d & T;
when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
when nextAddrZeroPage => myAddr <= "00000000" & d;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
if (enable = '1') and (halt_dly = '0') then
case nextAddr is
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
else myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
debugA <= A;
debugX <= X;
debugY <= Y;
debugS <= S;
debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddrphy is
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc2v : if tech = virtex2 generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc3se : if tech = spartan3e generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddr2phy is
begin
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex5_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk, tech => tech
)
port map (
rst, clk, clkref200, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddrphy is
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc2v : if tech = virtex2 generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc3se : if tech = spartan3e generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddr2phy is
begin
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex5_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk, tech => tech
)
port map (
rst, clk, clkref200, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
end generate;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_project2 is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type VHDLOUT_TYPE is array (0 downto 0) of std_logic;
end CONV_PACK_project2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_1_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_1_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_1_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac_DW_mult_tc_1 is
port( a, b : in std_logic_vector (7 downto 0); product : out
std_logic_vector (15 downto 0); clock : in std_logic);
end mac_DW_mult_tc_1;
architecture SYN_USE_DEFA_ARCH_NAME of mac_DW_mult_tc_1 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component CLKBUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X2
port( A, B : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
component FA_X1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n14, n15, n17, n19, n20
, n21, n22, n24, n26, n27, n28, n29, n30, n31, n32, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n52, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n67, n69, n70, n73, n74, n75,
n76, n77, n80, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94
, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107
, n108, n109, n110, n111, n112, n113, n114, n117, n118, n119, n120, n123,
n124, n125, n128, n131, n134, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n149, n150, n151, n152, n153, n154, n155, n157,
n158, n159, n160, n161, n162, n163, n165, n166, n167, n168, n169, n170,
n172, n173, n182, n191, n194, n200, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n275, n276, n277, n278, n280, n282, n284,
n285, n286, n287, n288, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n303, n306, n307, n308, n309, n310, n311, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n327,
n328, n329, n330, n333, n334, n336, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n_1008,
n_1009, n_1010, n_1011, n_1012, n_1013, n_1014, n_1015, n_1016, n_1017,
n_1018, n_1019, n_1020 : std_logic;
begin
U97 : FA_X1 port map( A => n142, B => n89, CI => n149, CO => n85, S => n86);
U98 : FA_X1 port map( A => n90, B => n143, CI => n93, CO => n87, S => n88);
U101 : FA_X1 port map( A => n150, B => n315, CI => n157, CO => n93, S => n94
);
U102 : FA_X1 port map( A => n103, B => n105, CI => n98, CO => n95, S => n96)
;
U103 : FA_X1 port map( A => n145, B => n151, CI => n100, CO => n97, S => n98
);
U109 : FA_X1 port map( A => n384, B => n112, CI => n110, CO => n107, S =>
n108);
U110 : FA_X1 port map( A => n153, B => n166, CI => n159, CO => n109, S =>
n110);
U111 : HA_X1 port map( A => n147, B => n137, CO => n111, S => n112);
U112 : FA_X1 port map( A => n119, B => n154, CI => n383, CO => n113, S =>
n114);
U115 : HA_X1 port map( A => n138, B => n155, CO => n119, S => n120);
U117 : HA_X1 port map( A => n163, B => n170, CO => n123, S => n124);
U237 : XNOR2_X1 port map( A => n111, B => n275, ZN => n104);
U241 : AND2_X1 port map( A1 => n323, A2 => n69, ZN => product(1));
U242 : XNOR2_X1 port map( A => n165, B => n152, ZN => n275);
U243 : NAND2_X1 port map( A1 => n111, A2 => n165, ZN => n276);
U244 : NAND2_X1 port map( A1 => n111, A2 => n152, ZN => n277);
U245 : NAND2_X1 port map( A1 => n165, A2 => n152, ZN => n278);
U246 : NAND3_X1 port map( A1 => n276, A2 => n277, A3 => n278, ZN => n103);
U248 : XNOR2_X2 port map( A => n365, B => n367, ZN => n334);
U250 : CLKBUF_X1 port map( A => n70, Z => n282);
U251 : CLKBUF_X1 port map( A => n55, Z => n284);
U252 : OAI21_X1 port map( B1 => n56, B2 => n58, A => n57, ZN => n55);
U253 : NAND3_X1 port map( A1 => n299, A2 => n298, A3 => n297, ZN => n285);
U254 : OAI21_X1 port map( B1 => n48, B2 => n50, A => n49, ZN => n47);
U255 : XNOR2_X1 port map( A => n120, B => n286, ZN => n118);
U256 : XNOR2_X1 port map( A => n161, B => n168, ZN => n286);
U257 : OR2_X1 port map( A1 => n385, A2 => n123, ZN => n287);
U258 : CLKBUF_X1 port map( A => n36, Z => n288);
U259 : NOR3_X1 port map( A1 => n290, A2 => n291, A3 => n292, ZN =>
product(15));
U260 : AND2_X1 port map( A1 => n285, A2 => n83, ZN => n290);
U261 : AND2_X1 port map( A1 => n141, A2 => n14, ZN => n291);
U262 : AND2_X1 port map( A1 => n141, A2 => n83, ZN => n292);
U263 : NAND2_X1 port map( A1 => n120, A2 => n161, ZN => n293);
U264 : NAND2_X1 port map( A1 => n120, A2 => n168, ZN => n294);
U265 : NAND2_X1 port map( A1 => n161, A2 => n168, ZN => n295);
U266 : NAND3_X1 port map( A1 => n293, A2 => n294, A3 => n295, ZN => n117);
U267 : XOR2_X1 port map( A => n85, B => n84, Z => n296);
U268 : XOR2_X1 port map( A => n296, B => n282, Z => product(13));
U269 : NAND2_X1 port map( A1 => n85, A2 => n84, ZN => n297);
U270 : NAND2_X1 port map( A1 => n85, A2 => n70, ZN => n298);
U271 : NAND2_X1 port map( A1 => n84, A2 => n70, ZN => n299);
U272 : NAND3_X1 port map( A1 => n298, A2 => n299, A3 => n297, ZN => n14);
U273 : XOR2_X1 port map( A => n141, B => n83, Z => n300);
U274 : XOR2_X1 port map( A => n300, B => n285, Z => product(14));
U275 : CLKBUF_X1 port map( A => n99, Z => n315);
U278 : XNOR2_X1 port map( A => n303, B => n94, ZN => n92);
U279 : XNOR2_X1 port map( A => n97, B => n144, ZN => n303);
U280 : NAND2_X1 port map( A1 => n365, A2 => n367, ZN => n306);
U281 : NAND2_X1 port map( A1 => n382, A2 => n377, ZN => n307);
U282 : NAND2_X1 port map( A1 => n306, A2 => n307, ZN => n226);
U285 : AOI21_X1 port map( B1 => n39, B2 => n47, A => n40, ZN => n308);
U286 : NAND2_X1 port map( A1 => n94, A2 => n97, ZN => n309);
U287 : NAND2_X1 port map( A1 => n94, A2 => n144, ZN => n310);
U288 : NAND2_X1 port map( A1 => n97, A2 => n144, ZN => n311);
U289 : NAND3_X1 port map( A1 => n309, A2 => n310, A3 => n311, ZN => n91);
U291 : CLKBUF_X1 port map( A => n29, Z => n313);
U292 : CLKBUF_X1 port map( A => n20, Z => n314);
U293 : AOI21_X1 port map( B1 => n325, B2 => n284, A => n52, ZN => n316);
U294 : NOR2_X1 port map( A1 => n107, A2 => n102, ZN => n317);
U295 : NAND2_X1 port map( A1 => n217, A2 => n225, ZN => n318);
U296 : NOR2_X1 port map( A1 => n92, A2 => n95, ZN => n319);
U297 : OR2_X1 port map( A1 => n88, A2 => n91, ZN => n321);
U298 : XNOR2_X1 port map( A => n37, B => n4, ZN => product(9));
U299 : INV_X1 port map( A => n35, ZN => n74);
U300 : INV_X1 port map( A => n26, ZN => n24);
U301 : NAND2_X1 port map( A1 => n77, A2 => n49, ZN => n7);
U302 : INV_X1 port map( A => n48, ZN => n77);
U303 : NAND2_X1 port map( A1 => n322, A2 => n19, ZN => n1);
U304 : XOR2_X1 port map( A => n46, B => n6, Z => product(7));
U305 : XOR2_X1 port map( A => n32, B => n3, Z => product(10));
U306 : NAND2_X1 port map( A1 => n73, A2 => n31, ZN => n3);
U307 : AOI21_X1 port map( B1 => n37, B2 => n74, A => n34, ZN => n32);
U308 : XOR2_X1 port map( A => n27, B => n2, Z => product(11));
U309 : NAND2_X1 port map( A1 => n321, A2 => n26, ZN => n2);
U310 : XNOR2_X1 port map( A => n43, B => n5, ZN => product(8));
U311 : NAND2_X1 port map( A1 => n75, A2 => n42, ZN => n5);
U312 : INV_X1 port map( A => n19, ZN => n17);
U313 : XNOR2_X1 port map( A => n104, B => n320, ZN => n102);
U314 : XNOR2_X1 port map( A => n106, B => n109, ZN => n320);
U316 : NOR2_X1 port map( A1 => n102, A2 => n107, ZN => n41);
U317 : NOR2_X1 port map( A1 => n92, A2 => n95, ZN => n30);
U318 : NAND2_X1 port map( A1 => n80, A2 => n61, ZN => n10);
U319 : INV_X1 port map( A => n60, ZN => n80);
U321 : XOR2_X1 port map( A => n9, B => n58, Z => product(4));
U322 : NAND2_X1 port map( A1 => n287, A2 => n57, ZN => n9);
U323 : OR2_X1 port map( A1 => n158, A2 => n146, ZN => n105);
U324 : NOR2_X1 port map( A1 => n114, A2 => n117, ZN => n48);
U325 : INV_X1 port map( A => n83, ZN => n84);
U326 : NAND2_X1 port map( A1 => n88, A2 => n91, ZN => n26);
U327 : NAND2_X1 port map( A1 => n87, A2 => n86, ZN => n19);
U328 : NAND2_X1 port map( A1 => n114, A2 => n117, ZN => n49);
U329 : INV_X1 port map( A => n59, ZN => n58);
U330 : OR2_X1 port map( A1 => n87, A2 => n86, ZN => n322);
U331 : INV_X1 port map( A => n128, ZN => n149);
U332 : INV_X1 port map( A => n89, ZN => n90);
U333 : OR2_X1 port map( A1 => n172, A2 => n140, ZN => n323);
U334 : NOR2_X1 port map( A1 => n385, A2 => n123, ZN => n56);
U335 : INV_X1 port map( A => n125, ZN => n141);
U337 : OR2_X1 port map( A1 => n118, A2 => n380, ZN => n325);
U340 : XOR2_X1 port map( A => n379, B => n356, Z => n182);
U343 : NAND2_X1 port map( A1 => n217, A2 => n225, ZN => n221);
U348 : NAND2_X1 port map( A1 => n76, A2 => n45, ZN => n6);
U349 : NAND2_X1 port map( A1 => n325, A2 => n54, ZN => n8);
U350 : NAND2_X1 port map( A1 => n74, A2 => n288, ZN => n4);
U351 : INV_X1 port map( A => n288, ZN => n34);
U352 : NAND2_X1 port map( A1 => n96, A2 => n101, ZN => n36);
U353 : NAND2_X1 port map( A1 => n385, A2 => n123, ZN => n57);
U355 : NAND2_X1 port map( A1 => n124, A2 => n139, ZN => n61);
U357 : XNOR2_X1 port map( A => n11, B => n67, ZN => product(2));
U359 : NAND2_X1 port map( A1 => n108, A2 => n113, ZN => n45);
U360 : NAND2_X1 port map( A1 => n92, A2 => n95, ZN => n31);
U361 : INV_X1 port map( A => n69, ZN => n67);
U362 : OAI21_X1 port map( B1 => n46, B2 => n44, A => n45, ZN => n43);
U363 : INV_X1 port map( A => n44, ZN => n76);
U364 : NOR2_X1 port map( A1 => n44, A2 => n317, ZN => n39);
U365 : NOR2_X1 port map( A1 => n108, A2 => n113, ZN => n44);
U366 : NAND2_X1 port map( A1 => n104, A2 => n106, ZN => n327);
U367 : NAND2_X1 port map( A1 => n104, A2 => n109, ZN => n328);
U368 : NAND2_X1 port map( A1 => n106, A2 => n109, ZN => n329);
U369 : NAND3_X1 port map( A1 => n327, A2 => n328, A3 => n329, ZN => n101);
U370 : XNOR2_X1 port map( A => n158, B => n146, ZN => n106);
U371 : NAND2_X1 port map( A1 => n102, A2 => n107, ZN => n42);
U373 : AOI21_X1 port map( B1 => n325, B2 => n55, A => n52, ZN => n50);
U374 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n168);
U375 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n167);
U376 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n170);
U377 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n169);
U378 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n200, B2 => n376, ZN
=> n166);
U379 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n140);
U380 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n172);
U381 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n324);
U382 : NAND2_X1 port map( A1 => n219, A2 => n227, ZN => n330);
U385 : NAND2_X1 port map( A1 => n227, A2 => n219, ZN => n223);
U386 : XNOR2_X1 port map( A => n361, B => n363, ZN => n227);
U395 : XNOR2_X1 port map( A => n373, B => n356, ZN => n173);
U396 : INV_X1 port map( A => n134, ZN => n165);
U397 : INV_X1 port map( A => n99, ZN => n100);
U399 : XOR2_X1 port map( A => n373, B => n371, Z => n217);
U400 : NOR2_X1 port map( A1 => n124, A2 => n139, ZN => n60);
U401 : INV_X1 port map( A => n131, ZN => n157);
U403 : XNOR2_X1 port map( A => n369, B => n371, ZN => n225);
U404 : OAI22_X1 port map( A1 => n200, A2 => n224, B1 => n200, B2 => n376, ZN
=> n134);
U406 : INV_X1 port map( A => n54, ZN => n52);
U407 : OAI21_X1 port map( B1 => n38, B2 => n21, A => n22, ZN => n20);
U408 : NAND2_X1 port map( A1 => n28, A2 => n321, ZN => n21);
U409 : NOR2_X1 port map( A1 => n96, A2 => n101, ZN => n35);
U410 : XNOR2_X1 port map( A => n8, B => n284, ZN => product(5));
U411 : XOR2_X1 port map( A => n10, B => n62, Z => product(3));
U412 : OAI21_X1 port map( B1 => n60, B2 => n62, A => n61, ZN => n59);
U413 : NAND2_X1 port map( A1 => n172, A2 => n140, ZN => n69);
U417 : XNOR2_X1 port map( A => n361, B => n356, ZN => n200);
U423 : XOR2_X1 port map( A => n361, B => n359, Z => n220);
U424 : OAI21_X1 port map( B1 => n45, B2 => n41, A => n42, ZN => n40);
U425 : INV_X1 port map( A => n317, ZN => n75);
U426 : AOI21_X1 port map( B1 => n37, B2 => n28, A => n313, ZN => n27);
U427 : INV_X1 port map( A => n319, ZN => n73);
U428 : AOI21_X1 port map( B1 => n29, B2 => n321, A => n24, ZN => n22);
U429 : NOR2_X1 port map( A1 => n35, A2 => n319, ZN => n28);
U430 : OAI21_X1 port map( B1 => n36, B2 => n30, A => n31, ZN => n29);
U431 : INV_X1 port map( A => n15, ZN => n70);
U433 : INV_X1 port map( A => n47, ZN => n46);
U434 : AOI21_X1 port map( B1 => n39, B2 => n47, A => n40, ZN => n38);
U435 : NAND2_X1 port map( A1 => n118, A2 => n380, ZN => n54);
U436 : OAI22_X1 port map( A1 => n182, A2 => n222, B1 => n182, B2 => n334, ZN
=> n128);
U437 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n154);
U438 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n182, B2 => n334, ZN
=> n89);
U439 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n151);
U440 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n153);
U441 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n150);
U446 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n138);
U447 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n155);
U450 : NAND2_X2 port map( A1 => n226, A2 => n218, ZN => n222);
U451 : XNOR2_X1 port map( A => n280, B => n356, ZN => n191);
U454 : XOR2_X1 port map( A => n365, B => n363, Z => n219);
U456 : XNOR2_X1 port map( A => n314, B => n1, ZN => product(12));
U457 : OAI22_X1 port map( A1 => n173, A2 => n221, B1 => n173, B2 => n336, ZN
=> n125);
U458 : AOI21_X1 port map( B1 => n20, B2 => n322, A => n17, ZN => n15);
U459 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n173, B2 => n225, ZN
=> n83);
U460 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n142);
U461 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n143);
U462 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n144);
U463 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n145);
U464 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n146);
U467 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n137);
U468 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n147);
U475 : XOR2_X1 port map( A => n369, B => n367, Z => n218);
U477 : XOR2_X1 port map( A => n7, B => n316, Z => product(6));
U478 : INV_X1 port map( A => n308, ZN => n37);
U479 : OAI22_X1 port map( A1 => n330, A2 => n382, B1 => n194, B2 => n333, ZN
=> n160);
U480 : OAI22_X1 port map( A1 => n330, A2 => n194, B1 => n194, B2 => n333, ZN
=> n158);
U481 : OAI22_X1 port map( A1 => n223, A2 => n382, B1 => n382, B2 => n333, ZN
=> n161);
U482 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n194, B2 => n333, ZN
=> n159);
U483 : OAI22_X1 port map( A1 => n330, A2 => n382, B1 => n382, B2 => n333, ZN
=> n139);
U484 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n382, B2 => n333, ZN
=> n162);
U485 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n191, B2 => n333, ZN
=> n99);
U486 : OAI22_X1 port map( A1 => n191, A2 => n330, B1 => n191, B2 => n333, ZN
=> n131);
U487 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n194, B2 => n333, ZN
=> n163);
clock_r_REG203_S4 : DFF_X1 port map( D => a(7), CK => clock, Q => n374, QN
=> n_1008);
clock_r_REG210_S4 : DFF_X1 port map( D => a(6), CK => clock, Q => n372, QN
=> n_1009);
clock_r_REG211_S5 : DFF_X1 port map( D => n372, CK => clock, Q => n371, QN
=> n_1010);
clock_r_REG214_S4 : DFF_X1 port map( D => a(5), CK => clock, Q => n370, QN
=> n_1011);
clock_r_REG215_S5 : DFF_X1 port map( D => n370, CK => clock, Q => n369, QN
=> n379);
clock_r_REG218_S4 : DFF_X1 port map( D => a(4), CK => clock, Q => n368, QN
=> n_1012);
clock_r_REG219_S5 : DFF_X1 port map( D => n368, CK => clock, Q => n367, QN
=> n377);
clock_r_REG222_S4 : DFF_X1 port map( D => a(3), CK => clock, Q => n366, QN
=> n_1013);
clock_r_REG223_S5 : DFF_X1 port map( D => n366, CK => clock, Q => n365, QN
=> n382);
clock_r_REG226_S4 : DFF_X1 port map( D => a(2), CK => clock, Q => n364, QN
=> n_1014);
clock_r_REG227_S5 : DFF_X1 port map( D => n364, CK => clock, Q => n363, QN
=> n_1015);
clock_r_REG230_S4 : DFF_X1 port map( D => a(1), CK => clock, Q => n362, QN
=> n_1016);
clock_r_REG231_S5 : DFF_X1 port map( D => n362, CK => clock, Q => n361, QN
=> n378);
clock_r_REG234_S4 : DFF_X1 port map( D => a(0), CK => clock, Q => n360, QN
=> n_1017);
clock_r_REG235_S5 : DFF_X1 port map( D => n360, CK => clock, Q => n359, QN
=> n376);
clock_r_REG314_S2 : DFF_X1 port map( D => b(7), CK => clock, Q => n358, QN
=> n_1018);
clock_r_REG315_S3 : DFF_X1 port map( D => n358, CK => clock, Q => n357, QN
=> n_1019);
clock_r_REG316_S4 : DFF_X1 port map( D => n357, CK => clock, Q => n356, QN
=> n_1020);
clock_r_REG204_S5 : DFF_X1 port map( D => n374, CK => clock, Q => n373, QN
=> n381);
U384 : CLKBUF_X2 port map( A => n227, Z => n333);
U238 : CLKBUF_X1 port map( A => n365, Z => n280);
U239 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n152);
U240 : NAND2_X1 port map( A1 => n220, A2 => n376, ZN => n224);
U247 : BUF_X1 port map( A => n225, Z => n336);
U249 : NAND2_X1 port map( A1 => n324, A2 => n67, ZN => n62);
U276 : AND2_X1 port map( A1 => n162, A2 => n169, ZN => n380);
U277 : INV_X1 port map( A => n280, ZN => n194);
U283 : XOR2_X1 port map( A => n167, B => n160, Z => n383);
U284 : AND2_X1 port map( A1 => n160, A2 => n167, ZN => n384);
U290 : XOR2_X1 port map( A => n169, B => n162, Z => n385);
U315 : INV_X1 port map( A => n324, ZN => n11);
end SYN_USE_DEFA_ARCH_NAME;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac_DW01_add_1 is
port( A, B : in std_logic_vector (18 downto 0); CI : in std_logic; SUM :
out std_logic_vector (18 downto 0); CO : out std_logic; clock : in
std_logic);
end mac_DW01_add_1;
architecture SYN_USE_DEFA_ARCH_NAME of mac_DW01_add_1 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n20, n21, n22, n23, n25, n27, n28, n29, n30, n31, n33, n35, n36, n37
, n38, n39, n43, n44, n45, n46, n47, n51, n52, n53, n54, n55, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75
, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n90,
n92, n95, n97, n99, n105, n106, n109, n110, SUM_2_port, SUM_3_port,
SUM_4_port, SUM_5_port, SUM_6_port, SUM_7_port, SUM_8_port, SUM_9_port,
SUM_10_port, SUM_11_port, SUM_12_port, SUM_13_port, SUM_14_port,
SUM_15_port, SUM_16_port, SUM_17_port, SUM_18_port, n178, n180, n181,
n182, n183, n186, n188, n189, n190, n191, n192, n193, n194, n195, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n238, n239, n240, n241, n242, n243,
SUM_1_port, n_1024, n_1025, n_1026, n_1027, n_1028, n_1029, n_1030,
n_1031, n_1032, n_1033, n_1034, n_1035, n_1036, n_1037 : std_logic;
begin
SUM <= ( SUM_18_port, SUM_17_port, SUM_16_port, SUM_15_port, SUM_14_port,
SUM_13_port, SUM_12_port, SUM_11_port, SUM_10_port, SUM_9_port,
SUM_8_port, SUM_7_port, SUM_6_port, SUM_5_port, SUM_4_port, SUM_3_port,
SUM_2_port, SUM_1_port, A(0) );
U138 : OR2_X1 port map( A1 => A(5), A2 => B(5), ZN => n178);
U140 : NOR2_X1 port map( A1 => A(7), A2 => B(7), ZN => n180);
U141 : AOI21_X1 port map( B1 => n44, B2 => n220, A => n238, ZN => n181);
U142 : NOR2_X1 port map( A1 => A(7), A2 => B(7), ZN => n65);
U143 : OAI21_X1 port map( B1 => n181, B2 => n37, A => n38, ZN => n182);
U144 : OAI21_X1 port map( B1 => n39, B2 => n37, A => n38, ZN => n183);
U145 : OAI21_X1 port map( B1 => n39, B2 => n37, A => n38, ZN => n36);
U148 : AOI21_X1 port map( B1 => n36, B2 => n194, A => n33, ZN => n186);
U150 : OAI21_X1 port map( B1 => n186, B2 => n29, A => n30, ZN => n188);
U151 : AOI21_X1 port map( B1 => n28, B2 => n195, A => n25, ZN => n189);
U153 : INV_X1 port map( A => n35, ZN => n33);
U155 : INV_X1 port map( A => n27, ZN => n25);
U156 : NOR2_X1 port map( A1 => n68, A2 => n180, ZN => n63);
U158 : NAND2_X1 port map( A1 => n242, A2 => n224, ZN => n10);
U160 : NAND2_X1 port map( A1 => n239, A2 => n225, ZN => n8);
U162 : NAND2_X1 port map( A1 => n99, A2 => n38, ZN => n6);
U163 : INV_X1 port map( A => n37, ZN => n99);
U164 : NAND2_X1 port map( A1 => n95, A2 => n22, ZN => n2);
U165 : INV_X1 port map( A => n21, ZN => n95);
U166 : NAND2_X1 port map( A1 => n97, A2 => n30, ZN => n4);
U167 : INV_X1 port map( A => n29, ZN => n97);
U168 : XOR2_X1 port map( A => n75, B => n14, Z => SUM_5_port);
U169 : NAND2_X1 port map( A1 => n178, A2 => n74, ZN => n14);
U170 : AOI21_X1 port map( B1 => n80, B2 => n76, A => n77, ZN => n75);
U171 : INV_X1 port map( A => n78, ZN => n76);
U172 : NAND2_X1 port map( A1 => n220, A2 => n227, ZN => n7);
U173 : NAND2_X1 port map( A1 => n195, A2 => n27, ZN => n3);
U174 : NAND2_X1 port map( A1 => n219, A2 => n226, ZN => n11);
U175 : NAND2_X1 port map( A1 => n194, A2 => n35, ZN => n5);
U176 : NAND2_X1 port map( A1 => n221, A2 => n228, ZN => n9);
U177 : XOR2_X1 port map( A => n92, B => n17, Z => SUM_2_port);
U178 : XOR2_X1 port map( A => n70, B => n13, Z => SUM_6_port);
U179 : NAND2_X1 port map( A1 => n106, A2 => n69, ZN => n13);
U180 : XNOR2_X1 port map( A => n67, B => n12, ZN => SUM_7_port);
U181 : NAND2_X1 port map( A1 => n105, A2 => n66, ZN => n12);
U182 : XNOR2_X1 port map( A => n80, B => n15, ZN => SUM_4_port);
U183 : NAND2_X1 port map( A1 => n76, A2 => n79, ZN => n15);
U184 : XNOR2_X1 port map( A => n86, B => n16, ZN => SUM_3_port);
U185 : NAND2_X1 port map( A1 => n109, A2 => n85, ZN => n16);
U186 : INV_X1 port map( A => n79, ZN => n77);
U187 : XNOR2_X1 port map( A => B(18), B => n236, ZN => n190);
U188 : NOR2_X1 port map( A1 => A(3), A2 => B(3), ZN => n84);
U189 : NOR2_X1 port map( A1 => A(2), A2 => B(2), ZN => n87);
U190 : NAND2_X1 port map( A1 => A(10), A2 => B(10), ZN => n51);
U191 : NAND2_X1 port map( A1 => A(12), A2 => B(12), ZN => n43);
U192 : NAND2_X1 port map( A1 => A(8), A2 => B(8), ZN => n59);
U193 : NAND2_X1 port map( A1 => n232, A2 => n230, ZN => n35);
U194 : NAND2_X1 port map( A1 => n234, A2 => B(16), ZN => n27);
U195 : NAND2_X1 port map( A1 => n231, A2 => n229, ZN => n38);
U196 : NAND2_X1 port map( A1 => A(11), A2 => B(11), ZN => n46);
U197 : NAND2_X1 port map( A1 => A(9), A2 => B(9), ZN => n54);
U198 : NAND2_X1 port map( A1 => n233, A2 => B(15), ZN => n30);
U199 : NAND2_X1 port map( A1 => n235, A2 => B(17), ZN => n22);
U200 : NOR2_X1 port map( A1 => n231, A2 => n229, ZN => n37);
U201 : NAND2_X1 port map( A1 => A(2), A2 => B(2), ZN => n88);
U202 : NOR2_X1 port map( A1 => A(11), A2 => B(11), ZN => n45);
U203 : NOR2_X1 port map( A1 => A(9), A2 => B(9), ZN => n53);
U204 : NOR2_X1 port map( A1 => n233, A2 => B(15), ZN => n29);
U205 : NOR2_X1 port map( A1 => n235, A2 => B(17), ZN => n21);
U206 : OR2_X1 port map( A1 => A(10), A2 => B(10), ZN => n191);
U207 : OR2_X1 port map( A1 => A(12), A2 => B(12), ZN => n192);
U208 : OR2_X1 port map( A1 => A(8), A2 => B(8), ZN => n193);
U209 : OR2_X1 port map( A1 => n232, A2 => n230, ZN => n194);
U210 : OR2_X1 port map( A1 => n234, A2 => B(16), ZN => n195);
U212 : NAND2_X1 port map( A1 => A(5), A2 => B(5), ZN => n74);
U213 : NOR2_X1 port map( A1 => A(5), A2 => B(5), ZN => n73);
U214 : XNOR2_X1 port map( A => n20, B => n190, ZN => SUM_18_port);
U220 : XOR2_X1 port map( A => n55, B => n10, Z => SUM_9_port);
U221 : OAI21_X1 port map( B1 => n55, B2 => n222, A => n224, ZN => n52);
U222 : AOI21_X1 port map( B1 => n218, B2 => n219, A => n241, ZN => n55);
U226 : OAI21_X1 port map( B1 => n92, B2 => n87, A => n88, ZN => n86);
U227 : INV_X1 port map( A => n87, ZN => n110);
U228 : NAND2_X1 port map( A1 => n110, A2 => n88, ZN => n17);
U229 : NOR2_X1 port map( A1 => n78, A2 => n73, ZN => n71);
U230 : INV_X1 port map( A => n81, ZN => n80);
U231 : NAND2_X1 port map( A1 => n71, A2 => n63, ZN => n61);
U232 : XNOR2_X1 port map( A => n218, B => n11, ZN => SUM_8_port);
U233 : OAI21_X1 port map( B1 => n81, B2 => n61, A => n62, ZN => n60);
U234 : OAI21_X1 port map( B1 => n65, B2 => n69, A => n66, ZN => n64);
U235 : INV_X1 port map( A => n180, ZN => n105);
U236 : AOI21_X1 port map( B1 => n82, B2 => n90, A => n83, ZN => n81);
U237 : AOI21_X1 port map( B1 => n63, B2 => n72, A => n64, ZN => n62);
U238 : NAND2_X1 port map( A1 => A(6), A2 => B(6), ZN => n69);
U240 : NAND2_X1 port map( A1 => A(1), A2 => B(1), ZN => n92);
U241 : INV_X1 port map( A => n68, ZN => n106);
U242 : OAI21_X1 port map( B1 => n70, B2 => n68, A => n69, ZN => n67);
U243 : NOR2_X1 port map( A1 => A(6), A2 => B(6), ZN => n68);
U244 : INV_X1 port map( A => n84, ZN => n109);
U245 : NOR2_X1 port map( A1 => n87, A2 => n84, ZN => n82);
U246 : OAI21_X1 port map( B1 => n84, B2 => n88, A => n85, ZN => n83);
U247 : AOI21_X1 port map( B1 => n80, B2 => n71, A => n72, ZN => n70);
U248 : OAI21_X1 port map( B1 => n73, B2 => n79, A => n74, ZN => n72);
U249 : NAND2_X1 port map( A1 => A(4), A2 => B(4), ZN => n79);
U250 : NOR2_X1 port map( A1 => A(4), A2 => B(4), ZN => n78);
U251 : NAND2_X1 port map( A1 => A(3), A2 => B(3), ZN => n85);
U252 : AOI21_X1 port map( B1 => n182, B2 => n194, A => n33, ZN => n31);
U253 : XOR2_X1 port map( A => n23, B => n2, Z => SUM_17_port);
U254 : OAI21_X1 port map( B1 => n189, B2 => n21, A => n22, ZN => n20);
U255 : AOI21_X1 port map( B1 => n188, B2 => n195, A => n25, ZN => n23);
U256 : XNOR2_X1 port map( A => n188, B => n3, ZN => SUM_16_port);
U257 : OAI21_X1 port map( B1 => n31, B2 => n29, A => n30, ZN => n28);
U258 : XNOR2_X1 port map( A => n183, B => n5, ZN => SUM_14_port);
U259 : XOR2_X1 port map( A => n186, B => n4, Z => SUM_15_port);
U260 : NAND2_X1 port map( A1 => A(7), A2 => B(7), ZN => n66);
U261 : XOR2_X1 port map( A => n47, B => n8, Z => SUM_11_port);
U262 : XNOR2_X1 port map( A => n52, B => n9, ZN => SUM_10_port);
U263 : XNOR2_X1 port map( A => n44, B => n7, ZN => SUM_12_port);
U264 : XOR2_X1 port map( A => n39, B => n6, Z => SUM_13_port);
U265 : AOI21_X1 port map( B1 => n44, B2 => n220, A => n238, ZN => n39);
U266 : AOI21_X1 port map( B1 => n52, B2 => n221, A => n240, ZN => n47);
clock_r_REG30_S3 : DFF_X1 port map( D => A(18), CK => clock, Q => n236, QN
=> n_1024);
clock_r_REG29_S3 : DFF_X1 port map( D => A(17), CK => clock, Q => n235, QN
=> n_1025);
clock_r_REG47_S3 : DFF_X1 port map( D => A(16), CK => clock, Q => n234, QN
=> n_1026);
clock_r_REG56_S3 : DFF_X1 port map( D => A(15), CK => clock, Q => n233, QN
=> n_1027);
clock_r_REG65_S3 : DFF_X1 port map( D => A(14), CK => clock, Q => n232, QN
=> n_1028);
clock_r_REG28_S3 : DFF_X1 port map( D => A(13), CK => clock, Q => n231, QN
=> n_1029);
clock_r_REG205_S6 : DFF_X1 port map( D => B(14), CK => clock, Q => n230, QN
=> n_1030);
clock_r_REG207_S6 : DFF_X1 port map( D => B(13), CK => clock, Q => n229, QN
=> n_1031);
clock_r_REG102_S3 : DFF_X1 port map( D => n51, CK => clock, Q => n228, QN =>
n240);
clock_r_REG83_S3 : DFF_X1 port map( D => n43, CK => clock, Q => n227, QN =>
n238);
clock_r_REG121_S3 : DFF_X1 port map( D => n59, CK => clock, Q => n226, QN =>
n241);
clock_r_REG92_S3 : DFF_X1 port map( D => n46, CK => clock, Q => n225, QN =>
n_1032);
clock_r_REG112_S3 : DFF_X1 port map( D => n54, CK => clock, Q => n224, QN =>
n_1033);
clock_r_REG27_S3 : DFF_X1 port map( D => n45, CK => clock, Q => n223, QN =>
n239);
clock_r_REG111_S3 : DFF_X1 port map( D => n53, CK => clock, Q => n222, QN =>
n242);
clock_r_REG101_S3 : DFF_X1 port map( D => n191, CK => clock, Q => n221, QN
=> n_1034);
clock_r_REG82_S3 : DFF_X1 port map( D => n192, CK => clock, Q => n220, QN =>
n_1035);
clock_r_REG26_S3 : DFF_X1 port map( D => n193, CK => clock, Q => n219, QN =>
n_1036);
clock_r_REG25_S3 : DFF_X1 port map( D => n60, CK => clock, Q => n218, QN =>
n_1037);
U135 : OAI21_X1 port map( B1 => n47, B2 => n223, A => n225, ZN => n44);
U136 : INV_X1 port map( A => n92, ZN => n90);
U137 : OR2_X1 port map( A1 => A(1), A2 => B(1), ZN => n243);
U139 : AND2_X1 port map( A1 => n243, A2 => n92, ZN => SUM_1_port);
end SYN_USE_DEFA_ARCH_NAME;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_2_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_2_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_2_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_0_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_0_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_0_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity ramR is
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (18
downto 0); dataout : out std_logic_vector (18 downto 0));
end ramR;
architecture SYN_ramR of ramR is
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NAND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
signal n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
ram_0_18_port, ram_0_17_port, ram_0_16_port, ram_0_15_port, ram_0_14_port
, ram_0_13_port, ram_0_12_port, ram_0_11_port, ram_0_10_port,
ram_0_9_port, ram_0_8_port, ram_0_7_port, ram_0_6_port, ram_0_5_port,
ram_0_4_port, ram_0_3_port, ram_0_2_port, ram_0_1_port, ram_0_0_port,
ram_1_18_port, ram_1_17_port, ram_1_16_port, ram_1_15_port, ram_1_14_port
, ram_1_13_port, ram_1_12_port, ram_1_11_port, ram_1_10_port,
ram_1_9_port, ram_1_8_port, ram_1_7_port, ram_1_6_port, ram_1_5_port,
ram_1_4_port, ram_1_3_port, ram_1_2_port, ram_1_1_port, ram_1_0_port,
ram_2_18_port, ram_2_17_port, ram_2_16_port, ram_2_15_port, ram_2_14_port
, ram_2_13_port, ram_2_12_port, ram_2_11_port, ram_2_10_port,
ram_2_9_port, ram_2_8_port, ram_2_7_port, ram_2_6_port, ram_2_5_port,
ram_2_4_port, ram_2_3_port, ram_2_2_port, ram_2_1_port, ram_2_0_port,
ram_3_18_port, ram_3_17_port, ram_3_16_port, ram_3_15_port, ram_3_14_port
, ram_3_13_port, ram_3_12_port, ram_3_11_port, ram_3_10_port,
ram_3_9_port, ram_3_8_port, ram_3_7_port, ram_3_6_port, ram_3_5_port,
ram_3_4_port, ram_3_3_port, ram_3_2_port, ram_3_1_port, ram_3_0_port,
ram_4_18_port, ram_4_17_port, ram_4_16_port, ram_4_15_port, ram_4_14_port
, ram_4_13_port, ram_4_12_port, ram_4_11_port, ram_4_10_port,
ram_4_9_port, ram_4_8_port, ram_4_7_port, ram_4_6_port, ram_4_5_port,
ram_4_4_port, ram_4_3_port, ram_4_2_port, ram_4_1_port, ram_4_0_port,
ram_5_18_port, ram_5_17_port, ram_5_16_port, ram_5_15_port, ram_5_14_port
, ram_5_13_port, ram_5_12_port, ram_5_11_port, ram_5_10_port,
ram_5_9_port, ram_5_8_port, ram_5_7_port, ram_5_6_port, ram_5_5_port,
ram_5_4_port, ram_5_3_port, ram_5_2_port, ram_5_1_port, ram_5_0_port,
ram_6_18_port, ram_6_17_port, ram_6_16_port, ram_6_15_port, ram_6_14_port
, ram_6_13_port, ram_6_12_port, ram_6_11_port, ram_6_10_port,
ram_6_9_port, ram_6_8_port, ram_6_7_port, ram_6_6_port, ram_6_5_port,
ram_6_4_port, ram_6_3_port, ram_6_2_port, ram_6_1_port, ram_6_0_port,
ram_7_18_port, ram_7_17_port, ram_7_16_port, ram_7_15_port, ram_7_14_port
, ram_7_13_port, ram_7_12_port, ram_7_11_port, ram_7_10_port,
ram_7_9_port, ram_7_8_port, ram_7_7_port, ram_7_6_port, ram_7_5_port,
ram_7_4_port, ram_7_3_port, ram_7_2_port, ram_7_1_port, ram_7_0_port, N30
, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44,
N45, N46, N47, N48, n2, n19, n26, n28, n29, n31_port, n33_port, n35_port,
n37_port, n38_port, n39_port, n40_port, n41_port, n42_port, n43_port,
n44_port, n45_port, n46_port, n47_port, n48_port, n49, n50, n51, n52, n53
, n54, n55, n57, n59, n1, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n20, n21, n22, n23, n24, n25, n27, n30_port,
n32_port, n34_port, n36_port, n56, n58, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n1195, n1196, n1197
, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365 : std_logic;
begin
U229 : NAND3_X1 port map( A1 => n26, A2 => n471, A3 => address(0), ZN => n2)
;
U2 : CLKBUF_X1 port map( A => read_enable, Z => n461);
U3 : AND2_X1 port map( A1 => write_enable, A2 => address(2), ZN => n26);
U4 : INV_X1 port map( A => address(1), ZN => n471);
U5 : INV_X1 port map( A => n35_port, ZN => n464);
U6 : INV_X1 port map( A => n19, ZN => n462);
U7 : INV_X1 port map( A => n2, ZN => n470);
U8 : INV_X1 port map( A => n33_port, ZN => n468);
U9 : INV_X1 port map( A => n57, ZN => n469);
U10 : INV_X1 port map( A => n28, ZN => n467);
U11 : INV_X1 port map( A => n31_port, ZN => n463);
U12 : INV_X1 port map( A => n59, ZN => n465);
U14 : NAND3_X1 port map( A1 => n466, A2 => n471, A3 => n26, ZN => n19);
U15 : AND2_X1 port map( A1 => n4, A2 => n466, ZN => n455);
U16 : AND2_X1 port map( A1 => n1, A2 => n466, ZN => n453);
U17 : AND2_X1 port map( A1 => n3, A2 => n466, ZN => n452);
U18 : AND2_X1 port map( A1 => n5, A2 => n466, ZN => n454);
U19 : NOR2_X1 port map( A1 => n472, A2 => address(2), ZN => n29);
U20 : INV_X1 port map( A => write_enable, ZN => n472);
U22 : NAND3_X1 port map( A1 => address(0), A2 => n26, A3 => address(1), ZN
=> n57);
U25 : NAND3_X1 port map( A1 => n26, A2 => n466, A3 => address(1), ZN => n59)
;
U26 : OAI22_X1 port map( A1 => n470, A2 => n1270, B1 => n2, B2 => n491, ZN
=> ram_5_0_port);
U27 : OAI22_X1 port map( A1 => n470, A2 => n1269, B1 => n2, B2 => n490, ZN
=> ram_5_1_port);
U28 : OAI22_X1 port map( A1 => n470, A2 => n1268, B1 => n2, B2 => n489, ZN
=> ram_5_2_port);
U29 : OAI22_X1 port map( A1 => n470, A2 => n1267, B1 => n2, B2 => n488, ZN
=> ram_5_3_port);
U30 : OAI22_X1 port map( A1 => n470, A2 => n1266, B1 => n2, B2 => n487, ZN
=> ram_5_4_port);
U31 : OAI22_X1 port map( A1 => n470, A2 => n1265, B1 => n2, B2 => n486, ZN
=> ram_5_5_port);
U32 : OAI22_X1 port map( A1 => n470, A2 => n1264, B1 => n2, B2 => n485, ZN
=> ram_5_6_port);
U33 : OAI22_X1 port map( A1 => n470, A2 => n1263, B1 => n2, B2 => n484, ZN
=> ram_5_7_port);
U34 : OAI22_X1 port map( A1 => n470, A2 => n1262, B1 => n2, B2 => n483, ZN
=> ram_5_8_port);
U35 : OAI22_X1 port map( A1 => n470, A2 => n1261, B1 => n2, B2 => n482, ZN
=> ram_5_9_port);
U36 : OAI22_X1 port map( A1 => n470, A2 => n1260, B1 => n2, B2 => n481, ZN
=> ram_5_10_port);
U37 : OAI22_X1 port map( A1 => n470, A2 => n1259, B1 => n2, B2 => n480, ZN
=> ram_5_11_port);
U38 : OAI22_X1 port map( A1 => n470, A2 => n1258, B1 => n2, B2 => n479, ZN
=> ram_5_12_port);
U39 : OAI22_X1 port map( A1 => n470, A2 => n1257, B1 => n2, B2 => n478, ZN
=> ram_5_13_port);
U40 : OAI22_X1 port map( A1 => n470, A2 => n1256, B1 => n2, B2 => n477, ZN
=> ram_5_14_port);
U41 : OAI22_X1 port map( A1 => n470, A2 => n1255, B1 => n2, B2 => n476, ZN
=> ram_5_15_port);
U42 : OAI22_X1 port map( A1 => n470, A2 => n1254, B1 => n2, B2 => n475, ZN
=> ram_5_16_port);
U43 : OAI22_X1 port map( A1 => n470, A2 => n1253, B1 => n2, B2 => n474, ZN
=> ram_5_17_port);
U44 : OAI22_X1 port map( A1 => n470, A2 => n1252, B1 => n2, B2 => n473, ZN
=> ram_5_18_port);
U45 : INV_X1 port map( A => address(0), ZN => n466);
U46 : INV_X1 port map( A => datain(0), ZN => n491);
U47 : INV_X1 port map( A => datain(1), ZN => n490);
U48 : INV_X1 port map( A => datain(2), ZN => n489);
U49 : INV_X1 port map( A => datain(3), ZN => n488);
U50 : INV_X1 port map( A => datain(4), ZN => n487);
U51 : INV_X1 port map( A => datain(5), ZN => n486);
U52 : INV_X1 port map( A => datain(6), ZN => n485);
U53 : INV_X1 port map( A => datain(7), ZN => n484);
U54 : INV_X1 port map( A => datain(8), ZN => n483);
U55 : INV_X1 port map( A => datain(9), ZN => n482);
U56 : INV_X1 port map( A => datain(10), ZN => n481);
U57 : INV_X1 port map( A => datain(11), ZN => n480);
U58 : INV_X1 port map( A => datain(12), ZN => n479);
U59 : INV_X1 port map( A => datain(13), ZN => n478);
U60 : INV_X1 port map( A => datain(14), ZN => n477);
U61 : INV_X1 port map( A => datain(15), ZN => n476);
U62 : INV_X1 port map( A => datain(16), ZN => n475);
U63 : INV_X1 port map( A => datain(17), ZN => n474);
U64 : OAI22_X1 port map( A1 => n468, A2 => n1251, B1 => n491, B2 => n33_port
, ZN => ram_1_0_port);
U65 : OAI22_X1 port map( A1 => n468, A2 => n1250, B1 => n490, B2 => n33_port
, ZN => ram_1_1_port);
U66 : OAI22_X1 port map( A1 => n468, A2 => n1249, B1 => n489, B2 => n33_port
, ZN => ram_1_2_port);
U67 : OAI22_X1 port map( A1 => n468, A2 => n1248, B1 => n488, B2 => n33_port
, ZN => ram_1_3_port);
U68 : OAI22_X1 port map( A1 => n468, A2 => n1247, B1 => n487, B2 => n33_port
, ZN => ram_1_4_port);
U69 : OAI22_X1 port map( A1 => n468, A2 => n1246, B1 => n486, B2 => n33_port
, ZN => ram_1_5_port);
U70 : OAI22_X1 port map( A1 => n468, A2 => n1245, B1 => n485, B2 => n33_port
, ZN => ram_1_6_port);
U71 : OAI22_X1 port map( A1 => n468, A2 => n1244, B1 => n484, B2 => n33_port
, ZN => ram_1_7_port);
U72 : OAI22_X1 port map( A1 => n468, A2 => n1243, B1 => n483, B2 => n33_port
, ZN => ram_1_8_port);
U73 : OAI22_X1 port map( A1 => n468, A2 => n1242, B1 => n482, B2 => n33_port
, ZN => ram_1_9_port);
U74 : OAI22_X1 port map( A1 => n468, A2 => n1241, B1 => n481, B2 => n33_port
, ZN => ram_1_10_port);
U75 : OAI22_X1 port map( A1 => n468, A2 => n1240, B1 => n480, B2 => n33_port
, ZN => ram_1_11_port);
U76 : OAI22_X1 port map( A1 => n468, A2 => n1239, B1 => n479, B2 => n33_port
, ZN => ram_1_12_port);
U77 : OAI22_X1 port map( A1 => n468, A2 => n1238, B1 => n478, B2 => n33_port
, ZN => ram_1_13_port);
U78 : OAI22_X1 port map( A1 => n468, A2 => n1237, B1 => n477, B2 => n33_port
, ZN => ram_1_14_port);
U79 : OAI22_X1 port map( A1 => n468, A2 => n1236, B1 => n476, B2 => n33_port
, ZN => ram_1_15_port);
U80 : OAI22_X1 port map( A1 => n468, A2 => n1235, B1 => n475, B2 => n33_port
, ZN => ram_1_16_port);
U81 : OAI22_X1 port map( A1 => n468, A2 => n1234, B1 => n474, B2 => n33_port
, ZN => ram_1_17_port);
U82 : OAI22_X1 port map( A1 => n468, A2 => n1233, B1 => n473, B2 => n33_port
, ZN => ram_1_18_port);
U83 : OAI22_X1 port map( A1 => n469, A2 => n1346, B1 => n491, B2 => n57, ZN
=> ram_7_0_port);
U84 : OAI22_X1 port map( A1 => n469, A2 => n1345, B1 => n490, B2 => n57, ZN
=> ram_7_1_port);
U85 : OAI22_X1 port map( A1 => n469, A2 => n1344, B1 => n489, B2 => n57, ZN
=> ram_7_2_port);
U86 : OAI22_X1 port map( A1 => n469, A2 => n1343, B1 => n488, B2 => n57, ZN
=> ram_7_3_port);
U87 : OAI22_X1 port map( A1 => n469, A2 => n1342, B1 => n487, B2 => n57, ZN
=> ram_7_4_port);
U88 : OAI22_X1 port map( A1 => n469, A2 => n1341, B1 => n486, B2 => n57, ZN
=> ram_7_5_port);
U89 : OAI22_X1 port map( A1 => n469, A2 => n1340, B1 => n485, B2 => n57, ZN
=> ram_7_6_port);
U90 : OAI22_X1 port map( A1 => n469, A2 => n1339, B1 => n484, B2 => n57, ZN
=> ram_7_7_port);
U91 : OAI22_X1 port map( A1 => n469, A2 => n1338, B1 => n483, B2 => n57, ZN
=> ram_7_8_port);
U92 : OAI22_X1 port map( A1 => n469, A2 => n1337, B1 => n482, B2 => n57, ZN
=> ram_7_9_port);
U93 : OAI22_X1 port map( A1 => n469, A2 => n1336, B1 => n481, B2 => n57, ZN
=> ram_7_10_port);
U94 : OAI22_X1 port map( A1 => n469, A2 => n1335, B1 => n480, B2 => n57, ZN
=> ram_7_11_port);
U95 : OAI22_X1 port map( A1 => n469, A2 => n1334, B1 => n479, B2 => n57, ZN
=> ram_7_12_port);
U96 : OAI22_X1 port map( A1 => n469, A2 => n1333, B1 => n478, B2 => n57, ZN
=> ram_7_13_port);
U97 : OAI22_X1 port map( A1 => n469, A2 => n1332, B1 => n477, B2 => n57, ZN
=> ram_7_14_port);
U98 : OAI22_X1 port map( A1 => n469, A2 => n1331, B1 => n476, B2 => n57, ZN
=> ram_7_15_port);
U99 : OAI22_X1 port map( A1 => n469, A2 => n1330, B1 => n475, B2 => n57, ZN
=> ram_7_16_port);
U100 : OAI22_X1 port map( A1 => n469, A2 => n1329, B1 => n474, B2 => n57, ZN
=> ram_7_17_port);
U101 : OAI22_X1 port map( A1 => n469, A2 => n1328, B1 => n473, B2 => n57, ZN
=> ram_7_18_port);
U102 : OAI22_X1 port map( A1 => n462, A2 => n1232, B1 => n19, B2 => n491, ZN
=> ram_4_0_port);
U103 : OAI22_X1 port map( A1 => n462, A2 => n1231, B1 => n19, B2 => n490, ZN
=> ram_4_1_port);
U104 : OAI22_X1 port map( A1 => n462, A2 => n1230, B1 => n19, B2 => n489, ZN
=> ram_4_2_port);
U105 : OAI22_X1 port map( A1 => n462, A2 => n1229, B1 => n19, B2 => n488, ZN
=> ram_4_3_port);
U106 : OAI22_X1 port map( A1 => n467, A2 => n1327, B1 => n491, B2 => n28, ZN
=> ram_3_0_port);
U107 : OAI22_X1 port map( A1 => n467, A2 => n1326, B1 => n490, B2 => n28, ZN
=> ram_3_1_port);
U108 : OAI22_X1 port map( A1 => n467, A2 => n1325, B1 => n489, B2 => n28, ZN
=> ram_3_2_port);
U109 : OAI22_X1 port map( A1 => n467, A2 => n1324, B1 => n488, B2 => n28, ZN
=> ram_3_3_port);
U110 : OAI22_X1 port map( A1 => n467, A2 => n1323, B1 => n487, B2 => n28, ZN
=> ram_3_4_port);
U111 : OAI22_X1 port map( A1 => n467, A2 => n1322, B1 => n486, B2 => n28, ZN
=> ram_3_5_port);
U112 : OAI22_X1 port map( A1 => n467, A2 => n1321, B1 => n485, B2 => n28, ZN
=> ram_3_6_port);
U113 : OAI22_X1 port map( A1 => n467, A2 => n1320, B1 => n484, B2 => n28, ZN
=> ram_3_7_port);
U114 : OAI22_X1 port map( A1 => n467, A2 => n1319, B1 => n483, B2 => n28, ZN
=> ram_3_8_port);
U115 : OAI22_X1 port map( A1 => n467, A2 => n1318, B1 => n482, B2 => n28, ZN
=> ram_3_9_port);
U116 : OAI22_X1 port map( A1 => n467, A2 => n1317, B1 => n481, B2 => n28, ZN
=> ram_3_10_port);
U117 : OAI22_X1 port map( A1 => n467, A2 => n1316, B1 => n480, B2 => n28, ZN
=> ram_3_11_port);
U118 : OAI22_X1 port map( A1 => n467, A2 => n1315, B1 => n479, B2 => n28, ZN
=> ram_3_12_port);
U119 : OAI22_X1 port map( A1 => n467, A2 => n1314, B1 => n478, B2 => n28, ZN
=> ram_3_13_port);
U120 : OAI22_X1 port map( A1 => n467, A2 => n1313, B1 => n477, B2 => n28, ZN
=> ram_3_14_port);
U121 : OAI22_X1 port map( A1 => n467, A2 => n1312, B1 => n476, B2 => n28, ZN
=> ram_3_15_port);
U122 : OAI22_X1 port map( A1 => n467, A2 => n1311, B1 => n475, B2 => n28, ZN
=> ram_3_16_port);
U123 : OAI22_X1 port map( A1 => n467, A2 => n1310, B1 => n474, B2 => n28, ZN
=> ram_3_17_port);
U124 : OAI22_X1 port map( A1 => n467, A2 => n1309, B1 => n473, B2 => n28, ZN
=> ram_3_18_port);
U125 : OAI22_X1 port map( A1 => n463, A2 => n1308, B1 => n491, B2 =>
n31_port, ZN => ram_2_0_port);
U126 : OAI22_X1 port map( A1 => n463, A2 => n1307, B1 => n490, B2 =>
n31_port, ZN => ram_2_1_port);
U127 : OAI22_X1 port map( A1 => n463, A2 => n1306, B1 => n489, B2 =>
n31_port, ZN => ram_2_2_port);
U128 : OAI22_X1 port map( A1 => n463, A2 => n1305, B1 => n488, B2 =>
n31_port, ZN => ram_2_3_port);
U129 : OAI22_X1 port map( A1 => n463, A2 => n1304, B1 => n487, B2 =>
n31_port, ZN => ram_2_4_port);
U130 : OAI22_X1 port map( A1 => n463, A2 => n1303, B1 => n486, B2 =>
n31_port, ZN => ram_2_5_port);
U131 : OAI22_X1 port map( A1 => n463, A2 => n1302, B1 => n485, B2 =>
n31_port, ZN => ram_2_6_port);
U132 : OAI22_X1 port map( A1 => n463, A2 => n1301, B1 => n484, B2 =>
n31_port, ZN => ram_2_7_port);
U133 : OAI22_X1 port map( A1 => n463, A2 => n1300, B1 => n483, B2 =>
n31_port, ZN => ram_2_8_port);
U134 : OAI22_X1 port map( A1 => n463, A2 => n1299, B1 => n482, B2 =>
n31_port, ZN => ram_2_9_port);
U135 : OAI22_X1 port map( A1 => n463, A2 => n1298, B1 => n481, B2 =>
n31_port, ZN => ram_2_10_port);
U136 : OAI22_X1 port map( A1 => n463, A2 => n1297, B1 => n480, B2 =>
n31_port, ZN => ram_2_11_port);
U137 : OAI22_X1 port map( A1 => n463, A2 => n1296, B1 => n479, B2 =>
n31_port, ZN => ram_2_12_port);
U138 : OAI22_X1 port map( A1 => n463, A2 => n1295, B1 => n478, B2 =>
n31_port, ZN => ram_2_13_port);
U139 : OAI22_X1 port map( A1 => n463, A2 => n1294, B1 => n477, B2 =>
n31_port, ZN => ram_2_14_port);
U140 : OAI22_X1 port map( A1 => n463, A2 => n1293, B1 => n476, B2 =>
n31_port, ZN => ram_2_15_port);
U141 : OAI22_X1 port map( A1 => n463, A2 => n1292, B1 => n475, B2 =>
n31_port, ZN => ram_2_16_port);
U142 : OAI22_X1 port map( A1 => n463, A2 => n1291, B1 => n474, B2 =>
n31_port, ZN => ram_2_17_port);
U143 : OAI22_X1 port map( A1 => n463, A2 => n1290, B1 => n473, B2 =>
n31_port, ZN => ram_2_18_port);
U144 : OAI22_X1 port map( A1 => n465, A2 => n1289, B1 => n491, B2 => n59, ZN
=> ram_6_0_port);
U145 : OAI22_X1 port map( A1 => n465, A2 => n1288, B1 => n490, B2 => n59, ZN
=> ram_6_1_port);
U146 : OAI22_X1 port map( A1 => n465, A2 => n1287, B1 => n489, B2 => n59, ZN
=> ram_6_2_port);
U147 : OAI22_X1 port map( A1 => n465, A2 => n1286, B1 => n488, B2 => n59, ZN
=> ram_6_3_port);
U148 : OAI22_X1 port map( A1 => n465, A2 => n1285, B1 => n487, B2 => n59, ZN
=> ram_6_4_port);
U149 : OAI22_X1 port map( A1 => n465, A2 => n1284, B1 => n486, B2 => n59, ZN
=> ram_6_5_port);
U150 : OAI22_X1 port map( A1 => n465, A2 => n1283, B1 => n485, B2 => n59, ZN
=> ram_6_6_port);
U151 : OAI22_X1 port map( A1 => n465, A2 => n1282, B1 => n484, B2 => n59, ZN
=> ram_6_7_port);
U152 : OAI22_X1 port map( A1 => n465, A2 => n1281, B1 => n483, B2 => n59, ZN
=> ram_6_8_port);
U153 : OAI22_X1 port map( A1 => n465, A2 => n1280, B1 => n482, B2 => n59, ZN
=> ram_6_9_port);
U154 : OAI22_X1 port map( A1 => n465, A2 => n1279, B1 => n481, B2 => n59, ZN
=> ram_6_10_port);
U155 : OAI22_X1 port map( A1 => n465, A2 => n1278, B1 => n480, B2 => n59, ZN
=> ram_6_11_port);
U156 : OAI22_X1 port map( A1 => n465, A2 => n1277, B1 => n479, B2 => n59, ZN
=> ram_6_12_port);
U157 : OAI22_X1 port map( A1 => n465, A2 => n1276, B1 => n478, B2 => n59, ZN
=> ram_6_13_port);
U158 : OAI22_X1 port map( A1 => n465, A2 => n1275, B1 => n477, B2 => n59, ZN
=> ram_6_14_port);
U159 : OAI22_X1 port map( A1 => n465, A2 => n1274, B1 => n476, B2 => n59, ZN
=> ram_6_15_port);
U160 : OAI22_X1 port map( A1 => n465, A2 => n1273, B1 => n475, B2 => n59, ZN
=> ram_6_16_port);
U161 : OAI22_X1 port map( A1 => n465, A2 => n1272, B1 => n474, B2 => n59, ZN
=> ram_6_17_port);
U162 : OAI22_X1 port map( A1 => n465, A2 => n1271, B1 => n473, B2 => n59, ZN
=> ram_6_18_port);
U163 : OAI22_X1 port map( A1 => n464, A2 => n1228, B1 => n491, B2 =>
n35_port, ZN => ram_0_0_port);
U164 : OAI22_X1 port map( A1 => n464, A2 => n1227, B1 => n490, B2 =>
n35_port, ZN => ram_0_1_port);
U165 : OAI22_X1 port map( A1 => n464, A2 => n1226, B1 => n489, B2 =>
n35_port, ZN => ram_0_2_port);
U166 : OAI22_X1 port map( A1 => n464, A2 => n1225, B1 => n488, B2 =>
n35_port, ZN => ram_0_3_port);
U167 : OAI22_X1 port map( A1 => n464, A2 => n1224, B1 => n487, B2 =>
n35_port, ZN => ram_0_4_port);
U168 : OAI22_X1 port map( A1 => n464, A2 => n1223, B1 => n486, B2 =>
n35_port, ZN => ram_0_5_port);
U169 : OAI22_X1 port map( A1 => n464, A2 => n1222, B1 => n485, B2 =>
n35_port, ZN => ram_0_6_port);
U170 : OAI22_X1 port map( A1 => n464, A2 => n1221, B1 => n484, B2 =>
n35_port, ZN => ram_0_7_port);
U171 : OAI22_X1 port map( A1 => n464, A2 => n1220, B1 => n483, B2 =>
n35_port, ZN => ram_0_8_port);
U172 : OAI22_X1 port map( A1 => n464, A2 => n1219, B1 => n482, B2 =>
n35_port, ZN => ram_0_9_port);
U173 : OAI22_X1 port map( A1 => n464, A2 => n1218, B1 => n481, B2 =>
n35_port, ZN => ram_0_10_port);
U174 : OAI22_X1 port map( A1 => n464, A2 => n1217, B1 => n480, B2 =>
n35_port, ZN => ram_0_11_port);
U175 : OAI22_X1 port map( A1 => n464, A2 => n1216, B1 => n479, B2 =>
n35_port, ZN => ram_0_12_port);
U176 : OAI22_X1 port map( A1 => n464, A2 => n1215, B1 => n478, B2 =>
n35_port, ZN => ram_0_13_port);
U177 : OAI22_X1 port map( A1 => n464, A2 => n1214, B1 => n477, B2 =>
n35_port, ZN => ram_0_14_port);
U178 : OAI22_X1 port map( A1 => n464, A2 => n1213, B1 => n476, B2 =>
n35_port, ZN => ram_0_15_port);
U179 : OAI22_X1 port map( A1 => n464, A2 => n1212, B1 => n475, B2 =>
n35_port, ZN => ram_0_16_port);
U180 : OAI22_X1 port map( A1 => n464, A2 => n1211, B1 => n474, B2 =>
n35_port, ZN => ram_0_17_port);
U181 : OAI22_X1 port map( A1 => n464, A2 => n1210, B1 => n473, B2 =>
n35_port, ZN => ram_0_18_port);
U182 : OAI22_X1 port map( A1 => n462, A2 => n1209, B1 => n487, B2 => n19, ZN
=> ram_4_4_port);
U183 : OAI22_X1 port map( A1 => n462, A2 => n1208, B1 => n486, B2 => n19, ZN
=> ram_4_5_port);
U184 : OAI22_X1 port map( A1 => n462, A2 => n1207, B1 => n485, B2 => n19, ZN
=> ram_4_6_port);
U185 : OAI22_X1 port map( A1 => n462, A2 => n1206, B1 => n484, B2 => n19, ZN
=> ram_4_7_port);
U186 : OAI22_X1 port map( A1 => n462, A2 => n1205, B1 => n483, B2 => n19, ZN
=> ram_4_8_port);
U187 : OAI22_X1 port map( A1 => n462, A2 => n1204, B1 => n482, B2 => n19, ZN
=> ram_4_9_port);
U188 : OAI22_X1 port map( A1 => n462, A2 => n1203, B1 => n481, B2 => n19, ZN
=> ram_4_10_port);
U189 : OAI22_X1 port map( A1 => n462, A2 => n1202, B1 => n480, B2 => n19, ZN
=> ram_4_11_port);
U190 : OAI22_X1 port map( A1 => n462, A2 => n1201, B1 => n479, B2 => n19, ZN
=> ram_4_12_port);
U191 : OAI22_X1 port map( A1 => n462, A2 => n1200, B1 => n478, B2 => n19, ZN
=> ram_4_13_port);
U192 : OAI22_X1 port map( A1 => n462, A2 => n1199, B1 => n477, B2 => n19, ZN
=> ram_4_14_port);
U193 : OAI22_X1 port map( A1 => n462, A2 => n1198, B1 => n476, B2 => n19, ZN
=> ram_4_15_port);
U194 : OAI22_X1 port map( A1 => n462, A2 => n1197, B1 => n475, B2 => n19, ZN
=> ram_4_16_port);
U195 : OAI22_X1 port map( A1 => n462, A2 => n1196, B1 => n474, B2 => n19, ZN
=> ram_4_17_port);
U196 : OAI22_X1 port map( A1 => n462, A2 => n1195, B1 => n473, B2 => n19, ZN
=> ram_4_18_port);
U197 : INV_X1 port map( A => address(2), ZN => n460);
U198 : OAI21_X1 port map( B1 => n461, B2 => n1365, A => n37_port, ZN =>
n1194);
U199 : NAND2_X1 port map( A1 => n461, A2 => N48, ZN => n37_port);
U200 : OAI21_X1 port map( B1 => read_enable, B2 => n1364, A => n38_port, ZN
=> n1193);
U201 : NAND2_X1 port map( A1 => N47, A2 => read_enable, ZN => n38_port);
U202 : OAI21_X1 port map( B1 => read_enable, B2 => n1363, A => n39_port, ZN
=> n1192);
U203 : NAND2_X1 port map( A1 => N46, A2 => read_enable, ZN => n39_port);
U204 : OAI21_X1 port map( B1 => read_enable, B2 => n1362, A => n40_port, ZN
=> n1191);
U205 : NAND2_X1 port map( A1 => N45, A2 => read_enable, ZN => n40_port);
U206 : OAI21_X1 port map( B1 => read_enable, B2 => n1361, A => n41_port, ZN
=> n1190);
U207 : NAND2_X1 port map( A1 => N44, A2 => read_enable, ZN => n41_port);
U208 : OAI21_X1 port map( B1 => read_enable, B2 => n1360, A => n42_port, ZN
=> n1189);
U209 : NAND2_X1 port map( A1 => N43, A2 => read_enable, ZN => n42_port);
U210 : OAI21_X1 port map( B1 => read_enable, B2 => n1359, A => n43_port, ZN
=> n1188);
U211 : NAND2_X1 port map( A1 => N42, A2 => read_enable, ZN => n43_port);
U212 : OAI21_X1 port map( B1 => read_enable, B2 => n1358, A => n44_port, ZN
=> n1187);
U213 : NAND2_X1 port map( A1 => N41, A2 => read_enable, ZN => n44_port);
U214 : OAI21_X1 port map( B1 => read_enable, B2 => n1357, A => n45_port, ZN
=> n1186);
U215 : NAND2_X1 port map( A1 => N40, A2 => n461, ZN => n45_port);
U216 : OAI21_X1 port map( B1 => read_enable, B2 => n1356, A => n46_port, ZN
=> n1185);
U217 : NAND2_X1 port map( A1 => N39, A2 => n461, ZN => n46_port);
U218 : OAI21_X1 port map( B1 => read_enable, B2 => n1355, A => n47_port, ZN
=> n1184);
U219 : NAND2_X1 port map( A1 => N38, A2 => n461, ZN => n47_port);
U220 : OAI21_X1 port map( B1 => read_enable, B2 => n1354, A => n48_port, ZN
=> n1183);
U221 : NAND2_X1 port map( A1 => N37, A2 => n461, ZN => n48_port);
U222 : OAI21_X1 port map( B1 => read_enable, B2 => n1353, A => n49, ZN =>
n1182);
U223 : NAND2_X1 port map( A1 => N36, A2 => n461, ZN => n49);
U224 : OAI21_X1 port map( B1 => n461, B2 => n1352, A => n50, ZN => n1181);
U225 : NAND2_X1 port map( A1 => N35, A2 => n461, ZN => n50);
U226 : OAI21_X1 port map( B1 => n461, B2 => n1351, A => n51, ZN => n1180);
U227 : NAND2_X1 port map( A1 => N34, A2 => read_enable, ZN => n51);
U228 : OAI21_X1 port map( B1 => n461, B2 => n1350, A => n52, ZN => n1179);
U230 : NAND2_X1 port map( A1 => N33, A2 => read_enable, ZN => n52);
U231 : OAI21_X1 port map( B1 => n461, B2 => n1349, A => n53, ZN => n1178);
U232 : NAND2_X1 port map( A1 => N32, A2 => read_enable, ZN => n53);
U233 : OAI21_X1 port map( B1 => n461, B2 => n1348, A => n54, ZN => n1177);
U234 : NAND2_X1 port map( A1 => N31, A2 => read_enable, ZN => n54);
U235 : OAI21_X1 port map( B1 => n461, B2 => n1347, A => n55, ZN => n1176);
U236 : NAND2_X1 port map( A1 => N30, A2 => n461, ZN => n55);
U237 : NOR2_X1 port map( A1 => n460, A2 => address(1), ZN => n1);
U238 : AND2_X1 port map( A1 => n1, A2 => address(0), ZN => n449);
U239 : NOR2_X1 port map( A1 => n460, A2 => n471, ZN => n3);
U240 : AND2_X1 port map( A1 => address(0), A2 => n3, ZN => n448);
U241 : AOI22_X1 port map( A1 => n814, A2 => n449, B1 => n776, B2 => n448, ZN
=> n9);
U242 : NOR2_X1 port map( A1 => address(1), A2 => address(2), ZN => n4);
U243 : AND2_X1 port map( A1 => n4, A2 => address(0), ZN => n451);
U244 : NOR2_X1 port map( A1 => n471, A2 => address(2), ZN => n5);
U245 : AND2_X1 port map( A1 => n5, A2 => address(0), ZN => n450);
U246 : AOI22_X1 port map( A1 => n795, A2 => n451, B1 => n753, B2 => n450, ZN
=> n8);
U247 : AOI22_X1 port map( A1 => n757, A2 => n453, B1 => n715, B2 => n452, ZN
=> n7);
U248 : AOI22_X1 port map( A1 => n696, A2 => n455, B1 => n734, B2 => n454, ZN
=> n6);
U249 : NAND4_X1 port map( A1 => n9, A2 => n8, A3 => n7, A4 => n6, ZN => N48)
;
U250 : AOI22_X1 port map( A1 => n813, A2 => n449, B1 => n775, B2 => n448, ZN
=> n13);
U251 : AOI22_X1 port map( A1 => n794, A2 => n451, B1 => n752, B2 => n450, ZN
=> n12);
U252 : AOI22_X1 port map( A1 => n756, A2 => n453, B1 => n714, B2 => n452, ZN
=> n11);
U253 : AOI22_X1 port map( A1 => n695, A2 => n455, B1 => n733, B2 => n454, ZN
=> n10);
U254 : NAND4_X1 port map( A1 => n13, A2 => n12, A3 => n11, A4 => n10, ZN =>
N47);
U255 : AOI22_X1 port map( A1 => n812, A2 => n449, B1 => n774, B2 => n448, ZN
=> n17);
U256 : AOI22_X1 port map( A1 => n793, A2 => n451, B1 => n751, B2 => n450, ZN
=> n16);
U257 : AOI22_X1 port map( A1 => n755, A2 => n453, B1 => n713, B2 => n452, ZN
=> n15);
U258 : AOI22_X1 port map( A1 => n694, A2 => n455, B1 => n732, B2 => n454, ZN
=> n14);
U259 : NAND4_X1 port map( A1 => n17, A2 => n16, A3 => n15, A4 => n14, ZN =>
N46);
U260 : AOI22_X1 port map( A1 => n811, A2 => n449, B1 => n773, B2 => n448, ZN
=> n22);
U261 : AOI22_X1 port map( A1 => n792, A2 => n451, B1 => n750, B2 => n450, ZN
=> n21);
U262 : AOI22_X1 port map( A1 => n754, A2 => n453, B1 => n712, B2 => n452, ZN
=> n20);
U263 : AOI22_X1 port map( A1 => n693, A2 => n455, B1 => n731, B2 => n454, ZN
=> n18);
U264 : NAND4_X1 port map( A1 => n22, A2 => n21, A3 => n20, A4 => n18, ZN =>
N45);
U265 : AOI22_X1 port map( A1 => n810, A2 => n449, B1 => n772, B2 => n448, ZN
=> n27);
U266 : AOI22_X1 port map( A1 => n791, A2 => n451, B1 => n749, B2 => n450, ZN
=> n25);
U267 : AOI22_X1 port map( A1 => n677, A2 => n453, B1 => n711, B2 => n452, ZN
=> n24);
U268 : AOI22_X1 port map( A1 => n692, A2 => n455, B1 => n730, B2 => n454, ZN
=> n23);
U269 : NAND4_X1 port map( A1 => n27, A2 => n25, A3 => n24, A4 => n23, ZN =>
N44);
U270 : AOI22_X1 port map( A1 => n809, A2 => n449, B1 => n771, B2 => n448, ZN
=> n36_port);
U271 : AOI22_X1 port map( A1 => n790, A2 => n451, B1 => n748, B2 => n450, ZN
=> n34_port);
U272 : AOI22_X1 port map( A1 => n676, A2 => n453, B1 => n710, B2 => n452, ZN
=> n32_port);
U273 : AOI22_X1 port map( A1 => n691, A2 => n455, B1 => n729, B2 => n454, ZN
=> n30_port);
U274 : NAND4_X1 port map( A1 => n36_port, A2 => n34_port, A3 => n32_port, A4
=> n30_port, ZN => N43);
U275 : AOI22_X1 port map( A1 => n808, A2 => n449, B1 => n770, B2 => n448, ZN
=> n403);
U276 : AOI22_X1 port map( A1 => n789, A2 => n451, B1 => n747, B2 => n450, ZN
=> n402);
U277 : AOI22_X1 port map( A1 => n675, A2 => n453, B1 => n709, B2 => n452, ZN
=> n58);
U278 : AOI22_X1 port map( A1 => n690, A2 => n455, B1 => n728, B2 => n454, ZN
=> n56);
U279 : NAND4_X1 port map( A1 => n403, A2 => n402, A3 => n58, A4 => n56, ZN
=> N42);
U280 : AOI22_X1 port map( A1 => n807, A2 => n449, B1 => n769, B2 => n448, ZN
=> n407);
U281 : AOI22_X1 port map( A1 => n788, A2 => n451, B1 => n746, B2 => n450, ZN
=> n406);
U282 : AOI22_X1 port map( A1 => n674, A2 => n453, B1 => n708, B2 => n452, ZN
=> n405);
U283 : AOI22_X1 port map( A1 => n689, A2 => n455, B1 => n727, B2 => n454, ZN
=> n404);
U284 : NAND4_X1 port map( A1 => n407, A2 => n406, A3 => n405, A4 => n404, ZN
=> N41);
U285 : AOI22_X1 port map( A1 => n806, A2 => n449, B1 => n768, B2 => n448, ZN
=> n411);
U286 : AOI22_X1 port map( A1 => n787, A2 => n451, B1 => n745, B2 => n450, ZN
=> n410);
U287 : AOI22_X1 port map( A1 => n673, A2 => n453, B1 => n707, B2 => n452, ZN
=> n409);
U288 : AOI22_X1 port map( A1 => n688, A2 => n455, B1 => n726, B2 => n454, ZN
=> n408);
U289 : NAND4_X1 port map( A1 => n411, A2 => n410, A3 => n409, A4 => n408, ZN
=> N40);
U290 : AOI22_X1 port map( A1 => n805, A2 => n449, B1 => n767, B2 => n448, ZN
=> n415);
U291 : AOI22_X1 port map( A1 => n786, A2 => n451, B1 => n744, B2 => n450, ZN
=> n414);
U292 : AOI22_X1 port map( A1 => n672, A2 => n453, B1 => n706, B2 => n452, ZN
=> n413);
U293 : AOI22_X1 port map( A1 => n687, A2 => n455, B1 => n725, B2 => n454, ZN
=> n412);
U294 : NAND4_X1 port map( A1 => n415, A2 => n414, A3 => n413, A4 => n412, ZN
=> N39);
U295 : AOI22_X1 port map( A1 => n804, A2 => n449, B1 => n766, B2 => n448, ZN
=> n419);
U296 : AOI22_X1 port map( A1 => n785, A2 => n451, B1 => n743, B2 => n450, ZN
=> n418);
U297 : AOI22_X1 port map( A1 => n671, A2 => n453, B1 => n705, B2 => n452, ZN
=> n417);
U298 : AOI22_X1 port map( A1 => n686, A2 => n455, B1 => n724, B2 => n454, ZN
=> n416);
U299 : NAND4_X1 port map( A1 => n419, A2 => n418, A3 => n417, A4 => n416, ZN
=> N38);
U300 : AOI22_X1 port map( A1 => n803, A2 => n449, B1 => n765, B2 => n448, ZN
=> n423);
U301 : AOI22_X1 port map( A1 => n784, A2 => n451, B1 => n742, B2 => n450, ZN
=> n422);
U302 : AOI22_X1 port map( A1 => n670, A2 => n453, B1 => n704, B2 => n452, ZN
=> n421);
U303 : AOI22_X1 port map( A1 => n685, A2 => n455, B1 => n723, B2 => n454, ZN
=> n420);
U304 : NAND4_X1 port map( A1 => n423, A2 => n422, A3 => n421, A4 => n420, ZN
=> N37);
U305 : AOI22_X1 port map( A1 => n802, A2 => n449, B1 => n764, B2 => n448, ZN
=> n427);
U306 : AOI22_X1 port map( A1 => n783, A2 => n451, B1 => n741, B2 => n450, ZN
=> n426);
U307 : AOI22_X1 port map( A1 => n669, A2 => n453, B1 => n703, B2 => n452, ZN
=> n425);
U308 : AOI22_X1 port map( A1 => n684, A2 => n455, B1 => n722, B2 => n454, ZN
=> n424);
U309 : NAND4_X1 port map( A1 => n427, A2 => n426, A3 => n425, A4 => n424, ZN
=> N36);
U310 : AOI22_X1 port map( A1 => n801, A2 => n449, B1 => n763, B2 => n448, ZN
=> n431);
U311 : AOI22_X1 port map( A1 => n782, A2 => n451, B1 => n740, B2 => n450, ZN
=> n430);
U312 : AOI22_X1 port map( A1 => n668, A2 => n453, B1 => n702, B2 => n452, ZN
=> n429);
U313 : AOI22_X1 port map( A1 => n683, A2 => n455, B1 => n721, B2 => n454, ZN
=> n428);
U314 : NAND4_X1 port map( A1 => n431, A2 => n430, A3 => n429, A4 => n428, ZN
=> N35);
U315 : AOI22_X1 port map( A1 => n800, A2 => n449, B1 => n762, B2 => n448, ZN
=> n435);
U316 : AOI22_X1 port map( A1 => n781, A2 => n451, B1 => n739, B2 => n450, ZN
=> n434);
U317 : AOI22_X1 port map( A1 => n667, A2 => n453, B1 => n701, B2 => n452, ZN
=> n433);
U318 : AOI22_X1 port map( A1 => n682, A2 => n455, B1 => n720, B2 => n454, ZN
=> n432);
U319 : NAND4_X1 port map( A1 => n435, A2 => n434, A3 => n433, A4 => n432, ZN
=> N34);
U320 : AOI22_X1 port map( A1 => n799, A2 => n449, B1 => n761, B2 => n448, ZN
=> n439);
U321 : AOI22_X1 port map( A1 => n780, A2 => n451, B1 => n738, B2 => n450, ZN
=> n438);
U322 : AOI22_X1 port map( A1 => n666, A2 => n453, B1 => n700, B2 => n452, ZN
=> n437);
U323 : AOI22_X1 port map( A1 => n681, A2 => n455, B1 => n719, B2 => n454, ZN
=> n436);
U324 : NAND4_X1 port map( A1 => n439, A2 => n438, A3 => n437, A4 => n436, ZN
=> N33);
U325 : AOI22_X1 port map( A1 => n798, A2 => n449, B1 => n760, B2 => n448, ZN
=> n443);
U326 : AOI22_X1 port map( A1 => n779, A2 => n451, B1 => n737, B2 => n450, ZN
=> n442);
U327 : AOI22_X1 port map( A1 => n665, A2 => n453, B1 => n699, B2 => n452, ZN
=> n441);
U328 : AOI22_X1 port map( A1 => n680, A2 => n455, B1 => n718, B2 => n454, ZN
=> n440);
U329 : NAND4_X1 port map( A1 => n443, A2 => n442, A3 => n441, A4 => n440, ZN
=> N32);
U330 : AOI22_X1 port map( A1 => n797, A2 => n449, B1 => n759, B2 => n448, ZN
=> n447);
U331 : AOI22_X1 port map( A1 => n778, A2 => n451, B1 => n736, B2 => n450, ZN
=> n446);
U332 : AOI22_X1 port map( A1 => n664, A2 => n453, B1 => n698, B2 => n452, ZN
=> n445);
U333 : AOI22_X1 port map( A1 => n679, A2 => n455, B1 => n717, B2 => n454, ZN
=> n444);
U334 : NAND4_X1 port map( A1 => n447, A2 => n446, A3 => n445, A4 => n444, ZN
=> N31);
U335 : AOI22_X1 port map( A1 => n796, A2 => n449, B1 => n758, B2 => n448, ZN
=> n459);
U336 : AOI22_X1 port map( A1 => n777, A2 => n451, B1 => n735, B2 => n450, ZN
=> n458);
U337 : AOI22_X1 port map( A1 => n663, A2 => n453, B1 => n697, B2 => n452, ZN
=> n457);
U338 : AOI22_X1 port map( A1 => n678, A2 => n455, B1 => n716, B2 => n454, ZN
=> n456);
U339 : NAND4_X1 port map( A1 => n459, A2 => n458, A3 => n457, A4 => n456, ZN
=> N30);
U340 : INV_X1 port map( A => datain(18), ZN => n473);
clock_r_REG12_S2 : DFF_X1 port map( D => n1194, CK => clock, Q => dataout(0)
, QN => n1365);
clock_r_REG19_S2 : DFF_X1 port map( D => n1193, CK => clock, Q => dataout(1)
, QN => n1364);
clock_r_REG18_S2 : DFF_X1 port map( D => n1192, CK => clock, Q => dataout(2)
, QN => n1363);
clock_r_REG17_S2 : DFF_X1 port map( D => n1191, CK => clock, Q => dataout(3)
, QN => n1362);
clock_r_REG16_S2 : DFF_X1 port map( D => n1190, CK => clock, Q => dataout(4)
, QN => n1361);
clock_r_REG15_S2 : DFF_X1 port map( D => n1189, CK => clock, Q => dataout(5)
, QN => n1360);
clock_r_REG14_S2 : DFF_X1 port map( D => n1188, CK => clock, Q => dataout(6)
, QN => n1359);
clock_r_REG13_S2 : DFF_X1 port map( D => n1187, CK => clock, Q => dataout(7)
, QN => n1358);
clock_r_REG11_S2 : DFF_X1 port map( D => n1186, CK => clock, Q => dataout(8)
, QN => n1357);
clock_r_REG10_S2 : DFF_X1 port map( D => n1185, CK => clock, Q => dataout(9)
, QN => n1356);
clock_r_REG9_S2 : DFF_X1 port map( D => n1184, CK => clock, Q => dataout(10)
, QN => n1355);
clock_r_REG8_S2 : DFF_X1 port map( D => n1183, CK => clock, Q => dataout(11)
, QN => n1354);
clock_r_REG7_S2 : DFF_X1 port map( D => n1182, CK => clock, Q => dataout(12)
, QN => n1353);
clock_r_REG6_S2 : DFF_X1 port map( D => n1181, CK => clock, Q => dataout(13)
, QN => n1352);
clock_r_REG5_S2 : DFF_X1 port map( D => n1180, CK => clock, Q => dataout(14)
, QN => n1351);
clock_r_REG4_S2 : DFF_X1 port map( D => n1179, CK => clock, Q => dataout(15)
, QN => n1350);
clock_r_REG3_S2 : DFF_X1 port map( D => n1178, CK => clock, Q => dataout(16)
, QN => n1349);
clock_r_REG2_S2 : DFF_X1 port map( D => n1177, CK => clock, Q => dataout(17)
, QN => n1348);
clock_r_REG1_S2 : DFF_X1 port map( D => n1176, CK => clock, Q => dataout(18)
, QN => n1347);
clock_r_REG200_S4 : DFF_X1 port map( D => ram_5_0_port, CK => clock, Q =>
n814, QN => n1270);
clock_r_REG191_S4 : DFF_X1 port map( D => ram_5_1_port, CK => clock, Q =>
n813, QN => n1269);
clock_r_REG183_S4 : DFF_X1 port map( D => ram_5_2_port, CK => clock, Q =>
n812, QN => n1268);
clock_r_REG174_S4 : DFF_X1 port map( D => ram_5_3_port, CK => clock, Q =>
n811, QN => n1267);
clock_r_REG165_S4 : DFF_X1 port map( D => ram_5_4_port, CK => clock, Q =>
n810, QN => n1266);
clock_r_REG157_S4 : DFF_X1 port map( D => ram_5_5_port, CK => clock, Q =>
n809, QN => n1265);
clock_r_REG147_S4 : DFF_X1 port map( D => ram_5_6_port, CK => clock, Q =>
n808, QN => n1264);
clock_r_REG138_S4 : DFF_X1 port map( D => ram_5_7_port, CK => clock, Q =>
n807, QN => n1263);
clock_r_REG129_S4 : DFF_X1 port map( D => ram_5_8_port, CK => clock, Q =>
n806, QN => n1262);
clock_r_REG120_S4 : DFF_X1 port map( D => ram_5_9_port, CK => clock, Q =>
n805, QN => n1261);
clock_r_REG110_S4 : DFF_X1 port map( D => ram_5_10_port, CK => clock, Q =>
n804, QN => n1260);
clock_r_REG100_S4 : DFF_X1 port map( D => ram_5_11_port, CK => clock, Q =>
n803, QN => n1259);
clock_r_REG91_S4 : DFF_X1 port map( D => ram_5_12_port, CK => clock, Q =>
n802, QN => n1258);
clock_r_REG81_S4 : DFF_X1 port map( D => ram_5_13_port, CK => clock, Q =>
n801, QN => n1257);
clock_r_REG73_S4 : DFF_X1 port map( D => ram_5_14_port, CK => clock, Q =>
n800, QN => n1256);
clock_r_REG64_S4 : DFF_X1 port map( D => ram_5_15_port, CK => clock, Q =>
n799, QN => n1255);
clock_r_REG55_S4 : DFF_X1 port map( D => ram_5_16_port, CK => clock, Q =>
n798, QN => n1254);
clock_r_REG46_S4 : DFF_X1 port map( D => ram_5_17_port, CK => clock, Q =>
n797, QN => n1253);
clock_r_REG38_S4 : DFF_X1 port map( D => ram_5_18_port, CK => clock, Q =>
n796, QN => n1252);
clock_r_REG199_S4 : DFF_X1 port map( D => ram_1_0_port, CK => clock, Q =>
n795, QN => n1251);
clock_r_REG190_S4 : DFF_X1 port map( D => ram_1_1_port, CK => clock, Q =>
n794, QN => n1250);
clock_r_REG182_S4 : DFF_X1 port map( D => ram_1_2_port, CK => clock, Q =>
n793, QN => n1249);
clock_r_REG173_S4 : DFF_X1 port map( D => ram_1_3_port, CK => clock, Q =>
n792, QN => n1248);
clock_r_REG164_S4 : DFF_X1 port map( D => ram_1_4_port, CK => clock, Q =>
n791, QN => n1247);
clock_r_REG156_S4 : DFF_X1 port map( D => ram_1_5_port, CK => clock, Q =>
n790, QN => n1246);
clock_r_REG146_S4 : DFF_X1 port map( D => ram_1_6_port, CK => clock, Q =>
n789, QN => n1245);
clock_r_REG137_S4 : DFF_X1 port map( D => ram_1_7_port, CK => clock, Q =>
n788, QN => n1244);
clock_r_REG128_S4 : DFF_X1 port map( D => ram_1_8_port, CK => clock, Q =>
n787, QN => n1243);
clock_r_REG119_S4 : DFF_X1 port map( D => ram_1_9_port, CK => clock, Q =>
n786, QN => n1242);
clock_r_REG109_S4 : DFF_X1 port map( D => ram_1_10_port, CK => clock, Q =>
n785, QN => n1241);
clock_r_REG99_S4 : DFF_X1 port map( D => ram_1_11_port, CK => clock, Q =>
n784, QN => n1240);
clock_r_REG90_S4 : DFF_X1 port map( D => ram_1_12_port, CK => clock, Q =>
n783, QN => n1239);
clock_r_REG80_S4 : DFF_X1 port map( D => ram_1_13_port, CK => clock, Q =>
n782, QN => n1238);
clock_r_REG72_S4 : DFF_X1 port map( D => ram_1_14_port, CK => clock, Q =>
n781, QN => n1237);
clock_r_REG63_S4 : DFF_X1 port map( D => ram_1_15_port, CK => clock, Q =>
n780, QN => n1236);
clock_r_REG54_S4 : DFF_X1 port map( D => ram_1_16_port, CK => clock, Q =>
n779, QN => n1235);
clock_r_REG45_S4 : DFF_X1 port map( D => ram_1_17_port, CK => clock, Q =>
n778, QN => n1234);
clock_r_REG37_S4 : DFF_X1 port map( D => ram_1_18_port, CK => clock, Q =>
n777, QN => n1233);
clock_r_REG198_S4 : DFF_X1 port map( D => ram_7_0_port, CK => clock, Q =>
n776, QN => n1346);
clock_r_REG189_S4 : DFF_X1 port map( D => ram_7_1_port, CK => clock, Q =>
n775, QN => n1345);
clock_r_REG181_S4 : DFF_X1 port map( D => ram_7_2_port, CK => clock, Q =>
n774, QN => n1344);
clock_r_REG172_S4 : DFF_X1 port map( D => ram_7_3_port, CK => clock, Q =>
n773, QN => n1343);
clock_r_REG163_S4 : DFF_X1 port map( D => ram_7_4_port, CK => clock, Q =>
n772, QN => n1342);
clock_r_REG155_S4 : DFF_X1 port map( D => ram_7_5_port, CK => clock, Q =>
n771, QN => n1341);
clock_r_REG145_S4 : DFF_X1 port map( D => ram_7_6_port, CK => clock, Q =>
n770, QN => n1340);
clock_r_REG136_S4 : DFF_X1 port map( D => ram_7_7_port, CK => clock, Q =>
n769, QN => n1339);
clock_r_REG127_S4 : DFF_X1 port map( D => ram_7_8_port, CK => clock, Q =>
n768, QN => n1338);
clock_r_REG118_S4 : DFF_X1 port map( D => ram_7_9_port, CK => clock, Q =>
n767, QN => n1337);
clock_r_REG108_S4 : DFF_X1 port map( D => ram_7_10_port, CK => clock, Q =>
n766, QN => n1336);
clock_r_REG98_S4 : DFF_X1 port map( D => ram_7_11_port, CK => clock, Q =>
n765, QN => n1335);
clock_r_REG89_S4 : DFF_X1 port map( D => ram_7_12_port, CK => clock, Q =>
n764, QN => n1334);
clock_r_REG79_S4 : DFF_X1 port map( D => ram_7_13_port, CK => clock, Q =>
n763, QN => n1333);
clock_r_REG71_S4 : DFF_X1 port map( D => ram_7_14_port, CK => clock, Q =>
n762, QN => n1332);
clock_r_REG62_S4 : DFF_X1 port map( D => ram_7_15_port, CK => clock, Q =>
n761, QN => n1331);
clock_r_REG53_S4 : DFF_X1 port map( D => ram_7_16_port, CK => clock, Q =>
n760, QN => n1330);
clock_r_REG44_S4 : DFF_X1 port map( D => ram_7_17_port, CK => clock, Q =>
n759, QN => n1329);
clock_r_REG36_S4 : DFF_X1 port map( D => ram_7_18_port, CK => clock, Q =>
n758, QN => n1328);
clock_r_REG197_S4 : DFF_X1 port map( D => ram_4_0_port, CK => clock, Q =>
n757, QN => n1232);
clock_r_REG188_S4 : DFF_X1 port map( D => ram_4_1_port, CK => clock, Q =>
n756, QN => n1231);
clock_r_REG180_S4 : DFF_X1 port map( D => ram_4_2_port, CK => clock, Q =>
n755, QN => n1230);
clock_r_REG171_S4 : DFF_X1 port map( D => ram_4_3_port, CK => clock, Q =>
n754, QN => n1229);
clock_r_REG196_S4 : DFF_X1 port map( D => ram_3_0_port, CK => clock, Q =>
n753, QN => n1327);
clock_r_REG187_S4 : DFF_X1 port map( D => ram_3_1_port, CK => clock, Q =>
n752, QN => n1326);
clock_r_REG179_S4 : DFF_X1 port map( D => ram_3_2_port, CK => clock, Q =>
n751, QN => n1325);
clock_r_REG170_S4 : DFF_X1 port map( D => ram_3_3_port, CK => clock, Q =>
n750, QN => n1324);
clock_r_REG162_S4 : DFF_X1 port map( D => ram_3_4_port, CK => clock, Q =>
n749, QN => n1323);
clock_r_REG154_S4 : DFF_X1 port map( D => ram_3_5_port, CK => clock, Q =>
n748, QN => n1322);
clock_r_REG144_S4 : DFF_X1 port map( D => ram_3_6_port, CK => clock, Q =>
n747, QN => n1321);
clock_r_REG135_S4 : DFF_X1 port map( D => ram_3_7_port, CK => clock, Q =>
n746, QN => n1320);
clock_r_REG126_S4 : DFF_X1 port map( D => ram_3_8_port, CK => clock, Q =>
n745, QN => n1319);
clock_r_REG117_S4 : DFF_X1 port map( D => ram_3_9_port, CK => clock, Q =>
n744, QN => n1318);
clock_r_REG107_S4 : DFF_X1 port map( D => ram_3_10_port, CK => clock, Q =>
n743, QN => n1317);
clock_r_REG97_S4 : DFF_X1 port map( D => ram_3_11_port, CK => clock, Q =>
n742, QN => n1316);
clock_r_REG88_S4 : DFF_X1 port map( D => ram_3_12_port, CK => clock, Q =>
n741, QN => n1315);
clock_r_REG78_S4 : DFF_X1 port map( D => ram_3_13_port, CK => clock, Q =>
n740, QN => n1314);
clock_r_REG70_S4 : DFF_X1 port map( D => ram_3_14_port, CK => clock, Q =>
n739, QN => n1313);
clock_r_REG61_S4 : DFF_X1 port map( D => ram_3_15_port, CK => clock, Q =>
n738, QN => n1312);
clock_r_REG52_S4 : DFF_X1 port map( D => ram_3_16_port, CK => clock, Q =>
n737, QN => n1311);
clock_r_REG43_S4 : DFF_X1 port map( D => ram_3_17_port, CK => clock, Q =>
n736, QN => n1310);
clock_r_REG35_S4 : DFF_X1 port map( D => ram_3_18_port, CK => clock, Q =>
n735, QN => n1309);
clock_r_REG195_S4 : DFF_X1 port map( D => ram_2_0_port, CK => clock, Q =>
n734, QN => n1308);
clock_r_REG186_S4 : DFF_X1 port map( D => ram_2_1_port, CK => clock, Q =>
n733, QN => n1307);
clock_r_REG178_S4 : DFF_X1 port map( D => ram_2_2_port, CK => clock, Q =>
n732, QN => n1306);
clock_r_REG169_S4 : DFF_X1 port map( D => ram_2_3_port, CK => clock, Q =>
n731, QN => n1305);
clock_r_REG161_S4 : DFF_X1 port map( D => ram_2_4_port, CK => clock, Q =>
n730, QN => n1304);
clock_r_REG153_S4 : DFF_X1 port map( D => ram_2_5_port, CK => clock, Q =>
n729, QN => n1303);
clock_r_REG143_S4 : DFF_X1 port map( D => ram_2_6_port, CK => clock, Q =>
n728, QN => n1302);
clock_r_REG134_S4 : DFF_X1 port map( D => ram_2_7_port, CK => clock, Q =>
n727, QN => n1301);
clock_r_REG125_S4 : DFF_X1 port map( D => ram_2_8_port, CK => clock, Q =>
n726, QN => n1300);
clock_r_REG116_S4 : DFF_X1 port map( D => ram_2_9_port, CK => clock, Q =>
n725, QN => n1299);
clock_r_REG106_S4 : DFF_X1 port map( D => ram_2_10_port, CK => clock, Q =>
n724, QN => n1298);
clock_r_REG96_S4 : DFF_X1 port map( D => ram_2_11_port, CK => clock, Q =>
n723, QN => n1297);
clock_r_REG87_S4 : DFF_X1 port map( D => ram_2_12_port, CK => clock, Q =>
n722, QN => n1296);
clock_r_REG77_S4 : DFF_X1 port map( D => ram_2_13_port, CK => clock, Q =>
n721, QN => n1295);
clock_r_REG69_S4 : DFF_X1 port map( D => ram_2_14_port, CK => clock, Q =>
n720, QN => n1294);
clock_r_REG60_S4 : DFF_X1 port map( D => ram_2_15_port, CK => clock, Q =>
n719, QN => n1293);
clock_r_REG51_S4 : DFF_X1 port map( D => ram_2_16_port, CK => clock, Q =>
n718, QN => n1292);
clock_r_REG42_S4 : DFF_X1 port map( D => ram_2_17_port, CK => clock, Q =>
n717, QN => n1291);
clock_r_REG34_S4 : DFF_X1 port map( D => ram_2_18_port, CK => clock, Q =>
n716, QN => n1290);
clock_r_REG194_S4 : DFF_X1 port map( D => ram_6_0_port, CK => clock, Q =>
n715, QN => n1289);
clock_r_REG185_S4 : DFF_X1 port map( D => ram_6_1_port, CK => clock, Q =>
n714, QN => n1288);
clock_r_REG177_S4 : DFF_X1 port map( D => ram_6_2_port, CK => clock, Q =>
n713, QN => n1287);
clock_r_REG168_S4 : DFF_X1 port map( D => ram_6_3_port, CK => clock, Q =>
n712, QN => n1286);
clock_r_REG160_S4 : DFF_X1 port map( D => ram_6_4_port, CK => clock, Q =>
n711, QN => n1285);
clock_r_REG152_S4 : DFF_X1 port map( D => ram_6_5_port, CK => clock, Q =>
n710, QN => n1284);
clock_r_REG142_S4 : DFF_X1 port map( D => ram_6_6_port, CK => clock, Q =>
n709, QN => n1283);
clock_r_REG133_S4 : DFF_X1 port map( D => ram_6_7_port, CK => clock, Q =>
n708, QN => n1282);
clock_r_REG124_S4 : DFF_X1 port map( D => ram_6_8_port, CK => clock, Q =>
n707, QN => n1281);
clock_r_REG115_S4 : DFF_X1 port map( D => ram_6_9_port, CK => clock, Q =>
n706, QN => n1280);
clock_r_REG105_S4 : DFF_X1 port map( D => ram_6_10_port, CK => clock, Q =>
n705, QN => n1279);
clock_r_REG95_S4 : DFF_X1 port map( D => ram_6_11_port, CK => clock, Q =>
n704, QN => n1278);
clock_r_REG86_S4 : DFF_X1 port map( D => ram_6_12_port, CK => clock, Q =>
n703, QN => n1277);
clock_r_REG76_S4 : DFF_X1 port map( D => ram_6_13_port, CK => clock, Q =>
n702, QN => n1276);
clock_r_REG68_S4 : DFF_X1 port map( D => ram_6_14_port, CK => clock, Q =>
n701, QN => n1275);
clock_r_REG59_S4 : DFF_X1 port map( D => ram_6_15_port, CK => clock, Q =>
n700, QN => n1274);
clock_r_REG50_S4 : DFF_X1 port map( D => ram_6_16_port, CK => clock, Q =>
n699, QN => n1273);
clock_r_REG41_S4 : DFF_X1 port map( D => ram_6_17_port, CK => clock, Q =>
n698, QN => n1272);
clock_r_REG33_S4 : DFF_X1 port map( D => ram_6_18_port, CK => clock, Q =>
n697, QN => n1271);
clock_r_REG193_S4 : DFF_X1 port map( D => ram_0_0_port, CK => clock, Q =>
n696, QN => n1228);
clock_r_REG184_S4 : DFF_X1 port map( D => ram_0_1_port, CK => clock, Q =>
n695, QN => n1227);
clock_r_REG176_S4 : DFF_X1 port map( D => ram_0_2_port, CK => clock, Q =>
n694, QN => n1226);
clock_r_REG167_S4 : DFF_X1 port map( D => ram_0_3_port, CK => clock, Q =>
n693, QN => n1225);
clock_r_REG159_S4 : DFF_X1 port map( D => ram_0_4_port, CK => clock, Q =>
n692, QN => n1224);
clock_r_REG151_S4 : DFF_X1 port map( D => ram_0_5_port, CK => clock, Q =>
n691, QN => n1223);
clock_r_REG141_S4 : DFF_X1 port map( D => ram_0_6_port, CK => clock, Q =>
n690, QN => n1222);
clock_r_REG132_S4 : DFF_X1 port map( D => ram_0_7_port, CK => clock, Q =>
n689, QN => n1221);
clock_r_REG123_S4 : DFF_X1 port map( D => ram_0_8_port, CK => clock, Q =>
n688, QN => n1220);
clock_r_REG114_S4 : DFF_X1 port map( D => ram_0_9_port, CK => clock, Q =>
n687, QN => n1219);
clock_r_REG104_S4 : DFF_X1 port map( D => ram_0_10_port, CK => clock, Q =>
n686, QN => n1218);
clock_r_REG94_S4 : DFF_X1 port map( D => ram_0_11_port, CK => clock, Q =>
n685, QN => n1217);
clock_r_REG85_S4 : DFF_X1 port map( D => ram_0_12_port, CK => clock, Q =>
n684, QN => n1216);
clock_r_REG75_S4 : DFF_X1 port map( D => ram_0_13_port, CK => clock, Q =>
n683, QN => n1215);
clock_r_REG67_S4 : DFF_X1 port map( D => ram_0_14_port, CK => clock, Q =>
n682, QN => n1214);
clock_r_REG58_S4 : DFF_X1 port map( D => ram_0_15_port, CK => clock, Q =>
n681, QN => n1213);
clock_r_REG49_S4 : DFF_X1 port map( D => ram_0_16_port, CK => clock, Q =>
n680, QN => n1212);
clock_r_REG40_S4 : DFF_X1 port map( D => ram_0_17_port, CK => clock, Q =>
n679, QN => n1211);
clock_r_REG32_S4 : DFF_X1 port map( D => ram_0_18_port, CK => clock, Q =>
n678, QN => n1210);
clock_r_REG158_S4 : DFF_X1 port map( D => ram_4_4_port, CK => clock, Q =>
n677, QN => n1209);
clock_r_REG150_S4 : DFF_X1 port map( D => ram_4_5_port, CK => clock, Q =>
n676, QN => n1208);
clock_r_REG140_S4 : DFF_X1 port map( D => ram_4_6_port, CK => clock, Q =>
n675, QN => n1207);
clock_r_REG131_S4 : DFF_X1 port map( D => ram_4_7_port, CK => clock, Q =>
n674, QN => n1206);
clock_r_REG122_S4 : DFF_X1 port map( D => ram_4_8_port, CK => clock, Q =>
n673, QN => n1205);
clock_r_REG113_S4 : DFF_X1 port map( D => ram_4_9_port, CK => clock, Q =>
n672, QN => n1204);
clock_r_REG103_S4 : DFF_X1 port map( D => ram_4_10_port, CK => clock, Q =>
n671, QN => n1203);
clock_r_REG93_S4 : DFF_X1 port map( D => ram_4_11_port, CK => clock, Q =>
n670, QN => n1202);
clock_r_REG84_S4 : DFF_X1 port map( D => ram_4_12_port, CK => clock, Q =>
n669, QN => n1201);
clock_r_REG74_S4 : DFF_X1 port map( D => ram_4_13_port, CK => clock, Q =>
n668, QN => n1200);
clock_r_REG66_S4 : DFF_X1 port map( D => ram_4_14_port, CK => clock, Q =>
n667, QN => n1199);
clock_r_REG57_S4 : DFF_X1 port map( D => ram_4_15_port, CK => clock, Q =>
n666, QN => n1198);
clock_r_REG48_S4 : DFF_X1 port map( D => ram_4_16_port, CK => clock, Q =>
n665, QN => n1197);
clock_r_REG39_S4 : DFF_X1 port map( D => ram_4_17_port, CK => clock, Q =>
n664, QN => n1196);
clock_r_REG31_S4 : DFF_X1 port map( D => ram_4_18_port, CK => clock, Q =>
n663, QN => n1195);
U13 : NAND3_X1 port map( A1 => n466, A2 => n471, A3 => n29, ZN => n35_port);
U23 : NAND3_X1 port map( A1 => n29, A2 => address(0), A3 => address(1), ZN
=> n28);
U24 : NAND3_X1 port map( A1 => n29, A2 => n466, A3 => address(1), ZN =>
n31_port);
U21 : NAND3_X1 port map( A1 => address(0), A2 => n471, A3 => n29, ZN =>
n33_port);
end SYN_ramR;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_1 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_1;
architecture SYN_counter_address_generator of counter_address_generator_1 is
component counter_address_generator_1_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n61, n62, n63, n64, n65, n66, n67, n68, N10, N11, N12, N13, N14, N15,
N16, N17, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
address_0_port, address_1_port, address_2_port, address_3_port,
address_4_port, address_5_port, address_6_port, address_7_port, n_1038,
n_1039, n_1040, n_1041, n_1042, n_1043, n_1044, n_1045 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n26, ZN =>
n27);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n26);
U5 : INV_X1 port map( A => n28, ZN => n61);
U6 : AOI22_X1 port map( A1 => N17, A2 => n27, B1 => address_7_port, B2 =>
n26, ZN => n28);
U7 : INV_X1 port map( A => n25, ZN => n62);
U8 : AOI22_X1 port map( A1 => N16, A2 => n27, B1 => address_6_port, B2 =>
n26, ZN => n25);
U9 : INV_X1 port map( A => n24, ZN => n63);
U10 : AOI22_X1 port map( A1 => N15, A2 => n27, B1 => address_5_port, B2 =>
n26, ZN => n24);
U11 : INV_X1 port map( A => n23, ZN => n64);
U12 : AOI22_X1 port map( A1 => N14, A2 => n27, B1 => address_4_port, B2 =>
n26, ZN => n23);
U13 : INV_X1 port map( A => n22, ZN => n65);
U14 : AOI22_X1 port map( A1 => N13, A2 => n27, B1 => address_3_port, B2 =>
n26, ZN => n22);
U15 : INV_X1 port map( A => n21, ZN => n66);
U16 : AOI22_X1 port map( A1 => N12, A2 => n27, B1 => address_2_port, B2 =>
n26, ZN => n21);
U17 : INV_X1 port map( A => n20, ZN => n67);
U18 : AOI22_X1 port map( A1 => N11, A2 => n27, B1 => address_1_port, B2 =>
n26, ZN => n20);
U19 : INV_X1 port map( A => n19, ZN => n68);
U20 : AOI22_X1 port map( A1 => N10, A2 => n27, B1 => address_0_port, B2 =>
n26, ZN => n19);
clock_r_REG306_S2 : DFF_X1 port map( D => n61, CK => clock, Q =>
address_7_port, QN => n_1038);
clock_r_REG305_S2 : DFF_X1 port map( D => n62, CK => clock, Q =>
address_6_port, QN => n_1039);
clock_r_REG304_S2 : DFF_X1 port map( D => n63, CK => clock, Q =>
address_5_port, QN => n_1040);
clock_r_REG303_S2 : DFF_X1 port map( D => n64, CK => clock, Q =>
address_4_port, QN => n_1041);
clock_r_REG302_S2 : DFF_X1 port map( D => n65, CK => clock, Q =>
address_3_port, QN => n_1042);
clock_r_REG301_S2 : DFF_X1 port map( D => n66, CK => clock, Q =>
address_2_port, QN => n_1043);
clock_r_REG300_S2 : DFF_X1 port map( D => n67, CK => clock, Q =>
address_1_port, QN => n_1044);
clock_r_REG20_S2 : DFF_X1 port map( D => n68, CK => clock, Q =>
address_0_port, QN => n_1045);
add_38 : counter_address_generator_1_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity fsm is
port( clock, reset : in std_logic; ramA_address : in std_logic_vector (4
downto 0); ramR_address, rom_address : in std_logic_vector (7 downto
0); hold_me : in std_logic; ramR_readEnable, ramA_writeEnable,
ramA_readEnable, ramR_writeEnable, rom_enable,
counterAddressGen_H_enable, counterAddressGen_R_enable,
counterAddressGen_A_restart, counterAddressGen_R_restart,
counterAddressGen_H_restart, mac_clean, reset_fsm, hold_prev : out
std_logic);
end fsm;
architecture SYN_fsm of fsm is
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NAND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal ramA_readEnable_port, status_1_port, status_0_port, n20, n22, n26,
n27, n31, n32, n33, n34, n35, n37, counterAddressGen_A_restart_port, n2,
n4, n5, n6, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n21, n24,
n25, n28, n30, n36, n38, n39, n40, n41, n43, n44, n48, n49, n50, n57, n58
, n59 : std_logic;
begin
ramA_readEnable <= ramA_readEnable_port;
ramR_writeEnable <= n5;
rom_enable <= ramA_readEnable_port;
counterAddressGen_A_restart <= counterAddressGen_A_restart_port;
counterAddressGen_R_restart <= counterAddressGen_A_restart_port;
counterAddressGen_H_restart <= counterAddressGen_A_restart_port;
reset_fsm <= counterAddressGen_A_restart_port;
U46 : NAND3_X1 port map( A1 => rom_address(1), A2 => n41, A3 => n33, ZN =>
n32);
U3 : NAND2_X1 port map( A1 => n4, A2 => n38, ZN =>
counterAddressGen_A_restart_port);
U5 : INV_X1 port map( A => n26, ZN => n40);
U7 : OR2_X1 port map( A1 => n58, A2 => n59, ZN => n4);
U8 : NAND2_X1 port map( A1 => n4, A2 => n38, ZN => n43);
U9 : OR2_X1 port map( A1 => n28, A2 => n58, ZN => n30);
U10 : NOR2_X1 port map( A1 => n28, A2 => n58, ZN => n5);
U11 : INV_X1 port map( A => n34, ZN => n41);
U12 : NOR3_X1 port map( A1 => rom_address(5), A2 => rom_address(4), A3 =>
rom_address(3), ZN => n34);
U13 : NOR3_X1 port map( A1 => ramA_address(1), A2 => ramA_address(0), A3 =>
n37, ZN => n27);
U14 : OR3_X1 port map( A1 => ramA_address(4), A2 => ramA_address(3), A3 =>
ramA_address(2), ZN => n37);
U15 : AOI21_X1 port map( B1 => n26, B2 => n32, A => rom_address(0), ZN =>
n31);
U16 : NOR3_X1 port map( A1 => rom_address(2), A2 => rom_address(7), A3 =>
rom_address(6), ZN => n33);
U17 : NAND4_X1 port map( A1 => rom_address(6), A2 => rom_address(1), A3 =>
n35, A4 => n34, ZN => n26);
U18 : NOR2_X1 port map( A1 => rom_address(7), A2 => rom_address(2), ZN =>
n35);
U19 : AND3_X1 port map( A1 => ramR_address(0), A2 => n44, A3 =>
ramR_address(1), ZN => n20);
U20 : INV_X1 port map( A => hold_me, ZN => n44);
U21 : AND2_X1 port map( A1 => n40, A2 => rom_address(0), ZN => n6);
U22 : OR2_X1 port map( A1 => ramR_address(5), A2 => ramR_address(4), ZN =>
n22);
U25 : AOI22_X1 port map( A1 => n27, A2 => n58, B1 => n31, B2 => n57, ZN =>
n11);
U26 : NAND3_X1 port map( A1 => hold_me, A2 => n49, A3 => n58, ZN => n10);
U27 : NAND3_X1 port map( A1 => n58, A2 => n57, A3 => n59, ZN => n38);
U28 : OAI211_X1 port map( C1 => n49, C2 => n11, A => n10, B => n38, ZN =>
n13);
U29 : INV_X1 port map( A => reset, ZN => n12);
U30 : AND2_X1 port map( A1 => n13, A2 => n12, ZN => status_0_port);
U31 : NAND2_X1 port map( A1 => n59, A2 => n50, ZN => n28);
U33 : NAND4_X1 port map( A1 => ramR_address(3), A2 => n20, A3 =>
ramR_address(2), A4 => n57, ZN => n14);
U34 : NOR4_X1 port map( A1 => n14, A2 => n22, A3 => ramR_address(7), A4 =>
ramR_address(6), ZN => n15);
U35 : NOR3_X1 port map( A1 => n15, A2 => n48, A3 => n59, ZN => n16);
U36 : AOI21_X1 port map( B1 => n6, B2 => n5, A => n16, ZN => n17);
U37 : NOR2_X1 port map( A1 => reset, A2 => n17, ZN => n2);
U38 : INV_X1 port map( A => n27, ZN => n18);
U39 : NAND3_X1 port map( A1 => n58, A2 => n18, A3 => n50, ZN => n19);
U40 : OAI21_X1 port map( B1 => n58, B2 => n6, A => n19, ZN => n21);
U41 : NAND2_X1 port map( A1 => n59, A2 => n21, ZN => n24);
U42 : NAND3_X1 port map( A1 => n48, A2 => n57, A3 => n59, ZN => n25);
U43 : AOI21_X1 port map( B1 => n24, B2 => n25, A => reset, ZN =>
status_1_port);
U44 : NAND2_X1 port map( A1 => n25, A2 => n30, ZN => ramA_readEnable_port);
U45 : INV_X1 port map( A => ramA_readEnable_port, ZN => n36);
U47 : NAND2_X1 port map( A1 => n28, A2 => n36, ZN => hold_prev);
U48 : NAND3_X1 port map( A1 => n57, A2 => n49, A3 => n58, ZN => n39);
U49 : NAND3_X1 port map( A1 => n30, A2 => n38, A3 => n39, ZN =>
counterAddressGen_R_enable);
U50 : NAND2_X1 port map( A1 => n38, A2 => n36, ZN =>
counterAddressGen_H_enable);
U51 : NAND3_X1 port map( A1 => n48, A2 => n38, A3 => n59, ZN =>
ramA_writeEnable);
U52 : INV_X1 port map( A => n39, ZN => ramR_readEnable);
clock_r_REG23_S2 : DFF_X1 port map( D => status_0_port, CK => clock, Q =>
n50, QN => n57);
clock_r_REG21_S1 : DFF_X1 port map( D => n2, CK => clock, Q => n49, QN =>
n59);
clock_r_REG0_S1 : DFF_X1 port map( D => status_1_port, CK => clock, Q => n48
, QN => n58);
U4 : OR2_X1 port map( A1 => n43, A2 => n5, ZN => mac_clean);
end SYN_fsm;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac is
port( clock : in std_logic; ai, xi : in std_logic_vector (7 downto 0);
mac_clean : in std_logic; data_out : out std_logic_vector (18 downto
0));
end mac;
architecture SYN_multiplier_accumulator_implentation of mac is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component mac_DW_mult_tc_1
port( a, b : in std_logic_vector (7 downto 0); product : out
std_logic_vector (15 downto 0); clock : in std_logic);
end component;
component mac_DW01_add_1
port( A, B : in std_logic_vector (18 downto 0); CI : in std_logic; SUM
: out std_logic_vector (18 downto 0); CO : out std_logic; clock :
in std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n164, n165, n166, n167, n168, n169, n170, data_out_18_port,
data_out_17_port, data_out_16_port, data_out_15_port, data_out_14_port,
data_out_13_port, data_out_12_port, data_out_11_port, data_out_10_port,
data_out_9_port, data_out_8_port, n147, n148, n149, n150, n151, n152,
n153, n154, mult_out_14_port, mult_out_13_port, mult_out_12_port,
mult_out_11_port, mult_out_10_port, mult_out_9_port, mult_out_8_port,
mult_out_7_port, mult_out_6_port, mult_out_5_port, mult_out_4_port,
mult_out_3_port, mult_out_2_port, mult_out_1_port, mult_out_0_port,
mult_out_reg_15_port, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29,
N30, N31, N32, N33, N34, N35, N36, N37, N38, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, data_out_0_port, data_out_1_port, data_out_2_port
, data_out_3_port, data_out_4_port, data_out_5_port, data_out_6_port,
data_out_7_port, n38_port, n156, n157, n158, n159, n160, n161, n162, n163
, n_1053, n_1054, n_1055 : std_logic;
begin
data_out <= ( data_out_18_port, data_out_17_port, data_out_16_port,
data_out_15_port, data_out_14_port, data_out_13_port, data_out_12_port,
data_out_11_port, data_out_10_port, data_out_9_port, data_out_8_port,
data_out_7_port, data_out_6_port, data_out_5_port, data_out_4_port,
data_out_3_port, data_out_2_port, data_out_1_port, data_out_0_port );
n2 <= '0';
U3 : NOR2_X1 port map( A1 => mac_clean, A2 => n3, ZN => N38);
U5 : NOR2_X1 port map( A1 => mac_clean, A2 => n4, ZN => N37);
U6 : NOR2_X1 port map( A1 => mac_clean, A2 => n5, ZN => N36);
U7 : NOR2_X1 port map( A1 => mac_clean, A2 => n6, ZN => N35);
U8 : NOR2_X1 port map( A1 => mac_clean, A2 => n7, ZN => N34);
U9 : NOR2_X1 port map( A1 => mac_clean, A2 => n8, ZN => N33);
U10 : NOR2_X1 port map( A1 => mac_clean, A2 => n9, ZN => N32);
U11 : NOR2_X1 port map( A1 => mac_clean, A2 => n10, ZN => N31);
U12 : NOR2_X1 port map( A1 => mac_clean, A2 => n11, ZN => N30);
U13 : NOR2_X1 port map( A1 => mac_clean, A2 => n12, ZN => N29);
U14 : NOR2_X1 port map( A1 => mac_clean, A2 => n13, ZN => N28);
U15 : NOR2_X1 port map( A1 => mac_clean, A2 => n163, ZN => N27);
U16 : NOR2_X1 port map( A1 => mac_clean, A2 => n162, ZN => N26);
U17 : NOR2_X1 port map( A1 => mac_clean, A2 => n161, ZN => N25);
U18 : NOR2_X1 port map( A1 => mac_clean, A2 => n160, ZN => N24);
U19 : NOR2_X1 port map( A1 => mac_clean, A2 => n159, ZN => N23);
U20 : NOR2_X1 port map( A1 => mac_clean, A2 => n158, ZN => N22);
U21 : NOR2_X1 port map( A1 => mac_clean, A2 => n157, ZN => N21);
U22 : NOR2_X1 port map( A1 => mac_clean, A2 => n156, ZN => N20);
clock_r_REG130_S3 : DFF_X1 port map( D => n147, CK => clock, Q =>
data_out_7_port, QN => n163);
clock_r_REG139_S3 : DFF_X1 port map( D => n148, CK => clock, Q =>
data_out_6_port, QN => n162);
clock_r_REG149_S3 : DFF_X1 port map( D => n149, CK => clock, Q =>
data_out_5_port, QN => n161);
clock_r_REG148_S3 : DFF_X1 port map( D => n150, CK => clock, Q =>
data_out_4_port, QN => n160);
clock_r_REG166_S3 : DFF_X1 port map( D => n151, CK => clock, Q =>
data_out_3_port, QN => n159);
clock_r_REG175_S3 : DFF_X1 port map( D => n152, CK => clock, Q =>
data_out_2_port, QN => n158);
clock_r_REG24_S3 : DFF_X1 port map( D => n153, CK => clock, Q =>
data_out_1_port, QN => n157);
clock_r_REG192_S3 : DFF_X1 port map( D => n154, CK => clock, Q =>
data_out_0_port, QN => n156);
U31 : INV_X1 port map( A => data_out_8_port, ZN => n13);
U32 : INV_X1 port map( A => data_out_9_port, ZN => n12);
U33 : INV_X1 port map( A => data_out_10_port, ZN => n11);
U34 : INV_X1 port map( A => data_out_11_port, ZN => n10);
U35 : INV_X1 port map( A => data_out_12_port, ZN => n9);
U36 : INV_X1 port map( A => data_out_13_port, ZN => n8);
U37 : INV_X1 port map( A => data_out_14_port, ZN => n7);
U38 : INV_X1 port map( A => data_out_15_port, ZN => n6);
U39 : INV_X1 port map( A => data_out_16_port, ZN => n5);
U41 : INV_X1 port map( A => data_out_18_port, ZN => n3);
add_37_aco : mac_DW01_add_1 port map( A(18) => N38, A(17) => N37, A(16) =>
N36, A(15) => N35, A(14) => N34, A(13) => N33, A(12)
=> N32, A(11) => N31, A(10) => N30, A(9) => N29,
A(8) => N28, A(7) => N27, A(6) => N26, A(5) => N25,
A(4) => N24, A(3) => N23, A(2) => N22, A(1) => N21,
A(0) => N20, B(18) => n38_port, B(17) => n38_port,
B(16) => n38_port, B(15) => n38_port, B(14) =>
mult_out_14_port, B(13) => mult_out_13_port, B(12)
=> mult_out_12_port, B(11) => mult_out_11_port,
B(10) => mult_out_10_port, B(9) => mult_out_9_port,
B(8) => mult_out_8_port, B(7) => mult_out_7_port,
B(6) => mult_out_6_port, B(5) => mult_out_5_port,
B(4) => mult_out_4_port, B(3) => mult_out_3_port,
B(2) => mult_out_2_port, B(1) => mult_out_1_port,
B(0) => mult_out_0_port, CI => n2, SUM(18) =>
data_out_18_port, SUM(17) => data_out_17_port,
SUM(16) => data_out_16_port, SUM(15) =>
data_out_15_port, SUM(14) => data_out_14_port,
SUM(13) => data_out_13_port, SUM(12) =>
data_out_12_port, SUM(11) => data_out_11_port,
SUM(10) => data_out_10_port, SUM(9) =>
data_out_9_port, SUM(8) => data_out_8_port, SUM(7)
=> n147, SUM(6) => n148, SUM(5) => n149, SUM(4) =>
n150, SUM(3) => n151, SUM(2) => n152, SUM(1) => n153
, SUM(0) => n154, CO => n_1053, clock => clock);
mult_32 : mac_DW_mult_tc_1 port map( a(7) => ai(7), a(6) => ai(6), a(5) =>
ai(5), a(4) => ai(4), a(3) => ai(3), a(2) => ai(2),
a(1) => ai(1), a(0) => ai(0), b(7) => xi(7), b(6) =>
n164, b(5) => n165, b(4) => n166, b(3) => n167, b(2)
=> n168, b(1) => n169, b(0) => n170, product(15) =>
mult_out_reg_15_port, product(14) =>
mult_out_14_port, product(13) => mult_out_13_port,
product(12) => mult_out_12_port, product(11) =>
mult_out_11_port, product(10) => mult_out_10_port,
product(9) => mult_out_9_port, product(8) =>
mult_out_8_port, product(7) => mult_out_7_port,
product(6) => mult_out_6_port, product(5) =>
mult_out_5_port, product(4) => mult_out_4_port,
product(3) => mult_out_3_port, product(2) =>
mult_out_2_port, product(1) => mult_out_1_port,
product(0) => n_1054, clock => clock);
clock_r_REG206_S6 : DFF_X1 port map( D => mult_out_reg_15_port, CK => clock,
Q => n38_port, QN => n_1055);
U23 : INV_X1 port map( A => data_out_17_port, ZN => n4);
mult_out_0_port <= '0';
n170 <= '0';
n169 <= '0';
n168 <= '0';
n167 <= '0';
n166 <= '0';
n165 <= '0';
n164 <= '0';
end SYN_multiplier_accumulator_implentation;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity rom is
port( clock : in std_logic; address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic; data : out std_logic_vector (7 downto 0));
end rom;
architecture SYN_rom of rom is
signal n_1063, n_1064, n_1065, n_1066, n_1067, n_1068, n_1069 : std_logic;
begin
data <= ( rom_enable, n_1063, n_1064, n_1065, n_1066, n_1067, n_1068, n_1069
);
end SYN_rom;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_2 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_2;
architecture SYN_counter_address_generator of counter_address_generator_2 is
component counter_address_generator_2_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n61, n62, n63, n64, n65, n66, n67, n68, N10, N11, N12, N13, N14, N15,
N16, N17, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
address_0_port, address_1_port, address_2_port, address_3_port,
address_4_port, address_5_port, address_6_port, address_7_port, n_1070,
n_1071, n_1072, n_1073, n_1074, n_1075, n_1076, n_1077 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n26, ZN =>
n27);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n26);
U5 : INV_X1 port map( A => n28, ZN => n61);
U6 : AOI22_X1 port map( A1 => N17, A2 => n27, B1 => address_7_port, B2 =>
n26, ZN => n28);
U7 : INV_X1 port map( A => n25, ZN => n62);
U8 : AOI22_X1 port map( A1 => N16, A2 => n27, B1 => address_6_port, B2 =>
n26, ZN => n25);
U9 : INV_X1 port map( A => n24, ZN => n63);
U10 : AOI22_X1 port map( A1 => N15, A2 => n27, B1 => address_5_port, B2 =>
n26, ZN => n24);
U11 : INV_X1 port map( A => n23, ZN => n64);
U12 : AOI22_X1 port map( A1 => N14, A2 => n27, B1 => address_4_port, B2 =>
n26, ZN => n23);
U13 : INV_X1 port map( A => n22, ZN => n65);
U14 : AOI22_X1 port map( A1 => N13, A2 => n27, B1 => address_3_port, B2 =>
n26, ZN => n22);
U15 : INV_X1 port map( A => n21, ZN => n66);
U16 : AOI22_X1 port map( A1 => N12, A2 => n27, B1 => address_2_port, B2 =>
n26, ZN => n21);
U17 : INV_X1 port map( A => n20, ZN => n67);
U18 : AOI22_X1 port map( A1 => N11, A2 => n27, B1 => address_1_port, B2 =>
n26, ZN => n20);
U19 : INV_X1 port map( A => n19, ZN => n68);
U20 : AOI22_X1 port map( A1 => N10, A2 => n27, B1 => address_0_port, B2 =>
n26, ZN => n19);
clock_r_REG313_S2 : DFF_X1 port map( D => n61, CK => clock, Q =>
address_7_port, QN => n_1070);
clock_r_REG312_S2 : DFF_X1 port map( D => n62, CK => clock, Q =>
address_6_port, QN => n_1071);
clock_r_REG311_S2 : DFF_X1 port map( D => n63, CK => clock, Q =>
address_5_port, QN => n_1072);
clock_r_REG310_S2 : DFF_X1 port map( D => n64, CK => clock, Q =>
address_4_port, QN => n_1073);
clock_r_REG309_S2 : DFF_X1 port map( D => n65, CK => clock, Q =>
address_3_port, QN => n_1074);
clock_r_REG308_S2 : DFF_X1 port map( D => n66, CK => clock, Q =>
address_2_port, QN => n_1075);
clock_r_REG307_S2 : DFF_X1 port map( D => n67, CK => clock, Q =>
address_1_port, QN => n_1076);
clock_r_REG22_S2 : DFF_X1 port map( D => n68, CK => clock, Q =>
address_0_port, QN => n_1077);
add_38 : counter_address_generator_2_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity ramA is
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (7 downto
0); dataout : out std_logic_vector (7 downto 0));
end ramA;
architecture SYN_ramA of ramA is
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AOI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n511, n512, n513, n514, n222, n515, n516, n517, ram_0_7_port,
ram_0_6_port, ram_0_5_port, ram_0_4_port, ram_0_3_port, ram_0_2_port,
ram_0_1_port, ram_0_0_port, ram_1_7_port, ram_1_6_port, ram_1_5_port,
ram_1_4_port, ram_1_3_port, ram_1_2_port, ram_1_1_port, ram_1_0_port,
ram_2_7_port, ram_2_6_port, ram_2_5_port, ram_2_4_port, ram_2_3_port,
ram_2_2_port, ram_2_1_port, ram_2_0_port, ram_3_7_port, ram_3_6_port,
ram_3_5_port, ram_3_4_port, ram_3_3_port, ram_3_2_port, ram_3_1_port,
ram_3_0_port, ram_4_7_port, ram_4_6_port, ram_4_5_port, ram_4_4_port,
ram_4_3_port, ram_4_2_port, ram_4_1_port, ram_4_0_port, ram_5_7_port,
ram_5_6_port, ram_5_5_port, ram_5_4_port, ram_5_3_port, ram_5_2_port,
ram_5_1_port, ram_5_0_port, ram_6_7_port, ram_6_6_port, ram_6_5_port,
ram_6_4_port, ram_6_3_port, ram_6_2_port, ram_6_1_port, ram_6_0_port,
ram_7_7_port, ram_7_6_port, ram_7_5_port, ram_7_4_port, ram_7_3_port,
ram_7_2_port, ram_7_1_port, ram_7_0_port, N33, N34, N35, N36, N37, N38,
N39, N40, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32
, n33_port, n34_port, n35_port, n36_port, n37_port, n38_port, n39_port,
n40_port, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53
, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82
, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n100, n101, n102
, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n94, n95, n96, n97, n98, n99, n167, n168, n169, n170, n171
, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n199, n200, n201, n202, n203, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, dataout_4_port, n360,
dataout_2_port, dataout_1_port, dataout_0_port, dataout_5_port,
dataout_7_port, dataout_6_port, n_1078, n_1079, n_1080, n_1081, n_1082,
n_1083, n_1084, n_1085, n_1086, n_1087, n_1088, n_1089, n_1090, n_1091,
n_1092, n_1093, n_1094, n_1095, n_1096, n_1097, n_1098, n_1099, n_1100,
n_1101, n_1102, n_1103, n_1104, n_1105, n_1106, n_1107, n_1108, n_1109,
n_1110, n_1111, n_1112, n_1113, n_1114, n_1115, n_1116, n_1117, n_1118,
n_1119, n_1120, n_1121, n_1122, n_1123, n_1124, n_1125, n_1126, n_1127,
n_1128, n_1129, n_1130, n_1131, n_1132, n_1133, n_1134, n_1135, n_1136,
n_1137, n_1138, n_1139, n_1140, n_1141, n_1142, n_1143, n_1144, n_1145,
n_1146, n_1147, n_1148, n_1149 : std_logic;
begin
dataout <= ( dataout_7_port, dataout_6_port, dataout_5_port, dataout_4_port,
n360, dataout_2_port, dataout_1_port, dataout_0_port );
U161 : NAND3_X1 port map( A1 => address(0), A2 => n29, A3 => address(1), ZN
=> n20);
U163 : NAND3_X1 port map( A1 => n29, A2 => n213, A3 => address(0), ZN =>
n39_port);
U167 : NAND3_X1 port map( A1 => address(0), A2 => n213, A3 => n66, ZN => n76
);
U3 : NOR2_X2 port map( A1 => n179, A2 => address(1), ZN => n176);
U4 : NOR2_X2 port map( A1 => address(1), A2 => address(2), ZN => n173);
U5 : NOR2_X1 port map( A1 => read_enable, A2 => write_enable, ZN => n1);
U6 : NOR2_X2 port map( A1 => n179, A2 => n213, ZN => n175);
U7 : NAND3_X1 port map( A1 => n180, A2 => n213, A3 => n66, ZN => n85);
U8 : NAND3_X1 port map( A1 => n180, A2 => n213, A3 => n29, ZN => n48);
U9 : NAND3_X1 port map( A1 => address(1), A2 => address(0), A3 => n66, ZN =>
n57);
U10 : NOR2_X1 port map( A1 => n212, A2 => address(2), ZN => n66);
U11 : INV_X1 port map( A => write_enable, ZN => n212);
U12 : NAND3_X1 port map( A1 => address(1), A2 => n180, A3 => n66, ZN => n67)
;
U13 : NAND3_X1 port map( A1 => n29, A2 => n180, A3 => address(1), ZN => n30)
;
U14 : NOR2_X2 port map( A1 => n213, A2 => address(2), ZN => n172);
U15 : INV_X1 port map( A => n174, ZN => n196);
U16 : INV_X1 port map( A => n97, ZN => n194);
U17 : INV_X1 port map( A => n7, ZN => n190);
U18 : INV_X1 port map( A => n3, ZN => n189);
U19 : INV_X1 port map( A => n11, ZN => n191);
U20 : INV_X1 port map( A => n15, ZN => n192);
U21 : INV_X1 port map( A => n19, ZN => n193);
U22 : INV_X1 port map( A => n168, ZN => n195);
U23 : OAI21_X1 port map( B1 => n20, B2 => n221, A => n21, ZN => ram_7_0_port
);
U24 : NAND2_X1 port map( A1 => n358, A2 => n20, ZN => n21);
U25 : OAI21_X1 port map( B1 => n20, B2 => n220, A => n22, ZN => ram_7_1_port
);
U26 : NAND2_X1 port map( A1 => n357, A2 => n20, ZN => n22);
U27 : OAI21_X1 port map( B1 => n20, B2 => n219, A => n23, ZN => ram_7_2_port
);
U28 : NAND2_X1 port map( A1 => n356, A2 => n20, ZN => n23);
U29 : OAI21_X1 port map( B1 => n20, B2 => n218, A => n24, ZN => ram_7_3_port
);
U30 : NAND2_X1 port map( A1 => n355, A2 => n20, ZN => n24);
U31 : OAI21_X1 port map( B1 => n20, B2 => n217, A => n25, ZN => ram_7_4_port
);
U32 : NAND2_X1 port map( A1 => n354, A2 => n20, ZN => n25);
U33 : OAI21_X1 port map( B1 => n20, B2 => n216, A => n26, ZN => ram_7_5_port
);
U34 : NAND2_X1 port map( A1 => n353, A2 => n20, ZN => n26);
U35 : OAI21_X1 port map( B1 => n20, B2 => n215, A => n27, ZN => ram_7_6_port
);
U36 : NAND2_X1 port map( A1 => n352, A2 => n20, ZN => n27);
U37 : OAI21_X1 port map( B1 => n20, B2 => n214, A => n28, ZN => ram_7_7_port
);
U38 : NAND2_X1 port map( A1 => n351, A2 => n20, ZN => n28);
U39 : OAI21_X1 port map( B1 => n221, B2 => n76, A => n77, ZN => ram_1_0_port
);
U40 : NAND2_X1 port map( A1 => n350, A2 => n76, ZN => n77);
U41 : OAI21_X1 port map( B1 => n220, B2 => n76, A => n78, ZN => ram_1_1_port
);
U42 : NAND2_X1 port map( A1 => n349, A2 => n76, ZN => n78);
U43 : OAI21_X1 port map( B1 => n219, B2 => n76, A => n79, ZN => ram_1_2_port
);
U44 : NAND2_X1 port map( A1 => n348, A2 => n76, ZN => n79);
U45 : OAI21_X1 port map( B1 => n218, B2 => n76, A => n80, ZN => ram_1_3_port
);
U46 : NAND2_X1 port map( A1 => n347, A2 => n76, ZN => n80);
U47 : OAI21_X1 port map( B1 => n217, B2 => n76, A => n81, ZN => ram_1_4_port
);
U48 : NAND2_X1 port map( A1 => n346, A2 => n76, ZN => n81);
U49 : OAI21_X1 port map( B1 => n216, B2 => n76, A => n82, ZN => ram_1_5_port
);
U50 : NAND2_X1 port map( A1 => n345, A2 => n76, ZN => n82);
U51 : OAI21_X1 port map( B1 => n215, B2 => n76, A => n83, ZN => ram_1_6_port
);
U52 : NAND2_X1 port map( A1 => n344, A2 => n76, ZN => n83);
U53 : OAI21_X1 port map( B1 => n214, B2 => n76, A => n84, ZN => ram_1_7_port
);
U54 : NAND2_X1 port map( A1 => n343, A2 => n76, ZN => n84);
U55 : OAI21_X1 port map( B1 => n221, B2 => n39_port, A => n40_port, ZN =>
ram_5_0_port);
U56 : NAND2_X1 port map( A1 => n342, A2 => n39_port, ZN => n40_port);
U57 : OAI21_X1 port map( B1 => n220, B2 => n39_port, A => n41, ZN =>
ram_5_1_port);
U58 : NAND2_X1 port map( A1 => n341, A2 => n39_port, ZN => n41);
U59 : OAI21_X1 port map( B1 => n219, B2 => n39_port, A => n42, ZN =>
ram_5_2_port);
U60 : NAND2_X1 port map( A1 => n340, A2 => n39_port, ZN => n42);
U61 : OAI21_X1 port map( B1 => n218, B2 => n39_port, A => n43, ZN =>
ram_5_3_port);
U62 : NAND2_X1 port map( A1 => n339, A2 => n39_port, ZN => n43);
U63 : OAI21_X1 port map( B1 => n217, B2 => n39_port, A => n44, ZN =>
ram_5_4_port);
U64 : NAND2_X1 port map( A1 => n338, A2 => n39_port, ZN => n44);
U65 : OAI21_X1 port map( B1 => n216, B2 => n39_port, A => n45, ZN =>
ram_5_5_port);
U66 : NAND2_X1 port map( A1 => n337, A2 => n39_port, ZN => n45);
U67 : OAI21_X1 port map( B1 => n215, B2 => n39_port, A => n46, ZN =>
ram_5_6_port);
U68 : NAND2_X1 port map( A1 => n336, A2 => n39_port, ZN => n46);
U69 : OAI21_X1 port map( B1 => n214, B2 => n39_port, A => n47, ZN =>
ram_5_7_port);
U70 : NAND2_X1 port map( A1 => n335, A2 => n39_port, ZN => n47);
U71 : INV_X1 port map( A => address(0), ZN => n180);
U72 : INV_X1 port map( A => address(1), ZN => n213);
U73 : AND2_X1 port map( A1 => write_enable, A2 => address(2), ZN => n29);
U74 : OAI21_X1 port map( B1 => n221, B2 => n57, A => n58, ZN => ram_3_0_port
);
U75 : NAND2_X1 port map( A1 => n334, A2 => n57, ZN => n58);
U76 : OAI21_X1 port map( B1 => n220, B2 => n57, A => n59, ZN => ram_3_1_port
);
U77 : NAND2_X1 port map( A1 => n333, A2 => n57, ZN => n59);
U78 : OAI21_X1 port map( B1 => n219, B2 => n57, A => n60, ZN => ram_3_2_port
);
U79 : NAND2_X1 port map( A1 => n332, A2 => n57, ZN => n60);
U80 : OAI21_X1 port map( B1 => n218, B2 => n57, A => n61, ZN => ram_3_3_port
);
U81 : NAND2_X1 port map( A1 => n331, A2 => n57, ZN => n61);
U82 : OAI21_X1 port map( B1 => n217, B2 => n57, A => n62, ZN => ram_3_4_port
);
U83 : NAND2_X1 port map( A1 => n330, A2 => n57, ZN => n62);
U84 : OAI21_X1 port map( B1 => n216, B2 => n57, A => n63, ZN => ram_3_5_port
);
U85 : NAND2_X1 port map( A1 => n329, A2 => n57, ZN => n63);
U86 : OAI21_X1 port map( B1 => n215, B2 => n57, A => n64, ZN => ram_3_6_port
);
U87 : NAND2_X1 port map( A1 => n328, A2 => n57, ZN => n64);
U88 : OAI21_X1 port map( B1 => n214, B2 => n57, A => n65, ZN => ram_3_7_port
);
U89 : NAND2_X1 port map( A1 => n327, A2 => n57, ZN => n65);
U90 : OAI21_X1 port map( B1 => n221, B2 => n67, A => n68, ZN => ram_2_0_port
);
U91 : NAND2_X1 port map( A1 => n326, A2 => n67, ZN => n68);
U92 : OAI21_X1 port map( B1 => n220, B2 => n67, A => n69, ZN => ram_2_1_port
);
U93 : NAND2_X1 port map( A1 => n325, A2 => n67, ZN => n69);
U94 : OAI21_X1 port map( B1 => n219, B2 => n67, A => n70, ZN => ram_2_2_port
);
U95 : NAND2_X1 port map( A1 => n324, A2 => n67, ZN => n70);
U96 : OAI21_X1 port map( B1 => n218, B2 => n67, A => n71, ZN => ram_2_3_port
);
U97 : NAND2_X1 port map( A1 => n323, A2 => n67, ZN => n71);
U98 : OAI21_X1 port map( B1 => n217, B2 => n67, A => n72, ZN => ram_2_4_port
);
U99 : NAND2_X1 port map( A1 => n322, A2 => n67, ZN => n72);
U100 : OAI21_X1 port map( B1 => n216, B2 => n67, A => n73, ZN =>
ram_2_5_port);
U101 : NAND2_X1 port map( A1 => n321, A2 => n67, ZN => n73);
U102 : OAI21_X1 port map( B1 => n215, B2 => n67, A => n74, ZN =>
ram_2_6_port);
U103 : NAND2_X1 port map( A1 => n320, A2 => n67, ZN => n74);
U104 : OAI21_X1 port map( B1 => n214, B2 => n67, A => n75, ZN =>
ram_2_7_port);
U105 : NAND2_X1 port map( A1 => n319, A2 => n67, ZN => n75);
U106 : OAI21_X1 port map( B1 => n221, B2 => n30, A => n31, ZN =>
ram_6_0_port);
U107 : NAND2_X1 port map( A1 => n318, A2 => n30, ZN => n31);
U108 : OAI21_X1 port map( B1 => n220, B2 => n30, A => n32, ZN =>
ram_6_1_port);
U109 : NAND2_X1 port map( A1 => n317, A2 => n30, ZN => n32);
U110 : OAI21_X1 port map( B1 => n219, B2 => n30, A => n33_port, ZN =>
ram_6_2_port);
U111 : NAND2_X1 port map( A1 => n316, A2 => n30, ZN => n33_port);
U112 : OAI21_X1 port map( B1 => n218, B2 => n30, A => n34_port, ZN =>
ram_6_3_port);
U113 : NAND2_X1 port map( A1 => n315, A2 => n30, ZN => n34_port);
U114 : OAI21_X1 port map( B1 => n217, B2 => n30, A => n35_port, ZN =>
ram_6_4_port);
U115 : NAND2_X1 port map( A1 => n314, A2 => n30, ZN => n35_port);
U116 : OAI21_X1 port map( B1 => n216, B2 => n30, A => n36_port, ZN =>
ram_6_5_port);
U117 : NAND2_X1 port map( A1 => n313, A2 => n30, ZN => n36_port);
U118 : OAI21_X1 port map( B1 => n215, B2 => n30, A => n37_port, ZN =>
ram_6_6_port);
U119 : NAND2_X1 port map( A1 => n312, A2 => n30, ZN => n37_port);
U120 : OAI21_X1 port map( B1 => n214, B2 => n30, A => n38_port, ZN =>
ram_6_7_port);
U121 : NAND2_X1 port map( A1 => n311, A2 => n30, ZN => n38_port);
U122 : OAI21_X1 port map( B1 => n221, B2 => n85, A => n86, ZN =>
ram_0_0_port);
U123 : NAND2_X1 port map( A1 => n310, A2 => n85, ZN => n86);
U124 : OAI21_X1 port map( B1 => n220, B2 => n85, A => n87, ZN =>
ram_0_1_port);
U125 : NAND2_X1 port map( A1 => n309, A2 => n85, ZN => n87);
U126 : OAI21_X1 port map( B1 => n219, B2 => n85, A => n88, ZN =>
ram_0_2_port);
U127 : NAND2_X1 port map( A1 => n308, A2 => n85, ZN => n88);
U128 : OAI21_X1 port map( B1 => n218, B2 => n85, A => n89, ZN =>
ram_0_3_port);
U129 : NAND2_X1 port map( A1 => n307, A2 => n85, ZN => n89);
U130 : OAI21_X1 port map( B1 => n217, B2 => n85, A => n90, ZN =>
ram_0_4_port);
U131 : NAND2_X1 port map( A1 => n306, A2 => n85, ZN => n90);
U132 : OAI21_X1 port map( B1 => n216, B2 => n85, A => n91, ZN =>
ram_0_5_port);
U133 : NAND2_X1 port map( A1 => n305, A2 => n85, ZN => n91);
U134 : OAI21_X1 port map( B1 => n215, B2 => n85, A => n92, ZN =>
ram_0_6_port);
U135 : NAND2_X1 port map( A1 => n304, A2 => n85, ZN => n92);
U136 : OAI21_X1 port map( B1 => n214, B2 => n85, A => n93, ZN =>
ram_0_7_port);
U137 : NAND2_X1 port map( A1 => n303, A2 => n85, ZN => n93);
U138 : OAI21_X1 port map( B1 => n221, B2 => n48, A => n49, ZN =>
ram_4_0_port);
U139 : NAND2_X1 port map( A1 => n302, A2 => n48, ZN => n49);
U140 : OAI21_X1 port map( B1 => n220, B2 => n48, A => n50, ZN =>
ram_4_1_port);
U141 : NAND2_X1 port map( A1 => n301, A2 => n48, ZN => n50);
U142 : OAI21_X1 port map( B1 => n219, B2 => n48, A => n51, ZN =>
ram_4_2_port);
U143 : NAND2_X1 port map( A1 => n300, A2 => n48, ZN => n51);
U144 : OAI21_X1 port map( B1 => n218, B2 => n48, A => n52, ZN =>
ram_4_3_port);
U145 : NAND2_X1 port map( A1 => n299, A2 => n48, ZN => n52);
U146 : OAI21_X1 port map( B1 => n217, B2 => n48, A => n53, ZN =>
ram_4_4_port);
U147 : NAND2_X1 port map( A1 => n298, A2 => n48, ZN => n53);
U148 : OAI21_X1 port map( B1 => n216, B2 => n48, A => n54, ZN =>
ram_4_5_port);
U149 : NAND2_X1 port map( A1 => n297, A2 => n48, ZN => n54);
U150 : OAI21_X1 port map( B1 => n215, B2 => n48, A => n55, ZN =>
ram_4_6_port);
U151 : NAND2_X1 port map( A1 => n296, A2 => n48, ZN => n55);
U152 : OAI21_X1 port map( B1 => n214, B2 => n48, A => n56, ZN =>
ram_4_7_port);
U153 : NAND2_X1 port map( A1 => n295, A2 => n48, ZN => n56);
U154 : INV_X1 port map( A => address(2), ZN => n179);
U155 : INV_X1 port map( A => n171, ZN => n188);
U156 : INV_X1 port map( A => n96, ZN => n186);
U157 : INV_X1 port map( A => n6, ZN => n182);
U158 : INV_X1 port map( A => n2, ZN => n181);
U159 : INV_X1 port map( A => n10, ZN => n183);
U160 : INV_X1 port map( A => n14, ZN => n184);
U162 : INV_X1 port map( A => n18, ZN => n185);
U164 : INV_X1 port map( A => n167, ZN => n187);
U165 : INV_X1 port map( A => n101, ZN => n512);
U166 : AOI22_X1 port map( A1 => N34, A2 => read_enable, B1 => dataout_6_port
, B2 => n1, ZN => n101);
U168 : INV_X1 port map( A => datain(0), ZN => n221);
U169 : INV_X1 port map( A => datain(1), ZN => n220);
U170 : INV_X1 port map( A => datain(2), ZN => n219);
U171 : INV_X1 port map( A => datain(3), ZN => n218);
U172 : INV_X1 port map( A => datain(4), ZN => n217);
U173 : INV_X1 port map( A => datain(5), ZN => n216);
U174 : INV_X1 port map( A => datain(6), ZN => n215);
U175 : INV_X1 port map( A => datain(7), ZN => n214);
U176 : AOI22_X1 port map( A1 => n350, A2 => n173, B1 => n334, B2 => n172, ZN
=> n2);
U177 : AOI221_X1 port map( B1 => n342, B2 => n176, C1 => n358, C2 => n175, A
=> n181, ZN => n5);
U178 : AOI22_X1 port map( A1 => n310, A2 => n173, B1 => n326, B2 => n172, ZN
=> n3);
U179 : AOI221_X1 port map( B1 => n302, B2 => n176, C1 => n318, C2 => n175, A
=> n189, ZN => n4);
U180 : OAI22_X1 port map( A1 => n180, A2 => n5, B1 => address(0), B2 => n4,
ZN => N40);
U181 : AOI22_X1 port map( A1 => n349, A2 => n173, B1 => n333, B2 => n172, ZN
=> n6);
U182 : AOI221_X1 port map( B1 => n341, B2 => n176, C1 => n357, C2 => n175, A
=> n182, ZN => n9);
U183 : AOI22_X1 port map( A1 => n309, A2 => n173, B1 => n325, B2 => n172, ZN
=> n7);
U184 : AOI221_X1 port map( B1 => n301, B2 => n176, C1 => n317, C2 => n175, A
=> n190, ZN => n8);
U185 : OAI22_X1 port map( A1 => n180, A2 => n9, B1 => address(0), B2 => n8,
ZN => N39);
U186 : AOI22_X1 port map( A1 => n348, A2 => n173, B1 => n332, B2 => n172, ZN
=> n10);
U187 : AOI221_X1 port map( B1 => n340, B2 => n176, C1 => n356, C2 => n175, A
=> n183, ZN => n13);
U188 : AOI22_X1 port map( A1 => n308, A2 => n173, B1 => n324, B2 => n172, ZN
=> n11);
U189 : AOI221_X1 port map( B1 => n300, B2 => n176, C1 => n316, C2 => n175, A
=> n191, ZN => n12);
U190 : OAI22_X1 port map( A1 => n180, A2 => n13, B1 => address(0), B2 => n12
, ZN => N38);
U191 : AOI22_X1 port map( A1 => n347, A2 => n173, B1 => n331, B2 => n172, ZN
=> n14);
U192 : AOI221_X1 port map( B1 => n339, B2 => n176, C1 => n355, C2 => n175, A
=> n184, ZN => n17);
U193 : AOI22_X1 port map( A1 => n307, A2 => n173, B1 => n323, B2 => n172, ZN
=> n15);
U194 : AOI221_X1 port map( B1 => n299, B2 => n176, C1 => n315, C2 => n175, A
=> n192, ZN => n16);
U195 : OAI22_X1 port map( A1 => n180, A2 => n17, B1 => address(0), B2 => n16
, ZN => N37);
U196 : AOI22_X1 port map( A1 => n346, A2 => n173, B1 => n330, B2 => n172, ZN
=> n18);
U197 : AOI221_X1 port map( B1 => n338, B2 => n176, C1 => n354, C2 => n175, A
=> n185, ZN => n95);
U198 : AOI22_X1 port map( A1 => n306, A2 => n173, B1 => n322, B2 => n172, ZN
=> n19);
U199 : AOI221_X1 port map( B1 => n298, B2 => n176, C1 => n314, C2 => n175, A
=> n193, ZN => n94);
U200 : OAI22_X1 port map( A1 => n180, A2 => n95, B1 => address(0), B2 => n94
, ZN => N36);
U201 : AOI22_X1 port map( A1 => n345, A2 => n173, B1 => n329, B2 => n172, ZN
=> n96);
U202 : AOI221_X1 port map( B1 => n337, B2 => n176, C1 => n353, C2 => n175, A
=> n186, ZN => n99);
U203 : AOI22_X1 port map( A1 => n305, A2 => n173, B1 => n321, B2 => n172, ZN
=> n97);
U204 : AOI221_X1 port map( B1 => n297, B2 => n176, C1 => n313, C2 => n175, A
=> n194, ZN => n98);
U205 : OAI22_X1 port map( A1 => n180, A2 => n99, B1 => address(0), B2 => n98
, ZN => N35);
U206 : AOI22_X1 port map( A1 => n344, A2 => n173, B1 => n328, B2 => n172, ZN
=> n167);
U207 : AOI221_X1 port map( B1 => n336, B2 => n176, C1 => n352, C2 => n175, A
=> n187, ZN => n170);
U208 : AOI22_X1 port map( A1 => n304, A2 => n173, B1 => n320, B2 => n172, ZN
=> n168);
U209 : AOI221_X1 port map( B1 => n296, B2 => n176, C1 => n312, C2 => n175, A
=> n195, ZN => n169);
U210 : OAI22_X1 port map( A1 => n180, A2 => n170, B1 => address(0), B2 =>
n169, ZN => N34);
U211 : AOI22_X1 port map( A1 => n343, A2 => n173, B1 => n327, B2 => n172, ZN
=> n171);
U212 : AOI221_X1 port map( B1 => n335, B2 => n176, C1 => n351, C2 => n175, A
=> n188, ZN => n178);
U213 : AOI22_X1 port map( A1 => n303, A2 => n173, B1 => n319, B2 => n172, ZN
=> n174);
U214 : AOI221_X1 port map( B1 => n295, B2 => n176, C1 => n311, C2 => n175, A
=> n196, ZN => n177);
U215 : OAI22_X1 port map( A1 => n178, A2 => n180, B1 => address(0), B2 =>
n177, ZN => N33);
U216 : INV_X1 port map( A => n102, ZN => n511);
U218 : INV_X1 port map( A => n100, ZN => n513);
U219 : AOI22_X1 port map( A1 => N33, A2 => read_enable, B1 => dataout_7_port
, B2 => n1, ZN => n102);
U220 : AOI22_X1 port map( A1 => N35, A2 => read_enable, B1 => dataout_5_port
, B2 => n1, ZN => n100);
U221 : AOI22_X1 port map( A1 => N40, A2 => read_enable, B1 => dataout_0_port
, B2 => n1, ZN => n199);
U222 : INV_X1 port map( A => n199, ZN => n517);
U223 : AOI22_X1 port map( A1 => N39, A2 => read_enable, B1 => dataout_1_port
, B2 => n1, ZN => n200);
U224 : INV_X1 port map( A => n200, ZN => n516);
U225 : AOI22_X1 port map( A1 => N38, A2 => read_enable, B1 => dataout_2_port
, B2 => n1, ZN => n201);
U226 : INV_X1 port map( A => n201, ZN => n515);
U227 : AOI22_X1 port map( A1 => N37, A2 => read_enable, B1 => n360, B2 => n1
, ZN => n202);
U228 : INV_X1 port map( A => n202, ZN => n222);
U229 : AOI22_X1 port map( A1 => N36, A2 => read_enable, B1 => dataout_4_port
, B2 => n1, ZN => n203);
U230 : INV_X1 port map( A => n203, ZN => n514);
clock_r_REG209_S3 : DFF_X1 port map( D => n512, CK => clock, Q =>
dataout_6_port, QN => n_1078);
clock_r_REG202_S3 : DFF_X1 port map( D => n511, CK => clock, Q =>
dataout_7_port, QN => n_1079);
clock_r_REG213_S3 : DFF_X1 port map( D => n513, CK => clock, Q =>
dataout_5_port, QN => n_1080);
clock_r_REG233_S3 : DFF_X1 port map( D => n517, CK => clock, Q =>
dataout_0_port, QN => n_1081);
clock_r_REG229_S3 : DFF_X1 port map( D => n516, CK => clock, Q =>
dataout_1_port, QN => n_1082);
clock_r_REG225_S3 : DFF_X1 port map( D => n515, CK => clock, Q =>
dataout_2_port, QN => n_1083);
clock_r_REG221_S3 : DFF_X1 port map( D => n222, CK => clock, Q => n360, QN
=> n_1084);
clock_r_REG217_S3 : DFF_X1 port map( D => n514, CK => clock, Q =>
dataout_4_port, QN => n_1085);
clock_r_REG232_S2 : DFF_X1 port map( D => ram_7_0_port, CK => clock, Q =>
n358, QN => n_1086);
clock_r_REG228_S2 : DFF_X1 port map( D => ram_7_1_port, CK => clock, Q =>
n357, QN => n_1087);
clock_r_REG224_S2 : DFF_X1 port map( D => ram_7_2_port, CK => clock, Q =>
n356, QN => n_1088);
clock_r_REG220_S2 : DFF_X1 port map( D => ram_7_3_port, CK => clock, Q =>
n355, QN => n_1089);
clock_r_REG216_S2 : DFF_X1 port map( D => ram_7_4_port, CK => clock, Q =>
n354, QN => n_1090);
clock_r_REG212_S2 : DFF_X1 port map( D => ram_7_5_port, CK => clock, Q =>
n353, QN => n_1091);
clock_r_REG208_S2 : DFF_X1 port map( D => ram_7_6_port, CK => clock, Q =>
n352, QN => n_1092);
clock_r_REG201_S2 : DFF_X1 port map( D => ram_7_7_port, CK => clock, Q =>
n351, QN => n_1093);
clock_r_REG267_S2 : DFF_X1 port map( D => ram_1_0_port, CK => clock, Q =>
n350, QN => n_1094);
clock_r_REG266_S2 : DFF_X1 port map( D => ram_1_1_port, CK => clock, Q =>
n349, QN => n_1095);
clock_r_REG265_S2 : DFF_X1 port map( D => ram_1_2_port, CK => clock, Q =>
n348, QN => n_1096);
clock_r_REG264_S2 : DFF_X1 port map( D => ram_1_3_port, CK => clock, Q =>
n347, QN => n_1097);
clock_r_REG263_S2 : DFF_X1 port map( D => ram_1_4_port, CK => clock, Q =>
n346, QN => n_1098);
clock_r_REG262_S2 : DFF_X1 port map( D => ram_1_5_port, CK => clock, Q =>
n345, QN => n_1099);
clock_r_REG261_S2 : DFF_X1 port map( D => ram_1_6_port, CK => clock, Q =>
n344, QN => n_1100);
clock_r_REG260_S2 : DFF_X1 port map( D => ram_1_7_port, CK => clock, Q =>
n343, QN => n_1101);
clock_r_REG243_S2 : DFF_X1 port map( D => ram_5_0_port, CK => clock, Q =>
n342, QN => n_1102);
clock_r_REG242_S2 : DFF_X1 port map( D => ram_5_1_port, CK => clock, Q =>
n341, QN => n_1103);
clock_r_REG241_S2 : DFF_X1 port map( D => ram_5_2_port, CK => clock, Q =>
n340, QN => n_1104);
clock_r_REG240_S2 : DFF_X1 port map( D => ram_5_3_port, CK => clock, Q =>
n339, QN => n_1105);
clock_r_REG239_S2 : DFF_X1 port map( D => ram_5_4_port, CK => clock, Q =>
n338, QN => n_1106);
clock_r_REG238_S2 : DFF_X1 port map( D => ram_5_5_port, CK => clock, Q =>
n337, QN => n_1107);
clock_r_REG237_S2 : DFF_X1 port map( D => ram_5_6_port, CK => clock, Q =>
n336, QN => n_1108);
clock_r_REG236_S2 : DFF_X1 port map( D => ram_5_7_port, CK => clock, Q =>
n335, QN => n_1109);
clock_r_REG283_S2 : DFF_X1 port map( D => ram_3_0_port, CK => clock, Q =>
n334, QN => n_1110);
clock_r_REG282_S2 : DFF_X1 port map( D => ram_3_1_port, CK => clock, Q =>
n333, QN => n_1111);
clock_r_REG281_S2 : DFF_X1 port map( D => ram_3_2_port, CK => clock, Q =>
n332, QN => n_1112);
clock_r_REG280_S2 : DFF_X1 port map( D => ram_3_3_port, CK => clock, Q =>
n331, QN => n_1113);
clock_r_REG279_S2 : DFF_X1 port map( D => ram_3_4_port, CK => clock, Q =>
n330, QN => n_1114);
clock_r_REG278_S2 : DFF_X1 port map( D => ram_3_5_port, CK => clock, Q =>
n329, QN => n_1115);
clock_r_REG277_S2 : DFF_X1 port map( D => ram_3_6_port, CK => clock, Q =>
n328, QN => n_1116);
clock_r_REG276_S2 : DFF_X1 port map( D => ram_3_7_port, CK => clock, Q =>
n327, QN => n_1117);
clock_r_REG275_S2 : DFF_X1 port map( D => ram_2_0_port, CK => clock, Q =>
n326, QN => n_1118);
clock_r_REG274_S2 : DFF_X1 port map( D => ram_2_1_port, CK => clock, Q =>
n325, QN => n_1119);
clock_r_REG273_S2 : DFF_X1 port map( D => ram_2_2_port, CK => clock, Q =>
n324, QN => n_1120);
clock_r_REG272_S2 : DFF_X1 port map( D => ram_2_3_port, CK => clock, Q =>
n323, QN => n_1121);
clock_r_REG271_S2 : DFF_X1 port map( D => ram_2_4_port, CK => clock, Q =>
n322, QN => n_1122);
clock_r_REG270_S2 : DFF_X1 port map( D => ram_2_5_port, CK => clock, Q =>
n321, QN => n_1123);
clock_r_REG269_S2 : DFF_X1 port map( D => ram_2_6_port, CK => clock, Q =>
n320, QN => n_1124);
clock_r_REG268_S2 : DFF_X1 port map( D => ram_2_7_port, CK => clock, Q =>
n319, QN => n_1125);
clock_r_REG251_S2 : DFF_X1 port map( D => ram_6_0_port, CK => clock, Q =>
n318, QN => n_1126);
clock_r_REG250_S2 : DFF_X1 port map( D => ram_6_1_port, CK => clock, Q =>
n317, QN => n_1127);
clock_r_REG249_S2 : DFF_X1 port map( D => ram_6_2_port, CK => clock, Q =>
n316, QN => n_1128);
clock_r_REG248_S2 : DFF_X1 port map( D => ram_6_3_port, CK => clock, Q =>
n315, QN => n_1129);
clock_r_REG247_S2 : DFF_X1 port map( D => ram_6_4_port, CK => clock, Q =>
n314, QN => n_1130);
clock_r_REG246_S2 : DFF_X1 port map( D => ram_6_5_port, CK => clock, Q =>
n313, QN => n_1131);
clock_r_REG245_S2 : DFF_X1 port map( D => ram_6_6_port, CK => clock, Q =>
n312, QN => n_1132);
clock_r_REG244_S2 : DFF_X1 port map( D => ram_6_7_port, CK => clock, Q =>
n311, QN => n_1133);
clock_r_REG291_S2 : DFF_X1 port map( D => ram_0_0_port, CK => clock, Q =>
n310, QN => n_1134);
clock_r_REG290_S2 : DFF_X1 port map( D => ram_0_1_port, CK => clock, Q =>
n309, QN => n_1135);
clock_r_REG289_S2 : DFF_X1 port map( D => ram_0_2_port, CK => clock, Q =>
n308, QN => n_1136);
clock_r_REG288_S2 : DFF_X1 port map( D => ram_0_3_port, CK => clock, Q =>
n307, QN => n_1137);
clock_r_REG287_S2 : DFF_X1 port map( D => ram_0_4_port, CK => clock, Q =>
n306, QN => n_1138);
clock_r_REG286_S2 : DFF_X1 port map( D => ram_0_5_port, CK => clock, Q =>
n305, QN => n_1139);
clock_r_REG285_S2 : DFF_X1 port map( D => ram_0_6_port, CK => clock, Q =>
n304, QN => n_1140);
clock_r_REG284_S2 : DFF_X1 port map( D => ram_0_7_port, CK => clock, Q =>
n303, QN => n_1141);
clock_r_REG259_S2 : DFF_X1 port map( D => ram_4_0_port, CK => clock, Q =>
n302, QN => n_1142);
clock_r_REG258_S2 : DFF_X1 port map( D => ram_4_1_port, CK => clock, Q =>
n301, QN => n_1143);
clock_r_REG257_S2 : DFF_X1 port map( D => ram_4_2_port, CK => clock, Q =>
n300, QN => n_1144);
clock_r_REG256_S2 : DFF_X1 port map( D => ram_4_3_port, CK => clock, Q =>
n299, QN => n_1145);
clock_r_REG255_S2 : DFF_X1 port map( D => ram_4_4_port, CK => clock, Q =>
n298, QN => n_1146);
clock_r_REG254_S2 : DFF_X1 port map( D => ram_4_5_port, CK => clock, Q =>
n297, QN => n_1147);
clock_r_REG253_S2 : DFF_X1 port map( D => ram_4_6_port, CK => clock, Q =>
n296, QN => n_1148);
clock_r_REG252_S2 : DFF_X1 port map( D => ram_4_7_port, CK => clock, Q =>
n295, QN => n_1149);
end SYN_ramA;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_0 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_0;
architecture SYN_counter_address_generator of counter_address_generator_0 is
component counter_address_generator_0_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n51, n52, n53, n54, n55, n56, n57, n58, N10, N11, N12, N13, N14, N15,
N16, N17, n9, n10_port, n11_port, n12_port, n13_port, n14_port, n15_port,
n16_port, n17_port, n18, address_0_port, address_1_port, address_2_port,
address_3_port, address_4_port, address_5_port, address_6_port,
address_7_port, n_1150, n_1151, n_1152, n_1153, n_1154, n_1155, n_1156,
n_1157 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n11_port, ZN
=> n10_port);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n11_port);
U5 : INV_X1 port map( A => n9, ZN => n51);
U6 : AOI22_X1 port map( A1 => N17, A2 => n10_port, B1 => address_7_port, B2
=> n11_port, ZN => n9);
U7 : INV_X1 port map( A => n12_port, ZN => n52);
U8 : AOI22_X1 port map( A1 => N16, A2 => n10_port, B1 => address_6_port, B2
=> n11_port, ZN => n12_port);
U9 : INV_X1 port map( A => n13_port, ZN => n53);
U10 : AOI22_X1 port map( A1 => N15, A2 => n10_port, B1 => address_5_port, B2
=> n11_port, ZN => n13_port);
U11 : INV_X1 port map( A => n14_port, ZN => n54);
U12 : AOI22_X1 port map( A1 => N14, A2 => n10_port, B1 => address_4_port, B2
=> n11_port, ZN => n14_port);
U13 : INV_X1 port map( A => n15_port, ZN => n55);
U14 : AOI22_X1 port map( A1 => N13, A2 => n10_port, B1 => address_3_port, B2
=> n11_port, ZN => n15_port);
U15 : INV_X1 port map( A => n16_port, ZN => n56);
U16 : AOI22_X1 port map( A1 => N12, A2 => n10_port, B1 => address_2_port, B2
=> n11_port, ZN => n16_port);
U17 : INV_X1 port map( A => n17_port, ZN => n57);
U18 : AOI22_X1 port map( A1 => N11, A2 => n10_port, B1 => address_1_port, B2
=> n11_port, ZN => n17_port);
U19 : INV_X1 port map( A => n18, ZN => n58);
U20 : AOI22_X1 port map( A1 => N10, A2 => n10_port, B1 => address_0_port, B2
=> n11_port, ZN => n18);
clock_r_REG299_S3 : DFF_X1 port map( D => n51, CK => clock, Q =>
address_7_port, QN => n_1150);
clock_r_REG298_S3 : DFF_X1 port map( D => n52, CK => clock, Q =>
address_6_port, QN => n_1151);
clock_r_REG297_S3 : DFF_X1 port map( D => n53, CK => clock, Q =>
address_5_port, QN => n_1152);
clock_r_REG296_S3 : DFF_X1 port map( D => n54, CK => clock, Q =>
address_4_port, QN => n_1153);
clock_r_REG295_S3 : DFF_X1 port map( D => n55, CK => clock, Q =>
address_3_port, QN => n_1154);
clock_r_REG294_S3 : DFF_X1 port map( D => n56, CK => clock, Q =>
address_2_port, QN => n_1155);
clock_r_REG293_S3 : DFF_X1 port map( D => n57, CK => clock, Q =>
address_1_port, QN => n_1156);
clock_r_REG292_S3 : DFF_X1 port map( D => n58, CK => clock, Q =>
address_0_port, QN => n_1157);
add_38 : counter_address_generator_0_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity project2 is
port( clock, reset, valid, hold_me : in std_logic; data_in : in
std_logic_vector (7 downto 0); data_out : out std_logic_vector (18
downto 0); hold_prev : out std_logic);
end project2;
architecture SYN_project_2 of project2 is
component ramR
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (18
downto 0); dataout : out std_logic_vector (18 downto 0));
end component;
component counter_address_generator_1
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
component fsm
port( clock, reset : in std_logic; ramA_address : in std_logic_vector (4
downto 0); ramR_address, rom_address : in std_logic_vector (7
downto 0); hold_me : in std_logic; ramR_readEnable,
ramA_writeEnable, ramA_readEnable, ramR_writeEnable, rom_enable,
counterAddressGen_H_enable, counterAddressGen_R_enable,
counterAddressGen_A_restart, counterAddressGen_R_restart,
counterAddressGen_H_restart, mac_clean, reset_fsm, hold_prev : out
std_logic);
end component;
component mac
port( clock : in std_logic; ai, xi : in std_logic_vector (7 downto 0);
mac_clean : in std_logic; data_out : out std_logic_vector (18
downto 0));
end component;
component rom
port( clock : in std_logic; address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic; data : out std_logic_vector (7 downto
0));
end component;
component counter_address_generator_2
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
component ramA
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (7
downto 0); dataout : out std_logic_vector (7 downto 0));
end component;
component counter_address_generator_0
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
signal reset_fsm, CAG_A_restart, ramA_read_enable, addressA_7_port,
addressA_6_port, addressA_5_port, addressA_4_port, addressA_3_port,
addressA_2_port, addressA_1_port, addressA_0_port, ramA_write_enable,
Ai_7_port, Ai_6_port, Ai_5_port, Ai_4_port, Ai_3_port, Ai_2_port,
Ai_1_port, Ai_0_port, CAG_H_restart, CAG_H_enable, addressH_7_port,
addressH_6_port, addressH_5_port, addressH_4_port, addressH_3_port,
addressH_2_port, addressH_1_port, addressH_0_port, romH_enable, Hi_7_port
, Hi_6_port, Hi_5_port, Hi_4_port, Hi_3_port, Hi_2_port, Hi_1_port,
Hi_0_port, clear_register, Ri_18_port, Ri_17_port, Ri_16_port, Ri_15_port
, Ri_14_port, Ri_13_port, Ri_12_port, Ri_11_port, Ri_10_port, Ri_9_port,
Ri_8_port, Ri_7_port, Ri_6_port, Ri_5_port, Ri_4_port, Ri_3_port,
Ri_2_port, Ri_1_port, Ri_0_port, addressR_7_port, addressR_6_port,
addressR_5_port, addressR_4_port, addressR_3_port, addressR_2_port,
addressR_1_port, addressR_0_port, ramR_read_enable, ramR_write_enable,
CAG_R_enable, CAG_R_restart, n1, n2, n3, n4, n5, n6, n7, n_1158, n_1159,
n_1160, n_1161, n_1162, n_1163, n_1164 : std_logic;
begin
Hi_0_port <= '0';
Hi_1_port <= '0';
Hi_2_port <= '0';
Hi_3_port <= '0';
Hi_4_port <= '0';
Hi_5_port <= '0';
Hi_6_port <= '0';
n1 <= '0';
n2 <= '0';
n3 <= '0';
n4 <= '0';
n5 <= '0';
n6 <= '0';
counterAddressGenA : counter_address_generator_0 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_A_restart,
enable => valid, read_enable => ramA_read_enable,
address(7) => addressA_7_port, address(6) =>
addressA_6_port, address(5) => addressA_5_port,
address(4) => addressA_4_port, address(3) =>
addressA_3_port, address(2) => addressA_2_port,
address(1) => addressA_1_port, address(0) =>
addressA_0_port);
RAMA_UNIT : ramA port map( clock => clock, write_enable => ramA_write_enable
, read_enable => ramA_read_enable, address(2) =>
addressA_2_port, address(1) => addressA_1_port,
address(0) => addressA_0_port, datain(7) =>
data_in(7), datain(6) => data_in(6), datain(5) =>
data_in(5), datain(4) => data_in(4), datain(3) =>
data_in(3), datain(2) => data_in(2), datain(1) =>
data_in(1), datain(0) => data_in(0), dataout(7) =>
Ai_7_port, dataout(6) => Ai_6_port, dataout(5) =>
Ai_5_port, dataout(4) => Ai_4_port, dataout(3) =>
Ai_3_port, dataout(2) => Ai_2_port, dataout(1) =>
Ai_1_port, dataout(0) => Ai_0_port);
counterAddressGenH : counter_address_generator_2 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_H_restart,
enable => CAG_H_enable, read_enable => CAG_H_enable,
address(7) => addressH_7_port, address(6) =>
addressH_6_port, address(5) => addressH_5_port,
address(4) => addressH_4_port, address(3) =>
addressH_3_port, address(2) => addressH_2_port,
address(1) => addressH_1_port, address(0) =>
addressH_0_port);
ROMH : rom port map( clock => n7, address(5) => n1, address(4) => n2,
address(3) => n3, address(2) => n4, address(1) => n5
, address(0) => n6, rom_enable => romH_enable,
data(7) => Hi_7_port, data(6) => n_1158, data(5) =>
n_1159, data(4) => n_1160, data(3) => n_1161,
data(2) => n_1162, data(1) => n_1163, data(0) =>
n_1164);
MAC_UNIT : mac port map( clock => clock, ai(7) => Ai_7_port, ai(6) =>
Ai_6_port, ai(5) => Ai_5_port, ai(4) => Ai_4_port,
ai(3) => Ai_3_port, ai(2) => Ai_2_port, ai(1) =>
Ai_1_port, ai(0) => Ai_0_port, xi(7) => Hi_7_port,
xi(6) => Hi_6_port, xi(5) => Hi_5_port, xi(4) =>
Hi_4_port, xi(3) => Hi_3_port, xi(2) => Hi_2_port,
xi(1) => Hi_1_port, xi(0) => Hi_0_port, mac_clean =>
clear_register, data_out(18) => Ri_18_port,
data_out(17) => Ri_17_port, data_out(16) =>
Ri_16_port, data_out(15) => Ri_15_port, data_out(14)
=> Ri_14_port, data_out(13) => Ri_13_port,
data_out(12) => Ri_12_port, data_out(11) =>
Ri_11_port, data_out(10) => Ri_10_port, data_out(9)
=> Ri_9_port, data_out(8) => Ri_8_port, data_out(7)
=> Ri_7_port, data_out(6) => Ri_6_port, data_out(5)
=> Ri_5_port, data_out(4) => Ri_4_port, data_out(3)
=> Ri_3_port, data_out(2) => Ri_2_port, data_out(1)
=> Ri_1_port, data_out(0) => Ri_0_port);
FSM_UNIT : fsm port map( clock => clock, reset => reset, ramA_address(4) =>
addressA_7_port, ramA_address(3) => addressA_6_port,
ramA_address(2) => addressA_5_port, ramA_address(1)
=> addressA_4_port, ramA_address(0) =>
addressA_3_port, ramR_address(7) => addressR_7_port,
ramR_address(6) => addressR_6_port, ramR_address(5)
=> addressR_5_port, ramR_address(4) =>
addressR_4_port, ramR_address(3) => addressR_3_port,
ramR_address(2) => addressR_2_port, ramR_address(1)
=> addressR_1_port, ramR_address(0) =>
addressR_0_port, rom_address(7) => addressH_7_port,
rom_address(6) => addressH_6_port, rom_address(5) =>
addressH_5_port, rom_address(4) => addressH_4_port,
rom_address(3) => addressH_3_port, rom_address(2) =>
addressH_2_port, rom_address(1) => addressH_1_port,
rom_address(0) => addressH_0_port, hold_me =>
hold_me, ramR_readEnable => ramR_read_enable,
ramA_writeEnable => ramA_write_enable,
ramA_readEnable => ramA_read_enable,
ramR_writeEnable => ramR_write_enable, rom_enable =>
romH_enable, counterAddressGen_H_enable =>
CAG_H_enable, counterAddressGen_R_enable =>
CAG_R_enable, counterAddressGen_A_restart =>
CAG_A_restart, counterAddressGen_R_restart =>
CAG_R_restart, counterAddressGen_H_restart =>
CAG_H_restart, mac_clean => clear_register,
reset_fsm => reset_fsm, hold_prev => hold_prev);
counterAddressGenR : counter_address_generator_1 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_R_restart,
enable => CAG_R_enable, read_enable =>
ramR_read_enable, address(7) => addressR_7_port,
address(6) => addressR_6_port, address(5) =>
addressR_5_port, address(4) => addressR_4_port,
address(3) => addressR_3_port, address(2) =>
addressR_2_port, address(1) => addressR_1_port,
address(0) => addressR_0_port);
RAMR_UNIT : ramR port map( clock => clock, write_enable => ramR_write_enable
, read_enable => ramR_read_enable, address(2) =>
addressR_2_port, address(1) => addressR_1_port,
address(0) => addressR_0_port, datain(18) =>
Ri_18_port, datain(17) => Ri_17_port, datain(16) =>
Ri_16_port, datain(15) => Ri_15_port, datain(14) =>
Ri_14_port, datain(13) => Ri_13_port, datain(12) =>
Ri_12_port, datain(11) => Ri_11_port, datain(10) =>
Ri_10_port, datain(9) => Ri_9_port, datain(8) =>
Ri_8_port, datain(7) => Ri_7_port, datain(6) =>
Ri_6_port, datain(5) => Ri_5_port, datain(4) =>
Ri_4_port, datain(3) => Ri_3_port, datain(2) =>
Ri_2_port, datain(1) => Ri_1_port, datain(0) =>
Ri_0_port, dataout(18) => data_out(18), dataout(17)
=> data_out(17), dataout(16) => data_out(16),
dataout(15) => data_out(15), dataout(14) =>
data_out(14), dataout(13) => data_out(13),
dataout(12) => data_out(12), dataout(11) =>
data_out(11), dataout(10) => data_out(10),
dataout(9) => data_out(9), dataout(8) => data_out(8)
, dataout(7) => data_out(7), dataout(6) =>
data_out(6), dataout(5) => data_out(5), dataout(4)
=> data_out(4), dataout(3) => data_out(3),
dataout(2) => data_out(2), dataout(1) => data_out(1)
, dataout(0) => data_out(0));
n7 <= '0';
end SYN_project_2;
|
architecture rtl of fifo is
variable v_element : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity servo_pwm is
generic (
ResW : positive := 7
);
port (
Clk : in bit1; -- Must be 64 kHz
RstN : in bit1;
--
Pos : in word(ResW-1 downto 0);
--
Servo : out bit1
);
end Servo_pwm;
architecture Behavioral of Servo_pwm is
constant MaxCnt : positive := 1279;
constant MaxCntW : positive := bits(MaxCnt);
-- Counter, from 0 to 1279.
signal Cnt_D : word(MaxCntW-1 downto 0);
-- Temporal signal used to generate the PWM pulse.
signal pwmi : word(8-1 downto 0);
begin
-- Minimum value should be 0.5ms.
pwmi <= ('0' & Pos) + 32;
-- Counter process, from 0 to 1279.
counter : process (RstN, Clk)
begin
if (RstN = '0') then
Cnt_D <= (others => '0');
elsif rising_edge(Clk) then
if Cnt_D = MaxCnt then
Cnt_D <= (others => '0');
else
Cnt_D <= Cnt_D + 1;
end if;
end if;
end process;
-- Output signal for the Servomotor.
Servo <= '1' when Cnt_D < pwmi else '0';
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) generate
u0 : unisim_inpad_ds generic map (level, voltage, term) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or (tech = spartan6)
or (tech = virtex6) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_inpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage, term) port map (padp(i), padn(i), o(i));
end generate;
end;
|
-- Title: SDRAMController.vhd
-- Original Author: Matthew Hagerty
-- Modified by: René Richard
-- Description:
--
-- LICENSE
--
-- This file is part of SDRAMController.
-- TDSN76489 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- Foobar is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with SDRAMController. If not, see <http://www.gnu.org/licenses/>.
--
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity SDRAMController is
port(
-- Host side
clk_100m0_i : in std_logic; -- Master clock
reset_i : in std_logic := '0'; -- Reset, active high
refresh_i : in std_logic := '0'; -- Initiate a refresh cycle, active high
rw_i : in std_logic := '0'; -- Initiate a read or write operation, active high
we_i : in std_logic := '0'; -- Write enable, active low
addr_i : in std_logic_vector(23 downto 0) := (others => '0'); -- Address from host to SDRAM
data_i : in std_logic_vector(15 downto 0) := (others => '0'); -- Data from host to SDRAM
ub_i : in std_logic; -- Data upper byte enable, active low
lb_i : in std_logic; -- Data lower byte enable, active low
ready_o : out std_logic := '0'; -- Set to '1' when the memory is ready
done_o : out std_logic := '0'; -- Read, write, or refresh, operation is done
data_o : out std_logic_vector(15 downto 0); -- Data from SDRAM to host
-- SDRAM side
sdCke_o : out std_logic; -- Clock-enable to SDRAM
sdCe_bo : out std_logic; -- Chip-select to SDRAM
sdRas_bo : out std_logic; -- SDRAM row address strobe
sdCas_bo : out std_logic; -- SDRAM column address strobe
sdWe_bo : out std_logic; -- SDRAM write enable
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address
sdAddr_o : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sdData_io : inout std_logic_vector(15 downto 0); -- Data to/from SDRAM
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true
);
end entity;
architecture SDRAMController_a of SDRAMController is
-- SDRAM controller states.
type fsm_state_type is (
ST_INIT_WAIT, ST_INIT_PRECHARGE, ST_INIT_REFRESH1, ST_INIT_MODE, ST_INIT_REFRESH2,
ST_IDLE, ST_REFRESH, ST_ACTIVATE, ST_RCD, ST_RW, ST_RAS1, ST_RAS2, ST_PRECHARGE);
signal state_r, state_x : fsm_state_type := ST_INIT_WAIT;
-- SDRAM mode register data sent on the address bus.
--
-- | A12-A10 | A9 | A8 A7 | A6 A5 A4 | A3 | A2 A1 A0 |
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
-- 0 0 0 0 0 0 0 1 0 0 0 0 0
constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "010" & "0" & "000";
-- SDRAM commands combine SDRAM inputs: cs, ras, cas, we.
subtype cmd_type is unsigned(3 downto 0);
constant CMD_ACTIVATE : cmd_type := "0011";
constant CMD_PRECHARGE : cmd_type := "0010";
constant CMD_WRITE : cmd_type := "0100";
constant CMD_READ : cmd_type := "0101";
constant CMD_MODE : cmd_type := "0000";
constant CMD_NOP : cmd_type := "0111";
constant CMD_REFRESH : cmd_type := "0001";
signal cmd_r : cmd_type;
signal cmd_x : cmd_type;
signal bank_s : std_logic_vector(1 downto 0);
signal row_s : std_logic_vector(12 downto 0);
signal col_s : std_logic_vector(8 downto 0);
signal addr_r : std_logic_vector(12 downto 0);
signal addr_x : std_logic_vector(12 downto 0); -- SDRAM row/column address.
signal sd_dout_r : std_logic_vector(15 downto 0);
signal sd_dout_x : std_logic_vector(15 downto 0);
signal sd_busdir_r : std_logic;
signal sd_busdir_x : std_logic;
signal timer_r, timer_x : natural range 0 to 20000 := 0;
signal refcnt_r, refcnt_x : natural range 0 to 7 := 0;
signal bank_r, bank_x : std_logic_vector(1 downto 0);
signal cke_r, cke_x : std_logic;
signal sd_dqmu_r, sd_dqmu_x : std_logic;
signal sd_dqml_r, sd_dqml_x : std_logic;
signal ready_r, ready_x : std_logic;
begin
-- SDRAM signals.
(sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo) <= cmd_r; -- SDRAM operation control bits
sdCke_o <= cke_r; -- SDRAM clock enable
sdBs_o <= bank_r; -- SDRAM bank address
sdAddr_o <= addr_r; -- SDRAM address
sdData_io <= sd_dout_r when sd_busdir_r = '1' else (others => 'Z'); -- SDRAM data bus.
sdDqmh_o <= sd_dqmu_r; -- SDRAM high data byte enable, active low
sdDqml_o <= sd_dqml_r; -- SDRAM low date byte enable, active low
ready_o <= ready_r;
-- Data back to host, not buffered and must be latched when done_o == '1'.
data_o <= sdData_io;
-- 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
-- BS0 BS1 | ROW (A12-A0) 8192 rows | COL (A8-A0) 512 cols |
bank_s <= addr_i(23 downto 22);
row_s <= addr_i(21 downto 9);
col_s <= addr_i(8 downto 0);
-- When rw_i activates:
-- hold_i | active_r
-- 0 | 0 -> 0 activate the row, issue read/write, precharge all rows when done
-- 1 | 0 -> 1 activate the row, issue read/write, do not precharage when done
-- 1 | 1 -> 1 issue read/write, do not precharge when done
-- 0 | 1 -> 0 issue read/write, precharge all rows when done
--
-- Thus, for a "one time" read / write, hold_i should be low. For a series of reads / writes
-- to the same bank, hold_i should be held high for all reads / writes, but then brought
-- low for the final read / write.
process (
state_r, timer_r, refcnt_r, cke_r, addr_r, sd_dout_r, sd_busdir_r, sd_dqmu_r, sd_dqml_r, ready_r,
bank_s, row_s, col_s,
rw_i, refresh_i, addr_i, data_i, we_i, ub_i, lb_i )
begin
state_x <= state_r; -- Stay in the same state unless changed.
timer_x <= timer_r; -- Hold the cycle timer by default.
refcnt_x <= refcnt_r; -- Hold the refresh timer by default.
cke_x <= cke_r; -- Stay in the same clock mode unless changed.
cmd_x <= CMD_NOP; -- Default to NOP unless changed.
bank_x <= bank_r; -- Register the SDRAM bank.
addr_x <= addr_r; -- Register the SDRAM address.
sd_dout_x <= sd_dout_r; -- Register the SDRAM write data.
sd_busdir_x <= sd_busdir_r; -- Register the SDRAM bus tristate control.
sd_dqmu_x <= sd_dqmu_r;
sd_dqml_x <= sd_dqml_r;
ready_x <= ready_r; -- Always ready unless performing initialization.
done_o <= '0'; -- Done tick, single cycle.
if timer_r /= 0 then
timer_x <= timer_r - 1;
else
cke_x <= '1';
bank_x <= bank_s;
addr_x <= "0000" & col_s; -- A10 low for rd/wr commands to suppress auto-precharge.
sd_dqmu_x <= '0';
sd_dqml_x <= '0';
case state_r is
when ST_INIT_WAIT =>
-- 1. Wait 200us with DQM signals high, cmd NOP.
-- 2. Precharge all banks.
-- 3. Eight refresh cycles.
-- 4. Set mode register.
-- 5. Eight refresh cycles.
state_x <= ST_INIT_PRECHARGE;
timer_x <= 20000; -- Wait 200us (20,000 cycles).
-- timer_x <= 2; -- for simulation
sd_dqmu_x <= '1';
sd_dqml_x <= '1';
when ST_INIT_PRECHARGE =>
state_x <= ST_INIT_REFRESH1;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
cmd_x <= CMD_PRECHARGE;
timer_x <= 1; -- Wait 1 cycles plus state overhead for 20ns Trp.
addr_x(10) <= '1'; -- Precharge all banks.
when ST_INIT_REFRESH1 =>
if refcnt_r = 0 then
state_x <= ST_INIT_MODE;
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
when ST_INIT_MODE =>
state_x <= ST_INIT_REFRESH2;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
bank_x <= "00";
addr_x <= MODE_REG;
cmd_x <= CMD_MODE;
timer_x <= 1; -- Trsc == 2 cycles after issuing MODE command.
when ST_INIT_REFRESH2 =>
if refcnt_r = 0 then
state_x <= ST_IDLE;
ready_x <= '1';
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
--
-- Normal Operation
--
when ST_IDLE =>
-- 60ns since activate when coming from PRECHARGE state.
-- 10ns since PRECHARGE. Trp == 20ns min.
if rw_i = '1' then
state_x <= ST_ACTIVATE;
cmd_x <= CMD_ACTIVATE;
addr_x <= row_s; -- Set bank select and row on activate command.
elsif refresh_i = '1' then
state_x <= ST_REFRESH;
cmd_x <= CMD_REFRESH;
timer_x <= 5; -- Wait 5 cycles plus state overhead for 70ns refresh.
end if;
when ST_REFRESH =>
state_x <= ST_IDLE;
done_o <= '1';
when ST_ACTIVATE =>
-- Trc (Active to Active Command Period) is 65ns min.
-- 70ns since activate when coming from PRECHARGE -> IDLE states.
-- 20ns since PRECHARGE.
-- ACTIVATE command is presented to the SDRAM. The command out of this
-- state will be NOP for one cycle.
state_x <= ST_RCD;
sd_dout_x <= data_i; -- Register any write data, even if not used.
when ST_RCD =>
-- 10ns since activate.
-- Trcd == 20ns min. The clock is 10ns, so the requirement is satisfied by this state.
-- READ or WRITE command will be active in the next cycle.
state_x <= ST_RW;
if we_i = '0' then
cmd_x <= CMD_WRITE;
sd_busdir_x <= '1'; -- The SDRAM latches the input data with the command.
sd_dqmu_x <= ub_i;
sd_dqml_x <= lb_i;
else
cmd_x <= CMD_READ;
end if;
when ST_RW =>
-- 20ns since activate.
-- READ or WRITE command presented to SDRAM.
state_x <= ST_RAS1;
sd_busdir_x <= '0';
when ST_RAS1 =>
-- 30ns since activate.
state_x <= ST_RAS2;
when ST_RAS2 =>
-- 40ns since activate.
-- Tras (Active to precharge Command Period) 45ns min.
-- PRECHARGE command will be active in the next cycle.
state_x <= ST_PRECHARGE;
cmd_x <= CMD_PRECHARGE;
addr_x(10) <= '1'; -- Precharge all banks.
when ST_PRECHARGE =>
-- 50ns since activate.
-- PRECHARGE presented to SDRAM.
state_x <= ST_IDLE;
done_o <= '1'; -- Read data is ready and should be latched by the host.
end case;
end if;
end process;
process (clk_100m0_i)
begin
if falling_edge(clk_100m0_i) then
if reset_i = '1' then
state_r <= ST_INIT_WAIT;
timer_r <= 0;
cmd_r <= CMD_NOP;
cke_r <= '0';
ready_r <= '0';
else
state_r <= state_x;
timer_r <= timer_x;
refcnt_r <= refcnt_x;
cke_r <= cke_x; -- CKE to SDRAM.
cmd_r <= cmd_x; -- Command to SDRAM.
bank_r <= bank_x; -- Bank to SDRAM.
addr_r <= addr_x; -- Address to SDRAM.
sd_dout_r <= sd_dout_x; -- Data to SDRAM.
sd_busdir_r <= sd_busdir_x; -- SDRAM bus direction.
sd_dqmu_r <= sd_dqmu_x; -- Upper byte enable to SDRAM.
sd_dqml_r <= sd_dqml_x; -- Lower byte enable to SDRAM.
ready_r <= ready_x;
end if;
end if;
end process;
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE rc5_pkg IS
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0);
type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input
ST_KEY_IN, -- In this state key has been fully loaded
ST_KEY_EXP, -- In this state key expansion is in progress
ST_READY); -- In this state RC5 key expansion has completed
--RC5 state machine has five key states
TYPE StateType IS(
ST_IDLE, -- In this state RC5 is ready for input
ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
-- ENCRYPTION ONLY
-- The reason it wasn't converged to only ST_ROUND
----Is for logical reasons
ST_ROUND_OP, -- In this state RC5 round op is performed.
-- The state machine remains in this state
-- for twelve clock cycles.
ST_POST_ROUND, -- In this state RC5 post-round op is performed
-- DECRYPTION ONLY
-- The reason it wasn't converged to only ST_ROUND
----Is for logical reasons
ST_READY -- In this state RC5 has completed encryption
);
COMPONENT rotLeft -- Left Rotate Module
PORT (
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Input to be rotated
amnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --Amount to Rotate by
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- Rotated Input
);
END COMPONENT;
COMPONENT rotRight -- Right Rotate Module
PORT (
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Input to be rotated
amnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --Amount to Rotate by
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- Rotated Input
);
END COMPONENT;
COMPONENT rc5_key -- Key expansion module
PORT(
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic
);
END COMPONENT;
COMPONENT rc5 -- Encryption module
PORT(
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; --1 for encryption 0 for decryption
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END COMPONENT;
END rc5_pkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
library LIB1;
use LIB1.pkg1_lib1.all;
entity com2_pkg1_lib1 is
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com2_pkg1_lib1;
architecture RTL of com2_pkg1_lib1 is
begin
inst: com1_pkg1_lib1
generic map (WITH_GENERIC => FALSE)
port map (
data_i => data_i,
data_o => data_o
);
end architecture RTL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-conf-c.vhd,v 1.1 2004/04/06 10:44:20 wig Exp $
-- $Date: 2004/04/06 10:44:20 $
-- $Log: ioblock0_e-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:44:20 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ioblock0_e_conf / ioblock0_e
--
configuration ioblock0_e_conf of ioblock0_e is
for rtl
-- Generated Configuration
for ioc_data_i1 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_data_o1 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
end for;
end ioblock0_e_conf;
--
-- End of Generated Configuration ioblock0_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fetch_tb IS
END fetch_tb;
ARCHITECTURE behavior OF fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fetch_tb IS
END fetch_tb;
ARCHITECTURE behavior OF fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fetch_tb IS
END fetch_tb;
ARCHITECTURE behavior OF fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1990.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01990ent IS
END c07s02b02x00p07n01i01990ent;
ARCHITECTURE c07s02b02x00p07n01i01990arch OF c07s02b02x00p07n01i01990ent IS
BEGIN
TESTING: PROCESS
type ft is file of integer;
file f1 : ft is "01.vhdl";
file f2 : ft is "02.vhdl";
BEGIN
if (f1/=f2) then -- Failure_here
-- equality and inequality operators are
NULL; -- not defined for file types.
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i01990 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01990arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1990.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01990ent IS
END c07s02b02x00p07n01i01990ent;
ARCHITECTURE c07s02b02x00p07n01i01990arch OF c07s02b02x00p07n01i01990ent IS
BEGIN
TESTING: PROCESS
type ft is file of integer;
file f1 : ft is "01.vhdl";
file f2 : ft is "02.vhdl";
BEGIN
if (f1/=f2) then -- Failure_here
-- equality and inequality operators are
NULL; -- not defined for file types.
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i01990 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01990arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1990.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01990ent IS
END c07s02b02x00p07n01i01990ent;
ARCHITECTURE c07s02b02x00p07n01i01990arch OF c07s02b02x00p07n01i01990ent IS
BEGIN
TESTING: PROCESS
type ft is file of integer;
file f1 : ft is "01.vhdl";
file f2 : ft is "02.vhdl";
BEGIN
if (f1/=f2) then -- Failure_here
-- equality and inequality operators are
NULL; -- not defined for file types.
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i01990 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01990arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY system_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_processing_system7_0_100M_0;
ARCHITECTURE system_rst_processing_system7_0_100M_0_arch OF system_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_processing_system7_0_100M_0_arch;
|
-- Retarda en N ciclos el vector recibido
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay_reg is
generic(
N: natural := 8;
DELAY: natural := 0
);
port(
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
A: in std_logic_vector(N-1 downto 0);
B: out std_logic_vector(N-1 downto 0)
);
end entity delay_reg;
architecture delay_arch of delay_reg is
type t_aux is array(0 to DELAY+1) of std_logic_vector(N-1 downto 0);
signal aux: t_aux;
begin
-- Entrada
aux(0) <= A;
gen_retardo: for i in 0 to DELAY generate
sin_retardo: if i = 0 generate
aux(1) <= aux(0);
end generate sin_retardo;
con_retardo: if i > 0 generate
reg: entity work.registroNb
generic map(N)
port map(
clk => clock,
rst => reset,
ena => enable,
d => aux(i),
q => aux(i+1)
);
end generate con_retardo;
end generate gen_retardo;
-- Salida
B <= aux(DELAY+1);
end architecture delay_arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
ENA => ENA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ENA => ENA_R,
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
-- NEED RESULT: ARCH00649: The keyword 'Variable' is optional in an interface variable declaration passed
-- NEED RESULT: ARCH00649: The mode and default expression are optional in an interface variable declaration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00649
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (9)
-- 4.3.3 (10)
-- 4.3.3 (11)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00649)
-- ENT00649_Test_Bench(ARCH00649_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00649 of E00000 is
procedure Proc1 ( P1 : inout integer ;
variable P2, P3, P4 : inout integer ) is
begin
test_report ( "ARCH00649" ,
"The keyword 'Variable' is optional in an "&
"interface variable declaration" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
P1 := 1 ;
end Proc1 ;
procedure Proc2 ( P1 : integer ;
P2, P3, P4 : in integer ) is
begin
test_report ( "ARCH00649" ,
"The mode and default expression are optional "&
"in an interface variable declaration" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
end Proc2 ;
begin
process
variable V1 : integer := 1 ;
variable V2 : integer := 2 ;
variable V3 : integer := 3 ;
variable V4 : integer := 4 ;
begin
Proc1 ( V1, V2, V3, V4 ) ;
Proc2 ( V1, V2, V3, V4 ) ;
wait ;
end process ;
end ARCH00649 ;
--
entity ENT00649_Test_Bench is
end ENT00649_Test_Bench ;
architecture ARCH00649_Test_Bench of ENT00649_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00649 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00649_Test_Bench ;
--
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_b3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-28 754 1.2 run at 120 MHz
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs
-- 2015-01-16 636 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** and/or disclosed only pursuant to the terms of a valid **
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-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
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-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
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