content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:52 11/09/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/EX_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- De... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:47 04/04/2013
-- Design Name:
-- Module Name: encoder8x3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international... |
-- wasca.vhd
-- Generated using ACDS version 15.1 193
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abu... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: artylib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: artylib
-- Description: Digilent Arty componen... |
-- This block makes double accumulator linear FM chirp generator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity chirp_gen is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end ... |
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'... |
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'... |
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'... |
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'... |
entity slice4 is
end entity;
architecture test of slice4 is
procedure proc1(x : in string) is
begin
report x;
report integer'image(x'left);
report integer'image(x'right);
report boolean'image(x'ascending);
assert x'left = 1;
assert x'right = 5;
assert x'... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Instruction_ROM.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- ---------------------------------------... |
-- ======================================================================
-- CBC-MAC-DES testbench
-- Copyright (C) 2015 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gen... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fol... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fol... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------... |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram for openMAC Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.... |
-------------------------------------------------------------------------------
--! @file nf_top_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief NanoFIP FPGA package.
-----------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity ddr4_dimm_u200_wrapper is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke ... |
entity tb_sram03 is
end tb_sram03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram03 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: en... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
--------------------------------------------... |
-- file: my_dcm_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not ... |
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_shiftreg is end;
architecture test_shiftreg of test_shiftreg is
component shift_reg
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
control:in std_logic_vector(1 downto 0);
Clear :... |
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEE... |
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEE... |
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEE... |
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEE... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "InputSwitchingMatrix"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ie... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
port
(
alu_input1: in std_logic_vector(15 downto 0);
alu_input2: in std_logic_vector(15 downto 0);
alu_output: out std_logic_vector(15 downto 0);
alu_operator: in std_logic_vector(2 downto ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineer... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich (pwsof... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_project2 is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type VHDLOUT_TYPE is array (0 downto 0) of std_logic;
end CONV_PACK_project2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;... |
architecture rtl of fifo is
variable v_element : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity servo_pwm is
generic (
ResW : positive := 7
);
port (
Clk : in bit1; -- Must be 64 kHz
RstN : in bit1;
--
Pos : in word(ResW-1 downto 0);
--
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Title: SDRAMController.vhd
-- Original Author: Matthew Hagerty
-- Modified by: René Richard
-- Description:
--
-- LICENSE
--
-- This file is part of SDRAMController.
-- TDSN76489 is free software: you can redistribute it and/or modify
-- it under the terms of the G... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE rc5_pkg IS
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0);
type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input
ST_KEY_I... |
library IEEE;
use IEEE.std_logic_1164.all;
library LIB1;
use LIB1.pkg1_lib1.all;
entity com2_pkg1_lib1 is
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com2_pkg1_lib1;
architecture RTL of com2_pkg1_lib1 is
begin
inst: com1_pkg1_lib1
generic map (WITH_GENERIC => FALSE... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:02 04/01/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- Retarda en N ciclos el vector recibido
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay_reg is
generic(
N: natural := 8;
DELAY: natural := 0
);
port(
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
A: in std... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
-- NEED RESULT: ARCH00649: The keyword 'Variable' is optional in an interface variable declaration passed
-- NEED RESULT: ARCH00649: The mode and default expression are optional in an interface variable declaration passed
-------------------------------------------------------------------------------
--
-- Cop... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogen... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *********************************************... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *********************************************... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *********************************************... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *********************************************... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *********************************************... |
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