content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word s... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_constant_library is
-- opcodes
constant OPCODE_R_TYPE : std_logic_vector(5 downto 0) := "000000";
constant OPCODE_LOAD_WORD : std_logic_vector(5 downto 0) := "100011";
constant OPCODE_STORE_WORD : std_logic_vector(5 downto 0) := "101011";... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- ch.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of th... |
library verilog;
use verilog.vl_types.all;
entity dps_mimsr is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_VALID : in vl_logic;
oREQ_VALID : out vl_logic;
oREQ_DATA : out vl_logic_vector(31 downto 0)
);
end dp... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000011... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000011... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000011... |
-- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0%
-- GENERATION: XML
-- master_reconfig.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity master_reconfig is
generic (
ENABLE_BYTEENABLE : boolean := false;
BYTEENABLE_W... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_376;
architecture augh of mul_376 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_376;
architecture augh of mul_376 is
signal tmp_res : signed(... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 20:31:10 10/25/2015
-- Design Name:
-- Module Name: B_Serial_Communication - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions: ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
-- Date : Thu Apr 5 01:27:52 2018
-- Host : varun-laptop running 64-bit Se... |
--
-- file: r2p_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now
-- rev. 1.2 May 18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request).
-... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- I2S_RX PAC
-- Copyright (c) Fernando Rodriguez, 2007
--
-- Configuration and type declarations for I2S_RX
--
-- This file is part of I2S_RX.
-- I2S_RX is free software: you can redistribute it and/or modify
-- it under the term... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/05/07 21:48:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
--------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/05/07 21:48:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
--------------------------------------... |
package pkg is
generic (N : integer := 2);
procedure showPackageN;
impure function c_int return integer;
attribute foreign of c_int : function is "VHPIDIRECT caux.so getInt";
end package pkg;
package body pkg is
procedure showPackageN is
begin
report integer'image(N);
end;
impure function c_int ... |
--------------------------------------------------------------------------------
--
-- UART loopback demo for the Arty FPGA board
--
-- Ports:
-- clk_100mhz_ipad : Arty 100MHz clock
-- ck_rst_n_ipad : Arty CK_RST active low reset pin
-- uart_rx_ipad : UART Rx line connected to the FT2232HQ chip Tx... |
-- NEED RESULT: ARCH00477: Functions can return dynamically sized objects passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------------... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_rnd;
architecture behaviour of dk27_rnd is
constant START: std_logic_vector(2 downto 0) :=... |
-- ####################################
-- # Project: Yarr
-- # Author: Vyassa Baratham
-- # E-Mail: vbaratham at berkeley.edu
-- # Comments: assert the output for the duration of the
-- # clock cycle following an edge on the input
-- # Data: 09/2017
-- # Outputs are synchronous to clk_i
-- ##################... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: stack_ctrl.vhd
-- // Date: 12/9/2004
-- // Description: Stack Controller
-- // Class: CSE 378
-- ==========================================... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
-- Accellera Standard V2.3 Open Verification Library (OVL)
-- Accellera Copyright (c) 2005-2008. All rights reserved.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE std_ovl IS
constant OVL_STD_DEFINES_H : boolean := true;
constant OVL_VERSION : string := "V2.3";
-- active edges
constant OVL_NOEDGE :... |
-- FPGA Clock Circuit for Altera DE-2 board
-- Cliff Chapman
-- 11/04/2013
--
-- Lab 9 - Digital Systems Design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY vendi IS
PORT (
-- Coins input
nickel_in : IN STD_LOGIC;
dime_in : IN STD_LOGIC;
quarter... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 24 17:28:31 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible micro... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bin_count is
generic(N: integer := 3);
port (
clk, reset: in std_logic;
count: out std_logic_vector((2 ** N) - 1 downto 0)
);
end bin_count;
architecture bin_count_arch of bin_c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY test_mux2 IS
END test_mux2;
ARCHITECTURE t_mux2_est OF test_mux2 IS
COMPONENT mux2
GENERIC (N: INTEGER:=32);
PORT (d0, d1: IN std_logic_vector(N-1 DOWNTO 0);
s: IN std_logic;
y: OUT std_logic_vector(N-1 DOWNTO 0));
E... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity wave5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wave5 is
type pair is record
a, b : integer;
end record;
type rec is record
x : integer;
y : std_logic_vector(1 to 3);
z : pair;
end record;
signal r : rec;
begin
mai... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- A simple multiplexer
--
-- outval is val1 if switch is LOW ('0'), val2 otherwise.
entity Mux is
generic(
WIDTH : integer := 16
);
Port(
val1 : in std_ulogic_vector(WIDTH - 1 downto 0);
val2 : in std_ulogic_vector(WIDTH - 1 downto 0)... |
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