content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
end config;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
end config;
|
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true); --true, if active-high; false, if active-low
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => "1111100000",
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw(i),
aRst => pRstLck);
end generate DataEncoders;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(1) <= vid_pData(15 downto 8); -- green is channel 1
pDataOut(0) <= vid_pData(7 downto 0); -- blue is channel 0
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_3166d4cc5b09c744.vhd when simulating
-- the core, cntr_11_0_3166d4cc5b09c744. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_3166d4cc5b09c744 IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END cntr_11_0_3166d4cc5b09c744;
ARCHITECTURE cntr_11_0_3166d4cc5b09c744_a OF cntr_11_0_3166d4cc5b09c744 IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_3166d4cc5b09c744
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_3166d4cc5b09c744 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 2,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_3166d4cc5b09c744
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_3166d4cc5b09c744_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_constant_library is
-- opcodes
constant OPCODE_R_TYPE : std_logic_vector(5 downto 0) := "000000";
constant OPCODE_LOAD_WORD : std_logic_vector(5 downto 0) := "100011";
constant OPCODE_STORE_WORD : std_logic_vector(5 downto 0) := "101011";
constant OPCODE_BRANCH_EQ : std_logic_vector(5 downto 0) := "000100";
constant OPCODE_ADDI : std_logic_vector(5 downto 0) := "001000";
-- funct
constant FUNCT_AND : std_logic_vector(5 downto 0) := "100100";
constant FUNCT_OR : std_logic_vector(5 downto 0) := "100101";
constant FUNCT_ADD : std_logic_vector(5 downto 0) := "100000";
constant FUNCT_SUBTRACT : std_logic_vector(5 downto 0) := "100010";
constant FUNCT_LESS_THAN : std_logic_vector(5 downto 0) := "101010";
constant FUNCT_NOR : std_logic_vector(5 downto 0) := "100111";
-- ALU signals
constant ALU_AND : std_logic_vector(3 downto 0) := "0000";
constant ALU_OR : std_logic_vector(3 downto 0) := "0001";
constant ALU_ADD : std_logic_vector(3 downto 0) := "0010";
constant ALU_SUBTRACT : std_logic_vector(3 downto 0) := "0110";
constant ALU_LESS_THAN : std_logic_vector(3 downto 0) := "0111";
constant ALU_NOR : std_logic_vector(3 downto 0) := "1100";
end cpu_constant_library;
package body cpu_constant_library is
end cpu_constant_library;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- ch.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity ch is
port (
x : in std_ulogic_vector(31 downto 0); -- first binary input
y : in std_ulogic_vector(31 downto 0); -- second binary input
z : in std_ulogic_vector(31 downto 0); -- third binary input
o : out std_ulogic_vector(31 downto 0) -- output
);
end entity ch;
architecture behav of ch is
begin
process(x, y, z) -- the process is woken up whenever the inputs change
begin
o <= (x and y) xor ((not (x)) and z);
end process;
end architecture behav;
|
library verilog;
use verilog.vl_types.all;
entity dps_mimsr is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_VALID : in vl_logic;
oREQ_VALID : out vl_logic;
oREQ_DATA : out vl_logic_vector(31 downto 0)
);
end dps_mimsr;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
a : in std_logic_vector(widthA-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
WIDTHB : natural := 4;
WIDTHA : natural := 4
);
port (
a : in std_logic_vector(4-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(4-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(8-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_bus_concat_GNBH75ZTOD is
generic (
WIDTHB : natural := 4;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(4-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(12-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNBH75ZTOD;
component alt_dspbuilder_bus_concat_GNXPBV3I7L is
generic (
WIDTHB : natural := 4;
WIDTHA : natural := 12
);
port (
a : in std_logic_vector(12-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(4-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(16-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNXPBV3I7L;
begin
alt_dspbuilder_bus_concat_GNAUBM7IRL_0: if ((WIDTHB = 4) and (WIDTHA = 4)) generate
inst_alt_dspbuilder_bus_concat_GNAUBM7IRL_0: alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map(WIDTHB => 4, WIDTHA => 4)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNBH75ZTOD_1: if ((WIDTHB = 4) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GNBH75ZTOD_1: alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map(WIDTHB => 4, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNXPBV3I7L_2: if ((WIDTHB = 4) and (WIDTHA = 12)) generate
inst_alt_dspbuilder_bus_concat_GNXPBV3I7L_2: alt_dspbuilder_bus_concat_GNXPBV3I7L
generic map(WIDTHB => 4, WIDTHA => 12)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 4) and (WIDTHA = 4)) or ((WIDTHB = 4) and (WIDTHA = 8)) or ((WIDTHB = 4) and (WIDTHA = 12)))
report "Please run generate again" severity error;
end architecture rtl;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
package A_NG is
end package;
package body A_NG is
procedure PROC(S: in integer; Q: out integer) is
begin
-- Spurious error without forward declaration
PROC(S,Q);
end procedure;
end package body;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
variable oo : integer;
begin
PROC_A(I,oo);
O <= oo;
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity post_norm_sqrt is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
fract_26_i : in std_logic_vector(FRAC_WIDTH+2 downto 0); -- hidden(1) & fraction(11)
exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
ine_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end post_norm_sqrt;
architecture rtl of post_norm_sqrt is
signal s_expa, s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fract_26_i : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_ine_i : std_logic;
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_sign_i : std_logic;
signal s_opa_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o : std_logic;
signal s_expo : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fraco1 : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_guard, s_round, s_sticky, s_roundup : std_logic;
signal s_frac_rnd : std_logic_vector(FRAC_WIDTH downto 0);
signal s_infa : std_logic;
signal s_nan_op, s_nan_a: std_logic;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_expa <= opa_i(30 downto 23);
s_sign_i <= opa_i(31);
s_fract_26_i <= fract_26_i;
s_ine_i <= ine_i;
s_exp_i <= exp_i;
s_rmode_i <= rmode_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
end if;
end process;
-- *** Stage 1 ***
s_expo <= s_exp_i;
s_fraco1 <= s_fract_26_i;
-- ***Stage 2***
-- Rounding
s_guard <= s_fraco1(1);
s_round <= s_fraco1(0);
s_sticky <= s_ine_i;
s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
'0'; -- round to zero(truncate = no rounding)
process(clk_i)
begin
if rising_edge(clk_i) then
if s_roundup='1' then
s_frac_rnd <= s_fraco1(25 downto 2) + '1';
else
s_frac_rnd <= s_fraco1(25 downto 2);
end if;
end if;
end process;
-- ***Stage 3***
-- Output
s_infa <= '1' when s_expa="11111111" else '0';
s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
s_nan_op <= '1' when s_sign_i='1' and or_reduce(s_opa_i(30 downto 0))='1' else '0'; -- sqrt(-x) = NaN
s_ine_o <= '1' when s_ine_i='1' and (s_infa or s_nan_a or s_nan_op)='0' else '0';
process( s_nan_a, s_nan_op, s_infa, s_sign_i, s_expo, s_frac_rnd)
begin
if (s_nan_a or s_nan_op)='1' then
s_output_o <= s_sign_i & QNAN;
elsif s_infa ='1' then
s_output_o <= s_sign_i & INF;
else
s_output_o <= s_sign_i & s_expo & s_frac_rnd(22 downto 0);
end if;
end process;
end rtl; |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity post_norm_sqrt is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
fract_26_i : in std_logic_vector(FRAC_WIDTH+2 downto 0); -- hidden(1) & fraction(11)
exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
ine_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end post_norm_sqrt;
architecture rtl of post_norm_sqrt is
signal s_expa, s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fract_26_i : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_ine_i : std_logic;
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_sign_i : std_logic;
signal s_opa_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o : std_logic;
signal s_expo : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fraco1 : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_guard, s_round, s_sticky, s_roundup : std_logic;
signal s_frac_rnd : std_logic_vector(FRAC_WIDTH downto 0);
signal s_infa : std_logic;
signal s_nan_op, s_nan_a: std_logic;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_expa <= opa_i(30 downto 23);
s_sign_i <= opa_i(31);
s_fract_26_i <= fract_26_i;
s_ine_i <= ine_i;
s_exp_i <= exp_i;
s_rmode_i <= rmode_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
end if;
end process;
-- *** Stage 1 ***
s_expo <= s_exp_i;
s_fraco1 <= s_fract_26_i;
-- ***Stage 2***
-- Rounding
s_guard <= s_fraco1(1);
s_round <= s_fraco1(0);
s_sticky <= s_ine_i;
s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
'0'; -- round to zero(truncate = no rounding)
process(clk_i)
begin
if rising_edge(clk_i) then
if s_roundup='1' then
s_frac_rnd <= s_fraco1(25 downto 2) + '1';
else
s_frac_rnd <= s_fraco1(25 downto 2);
end if;
end if;
end process;
-- ***Stage 3***
-- Output
s_infa <= '1' when s_expa="11111111" else '0';
s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
s_nan_op <= '1' when s_sign_i='1' and or_reduce(s_opa_i(30 downto 0))='1' else '0'; -- sqrt(-x) = NaN
s_ine_o <= '1' when s_ine_i='1' and (s_infa or s_nan_a or s_nan_op)='0' else '0';
process( s_nan_a, s_nan_op, s_infa, s_sign_i, s_expo, s_frac_rnd)
begin
if (s_nan_a or s_nan_op)='1' then
s_output_o <= s_sign_i & QNAN;
elsif s_infa ='1' then
s_output_o <= s_sign_i & INF;
else
s_output_o <= s_sign_i & s_expo & s_frac_rnd(22 downto 0);
end if;
end process;
end rtl; |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the square-root unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity post_norm_sqrt is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
fract_26_i : in std_logic_vector(FRAC_WIDTH+2 downto 0); -- hidden(1) & fraction(11)
exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
ine_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end post_norm_sqrt;
architecture rtl of post_norm_sqrt is
signal s_expa, s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fract_26_i : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_ine_i : std_logic;
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_sign_i : std_logic;
signal s_opa_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o : std_logic;
signal s_expo : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fraco1 : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal s_guard, s_round, s_sticky, s_roundup : std_logic;
signal s_frac_rnd : std_logic_vector(FRAC_WIDTH downto 0);
signal s_infa : std_logic;
signal s_nan_op, s_nan_a: std_logic;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_expa <= opa_i(30 downto 23);
s_sign_i <= opa_i(31);
s_fract_26_i <= fract_26_i;
s_ine_i <= ine_i;
s_exp_i <= exp_i;
s_rmode_i <= rmode_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
end if;
end process;
-- *** Stage 1 ***
s_expo <= s_exp_i;
s_fraco1 <= s_fract_26_i;
-- ***Stage 2***
-- Rounding
s_guard <= s_fraco1(1);
s_round <= s_fraco1(0);
s_sticky <= s_ine_i;
s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
'0'; -- round to zero(truncate = no rounding)
process(clk_i)
begin
if rising_edge(clk_i) then
if s_roundup='1' then
s_frac_rnd <= s_fraco1(25 downto 2) + '1';
else
s_frac_rnd <= s_fraco1(25 downto 2);
end if;
end if;
end process;
-- ***Stage 3***
-- Output
s_infa <= '1' when s_expa="11111111" else '0';
s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
s_nan_op <= '1' when s_sign_i='1' and or_reduce(s_opa_i(30 downto 0))='1' else '0'; -- sqrt(-x) = NaN
s_ine_o <= '1' when s_ine_i='1' and (s_infa or s_nan_a or s_nan_op)='0' else '0';
process( s_nan_a, s_nan_op, s_infa, s_sign_i, s_expo, s_frac_rnd)
begin
if (s_nan_a or s_nan_op)='1' then
s_output_o <= s_sign_i & QNAN;
elsif s_infa ='1' then
s_output_o <= s_sign_i & INF;
else
s_output_o <= s_sign_i & s_expo & s_frac_rnd(22 downto 0);
end if;
end process;
end rtl; |
-- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0%
-- GENERATION: XML
-- master_reconfig.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity master_reconfig is
generic (
ENABLE_BYTEENABLE : boolean := false;
BYTEENABLE_WIDTH : integer := 4;
RECONFIG_ADDR_WIDTH : integer := 6;
RECONFIG_DATA_WIDTH : integer := 32;
reconf_width : integer := 64;
WAIT_FOR_LOCK : boolean := true
);
port (
mgmt_clk : in std_logic := '0'; -- mgmt_clk.clk
mgmt_reset : in std_logic := '0'; -- mgmt_reset.reset
mgmt_waitrequest : out std_logic; -- mgmt_avalon_slave.waitrequest
mgmt_read : in std_logic := '0'; -- .read
mgmt_write : in std_logic := '0'; -- .write
mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
mgmt_address : in std_logic_vector(5 downto 0) := (others => '0'); -- .address
mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll.reconfig_to_pll
reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => '0') -- reconfig_from_pll.reconfig_from_pll
);
end entity master_reconfig;
architecture rtl of master_reconfig is
component altera_pll_reconfig_top is
generic (
device_family : string := "";
ENABLE_MIF : boolean := false;
MIF_FILE_NAME : string := "";
ENABLE_BYTEENABLE : boolean := false;
BYTEENABLE_WIDTH : integer := 4;
RECONFIG_ADDR_WIDTH : integer := 6;
RECONFIG_DATA_WIDTH : integer := 32;
reconf_width : integer := 64;
WAIT_FOR_LOCK : boolean := true
);
port (
mgmt_clk : in std_logic := 'X'; -- clk
mgmt_reset : in std_logic := 'X'; -- reset
mgmt_waitrequest : out std_logic; -- waitrequest
mgmt_read : in std_logic := 'X'; -- read
mgmt_write : in std_logic := 'X'; -- write
mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata
mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll
reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_from_pll
mgmt_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component altera_pll_reconfig_top;
begin
master_reconfig_inst : component altera_pll_reconfig_top
generic map (
device_family => "Cyclone V",
ENABLE_MIF => false,
MIF_FILE_NAME => "",
ENABLE_BYTEENABLE => ENABLE_BYTEENABLE,
BYTEENABLE_WIDTH => BYTEENABLE_WIDTH,
RECONFIG_ADDR_WIDTH => RECONFIG_ADDR_WIDTH,
RECONFIG_DATA_WIDTH => RECONFIG_DATA_WIDTH,
reconf_width => reconf_width,
WAIT_FOR_LOCK => WAIT_FOR_LOCK
)
port map (
mgmt_clk => mgmt_clk, -- mgmt_clk.clk
mgmt_reset => mgmt_reset, -- mgmt_reset.reset
mgmt_waitrequest => mgmt_waitrequest, -- mgmt_avalon_slave.waitrequest
mgmt_read => mgmt_read, -- .read
mgmt_write => mgmt_write, -- .write
mgmt_readdata => mgmt_readdata, -- .readdata
mgmt_address => mgmt_address, -- .address
mgmt_writedata => mgmt_writedata, -- .writedata
reconfig_to_pll => reconfig_to_pll, -- reconfig_to_pll.reconfig_to_pll
reconfig_from_pll => reconfig_from_pll, -- reconfig_from_pll.reconfig_from_pll
mgmt_byteenable => "0000" -- (terminated)
);
end architecture rtl; -- of master_reconfig
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll_reconfig" version="18.0" >
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="ENABLE_MIF" value="false" />
-- Retrieval info: <generic name="MIF_FILE_NAME" value="" />
-- Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
-- Retrieval info: </instance>
-- IPFS_FILES : master_reconfig.vho
-- RELATED_FILES: master_reconfig.vhd, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_376;
architecture augh of mul_376 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_376;
architecture augh of mul_376 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 20:31:10 10/25/2015
-- Design Name:
-- Module Name: B_Serial_Communication - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Serial Communication from FPGA to PC
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity B_Serial_Communication is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Send : in STD_LOGIC;
SteamOut : out STD_LOGIC;
DataIn : in STD_LOGIC;
SwitchSeg : in STD_LOGIC_VECTOR (7 downto 0);
DataOut : out STD_LOGIC_VECTOR (7 downto 0));
end B_Serial_Communication;
architecture Behavioral of B_Serial_Communication is
--Embedded Signal
signal reg : STD_LOGIC_VECTOR (19 downto 0);
signal regtemp : STD_LOGIC_VECTOR (19 downto 0);
-- Signals and constants used by the Frequency divider process
constant Fosc : integer := 100000000; --Oscillator Frequency for Nexys3 board
constant Fdiv : integer := 19200; --Desired sampling baud rate (twice the input rate)
constant CtaMax : integer := Fosc / Fdiv; --Maximum count to obtain desired outputfreq
signal Cont : integer range 0 to CtaMax; --Define the counter
signal ClkOut : std_logic; --Defines that desired output frequency has ellapsed
-- Send Info
signal StreamSwitchTemp : STD_LOGIC_VECTOR (9 downto 0);
signal clockToggle : std_logic; -- toggle 1-send 0-wait
begin
--Obtain a 2 * baud rate signal derived from the FPGA board oscillator
Freq_Divider: process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process Freq_Divider;
process (Rst,Clk,ClkOut)
begin
if Rst = '1' then
reg <= (others => '1');
elsif (rising_edge(Clk) and ClkOut = '1') then
if reg(0) = '0' then
regtemp <= reg;
reg <= (others => '1');
else
reg <= DataIn & reg(19 downto 1);
end if;
end if;
end process;
process (Rst,Clk,ClkOut,Send, SwitchSeg)
begin
if Send = '1' then
StreamSwitchTemp <= SwitchSeg(7 downto 0) & '0' & '1';
clockToggle <= '1';
elsif (rising_edge(Clk) and ClkOut = '1') then
if clockToggle = '1' then
SteamOut <= StreamSwitchTemp(0);
StreamSwitchTemp <= '1' & StreamSwitchTemp(9 downto 1);
end if;
clockToggle <= not clockToggle; -- 1-send 0-wait
end if;
end process;
-- Read correct bits from shift register
SendDataOut:
for i in 0 to 7 generate
begin
DataOut(i) <= regtemp(i*2 +3);
end generate;
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_06 is
end entity fg_07_06;
architecture test of fg_07_06 is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_06 is
end entity fg_07_06;
architecture test of fg_07_06 is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_06 is
end entity fg_07_06;
architecture test of fg_07_06 is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal BLOCK_HEADER : std_logic_vector (31 downto 0) := (others => '0');
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send_1st_clk : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal receiving_state_clk40, do_transmit_timeout_trailers,timout_ena,timeout_trailer_send : std_logic := '0';
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
process(clk40,rst)
begin
if rst = '1' then
receiving_state_clk40 <= '0';
elsif rising_edge (clk40) then
receiving_state_clk40 <= receiving_state;
end if;
end process;
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
elsif rising_edge (clk40) then
if receiving_state_clk40 = '1' then
timeCnt_lastClk <= timeCntIn;
end if;
end if;
end process;
--
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send_1st_clk);
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif ((DIN_RDY = '1' and DIN(9 downto 8) /= "11") or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timeout_trailer_send <= '0';
elsif rising_edge (clk160) then
if timeout_trailer_send_1st_clk = '1' then
timeout_trailer_send <= '1';
elsif data16bit_rdy = '1' then -- timeout_trailer was sent once, the rest of the block will be filled with null-trailers
timeout_trailer_send <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if receiving_state = '1' then
timout_ena <= '1';
elsif do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if do_transmit_timeout_trailers = '0' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_s <= "0100000000";
DIN_RDY_s <= '1';
end if;
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= DIN_RDY_s; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- DIN_r <= DIN_s(7 downto 0);
-- end if;
--end process;
--
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- if direct_data_mode = '1' then
-- if DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1' then
-- DIN_CODE_r <= "10"; -- soc
-- else
-- DIN_CODE_r <= "00"; -- data
-- end if;
-- else
-- DIN_CODE_r <= DIN_s(9 downto 8);
-- end if;
-- end if;
--end process;
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8))
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
DIN_CODE_r <= DIN_s(9 downto 8);
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK;
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
--BLOCK_HEADER <= "1010101111001101" & "00000" & "0000" & egroupID & '0' & epathID; -- 0xABCD_
--std_logic_vector(to_unsigned(GBTid, 5))
-- [0xABCD_16] [[00000_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & "00000" & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
PORT MAP(
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
BLOCK_HEADER => BLOCK_HEADER,
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
-- Date : Thu Apr 5 01:27:52 2018
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/snickerdoodle_try/snickerdoodle_try.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl
-- Design : design_1_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_processing_system7_0_0 is
Port (
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end design_1_processing_system7_0_0;
architecture stub of design_1_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.4.1";
begin
end;
|
--
-- file: r2p_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now
-- rev. 1.2 May 18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request).
-- rev. 1.3 June 4th, 2001. Richard Herveille. Revised design (made it simpler and easier to understand).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity r2p_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity r2p_CordicPipe;
architecture dataflow of r2p_CordicPipe is
--
-- functions
--
-- Function CATAN (constante arc-tangent).
-- This is a lookup table containing pre-calculated arc-tangents.
-- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
-- The numbers are calculated as follows: Z(n) = atan(1/2^n)
-- examples:
-- 20bit values => 2^20 = 2pi(rad)
-- 1(rad) = 2^20/2pi = 166886.053....
-- n:1, atan(1/2) = 0.4636...(rad)
-- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
-- n:2, atan(1/4) = 0.2449...(rad)
-- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
-- n:3, atan(1/8) = 0.1243...(rad)
-- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
--
function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#09FB4#;
when 3 => result := 16#05111#;
when 4 => result := 16#028B1#;
when 5 => result := 16#0145D#;
when 6 => result := 16#0A2F#;
when 7 => result := 16#0518#;
when 8 => result := 16#028C#;
when 9 => result := 16#0146#;
when 10 => result := 16#0A3#;
when 11 => result := 16#051#;
when 12 => result := 16#029#;
when 13 => result := 16#014#;
when 14 => result := 16#0A#;
when 15 => result := 16#05#;
when 16 => result := 16#03#;
when 17 => result := 16#01#;
when others => result := 16#0#;
end case;
return result;
end CATAN;
-- function Delta is actually an arithmatic shift right
-- This strange construction is needed for compatibility with Xilinx WebPack
function Delta(Arg : signed; Cnt : natural) return signed is
variable tmp : signed(Arg'range);
constant lo : integer := Arg'high -cnt +1;
begin
for n in Arg'high downto lo loop
tmp(n) := Arg(Arg'high);
end loop;
for n in Arg'high -cnt downto 0 loop
tmp(n) := Arg(n +cnt);
end loop;
return tmp;
end function Delta;
function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
begin
if (add_sub = '1') then
return dataa + datab;
else
return dataa - datab;
end if;
end;
--
-- ARCHITECTURE BODY
--
signal dX, Xresult : signed(WIDTH -1 downto 0);
signal dY, Yresult : signed(WIDTH -1 downto 0);
signal atan, Zresult : signed(19 downto 0);
signal Yneg, Ypos : std_logic;
begin
dX <= Delta(Xi, PIPEID);
dY <= Delta(Yi, PIPEID);
atan <= conv_signed( catan(PIPEID), 20); -- Angle can not be negative, catan never returns a negative value, so conv_signed can be used
-- generate adder structures
Yneg <= Yi(WIDTH -1);
Ypos <= not Yi(WIDTH -1);
-- xadd
Xresult <= AddSub(Xi, dY, YPos);
-- yadd
Yresult <= AddSub(Yi, dX, Yneg);
-- zadd
Zresult <= AddSub(Zi, atan, Ypos);
gen_regs: process(clk)
begin
if(clk'event and clk='1') then
if (ena = '1') then
Xo <= Xresult;
Yo <= Yresult;
Zo <= Zresult;
end if;
end if;
end process;
end architecture dataflow;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics evaluation.
library ieee;
use ieee.std_logic_1164.all;
entity eval_generic is
generic(
msb : integer range 1 to 7 := 7;
bit_select : integer range 0 to 7 := 3
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end entity eval_generic;
architecture test of eval_generic is
begin
out_bit <= in_word(bit_select);
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
entity test_eval_generic is
port(
in_word : in std_logic_vector(7 downto 0);
out_bit_def, out_bit_ovr : out std_logic
);
end entity test_eval_generic;
architecture test of test_eval_generic is
constant const_int : integer := 7;
component eval_generic is
generic(
msb : integer range 1 to 7;
bit_select : integer range 0 to 7
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end component eval_generic;
begin
override_test_unit: eval_generic
generic map(bit_select => 2,
msb => const_int)
port map(
in_word => (others => '1'),
out_bit => out_bit_ovr
);
default_test_unit: eval_generic
port map(
in_word => in_word,
out_bit => out_bit_def
);
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics evaluation.
library ieee;
use ieee.std_logic_1164.all;
entity eval_generic is
generic(
msb : integer range 1 to 7 := 7;
bit_select : integer range 0 to 7 := 3
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end entity eval_generic;
architecture test of eval_generic is
begin
out_bit <= in_word(bit_select);
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
entity test_eval_generic is
port(
in_word : in std_logic_vector(7 downto 0);
out_bit_def, out_bit_ovr : out std_logic
);
end entity test_eval_generic;
architecture test of test_eval_generic is
constant const_int : integer := 7;
component eval_generic is
generic(
msb : integer range 1 to 7;
bit_select : integer range 0 to 7
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end component eval_generic;
begin
override_test_unit: eval_generic
generic map(bit_select => 2,
msb => const_int)
port map(
in_word => (others => '1'),
out_bit => out_bit_ovr
);
default_test_unit: eval_generic
port map(
in_word => in_word,
out_bit => out_bit_def
);
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics evaluation.
library ieee;
use ieee.std_logic_1164.all;
entity eval_generic is
generic(
msb : integer range 1 to 7 := 7;
bit_select : integer range 0 to 7 := 3
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end entity eval_generic;
architecture test of eval_generic is
begin
out_bit <= in_word(bit_select);
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
entity test_eval_generic is
port(
in_word : in std_logic_vector(7 downto 0);
out_bit_def, out_bit_ovr : out std_logic
);
end entity test_eval_generic;
architecture test of test_eval_generic is
constant const_int : integer := 7;
component eval_generic is
generic(
msb : integer range 1 to 7;
bit_select : integer range 0 to 7
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end component eval_generic;
begin
override_test_unit: eval_generic
generic map(bit_select => 2,
msb => const_int)
port map(
in_word => (others => '1'),
out_bit => out_bit_ovr
);
default_test_unit: eval_generic
port map(
in_word => in_word,
out_bit => out_bit_def
);
end architecture test;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY base_zynq_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END base_zynq_design_axi_bram_ctrl_0_0;
ARCHITECTURE base_zynq_design_axi_bram_ctrl_0_0_arch OF base_zynq_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "base_zynq_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "base_zynq_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END base_zynq_design_axi_bram_ctrl_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1857.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01857ent IS
END c07s01b00x00p08n01i01857ent;
ARCHITECTURE c07s01b00x00p08n01i01857arch OF c07s01b00x00p08n01i01857ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus, obus, obus2 : cmd_bus(small_int);
signal s_int : small_int := 0;
signal bool : boolean;
BEGIN
s : bool <= s_int = ibus'right(1) after 5 ns;
with bool select
obus (ch0701_p00801_48_arch)<= 5 after 5 ns when true, -- body name illegal here
obus (5) <= 5 after 5 ns when false;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01857 - Architecture body names are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01857arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1857.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01857ent IS
END c07s01b00x00p08n01i01857ent;
ARCHITECTURE c07s01b00x00p08n01i01857arch OF c07s01b00x00p08n01i01857ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus, obus, obus2 : cmd_bus(small_int);
signal s_int : small_int := 0;
signal bool : boolean;
BEGIN
s : bool <= s_int = ibus'right(1) after 5 ns;
with bool select
obus (ch0701_p00801_48_arch)<= 5 after 5 ns when true, -- body name illegal here
obus (5) <= 5 after 5 ns when false;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01857 - Architecture body names are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01857arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1857.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01857ent IS
END c07s01b00x00p08n01i01857ent;
ARCHITECTURE c07s01b00x00p08n01i01857arch OF c07s01b00x00p08n01i01857ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus, obus, obus2 : cmd_bus(small_int);
signal s_int : small_int := 0;
signal bool : boolean;
BEGIN
s : bool <= s_int = ibus'right(1) after 5 ns;
with bool select
obus (ch0701_p00801_48_arch)<= 5 after 5 ns when true, -- body name illegal here
obus (5) <= 5 after 5 ns when false;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01857 - Architecture body names are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01857arch;
|
----------------------------------------------------------------------------------
-- I2S_RX PAC
-- Copyright (c) Fernando Rodriguez, 2007
--
-- Configuration and type declarations for I2S_RX
--
-- This file is part of I2S_RX.
-- I2S_RX is free software: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- I2S_RX is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with I2S_RX. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package I2S is
constant num_inputs : integer :=4;
constant log_num_inputs : integer :=2;
type sr_type is array (num_inputs-1 downto 0) of std_logic_vector(23 downto 0);
end I2S;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc846.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and2g is
end and2g;
architecture behavior of and2g is
begin
end behavior;
entity full_adder is
end full_adder;
architecture structural of full_adder is
component and2
end component;
begin
C1: and2;
end structural;
ENTITY c01s03b01x00p08n01i00846ent IS
END c01s03b01x00p08n01i00846ent;
ARCHITECTURE c01s03b01x00p08n01i00846arch OF c01s03b01x00p08n01i00846ent IS
component adder
end component;
BEGIN
A1 : adder;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p08n01i00846"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p08n01i00846arch;
configuration c01s03b01x00p08n01i00846cfg of c01s03b01x00p08n01i00846ent is
for c01s03b01x00p08n01i00846arch
for A1: adder use -- component configuration
entity work.full_adder(structural);
for structural -- no_failure_here
for C1: and2 use
entity work.and2g(behavior);
end for;
end for;
end for;
end for;
end c01s03b01x00p08n01i00846cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc846.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and2g is
end and2g;
architecture behavior of and2g is
begin
end behavior;
entity full_adder is
end full_adder;
architecture structural of full_adder is
component and2
end component;
begin
C1: and2;
end structural;
ENTITY c01s03b01x00p08n01i00846ent IS
END c01s03b01x00p08n01i00846ent;
ARCHITECTURE c01s03b01x00p08n01i00846arch OF c01s03b01x00p08n01i00846ent IS
component adder
end component;
BEGIN
A1 : adder;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p08n01i00846"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p08n01i00846arch;
configuration c01s03b01x00p08n01i00846cfg of c01s03b01x00p08n01i00846ent is
for c01s03b01x00p08n01i00846arch
for A1: adder use -- component configuration
entity work.full_adder(structural);
for structural -- no_failure_here
for C1: and2 use
entity work.and2g(behavior);
end for;
end for;
end for;
end for;
end c01s03b01x00p08n01i00846cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc846.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and2g is
end and2g;
architecture behavior of and2g is
begin
end behavior;
entity full_adder is
end full_adder;
architecture structural of full_adder is
component and2
end component;
begin
C1: and2;
end structural;
ENTITY c01s03b01x00p08n01i00846ent IS
END c01s03b01x00p08n01i00846ent;
ARCHITECTURE c01s03b01x00p08n01i00846arch OF c01s03b01x00p08n01i00846ent IS
component adder
end component;
BEGIN
A1 : adder;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p08n01i00846"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p08n01i00846arch;
configuration c01s03b01x00p08n01i00846cfg of c01s03b01x00p08n01i00846ent is
for c01s03b01x00p08n01i00846arch
for A1: adder use -- component configuration
entity work.full_adder(structural);
for structural -- no_failure_here
for C1: and2 use
entity work.and2g(behavior);
end for;
end for;
end for;
end for;
end c01s03b01x00p08n01i00846cfg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/05/07 21:48:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ctrl_reg.vhd
--
-- Description: Control register with parameterizable width and two
-- write enables.
--
-------------------------------------------------------------------------------
-- Structure:
-- ctrl_reg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- -- Two point solution registers are declared
-- -- for this version as XST E.33 does not handle
-- -- the parameterized width.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end ctrl_reg;
architecture sim of ctrl_reg is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_6 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end ctrl_reg_0_to_6;
architecture sim of ctrl_reg_0_to_6 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_0 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end ctrl_reg_0_to_0;
architecture sim of ctrl_reg_0_to_0 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
-- XGR_E33 q <= C_RESET_VAL;
q <= C_RESET_VAL(0);
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/05/07 21:48:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ctrl_reg.vhd
--
-- Description: Control register with parameterizable width and two
-- write enables.
--
-------------------------------------------------------------------------------
-- Structure:
-- ctrl_reg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- -- Two point solution registers are declared
-- -- for this version as XST E.33 does not handle
-- -- the parameterized width.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end ctrl_reg;
architecture sim of ctrl_reg is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_6 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end ctrl_reg_0_to_6;
architecture sim of ctrl_reg_0_to_6 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_0 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end ctrl_reg_0_to_0;
architecture sim of ctrl_reg_0_to_0 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
-- XGR_E33 q <= C_RESET_VAL;
q <= C_RESET_VAL(0);
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
|
package pkg is
generic (N : integer := 2);
procedure showPackageN;
impure function c_int return integer;
attribute foreign of c_int : function is "VHPIDIRECT caux.so getInt";
end package pkg;
package body pkg is
procedure showPackageN is
begin
report integer'image(N);
end;
impure function c_int return integer is
begin
assert false report "c_int VHPI" severity failure;
end c_int;
end package body pkg;
|
--------------------------------------------------------------------------------
--
-- UART loopback demo for the Arty FPGA board
--
-- Ports:
-- clk_100mhz_ipad : Arty 100MHz clock
-- ck_rst_n_ipad : Arty CK_RST active low reset pin
-- uart_rx_ipad : UART Rx line connected to the FT2232HQ chip Tx line
-- uart_tx_opad : UART Tx line connected to the FT2232HQ chip Rx line
-- tx_fifo_full_out : Tx FIFO full
--
-- On reset, the module tranmits a "welcome" message and then switches to
-- loopback mode. In loopback mode any data received by the FPGA UART is
-- transmitted back (echo).
--
-- To test set the JP2 jumper, connect the Arty board through micro-USB to a
-- PC and open a serial terminal (eg. Putty). You should see the message at
-- the top. Any characters entered with the keyboard are echoed back to the
-- terminal. Each time you reconnect, the FT2232HQ chip on the board resets the
-- FPGA so the message is displayed with every new terminal connection.
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_loopback is
port(
clk_100mhz_ipad : in std_logic;
ck_rst_n_ipad : in std_logic;
uart_rx_ipad : in std_logic;
uart_tx_opad : out std_logic
);
end entity uart_loopback;
architecture rtl of uart_loopback is
------------------------------------------
-- to_slv
------------------------------------------
-- Converts a character to std_logic_vector
-- c : Input character
-- width : width of output std_logic_vector
function to_slv(c : character; width : positive) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(character'pos(c), width));
end to_slv;
type fsm_uart_type is (
UART_RST,
UART_LOOPBACK
);
signal fsm_uart : fsm_uart_type := UART_RST;
signal ck_rst_n_i : std_logic := '1';
signal rst : std_logic := '0';
signal uart_rx_r0 : std_logic := '1';
signal uart_rx_r1 : std_logic := '1';
signal rx_data_rd_sr : std_logic_vector(1 downto 0) := (others=>'0');
signal tx_data_wr_r : std_logic := '0';
signal tx_fifo_full_i : std_logic := '0';
signal rx_fifo_empty_i : std_logic := '0';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal tx_data_r : std_logic_vector(7 downto 0) := (others=>'0');
constant MSG : string(1 to 32) := "Arty UART v1.0" & CR & LF & "--------------" & CR & LF;
signal cnt_msg_r : integer range 0 to MSG'length-1 := 0;
begin
-- External reset is active low. No sync flip-flop needed
-- since the reset duration is ~1ms
rst <= not ck_rst_n_ipad;
-- Use a double flip-flop to synchronize the rx input
-- to the FPGA clock
proc_rx_dff:
process(clk_100mhz_ipad)
begin
if rising_edge(clk_100mhz_ipad) then
uart_rx_r0 <= uart_rx_ipad;
uart_rx_r1 <= uart_rx_r0;
end if;
end process;
proc_loopback:
process(clk_100mhz_ipad)
begin
if rising_edge(clk_100mhz_ipad) then
-- default assignments
rx_data_rd_sr <= rx_data_rd_sr(0) & '0';
tx_data_wr_r <= '0';
if (rst = '1') then
cnt_msg_r <= 0;
fsm_uart <= UART_RST;
else
case fsm_uart is
-- On reset transmit a "welcome" message before switching
-- to loopback mode.
when UART_RST =>
if (tx_fifo_full_i='0') and (tx_data_wr_r='0') then
tx_data_r <= to_slv(MSG(cnt_msg_r+1), 8);
tx_data_wr_r <= '1';
if (cnt_msg_r = MSG'length-1) then
cnt_msg_r <= 0;
fsm_uart <= UART_LOOPBACK;
else
cnt_msg_r <= cnt_msg_r + 1;
end if;
end if;
-- Read a word from the Rx FIFO and pass it to the Tx FIFO.
-- Transaction takes 2 clk cycles.
when UART_LOOPBACK =>
tx_data_wr_r <= rx_data_rd_sr(1);
tx_data_r <= rx_data_i;
if (rx_fifo_empty_i = '0') and (rx_data_rd_sr(0) = '0') then
rx_data_rd_sr <= rx_data_rd_sr(0) & '1';
end if;
end case;
end if;
end if;
end process;
---------------------------------------------
-- UART
---------------------------------------------
uart_inst : entity work.uart(rtl)
generic map(
G_BAUD_RATE => 115200,
G_CLOCK_FREQ => 100.0e6
)
port map(
clk => clk_100mhz_ipad,
rst => rst,
tx_data_in => tx_data_r,
tx_data_wr_in => tx_data_wr_r,
tx_fifo_full_out => tx_fifo_full_i,
tx_out => uart_tx_opad,
rx_in => uart_rx_r1,
rx_data_rd_in => rx_data_rd_sr(0),
rx_data_out => rx_data_i,
rx_fifo_empty_out => rx_fifo_empty_i
);
end architecture rtl; |
-- NEED RESULT: ARCH00477: Functions can return dynamically sized objects passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00477
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00477)
-- ENT00477_Test_Bench(ARCH00477_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
-- 11-DEC-1989 - GDT: added parameter "n" to function record_func to
-- eliminate global reference.
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00477 of E00000 is
function array_func ( n,x : integer ) return t_arr1 is
variable a : t_arr1 (lowb to n) ;
begin
for i in lowb to n loop
a(i) := st_int1 ( x + i ) ;
end loop ;
return a;
end array_func ;
procedure proc ( n : in integer ;
b : out boolean ;
x : out integer ) is
type rec is record
bo : boolean ;
a : t_arr1 (lowb to n) ;
end record ;
variable rr : rec ;
function record_func ( k,n : integer ) return rec is
variable r : rec ;
begin
r.bo := true ;
for i in lowb to n loop
r.a(i) := st_int1 ( k + i ) ;
end loop ;
return r;
end record_func ;
begin
rr := record_func(13, n) ;
b := rr.bo ;
x := integer ( rr.a(n-1) ) ;
end proc ;
begin
P :
process
variable b : boolean;
variable x : integer;
begin
proc (10, b, x) ;
test_report ( "ARCH00477" ,
"Functions can return dynamically sized objects" ,
(b = true) and
(x = 13+10-1) and
(array_func(10,15) (9) = 15+9)
) ;
wait ;
end process P ;
end ARCH00477 ;
entity ENT00477_Test_Bench is
end ENT00477_Test_Bench ;
architecture ARCH00477_Test_Bench of ENT00477_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00477 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00477_Test_Bench ;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_rnd;
architecture behaviour of dk27_rnd is
constant START: std_logic_vector(2 downto 0) := "101";
constant state6: std_logic_vector(2 downto 0) := "010";
constant state2: std_logic_vector(2 downto 0) := "011";
constant state5: std_logic_vector(2 downto 0) := "110";
constant state3: std_logic_vector(2 downto 0) := "111";
constant state4: std_logic_vector(2 downto 0) := "001";
constant state7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
|
-- ####################################
-- # Project: Yarr
-- # Author: Vyassa Baratham
-- # E-Mail: vbaratham at berkeley.edu
-- # Comments: assert the output for the duration of the
-- # clock cycle following an edge on the input
-- # Data: 09/2017
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity edge_detector is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
rising_o : out std_logic;
falling_o : out std_logic
);
end edge_detector;
architecture rtl of edge_detector is
signal prev_dat_i : std_logic;
begin
proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
prev_dat_i <= '0';
rising_o <= '0';
falling_o <= '0';
elsif rising_edge(clk_i) then
if (dat_i /= prev_dat_i) then
falling_o <= prev_dat_i;
rising_o <= dat_i;
else
falling_o <= '0';
rising_o <= '0';
end if;
prev_dat_i <= dat_i;
end if;
end process proc;
end rtl;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cpu_types is
constant word_size : positive := 16;
subtype word is bit_vector(word_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cpu_types is
constant word_size : positive := 16;
subtype word is bit_vector(word_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cpu_types is
constant word_size : positive := 16;
subtype word is bit_vector(word_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: stack_ctrl.vhd
-- // Date: 12/9/2004
-- // Description: Stack Controller
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity stack_ctrl is
port (
clr: in STD_LOGIC;
clk: in STD_LOGIC;
push: in STD_LOGIC;
pop: in STD_LOGIC;
we: out STD_LOGIC;
amsel: out STD_LOGIC;
wr_addr: out STD_LOGIC_VECTOR(4 downto 0);
rd_addr: out STD_LOGIC_VECTOR(4 downto 0);
full: out STD_LOGIC;
empty: out STD_LOGIC
);
end stack_ctrl;
architecture stack_ctrl_arch of stack_ctrl is
signal full_flag, empty_flag: STD_LOGIC;
begin
stk: process(clr, clk, push, pop, full_flag, empty_flag)
variable push_addr, pop_addr: STD_LOGIC_VECTOR(4 downto 0);
begin
if clr = '1' then
push_addr := "11111";
pop_addr := "00000";
empty_flag <= '1';
full_flag <= '0';
wr_addr <= "11111";
rd_addr <= "00000";
full <= full_flag;
empty <= empty_flag;
elsif clk'event and clk = '1' then
if push = '1' then
if pop = '0' then
if full_flag = '0' then
push_addr := push_addr - 1;
pop_addr := push_addr + 1;
empty_flag <= '0';
if push_addr = "11111" then
full_flag <= '1';
push_addr := "00000";
end if;
end if;
end if;
elsif pop = '1' then
if empty_flag = '0' then
pop_addr := pop_addr + 1;
if full_flag = '0' then
push_addr := push_addr + 1;
end if;
full_flag <= '0';
if pop_addr = "00000" then
empty_flag <= '1';
end if;
end if;
end if;
wr_addr <= push_addr;
rd_addr <= pop_addr;
end if;
full <= full_flag;
empty <= empty_flag;
if push = '1' and full_flag = '0' then
we <= '1';
else
we <= '0';
end if;
if push = '1' and pop = '1' then
amsel <= '1';
else
amsel <= '0';
end if;
end process stk;
end stack_ctrl_arch;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
|
-- Accellera Standard V2.3 Open Verification Library (OVL)
-- Accellera Copyright (c) 2005-2008. All rights reserved.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE std_ovl IS
constant OVL_STD_DEFINES_H : boolean := true;
constant OVL_VERSION : string := "V2.3";
-- active edges
constant OVL_NOEDGE : integer := 0;
constant OVL_POSEDGE : integer := 1;
constant OVL_NEGEDGE : integer := 2;
constant OVL_ANYEDGE : integer := 3;
-- severity level
constant OVL_FATAL : integer := 0;
constant OVL_ERROR : integer := 1;
constant OVL_WARNING : integer := 2;
constant OVL_INFO : integer := 3;
-- coverage levels
constant OVL_COVER_NONE : integer := 0;
constant OVL_COVER_SANITY : integer := 1;
constant OVL_COVER_BASIC : integer := 2;
constant OVL_COVER_CORNER : integer := 4;
constant OVL_COVER_STATISTIC : integer := 8;
constant OVL_COVER_ALL : integer := 15;
-- property type
constant OVL_ASSERT : integer := 0;
constant OVL_ASSUME : integer := 1;
constant OVL_IGNORE : integer := 2;
-- necessary condition
constant OVL_TRIGGER_ON_MOST_PIPE : integer := 0;
constant OVL_TRIGGER_ON_FIRST_PIPE : integer := 1;
constant OVL_TRIGGER_ON_FIRST_NOPIPE : integer := 2;
-- action on new start
constant OVL_IGNORE_NEW_START : integer := 0;
constant OVL_RESET_ON_NEW_START : integer := 1;
constant OVL_ERROR_ON_NEW_START : integer := 2;
-- inactive levels
constant OVL_ALL_ZEROS : integer := 0;
constant OVL_ALL_ONES : integer := 1;
constant OVL_ONE_COLD : integer := 2;
-- Global reset
signal OVL_GLOBAL_RESET : boolean := false;
signal OVL_RESET_SIGNAL : std_ulogic;
-- End of simulation
signal OVL_END_OF_SIMULATION : std_ulogic := '0';
component assert_always
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_always_on_edge
generic (
severity_level : integer := OVL_ERROR;
edge_type : integer := OVL_NOEDGE;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
sampling_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_change
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_cycle_sequence
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 2;
necessary_condition : integer := OVL_TRIGGER_ON_MOST_PIPE;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
event_sequence : in std_ulogic_vector(num_cks-1 downto 0)
);
end component;
component assert_decrement
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
value : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_delta
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 1;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_even_parity
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_fifo_index
generic (
severity_level : integer := OVL_ERROR;
depth : integer := 1;
push_width : integer := 1;
pop_width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL;
simultaneous_push_pop : integer := 1
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
push : in std_ulogic_vector(push_width-1 downto 0);
pop : in std_ulogic_vector(pop_width-1 downto 0)
);
end component;
component assert_frame
generic (
severity_level : integer := OVL_ERROR;
min_cks : integer := 0;
max_cks : integer := 0;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_handshake
generic (
severity_level : integer := OVL_ERROR;
min_ack_cycle : integer := 0;
max_ack_cycle : integer := 0;
req_drop : integer := 0;
deassert_count : integer := 0;
max_ack_length : integer := 0;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
req : in std_ulogic;
ack : in std_ulogic
);
end component;
component assert_implication
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
antecedent_expr : in std_ulogic;
consequent_expr : in std_ulogic
);
end component;
component assert_increment
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
value : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_never
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_never_unknown
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
qualifier : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_never_unknown_async
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_next
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 1;
check_overlapping : integer := 1;
check_missing_start : integer := 0;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_no_overflow
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 0;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_no_transition
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
start_state : in std_ulogic_vector(width-1 downto 0);
next_state : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_no_underflow
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 0;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_odd_parity
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_one_cold
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
inactive : integer := OVL_ONE_COLD;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_one_hot
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_proposition
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_quiescent_state
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
state_expr : in std_ulogic_vector(width-1 downto 0);
check_value : in std_ulogic_vector(width-1 downto 0);
sample_event : in std_ulogic
);
end component;
component assert_range
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 1;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_time
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_transition
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
start_state : in std_ulogic_vector(width-1 downto 0);
next_state : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_unchange
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_width
generic (
severity_level : integer := OVL_ERROR;
min_cks : integer := 1;
max_cks : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_win_change
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
end_event : in std_ulogic
);
end component;
component assert_win_unchange
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
end_event : in std_ulogic
);
end component;
component assert_window
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic;
end_event : in std_ulogic
);
end component;
component assert_zero_one_hot
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
END std_ovl;
|
-- FPGA Clock Circuit for Altera DE-2 board
-- Cliff Chapman
-- 11/04/2013
--
-- Lab 9 - Digital Systems Design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY vendi IS
PORT (
-- Coins input
nickel_in : IN STD_LOGIC;
dime_in : IN STD_LOGIC;
quarter_in : IN STD_LOGIC;
-- User actions
dispense : IN STD_LOGIC;
coin_return : IN STD_LOGIC;
-- Machine data
clk : IN STD_LOGIC;
rst : IN STD_LOGIC := '1';
-- LED dispense status
change_back : OUT STD_LOGIC;
red_bull : OUT STD_LOGIC;
-- Coin amount displays
HEX0_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
HEX1_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END vendi;
ARCHITECTURE a OF vendi IS
COMPONENT sevenseg_bcd_display
PORT (
r : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values
HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
SIGNAL coin_val : STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Build an enumerated type for the state machine
-- This feels like a GREAT way to screw yourself over with
-- overloading common names. Maybe that's just me.
-- Either way that's why we have the _s hungarian postfix on these.
TYPE state_type IS
( idle_s, nickle_s, dime_s, quarter_s
, enough_s, excess_s, vend_s, change_s
);
-- Register to hold the current state
SIGNAL state : state_type;
BEGIN
-- Display output of current coin value
display : sevenseg_bcd_display PORT MAP (
r => coin_val,
s => '1',
HEX2 => OPEN,
HEX1 => HEX1_disp,
HEX0 => HEX0_disp
);
state_monitor : PROCESS (rst, clk)
BEGIN
IF (rst = '0') THEN
state <= idle_s;
ELSIF (rising_edge(clk)) THEN
CASE state IS
-- IDLE STATE
WHEN idle_s =>
IF (nickel_in = '1') THEN
state <= nickle_s;
ELSIF (dime_in = '1') THEN
state <= dime_s;
ELSIF (quarter_in = '1') THEN
state <= quarter_s;
ELSIF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
-- Coins states
WHEN nickle_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
WHEN dime_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
WHEN quarter_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
-- Enough money
WHEN enough_s =>
IF (coin_return = '1') THEN
state <= change_s;
ELSIF (dispense = '1') THEN
state <= vend_s;
ELSIF (nickel_in = '1') THEN
state <= excess_s;
ELSIF (dime_in = '1') THEN
state <= excess_s;
ELSIF (quarter_in = '1') THEN
state <= excess_s;
ELSE
state <= enough_s;
END IF;
-- Too much money (Display may overload, can store up to 255 cents)
-- TODO: add auto-return dump for values over 2 dollars?
WHEN excess_s =>
IF (coin_return = '1') THEN
state <= change_s;
ELSIF (dispense = '1') THEN
state <= vend_s;
-- Coin block again
ELSIF (nickel_in = '1') THEN
state <= excess_s;
ELSIF (dime_in = '1') THEN
state <= excess_s;
ELSIF (quarter_in = '1') THEN
state <= excess_s;
ELSE
state <= excess_s;
END IF;
WHEN vend_s =>
IF (coin_val = "00000000") THEN
state <= idle_s;
ELSIF (coin_val > "00000000") THEN
state <= change_s;
END IF;
WHEN OTHERS =>
state <= idle_s;
END CASE;
END IF;
END PROCESS state_monitor;
PROCESS (state)
BEGIN
IF (state = vend_s) THEN
red_bull <= '1';
ELSE
red_bull <= '0';
END IF;
IF (state = change_s) THEN
change_back <= '1';
ELSIF (state = excess_s) THEN
change_back <= '1';
ELSE
change_back <= '0';
END IF;
END PROCESS;
state_output : PROCESS (state, clk, rst)
VARIABLE coin_cnt : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
BEGIN
IF (rst = '0') THEN
coin_cnt := "00000000";
ELSIF (rising_edge(clk) AND rst = '1') THEN
CASE state IS
WHEN nickle_s => coin_cnt := coin_cnt + "00000101";
WHEN dime_s => coin_cnt := coin_cnt + "00001010";
WHEN quarter_s => coin_cnt := coin_cnt + "00011001";
WHEN vend_s => coin_cnt := coin_cnt - "01001011";
WHEN change_s => coin_cnt := "00000000";
WHEN OTHERS => coin_cnt := coin_cnt;
END CASE;
ELSE
coin_cnt := coin_cnt;
END IF;
coin_val <= coin_cnt;
END PROCESS state_output;
END ARCHITECTURE; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 24 17:28:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_buffer_1_0 -prefix
-- system_vga_buffer_1_0_ system_vga_buffer_1_0_stub.vhdl
-- Design : system_vga_buffer_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_buffer_1_0 is
Port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_buffer_1_0;
architecture stub of system_vga_buffer_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_buffer,Vivado 2016.4";
begin
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bin_count is
generic(N: integer := 3);
port (
clk, reset: in std_logic;
count: out std_logic_vector((2 ** N) - 1 downto 0)
);
end bin_count;
architecture bin_count_arch of bin_count is
signal bin: std_logic_vector(N - 1 downto 0);
begin
bled: entity work.bin_led(bin_led_arch)
port map(binary => bin, unary => count);
process(clk, reset)
begin
if (reset = '1') then
bin <= (others => '0');
elsif (clk'event and clk = '0') then
bin <= bin + 1;
end if;
end process;
end bin_count_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdiv23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sdiv23;
architecture rtl of sdiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
A_IN : in vl_logic_vector(63 downto 0);
PWRDWN : in vl_logic;
ADCRESET : in vl_logic;
SYSCLK : in vl_logic;
CHNUMBER : in vl_logic_vector(4 downto 0);
MODE : in vl_logic_vector(3 downto 0);
TVC : in vl_logic_vector(7 downto 0);
STC : in vl_logic_vector(7 downto 0);
ADCSTART : in vl_logic;
VAREFSEL_lat : out vl_logic;
BUSY : out vl_logic;
CALIBRATE : out vl_logic;
DATAVALID : out vl_logic;
SAMPLE : out vl_logic;
RESULT : out vl_logic_vector(11 downto 0)
);
end adc;
|
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
A_IN : in vl_logic_vector(63 downto 0);
PWRDWN : in vl_logic;
ADCRESET : in vl_logic;
SYSCLK : in vl_logic;
CHNUMBER : in vl_logic_vector(4 downto 0);
MODE : in vl_logic_vector(3 downto 0);
TVC : in vl_logic_vector(7 downto 0);
STC : in vl_logic_vector(7 downto 0);
ADCSTART : in vl_logic;
VAREFSEL_lat : out vl_logic;
BUSY : out vl_logic;
CALIBRATE : out vl_logic;
DATAVALID : out vl_logic;
SAMPLE : out vl_logic;
RESULT : out vl_logic_vector(11 downto 0)
);
end adc;
|
library verilog;
use verilog.vl_types.all;
entity adc is
generic(
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
VA_REF_INTERNAL : real := 2.560000
);
port(
VAREF_INPUT : in vl_logic_vector(63 downto 0);
VAREFSEL : in vl_logic;
A_IN : in vl_logic_vector(63 downto 0);
PWRDWN : in vl_logic;
ADCRESET : in vl_logic;
SYSCLK : in vl_logic;
CHNUMBER : in vl_logic_vector(4 downto 0);
MODE : in vl_logic_vector(3 downto 0);
TVC : in vl_logic_vector(7 downto 0);
STC : in vl_logic_vector(7 downto 0);
ADCSTART : in vl_logic;
VAREFSEL_lat : out vl_logic;
BUSY : out vl_logic;
CALIBRATE : out vl_logic;
DATAVALID : out vl_logic;
SAMPLE : out vl_logic;
RESULT : out vl_logic_vector(11 downto 0)
);
end adc;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY test_mux2 IS
END test_mux2;
ARCHITECTURE t_mux2_est OF test_mux2 IS
COMPONENT mux2
GENERIC (N: INTEGER:=32);
PORT (d0, d1: IN std_logic_vector(N-1 DOWNTO 0);
s: IN std_logic;
y: OUT std_logic_vector(N-1 DOWNTO 0));
END COMPONENT;
SIGNAL d0: std_logic_vector(31 DOWNTO 0):= x"00000000";
SIGNAL d1: std_logic_vector(31 DOWNTO 0):= x"11111111";
SIGNAL s: std_logic:= '0';
SIGNAL y0: std_logic_vector(31 DOWNTO 0);
SIGNAL b0: std_logic_vector(3 DOWNTO 0):= x"0";
SIGNAL b1: std_logic_vector(3 DOWNTO 0):= x"F";
SIGNAL y1: std_logic_vector(3 DOWNTO 0);
BEGIN
u1: mux2 GENERIC MAP (N => 32) PORT MAP(d0, d1, s, y0);
d0 <= x"00001111" AFTER 10 fs, x"0000122F" AFTER 20 fs;
d1 <= x"11110000" AFTER 10 fs, x"1111FABC" AFTER 20 fs;
s <= NOT s AFTER 5 fs;
u2: mux2 GENERIC MAP (N => 4) PORT MAP (b0, b1, s, y1);
b0 <= x"A" AFTER 10 fs, x"B" AFTER 20 fs;
b1 <= x"2" AFTER 10 fs, x"9" AFTER 20 fs;
s <= NOT s AFTER 5 fs;
END t_mux2_est;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc20.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n03i00020ent IS
END c04s02b00x00p09n03i00020ent;
ARCHITECTURE c04s02b00x00p09n03i00020arch OF c04s02b00x00p09n03i00020ent IS
type A2 is range 50.0 to 100.0;
subtype B2 is A2 range 1.0 to 60.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p09n03i00020 - Range constraints for the subtype declarations contradict the range of the subtype indication.(real)"
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s02b00x00p09n03i00020arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc20.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n03i00020ent IS
END c04s02b00x00p09n03i00020ent;
ARCHITECTURE c04s02b00x00p09n03i00020arch OF c04s02b00x00p09n03i00020ent IS
type A2 is range 50.0 to 100.0;
subtype B2 is A2 range 1.0 to 60.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p09n03i00020 - Range constraints for the subtype declarations contradict the range of the subtype indication.(real)"
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s02b00x00p09n03i00020arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc20.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n03i00020ent IS
END c04s02b00x00p09n03i00020ent;
ARCHITECTURE c04s02b00x00p09n03i00020arch OF c04s02b00x00p09n03i00020ent IS
type A2 is range 50.0 to 100.0;
subtype B2 is A2 range 1.0 to 60.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p09n03i00020 - Range constraints for the subtype declarations contradict the range of the subtype indication.(real)"
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s02b00x00p09n03i00020arch;
|
entity wave5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wave5 is
type pair is record
a, b : integer;
end record;
type rec is record
x : integer;
y : std_logic_vector(1 to 3);
z : pair;
end record;
signal r : rec;
begin
main: process is
begin
wait for 1 ns;
r.y <= "101";
wait for 1 ns;
r.z.b <= 5;
r.z.a <= 6;
wait for 1 ns;
r.x <= 2;
r.z.a <= 1;
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1617.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01617ent IS
END c08s12b00x00p03n01i01617ent;
ARCHITECTURE c08s12b00x00p03n01i01617arch OF c08s12b00x00p03n01i01617ent IS
function f1 (in1:real) return integer is
begin
return(12);
end f1;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := f1(2.3);
assert NOT(k = 12)
report "***PASSED TEST: c08s12b00x00p03n01i01617"
severity NOTE;
assert (k = 12)
report "***FAILED TEST: c08s12b00x00p03n01i01617 - A return statement is only allowed within the body of a function"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01617arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1617.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01617ent IS
END c08s12b00x00p03n01i01617ent;
ARCHITECTURE c08s12b00x00p03n01i01617arch OF c08s12b00x00p03n01i01617ent IS
function f1 (in1:real) return integer is
begin
return(12);
end f1;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := f1(2.3);
assert NOT(k = 12)
report "***PASSED TEST: c08s12b00x00p03n01i01617"
severity NOTE;
assert (k = 12)
report "***FAILED TEST: c08s12b00x00p03n01i01617 - A return statement is only allowed within the body of a function"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01617arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1617.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01617ent IS
END c08s12b00x00p03n01i01617ent;
ARCHITECTURE c08s12b00x00p03n01i01617arch OF c08s12b00x00p03n01i01617ent IS
function f1 (in1:real) return integer is
begin
return(12);
end f1;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := f1(2.3);
assert NOT(k = 12)
report "***PASSED TEST: c08s12b00x00p03n01i01617"
severity NOTE;
assert (k = 12)
report "***FAILED TEST: c08s12b00x00p03n01i01617 - A return statement is only allowed within the body of a function"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01617arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- A simple multiplexer
--
-- outval is val1 if switch is LOW ('0'), val2 otherwise.
entity Mux is
generic(
WIDTH : integer := 16
);
Port(
val1 : in std_ulogic_vector(WIDTH - 1 downto 0);
val2 : in std_ulogic_vector(WIDTH - 1 downto 0);
switch : in std_ulogic;
outval : out std_ulogic_vector(WIDTH - 1 downto 0)
);
end Mux;
architecture Behavioral of Mux is
begin
outval <= val1 when switch = '0' else val2;
end Behavioral;
|
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