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--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_adaptations_pkg is
-- Max length of line read from CSV file, used in csv_file_reader_pkg.vhd
constant C_CSV_FILE_MAX_LINE_LENGTH : positive := 256;
-- Delimiter when reading and writing CSV files.
constant C_CSV_DELIMITER : character := ',';
-------------------------------------------------------------------------------
-- VIP configuration record
-------------------------------------------------------------------------------
type t_spec_cov_config is record
missing_req_label_severity : t_alert_level; -- Alert level used when the tick_off_req_cov() procedure does not find the specified
-- requirement label in the requirement list.
csv_delimiter : character; -- Character used as delimiter in the CSV files. Default is ",".
max_requirements : natural; -- Maximum number of requirements in the req_map file used in initialize_req_cov().
max_testcases_per_req : natural; -- Max number of testcases allowed per requirement.
csv_max_line_length : positive; -- Max length of each line in any CSV file.
end record;
constant C_SPEC_COV_CONFIG_DEFAULT : t_spec_cov_config := (
missing_req_label_severity => TB_WARNING,
csv_delimiter => C_CSV_DELIMITER,
max_requirements => 1000,
max_testcases_per_req => 20,
csv_max_line_length => C_CSV_FILE_MAX_LINE_LENGTH
);
-- Shared variable for configuring the Spec Cov VIP from the testbench sequencer.
shared variable shared_spec_cov_config : t_spec_cov_config := C_SPEC_COV_CONFIG_DEFAULT;
end package local_adaptations_pkg;
package body local_adaptations_pkg is
end package body local_adaptations_pkg; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2708.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p11n01i02708ent IS
END c13s04b01x00p11n01i02708ent;
ARCHITECTURE c13s04b01x00p11n01i02708arch OF c13s04b01x00p11n01i02708ent IS
constant i : real := 00567.8;
constant k : real := 567.8;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( i=k )
report "***PASSED TEST: c13s04b01x00p11n01i02708"
severity NOTE;
assert ( i=k )
report "***FAILED TEST: c13s04b01x00p11n01i02708 - Leading zeros should be allowed for an real literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p11n01i02708arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2708.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p11n01i02708ent IS
END c13s04b01x00p11n01i02708ent;
ARCHITECTURE c13s04b01x00p11n01i02708arch OF c13s04b01x00p11n01i02708ent IS
constant i : real := 00567.8;
constant k : real := 567.8;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( i=k )
report "***PASSED TEST: c13s04b01x00p11n01i02708"
severity NOTE;
assert ( i=k )
report "***FAILED TEST: c13s04b01x00p11n01i02708 - Leading zeros should be allowed for an real literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p11n01i02708arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2708.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p11n01i02708ent IS
END c13s04b01x00p11n01i02708ent;
ARCHITECTURE c13s04b01x00p11n01i02708arch OF c13s04b01x00p11n01i02708ent IS
constant i : real := 00567.8;
constant k : real := 567.8;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( i=k )
report "***PASSED TEST: c13s04b01x00p11n01i02708"
severity NOTE;
assert ( i=k )
report "***FAILED TEST: c13s04b01x00p11n01i02708 - Leading zeros should be allowed for an real literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p11n01i02708arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualizador: process (entrada) begin
case entrada is
when "0000" => salida <= x"C0"; -- 0
when "0001" => salida <= x"F9"; -- 1
when "0010" => salida <= x"A4"; -- 2
when "0011" => salida <= x"B0"; -- 3
when "0100" => salida <= x"99"; -- 4
when "0101" => salida <= x"92"; -- 5
when "0110" => salida <= x"82"; -- 6
when "0111" => salida <= x"F8"; -- 7
when "1000" => salida <= x"80"; -- 8
when "1001" => salida <= x"98"; -- 9
when "1010" => salida <= x"88"; -- A
when "1011" => salida <= x"83"; -- B
when "1100" => salida <= x"C6"; -- C
when "1101" => salida <= x"A1"; -- D
when "1110" => salida <= x"86"; -- E
when "1111" => salida <= x"8E"; -- F
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualizador: process (entrada) begin
case entrada is
when "0000" => salida <= x"C0"; -- 0
when "0001" => salida <= x"F9"; -- 1
when "0010" => salida <= x"A4"; -- 2
when "0011" => salida <= x"B0"; -- 3
when "0100" => salida <= x"99"; -- 4
when "0101" => salida <= x"92"; -- 5
when "0110" => salida <= x"82"; -- 6
when "0111" => salida <= x"F8"; -- 7
when "1000" => salida <= x"80"; -- 8
when "1001" => salida <= x"98"; -- 9
when "1010" => salida <= x"88"; -- A
when "1011" => salida <= x"83"; -- B
when "1100" => salida <= x"C6"; -- C
when "1101" => salida <= x"A1"; -- D
when "1110" => salida <= x"86"; -- E
when "1111" => salida <= x"8E"; -- F
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualizador: process (entrada) begin
case entrada is
when "0000" => salida <= x"C0"; -- 0
when "0001" => salida <= x"F9"; -- 1
when "0010" => salida <= x"A4"; -- 2
when "0011" => salida <= x"B0"; -- 3
when "0100" => salida <= x"99"; -- 4
when "0101" => salida <= x"92"; -- 5
when "0110" => salida <= x"82"; -- 6
when "0111" => salida <= x"F8"; -- 7
when "1000" => salida <= x"80"; -- 8
when "1001" => salida <= x"98"; -- 9
when "1010" => salida <= x"88"; -- A
when "1011" => salida <= x"83"; -- B
when "1100" => salida <= x"C6"; -- C
when "1101" => salida <= x"A1"; -- D
when "1110" => salida <= x"86"; -- E
when "1111" => salida <= x"8E"; -- F
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualizador: process (entrada) begin
case entrada is
when "0000" => salida <= x"C0"; -- 0
when "0001" => salida <= x"F9"; -- 1
when "0010" => salida <= x"A4"; -- 2
when "0011" => salida <= x"B0"; -- 3
when "0100" => salida <= x"99"; -- 4
when "0101" => salida <= x"92"; -- 5
when "0110" => salida <= x"82"; -- 6
when "0111" => salida <= x"F8"; -- 7
when "1000" => salida <= x"80"; -- 8
when "1001" => salida <= x"98"; -- 9
when "1010" => salida <= x"88"; -- A
when "1011" => salida <= x"83"; -- B
when "1100" => salida <= x"C6"; -- C
when "1101" => salida <= x"A1"; -- D
when "1110" => salida <= x"86"; -- E
when "1111" => salida <= x"8E"; -- F
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Trigger logic core
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
-- # Adress Map:
-- #
-- # 0x0 - Trigger mask [3:0] ext, [4] eudet
-- # 0 = off
-- # 1 = on
-- # 0x1 - Trigger tag mode
-- # 0 = trigger counter
-- # 1 = clk_i timestamp
-- # 2 = eudet input
-- # 0x2 - Concidence/veto logic (entire config word used
-- # as selector of multiplexor)
-- # 0x3 - Trigger edge [3:0] ext, [:4] ignored
-- # 0 = rising
-- # 1 = falling
-- # 0x4..0x7 - Per-channel delay (clk_i cycles, max 8)
-- # 0x4 = ext[0] ... 0x7 = ext[3]
-- # 0x8 - deadtime (clk_i cycles)
-- # 0xFF - local reset (reset trigger tag values)
-- #
-- # See ./README.md for more detailed instructions
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_trigger_logic is
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end wb_trigger_logic;
architecture rtl of wb_trigger_logic is
-- Components
component edge_detector
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
rising_o : out std_logic;
falling_o : out std_logic
);
end component;
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
component delayer
generic (N : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
dat_o : out std_logic;
delay : in std_logic_vector
);
end component;
component eudet_tlu
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
deadtime_i : IN std_logic_vector(15 downto 0);
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end component;
constant delay_width : integer := 3;
-- Registers
signal trig_mask : std_logic_vector(31 downto 0);
signal trig_tag_mode : std_logic_vector(7 downto 0);
signal trig_logic : std_logic_vector(31 downto 0);
signal trig_edge : std_logic_vector(3 downto 0);
signal ch0_delay : std_logic_vector(delay_width-1 downto 0);
signal ch1_delay : std_logic_vector(delay_width-1 downto 0);
signal ch2_delay : std_logic_vector(delay_width-1 downto 0);
signal ch3_delay : std_logic_vector(delay_width-1 downto 0);
signal deadtime : std_logic_vector(15 downto 0); -- clk_i cycles
-- Local signals
signal edge_r : std_logic_vector(3 downto 0);
signal edge_f : std_logic_vector(3 downto 0);
signal sync_ext_trig_i : std_logic_vector(3 downto 0);
signal edge_ext_trig_i : std_logic_vector(3 downto 0);
signal del_ext_trig_i : std_logic_vector(3 downto 0);
signal sync_ext_busy_i : std_logic;
signal master_trig_t : std_logic;
signal prev_master_trig_t : std_logic; -- delay output one clk to sync w/ busy signal
signal master_busy_t : std_logic;
signal lcl_eudet_trig_t : std_logic;
signal eudet_trig_tag_t : std_logic_vector(15 downto 0);
signal trig_counter : unsigned (31 downto 0);
signal timestamp_cnt : unsigned(31 downto 0);
signal local_reset : std_logic;
signal deadtime_cnt : unsigned(15 downto 0);
signal busy_t : std_logic;
begin
-- Debug port
debug_o(3 downto 0) <= ext_trig_i;
debug_o(7 downto 4) <= sync_ext_trig_i;
debug_o(11 downto 8) <= edge_ext_trig_i;
debug_o(15 downto 12) <= del_ext_trig_i;
debug_o(16) <= master_trig_t;
debug_o(17) <= master_busy_t;
debug_o(22 downto 18) <= trig_mask(4 downto 0);
debug_o(31 downto 23) <= trig_logic(8 downto 0);
-- WB interface
wb_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
trig_mask <= x"00000001"; -- auto enable internal
trig_tag_mode <= x"01";
trig_logic <= (1 => '1', others => '0'); -- auto enable internal
trig_edge <= (others => '0');
ch0_delay <= (others => '0');
ch1_delay <= (others => '0');
ch2_delay <= (others => '0');
ch3_delay <= (others => '0');
deadtime <= std_logic_vector(to_unsigned(300, 16));
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
wb_dat_o <= (others => '0');
local_reset <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
case (wb_adr_i(7 downto 0)) is
when x"00" =>
trig_mask <= wb_dat_i;
when x"01" =>
trig_tag_mode <= wb_dat_i(7 downto 0);
when x"02" =>
trig_logic <= wb_dat_i;
when x"03" =>
trig_edge <= wb_dat_i(3 downto 0);
when x"04" =>
ch0_delay <= wb_dat_i(delay_width-1 downto 0);
when x"05" =>
ch1_delay <= wb_dat_i(delay_width-1 downto 0);
when x"06" =>
ch2_delay <= wb_dat_i(delay_width-1 downto 0);
when x"07" =>
ch3_delay <= wb_dat_i(delay_width-1 downto 0);
when x"08" =>
deadtime <= wb_dat_i(15 downto 0);
when x"FF" =>
local_reset <= '1'; -- Pulse local reset
when others =>
end case;
else
case (wb_adr_i(7 downto 0)) is
when x"00" =>
wb_dat_o <= trig_mask;
when x"01" =>
wb_dat_o <= std_logic_vector(resize(unsigned(trig_tag_mode), 32));
when x"02" =>
wb_dat_o <= trig_logic;
when x"03" =>
wb_dat_o <= std_logic_vector(resize(unsigned(trig_edge), 32));
when x"04" =>
wb_dat_o <= std_logic_vector(resize(unsigned(ch0_delay), 32));
when x"05" =>
wb_dat_o <= std_logic_vector(resize(unsigned(ch1_delay), 32));
when x"06" =>
wb_dat_o <= std_logic_vector(resize(unsigned(ch2_delay), 32));
when x"07" =>
wb_dat_o <= std_logic_vector(resize(unsigned(ch3_delay), 32));
when x"08" =>
wb_dat_o <= std_logic_vector(resize(unsigned(deadtime), 32));
when others =>
wb_dat_o <= x"DEADBEEF";
end case;
end if;
end if;
end if;
end process wb_proc;
-- Sync/edge detector inputs
trig_inputs: for I in 0 to 3 generate
begin
cmp_sync_trig: synchronizer
port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => ext_trig_i(I), sync_out => sync_ext_trig_i(I));
cmp_edge_trig: edge_detector
port map(clk_i => clk_i, rst_n_i => rst_n_i, dat_i => sync_ext_trig_i(I),
falling_o => edge_f(I), rising_o => edge_r(I) );
edge_ext_trig_i(I) <= edge_f(I) when trig_edge(I) = '1' else edge_r(I);
end generate trig_inputs;
cmp_delay_trig0: delayer
generic map(N => delay_width)
port map(clk_i => clk_i, rst_n_i => rst_n_i, dat_i => edge_ext_trig_i(0),
dat_o => del_ext_trig_i(0), delay => ch0_delay);
cmp_delay_trig1: delayer
generic map(N => delay_width)
port map(clk_i => clk_i, rst_n_i => rst_n_i, dat_i => edge_ext_trig_i(1),
dat_o => del_ext_trig_i(1), delay => ch1_delay);
cmp_delay_trig2: delayer
generic map(N => delay_width)
port map(clk_i => clk_i, rst_n_i => rst_n_i, dat_i => edge_ext_trig_i(2),
dat_o => del_ext_trig_i(2), delay => ch2_delay);
cmp_delay_trig3: delayer
generic map(N => delay_width)
port map(clk_i => clk_i, rst_n_i => rst_n_i, dat_i => edge_ext_trig_i(3),
dat_o => del_ext_trig_i(3), delay => ch3_delay);
cmp_sync_busy: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => ext_busy_i, sync_out => sync_ext_busy_i);
master_busy_t <= sync_ext_busy_i or busy_t;
ext_busy_o <= master_busy_t;
-- Apply coincidence/veto logic
master_trig_t <= trig_logic(to_integer(unsigned((lcl_eudet_trig_t & del_ext_trig_i) and trig_mask(4 downto 0))));
-- trig tag gen
trig_tag_proc: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_tag <= (others => '0');
trig_counter <= (others => '0');
timestamp_cnt <= (others => '0');
elsif rising_edge(clk_i) then
-- TODO need reset
if (local_reset = '1') then
trig_counter <= (others => '0');
elsif (master_trig_t = '1') then
trig_counter <= trig_counter + 1;
end if;
if (local_reset = '1') then
timestamp_cnt <= (others => '0');
else
timestamp_cnt <= timestamp_cnt + 1;
end if;
if (master_trig_t = '1' and master_busy_t = '0') then
case (trig_tag_mode) is
when x"00" =>
trig_tag <= std_logic_vector(trig_counter);
when x"01" =>
trig_tag <= std_logic_vector(timestamp_cnt);
when x"02" =>
trig_tag <= x"0000" & eudet_trig_tag_t;
when others =>
trig_tag <= x"DEADBEEF";
end case;
end if;
end if;
end process trig_tag_proc;
-- Output proc
out_proc: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ext_trig_o <= '0';
deadtime_cnt <= (others => '0');
busy_t <= '0';
prev_master_trig_t <= '0';
elsif rising_edge(clk_i) then
if (master_busy_t = '0') then
ext_trig_o <= prev_master_trig_t;
prev_master_trig_t <= master_trig_t;
end if;
if (prev_master_trig_t = '1') then
ext_trig_o <= '1' and not master_busy_t;
else
ext_trig_o <= '0';
end if;
if (deadtime_cnt > 0) then
-- This happens on the clk cycle after master_trig_t pulses (ie, when
-- ext_trig_o pulses), immediately setting ext_busy_o to '1'
deadtime_cnt <= deadtime_cnt - 1;
busy_t <= '1';
elsif (master_trig_t = '1') then
-- This happens on the clk cycle before ext_trig_o pulses
deadtime_cnt <= UNSIGNED(deadtime);
else
busy_t <= '0';
end if;
end if;
end process out_proc;
cmp_eudet_tlu: eudet_tlu
port map (
clk_i => clk_i,
rst_n_i => rst_n_i and (not local_reset),
eudet_trig_i => eudet_trig_i,
eudet_rst_i => eudet_rst_i,
eudet_busy_o => eudet_busy_o,
eudet_clk_o => eudet_clk_o,
busy_i => busy_t,
simple_mode_i => '0',
deadtime_i => deadtime,
trig_o => lcl_eudet_trig_t,
rst_o => open,
trig_tag_o => eudet_trig_tag_t
);
end rtl;
|
entity tb_case01 is
end tb_case01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_case01 is
signal a : std_logic_vector (1 downto 0);
signal o : std_logic_vector (1 downto 0);
signal clk : std_logic;
begin
dut: entity work.case01
port map (a, clk, o);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= "00";
pulse;
a <= "10";
pulse;
assert o = "00" severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
constant JTAG_IHP25RH1 : integer range 0 to 65535 := 16#251#;
constant JTAG_UT699RH : integer range 0 to 65535 := 16#699#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
constant JTAG_IHP25RH1 : integer range 0 to 65535 := 16#251#;
constant JTAG_UT699RH : integer range 0 to 65535 := 16#699#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
end;
|
-- $Id: sys_tst_rlink_cuff_atlys.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_atlys - syn
-- Description: rlink tester design for atlys with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_demu_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3
-- and sys_tst_fx2loop_atlys
------------------------------------------------------------------------------
-- Usage of Atlys Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_demu_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_demu_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_atlys is -- top level
-- implements atlys_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_USB_RXD : in slbit; -- USB UART receive data (board view)
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
I_HIO_SWI : in slv8; -- atlys hio switches
I_HIO_BTN : in slv6; -- atlys hio buttons
O_HIO_LED: out slv8; -- atlys hio leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_atlys;
architecture syn of sys_tst_rlink_cuff_atlys is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_USB_RXD,
O_TXD0 => O_USB_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_demu_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_HIO_SWI,
I_BTN => I_HIO_BTN,
O_LED => O_HIO_LED
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
end syn;
|
architecture RTL of FIFO is
procedure average_samples;
begin
average_samples;
PROC1 : process () is
begin
average_samples;
average_samples;
average_samples;
end process;
end architecture RTL;
|
-- rgb_win.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---
-- Provides RGB window bus. Converts WIN_SIZE rows to
-- a window of size WIN_SIZE x WIN_SIZE.
-- Current interface uses WIN_SIZE = 3 only.
---
entity rgb_win is
generic (
WIN_SIZE : integer := 3
);
port (
CLK : in std_logic;
CE : in std_logic;
ROW0_R : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW0_G : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW0_B : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW0_DE : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW0_HS : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW0_VS : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW1_R : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW1_G : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW1_B : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW1_DE : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW1_HS : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW1_VS : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW2_R : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW2_G : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW2_B : in std_logic_vector(WIN_SIZE * 8 - 1 downto 0);
ROW2_DE : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW2_HS : in std_logic_vector(WIN_SIZE - 1 downto 0);
ROW2_VS : in std_logic_vector(WIN_SIZE - 1 downto 0);
WIN_R : out std_logic_vector((WIN_SIZE ** 2) * 8 - 1 downto 0);
WIN_G : out std_logic_vector((WIN_SIZE ** 2) * 8 - 1 downto 0);
WIN_B : out std_logic_vector((WIN_SIZE ** 2) * 8 - 1 downto 0);
WIN_DE : out std_logic_vector((WIN_SIZE ** 2) - 1 downto 0);
WIN_HS : out std_logic_vector((WIN_SIZE ** 2) - 1 downto 0);
WIN_VS : out std_logic_vector((WIN_SIZE ** 2) - 1 downto 0)
);
end entity;
---
-- Introduces 1 CLK delay.
---
architecture rgb_win3 of rgb_win is
begin
assert WIN_SIZE = 3
report "Unsupported window size: " & integer'image(WIN_SIZE)
severity failure;
-------------------------------
reg_winp : process(CLK, CE)
begin
if rising_edge(CLK) then
if CE = '1' then
WIN_R(23 downto 0) <= ROW0_R;
WIN_G(23 downto 0) <= ROW0_G;
WIN_B(23 downto 0) <= ROW0_B;
WIN_DE(2 downto 0) <= ROW0_DE;
WIN_HS(2 downto 0) <= ROW0_HS;
WIN_VS(2 downto 0) <= ROW0_VS;
WIN_R(47 downto 24) <= ROW1_R;
WIN_G(47 downto 24) <= ROW1_G;
WIN_B(47 downto 24) <= ROW1_B;
WIN_DE(5 downto 3) <= ROW1_DE;
WIN_HS(5 downto 3) <= ROW1_HS;
WIN_VS(5 downto 3) <= ROW1_VS;
WIN_R(71 downto 48) <= ROW2_R;
WIN_G(71 downto 48) <= ROW2_G;
WIN_B(71 downto 48) <= ROW2_B;
WIN_DE(8 downto 6) <= ROW2_DE;
WIN_HS(8 downto 6) <= ROW2_HS;
WIN_VS(8 downto 6) <= ROW2_VS;
end if;
end if;
end process;
end architecture;
|
-- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______286.298____184.405
-- CLK_OUT2____50.526______0.000______50.0______265.785____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 24,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 19,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
-- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______286.298____184.405
-- CLK_OUT2____50.526______0.000______50.0______265.785____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 24,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 19,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v3 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed( 63 downto 0) := (others => '0');
signal mul_result, pgZFF_X0_quad_0, pgZFF_X1_quad_1, pgZFF_X2_quad_2, pgZFF_Y1_quad_1, pgZFF_Y2_quad_2 : signed( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter: integer:=1;
signal rst_cnt, s_trigger, s_multiply: std_logic;
constant shiftAddMultiply: boolean:=true;
constant DSPMultiply: boolean:=false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, cnt, Mul_stage_over, Mul_Ready, Mul_Ready1, Mul_Ready2, Mul_Ready3, Mul_Ready4, Mul_Ready5 : std_logic;
signal ZFF, Coef: std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rising_edge(clk)) then
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if (rising_edge(clk)) then
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig,Mul_Ready,Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul: entity work.multiplier
generic map(
MultiplierIsShiftAdd=> shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32,COUNT_WIDTH => 6)
Port map (CLK => CLK, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication: process(clk,rst_cnt,mul_coefs,Mul_Ready) begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier:process(counter,Coef_b0,Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result: process(clk,counter,mul_result,Mul_Ready)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 7);
end if;
end if;
end process;
end arch; |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v3 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed( 63 downto 0) := (others => '0');
signal mul_result, pgZFF_X0_quad_0, pgZFF_X1_quad_1, pgZFF_X2_quad_2, pgZFF_Y1_quad_1, pgZFF_Y2_quad_2 : signed( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter: integer:=1;
signal rst_cnt, s_trigger, s_multiply: std_logic;
constant shiftAddMultiply: boolean:=true;
constant DSPMultiply: boolean:=false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, cnt, Mul_stage_over, Mul_Ready, Mul_Ready1, Mul_Ready2, Mul_Ready3, Mul_Ready4, Mul_Ready5 : std_logic;
signal ZFF, Coef: std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rising_edge(clk)) then
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if (rising_edge(clk)) then
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig,Mul_Ready,Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul: entity work.multiplier
generic map(
MultiplierIsShiftAdd=> shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32,COUNT_WIDTH => 6)
Port map (CLK => CLK, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication: process(clk,rst_cnt,mul_coefs,Mul_Ready) begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier:process(counter,Coef_b0,Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result: process(clk,counter,mul_result,Mul_Ready)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 7);
end if;
end if;
end process;
end arch; |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v3 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed( 63 downto 0) := (others => '0');
signal mul_result, pgZFF_X0_quad_0, pgZFF_X1_quad_1, pgZFF_X2_quad_2, pgZFF_Y1_quad_1, pgZFF_Y2_quad_2 : signed( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter: integer:=1;
signal rst_cnt, s_trigger, s_multiply: std_logic;
constant shiftAddMultiply: boolean:=true;
constant DSPMultiply: boolean:=false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, cnt, Mul_stage_over, Mul_Ready, Mul_Ready1, Mul_Ready2, Mul_Ready3, Mul_Ready4, Mul_Ready5 : std_logic;
signal ZFF, Coef: std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rising_edge(clk)) then
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if (rising_edge(clk)) then
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig,Mul_Ready,Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul: entity work.multiplier
generic map(
MultiplierIsShiftAdd=> shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32,COUNT_WIDTH => 6)
Port map (CLK => CLK, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication: process(clk,rst_cnt,mul_coefs,Mul_Ready) begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier:process(counter,Coef_b0,Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result: process(clk,counter,mul_result,Mul_Ready)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 7);
end if;
end if;
end process;
end arch; |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v3 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed( 63 downto 0) := (others => '0');
signal mul_result, pgZFF_X0_quad_0, pgZFF_X1_quad_1, pgZFF_X2_quad_2, pgZFF_Y1_quad_1, pgZFF_Y2_quad_2 : signed( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter: integer:=1;
signal rst_cnt, s_trigger, s_multiply: std_logic;
constant shiftAddMultiply: boolean:=true;
constant DSPMultiply: boolean:=false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, cnt, Mul_stage_over, Mul_Ready, Mul_Ready1, Mul_Ready2, Mul_Ready3, Mul_Ready4, Mul_Ready5 : std_logic;
signal ZFF, Coef: std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rising_edge(clk)) then
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if (rising_edge(clk)) then
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig,Mul_Ready,Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul: entity work.multiplier
generic map(
MultiplierIsShiftAdd=> shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32,COUNT_WIDTH => 6)
Port map (CLK => CLK, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication: process(clk,rst_cnt,mul_coefs,Mul_Ready) begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier:process(counter,Coef_b0,Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result: process(clk,counter,mul_result,Mul_Ready)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 7);
end if;
end if;
end process;
end arch; |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:50:30 09/18/2015
-- Design Name:
-- Module Name: Magnitude_Comparator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Magnitude Comparator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Magnitude_Comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
AgtB : out STD_LOGIC;
AeqB : out STD_LOGIC;
AltB : out STD_LOGIC);
end Magnitude_Comparator;
architecture Magnitude_Comparator_Arch of Magnitude_Comparator is
-- Embedded signals are declare here
-- signal Tmp : std_logic_vector(2 downto 0);
begin
-- Signal Solution
-- process(A,B)
-- -- Variable should be declare here
-- -- variable Tmp : std_logic_vector(2 downto 0);
-- begin
-- -- Comparator implementation
-- if (A > B) then
-- Tmp <= "100";
-- elsif (A = B) then
-- Tmp <= "010";
-- else
-- Tmp <= "001";
-- end if;
-- end process;
--
-- AgtB <= Tmp(0);
-- AeqB <= Tmp(1);
-- AltB <= Tmp(2);
-- Variable solution
process(A,B)
-- Variable should be declare here
variable Tmp : std_logic_vector(2 downto 0);
begin
-- Comparator implementation
Tmp := "000"; -- Inicializar Tmp
if (A > B) then
Tmp(2) := '1';
elsif (A = B) then
Tmp(1) := '1';
else
Tmp(0) := '1';
end if;
AgtB <= Tmp(0);
AeqB <= Tmp(1);
AltB <= Tmp(2);
end process;
end Magnitude_Comparator_Arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal gtx_clk : std_logic := '0';
signal emdc, emdio: std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic;
signal can_rxd : std_logic;
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_logic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
-- wait;
wait for 355000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#0F#, 16#DD#, 16#94#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
|
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`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52624)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- 125MHZ ----->+ +------> open
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ATLYS is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXCLK : in std_logic;
RXD : in std_logic_vector(7 downto 0);
TXCLK : in std_logic;
GTXCLK : out std_logic;
TXD : out std_logic_vector(7 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity ATLYS;
architecture RTL of ATLYS is
component gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component gigabit_ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
--signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal INTERNAL_TXD : std_logic_vector(7 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
begin
gigabit_ethernet_inst_1 : gigabit_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--Ethernet Clock
CLK_125_MHZ => CLK_OUT3,
--GMII IF
GTXCLK => open,
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
PHY_RESET => PHY_RESET,
RXCLK => INTERNAL_RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(7 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 200.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
RST_INV <= not RST;
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
ODDR2_INST1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => GTXCLK, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Input buffering
--------------------------------------
BUFG_INST6 : IBUFG
port map
(O => RXCLK_BUF,
I => RXCLK);
-- DCM
--------------------------------------
dcm_sp_inst2: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF,
CLKFB => INTERNAL_RXCLK,
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
--------------------------------------
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
LOCKED_INTERNAL <= TX_LOCKED;
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 7 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- 125MHZ ----->+ +------> open
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ATLYS is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXCLK : in std_logic;
RXD : in std_logic_vector(7 downto 0);
TXCLK : in std_logic;
GTXCLK : out std_logic;
TXD : out std_logic_vector(7 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity ATLYS;
architecture RTL of ATLYS is
component gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component gigabit_ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
--signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal INTERNAL_TXD : std_logic_vector(7 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
begin
gigabit_ethernet_inst_1 : gigabit_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--Ethernet Clock
CLK_125_MHZ => CLK_OUT3,
--GMII IF
GTXCLK => open,
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
PHY_RESET => PHY_RESET,
RXCLK => INTERNAL_RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(7 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 200.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
RST_INV <= not RST;
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
ODDR2_INST1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => GTXCLK, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Input buffering
--------------------------------------
BUFG_INST6 : IBUFG
port map
(O => RXCLK_BUF,
I => RXCLK);
-- DCM
--------------------------------------
dcm_sp_inst2: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF,
CLKFB => INTERNAL_RXCLK,
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
--------------------------------------
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
LOCKED_INTERNAL <= TX_LOCKED;
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 7 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Ext_Mem_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
mem_mux_input : in std_logic; --mickey mux
R1_regfile_input: in std_logic_vector(15 downto 0);
ALU_address_input,stack_address_input : in std_logic_vector(9 downto 0);
ALU_out_input : in std_logic_vector(15 downto 0);
Z_input: in std_logic;
NF_input: in std_logic;
V_input: in std_logic;
C_input: in std_logic;
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
load_store_address_input : in std_logic_vector(15 downto 0); --LDM
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
op_code_output: out std_logic_vector(4 downto 0);
mem_mux_output : out std_logic; --mickey mux
R1_regfile_output: out std_logic_vector(15 downto 0);
ALU_address_output,stack_address_output : out std_logic_vector(9 downto 0);
ALU_out_output : out std_logic_vector(15 downto 0);
Z_output: out std_logic;
NF_output: out std_logic;
V_output: out std_logic;
C_output: out std_logic;
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
load_store_address_output : out std_logic_vector(15 downto 0)
);
end Ext_Mem_Buffer;
architecture arch_Ext_Mem_Buffer of Ext_Mem_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
pc_mux_map : nreg generic map (n=>2)port map(Clk,Rst,enable,pc_mux_input,pc_mux_output);
op_code_map : nreg generic map (n=>5)port map(Clk,Rst,enable,op_code_input,op_code_output);
mem_mux_map : Regis port map(Clk,Rst,enable,mem_mux_input,mem_mux_output);
R1_regfile_map : nreg generic map (n=>16)port map(Clk,Rst,enable,R1_regfile_input,R1_regfile_output);
ALU_address_map : nreg generic map (n=>10)port map(Clk,Rst,enable,ALU_address_input,ALU_address_output);
ALU_out_map : nreg generic map (n=>16)port map(Clk,Rst,enable,ALU_out_input,ALU_out_output);
Z_map : Regis port map(Clk,Rst,enable,Z_input,Z_output);
NF_map : Regis port map(Clk,Rst,enable,NF_input,NF_output);
V_map : Regis port map(Clk,Rst,enable,V_input,V_output);
C_map : Regis port map(Clk,Rst,enable,C_input,C_output);
outport_en_map : Regis port map(Clk,Rst,enable,outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,enable,reg_write_input,reg_write_output);
mem_write_map : Regis port map(Clk,Rst,enable,mem_write_input,mem_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,enable,write_data_reg_mux_input,write_data_reg_mux_output);
write_back_mux_map : nreg generic map (n=>16)port map(Clk,Rst,enable,write_back_mux_input,write_back_mux_output);
load_store_address_map : nreg generic map (n=>16)port map(Clk,Rst,enable,load_store_address_input,load_store_address_output);
end arch_Ext_Mem_Buffer;
|
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
ALU_cpi : out std_logic;
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_cpi : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: main_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY main_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END main_pll;
ARCHITECTURE SYN OF main_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 50,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 500,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=main_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "50"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "500"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "1.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.100000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "1.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "main_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "500"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL main_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_axcelerator
-- File: usbhc_axcelerator.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for axcelerator usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axcelerator;
use axcelerator.all;
library techmap;
use techmap.usbhc_axceleratorpkg.all;
entity usbhc_axcelerator is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_axcelerator;
architecture rtl of usbhc_axcelerator is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_axceleratorpkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_axceleratorpkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_axcelerator
-- File: usbhc_axcelerator.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for axcelerator usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axcelerator;
use axcelerator.all;
library techmap;
use techmap.usbhc_axceleratorpkg.all;
entity usbhc_axcelerator is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_axcelerator;
architecture rtl of usbhc_axcelerator is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_axceleratorpkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_axceleratorpkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_axcelerator_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/ip_design_axi_gpio_1_0_stub.vhdl
-- Design : ip_design_axi_gpio_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ip_design_axi_gpio_1_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ip_design_axi_gpio_1_0;
architecture stub of ip_design_axi_gpio_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[4:0],gpio2_io_i[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.3";
begin
end;
|
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (15 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(15 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg16Bit
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 14 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(15),
A(15),
B(15),
Ssoma(15),
CarryOutTemp0
);
END strc_RCA ; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_datamover_v5_1_13;
USE axi_datamover_v5_1_13.axi_datamover;
ENTITY system_axi_datamover_0_0 IS
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC
);
END system_axi_datamover_0_0;
ARCHITECTURE system_axi_datamover_0_0_arch OF system_axi_datamover_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_datamover IS
GENERIC (
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_ARID : INTEGER;
C_M_AXI_MM2S_ID_WIDTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_STSFIFO : INTEGER;
C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
C_MM2S_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_MM2S_BTT_USED : INTEGER;
C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_AWID : INTEGER;
C_M_AXI_S2MM_ID_WIDTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_STSFIFO : INTEGER;
C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
C_S2MM_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_S2MM_BTT_USED : INTEGER;
C_S2MM_SUPPORT_INDET_BTT : INTEGER;
C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
C_FAMILY : STRING;
C_MM2S_INCLUDE_SF : INTEGER;
C_S2MM_INCLUDE_SF : INTEGER;
C_ENABLE_CACHE_USER : INTEGER;
C_ENABLE_MM2S_TKEEP : INTEGER;
C_ENABLE_S2MM_TKEEP : INTEGER;
C_ENABLE_SKID_BUF : STRING;
C_ENABLE_S2MM_ADV_SIG : INTEGER;
C_ENABLE_MM2S_ADV_SIG : INTEGER;
C_CMD_WIDTH : INTEGER
);
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_halt : IN STD_LOGIC;
mm2s_halt_cmplt : OUT STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
mm2s_allow_addr_req : IN STD_LOGIC;
mm2s_addr_req_posted : OUT STD_LOGIC;
mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_halt : IN STD_LOGIC;
s2mm_halt_cmplt : OUT STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
s2mm_allow_addr_req : IN STD_LOGIC;
s2mm_addr_req_posted : OUT STD_LOGIC;
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
s2mm_ld_nxt_len : OUT STD_LOGIC;
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_datamover;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_MM2S_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_CMDSTS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_MM2S_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aruser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
BEGIN
U0 : axi_datamover
GENERIC MAP (
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_ARID => 0,
C_M_AXI_MM2S_ID_WIDTH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_STSFIFO => 1,
C_MM2S_STSCMD_FIFO_DEPTH => 4,
C_MM2S_STSCMD_IS_ASYNC => 1,
C_INCLUDE_MM2S_DRE => 0,
C_MM2S_BURST_SIZE => 16,
C_MM2S_BTT_USED => 16,
C_MM2S_ADDR_PIPE_DEPTH => 3,
C_INCLUDE_S2MM => 1,
C_M_AXI_S2MM_AWID => 0,
C_M_AXI_S2MM_ID_WIDTH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_STSFIFO => 1,
C_S2MM_STSCMD_FIFO_DEPTH => 4,
C_S2MM_STSCMD_IS_ASYNC => 1,
C_INCLUDE_S2MM_DRE => 0,
C_S2MM_BURST_SIZE => 16,
C_S2MM_BTT_USED => 16,
C_S2MM_SUPPORT_INDET_BTT => 0,
C_S2MM_ADDR_PIPE_DEPTH => 4,
C_FAMILY => "zynq",
C_MM2S_INCLUDE_SF => 1,
C_S2MM_INCLUDE_SF => 1,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_MM2S_TKEEP => 1,
C_ENABLE_S2MM_TKEEP => 1,
C_ENABLE_SKID_BUF => "11111",
C_ENABLE_S2MM_ADV_SIG => 0,
C_ENABLE_MM2S_ADV_SIG => 0,
C_CMD_WIDTH => 72
)
PORT MAP (
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn,
mm2s_halt => '0',
mm2s_err => mm2s_err,
m_axis_mm2s_cmdsts_aclk => m_axis_mm2s_cmdsts_aclk,
m_axis_mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn,
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata,
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep,
m_axis_mm2s_sts_tlast => m_axis_mm2s_sts_tlast,
mm2s_allow_addr_req => '1',
m_axi_mm2s_arid => m_axi_mm2s_arid,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_aruser => m_axi_mm2s_aruser,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
s2mm_halt => '0',
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
s2mm_allow_addr_req => '1',
m_axi_s2mm_awid => m_axi_s2mm_awid,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s2mm_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
);
END system_axi_datamover_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2217.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02217ent IS
END c07s02b06x00p01n01i02217ent;
ARCHITECTURE c07s02b06x00p01n01i02217arch OF c07s02b06x00p01n01i02217ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02217 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02217arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2217.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02217ent IS
END c07s02b06x00p01n01i02217ent;
ARCHITECTURE c07s02b06x00p01n01i02217arch OF c07s02b06x00p01n01i02217ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02217 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02217arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2217.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02217ent IS
END c07s02b06x00p01n01i02217ent;
ARCHITECTURE c07s02b06x00p01n01i02217arch OF c07s02b06x00p01n01i02217ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02217 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02217arch;
|
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 8 axis version with 24 I/O bits
entity HostMot5_8 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
IDX: in STD_LOGIC_VECTOR (7 downto 0);
PWM: inout STD_LOGIC_VECTOR (7 downto 0);
ENA: out STD_LOGIC_VECTOR (7 downto 0);
DIR: inout STD_LOGIC_VECTOR (7 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
-- IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_8; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_8 is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 8;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA010008"; -- MSW = rev 1, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"01FCA055"; -- = 33.3333 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfEightDecode(ena : std_logic; dec : std_logic_vector(2 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "000" => result := "00000001";
when "001" => result := "00000010";
when "010" => result := "00000100";
when "011" => result := "00001000";
when "100" => result := "00010000";
when "101" => result := "00100000";
when "110" => result := "01000000";
when "111" => result := "10000000";
when others => result := "00000000";
end case;
else
result := "00000000";
end if;
return result;
end OneOfEightDecode;
function OneOfEightMux(sel: std_logic_vector (2 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "000" => result := input(0);
when "001" => result := input(1);
when "010" => result := input(2);
when "011" => result := input(3);
when "100" => result := input(4);
when "101" => result := input(5);
when "110" => result := input(6);
when "111" => result := input(7);
when others => result := '0';
end case;
return result;
end OneOfEightMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgen
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgen;
component pwmref is
port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmref;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16+i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to 3 generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4)+3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgen port map (
clk => LClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
-- oportb: WordPR24 port map (
-- clear => '0',
-- clk => LClk,
-- ibus => LAD(23 downto 0),
-- obus => D(23 downto 0),
-- loadport => LoadPortB,
-- loadddr => LoadDDRB,
-- readddr => ReadDDRB,
-- portdata => IOBITSB
-- );
-- iportb: Word24RB port map (
-- obus => D(23 downto 0),
-- readport => ReadPortB,
-- portdata => IOBitsB
-- );
pwmrefcount: pwmref port map (
clk => LClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
-- if LatchedA(7 downto 2) = "101010" then -- 32 bit access
-- PortBSel <= '1';
-- else
-- PortBSel <= '0';
-- end if;
-- if LatchedA(7 downto 2) = "101011" then -- 32 bit access
-- DDRBSel <= '1';
-- else
-- DDRBSel <= '0';
-- end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfEightDecode(CounterSel,LatchedA(4 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfEightDecode(SCounterSel,LatchedA(4 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
-- PortBDecode: process (PortBSel,FastRead,LWR)
-- begin
-- if PortBSel = '1' and LWR = '0' then
-- LoadPortB <= '1';
-- else
-- LoadPortB <= '0';
-- end if;
-- if PortBSel = '1' and FastRead = '1' then
-- ReadPortB <= '1';
-- else
-- ReadPortB <= '0';
-- end if;
-- end process PortBDecode;
-- DDRBDecode: process (DDRBSel,FastRead,LWR)
-- begin
-- if DDRBSel = '1' and LWR = '0' then
-- LoadDDRB <= '1';
-- else
-- LoadDDRB <= '0';
-- end if;
-- if DDRBSel = '1' and FastRead = '1' then
-- ReadDDRB <= '1';
-- else
-- ReadDDRB <= '0';
-- end if;
-- end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfEightMux(LEDView(2 downto 0),A);
LEDS(5) <= not OneOfEightMux(LEDView(2 downto 0),B);
LEDS(4) <= not OneOfEightMux(LEDView(2 downto 0),Idx);
LEDS(3) <= not OneOfEightMux(LEDView(2 downto 0),Dir);
LEDS(2) <= not OneOfEightMux(LEDView(2 downto 0),PWM);
LEDS(1) <= OneOfEightMux(LEDView(2 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:02 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_stub.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[47:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bid[47:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_arid[47:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rid[47:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1202.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01202ent IS
END c08s01b00x00p08n03i01202ent;
ARCHITECTURE c08s01b00x00p08n03i01202arch OF c08s01b00x00p08n03i01202ent IS
signal A : bit_vector (10 to 13) := B"0101";
BEGIN
TESTING: PROCESS
variable k : integer := 11;
BEGIN
wait on A(k);
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01202 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01202arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1202.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01202ent IS
END c08s01b00x00p08n03i01202ent;
ARCHITECTURE c08s01b00x00p08n03i01202arch OF c08s01b00x00p08n03i01202ent IS
signal A : bit_vector (10 to 13) := B"0101";
BEGIN
TESTING: PROCESS
variable k : integer := 11;
BEGIN
wait on A(k);
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01202 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01202arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1202.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01202ent IS
END c08s01b00x00p08n03i01202ent;
ARCHITECTURE c08s01b00x00p08n03i01202arch OF c08s01b00x00p08n03i01202ent IS
signal A : bit_vector (10 to 13) := B"0101";
BEGIN
TESTING: PROCESS
variable k : integer := 11;
BEGIN
wait on A(k);
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01202 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01202arch;
|
-------------------------------------------------------------------------------
--
-- The testbench for t8243 core.
--
-- $Id: tb_t8243.vhd,v 1.1 2006-07-14 01:02:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8243 is
end tb_t8243;
use work.t48_core_comp_pack.all;
use work.t8243_comp_pack.t8243_sync_notri;
use work.t48_tb_pack.all;
architecture behav of tb_t8243 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component if_timing
port(
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end component;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal xtal_n_s : std_logic;
signal res_n_s : std_logic;
signal xtal3_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal rom_addr_s : std_logic_vector(11 downto 0);
signal rom_data_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_addr_s : std_logic_vector( 7 downto 0);
signal ram_we_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal t48_p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal t48_p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal bus_s : std_logic_vector( 7 downto 0);
signal t48_bus_s : std_logic_vector( 7 downto 0);
signal bus_dir_s : std_logic;
signal ext_mem_addr_q : std_logic_vector( 7 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_q : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal ext_rom_addr_s : std_logic_vector(11 downto 0);
signal tb_p1_q : std_logic_vector( 7 downto 0);
signal tb_p2_q : std_logic_vector( 7 downto 0);
signal ext_mem_sel_we_q : boolean;
signal ena_ext_ram_q : boolean;
signal ena_tb_periph_q : boolean;
signal t8243_p2_s : std_logic_vector(3 downto 0);
signal t8243_p2_en_s : std_logic;
signal p4_s,
p5_s,
p6_s,
p7_s : std_logic_vector(3 downto 0);
signal p4_p6_s,
p5_p7_s : std_logic_vector(3 downto 0);
signal p4_en_s,
p5_en_s,
p6_en_s,
p7_en_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
signal zero_byte_s : std_logic_vector( 7 downto 0);
begin
zero_s <= '0';
one_s <= '1';
zero_byte_s <= (others => '0');
-----------------------------------------------------------------------------
-- Internal ROM, 2k bytes
-- Initialized by file rom_t49.hex.
-----------------------------------------------------------------------------
rom_internal_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => rom_data_s
);
-----------------------------------------------------------------------------
-- External ROM, 2k bytes
-- Initialized by file rom_t49_ext.hex.
-----------------------------------------------------------------------------
ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0);
ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q;
rom_external_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
-----------------------------------------------------------------------------
-- Internal RAM, 256 bytes
-----------------------------------------------------------------------------
ram_256 : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ram_addr_s,
we_i => ram_we_s,
ena_i => one_s,
d_i => ram_data_to_s,
d_o => ram_data_from_s
);
-----------------------------------------------------------------------------
-- External RAM, 256 bytes
-----------------------------------------------------------------------------
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_q,
we_i => ext_ram_we_q,
ena_i => one_s,
d_i => bus_s,
d_o => ext_ram_data_from_s
);
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_s,
xtal_en_i => one_s,
reset_i => res_n_s,
t0_i => p1_s(0),
t0_o => open,
t0_dir_o => open,
int_n_i => int_n_s,
ea_i => rom_addr_s(11),
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => bus_s,
db_o => t48_bus_s,
db_dir_o => bus_dir_s,
t1_i => p1_s(1),
p2_i => p2_s,
p2_o => t48_p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_s,
p1_o => t48_p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_s,
clk_i => xtal_s,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => ram_addr_s,
dmem_we_o => ram_we_s,
dmem_data_i => ram_data_from_s,
dmem_data_o => ram_data_to_s,
pmem_addr_o => rom_addr_s,
pmem_data_i => rom_data_s
);
if_timing_b : if_timing
port map (
xtal_i => xtal_s,
ale_i => ale_s,
psen_n_i => psen_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
prog_n_i => prog_n_s,
db_bus_i => bus_s,
p2_i => t48_p2_s
);
t8243_sync_notri_b : t8243_sync_notri
port map (
clk_i => xtal_s,
clk_en_i => one_s,
reset_n_i => one_s,
cs_n_i => zero_s,
prog_n_i => prog_n_s,
p2_i => t48_p2_s(3 downto 0),
p2_o => t8243_p2_s,
p2_en_o => t8243_p2_en_s,
p4_i => p4_p6_s,
p4_o => p4_s,
p4_en_o => p4_en_s,
p5_i => p5_p7_s,
p5_o => p5_s,
p5_en_o => p5_en_s,
p6_i => p4_p6_s,
p6_o => p6_s,
p6_en_o => p6_en_s,
p7_i => p5_p7_s,
p7_o => p7_s,
p7_en_o => p7_en_s
);
p4_p6_s <= p4_s
when p4_en_s = '1' else
(others => 'Z');
p5_p7_s <= p5_s
when p5_en_s = '1' else
(others => 'Z');
p4_p6_s <= p6_s
when p6_en_s = '1' else
(others => 'Z');
p5_p7_s <= p7_s
when p7_en_s = '1' else
(others => 'Z');
-----------------------------------------------------------------------------
-- Port logic
--
ports: process (t48_p1_s,
p1_low_imp_s,
t48_p2_s,
p2l_low_imp_s,
p2h_low_imp_s)
function t48_port_f(t48_p : std_logic_vector;
low_imp : std_logic) return std_logic_vector is
variable p_v : std_logic_vector(t48_p'range);
begin
if low_imp = '1' then
p_v := t48_p;
else
for i in p_v'range loop
if t48_p(i) = '1' then
p_v(i) := 'H';
else
p_v(i) := t48_p(i);
end if;
end loop;
end if;
return p_v;
end;
begin
p1_s <= t48_port_f(t48_p => t48_p1_s,
low_imp => p1_low_imp_s);
p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process ports;
--
-----------------------------------------------------------------------------
t8243_p2: process (t8243_p2_s,
t8243_p2_en_s)
begin
p2_s <= (others => 'Z');
if t8243_p2_en_s = '1' then
p2_s(3 downto 0) <= t8243_p2_s;
end if;
end process t8243_p2;
bus_s <= t48_bus_s
when bus_dir_s = '1' else
(others => 'Z');
bus_s <= ext_ram_data_from_s
when rd_n_s = '0' and ena_ext_ram_q else
(others => 'Z');
bus_s <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
-----------------------------------------------------------------------------
-- External memory access signals
--
ext_mem: process (wr_n_s,
ext_mem_addr_q,
ena_ext_ram_q,
ale_s,
bus_s,
xtal_s)
begin
if ale_s'event and ale_s = '0' then
if not is_X(bus_s) then
ext_mem_addr_q <= bus_s;
else
ext_mem_addr_q <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
-- write enable for external RAM
if ena_ext_ram_q then
ext_ram_we_q <= '1';
end if;
-- process external memory selector
if ext_mem_addr_q = "11111111" then
ext_mem_sel_we_q <= true;
end if;
end if;
if xtal_s'event and xtal_s = '1' then
ext_ram_we_q <= '0';
ext_mem_sel_we_q <= false;
end if;
end process ext_mem;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ext_mem_sel
--
-- Purpose:
-- Select external memory address space.
-- This is either
-- + external RAM
-- + testbench peripherals
--
ext_mem_sel: process (res_n_s, xtal_s)
begin
if res_n_s = '0' then
ena_ext_ram_q <= true;
ena_tb_periph_q <= false;
elsif xtal_s'event and xtal_s = '1' then
if ext_mem_sel_we_q then
if bus_s(0) = '1' then
ena_ext_ram_q <= true;
else
ena_ext_ram_q <= false;
end if;
if bus_s(1) = '1' then
ena_tb_periph_q <= true;
else
ena_tb_periph_q <= false;
end if;
end if;
end if;
end process ext_mem_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process tb_periph
--
-- Purpose:
-- Implements the testbenc peripherals driving P1 and P2.
--
tb_periph: process (res_n_s, wr_n_s)
function oc_f (pX : std_logic_vector) return std_logic_vector is
variable r_v : std_logic_vector(pX'range);
begin
for i in pX'range loop
if pX(i) = '0' then
r_v(i) := '0';
else
r_v(i) := 'H';
end if;
end loop;
return r_v;
end;
begin
if res_n_s = '0' then
tb_p1_q <= (others => 'H');
tb_p2_q <= (others => 'H');
elsif wr_n_s'event and wr_n_s = '1' then
if ena_tb_periph_q then
case ext_mem_addr_q is
-- P1
when "00000000" =>
tb_p1_q <= oc_f(t48_bus_s);
-- P2
when "00000001" =>
tb_p2_q <= oc_f(t48_bus_s);
when others =>
null;
end case;
end if;
end if;
end process tb_periph;
--
-----------------------------------------------------------------------------
p1_s <= tb_p1_q;
p2_s <= tb_p2_q;
xtal_n_s <= not xtal_s;
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : test1
-- Project :
-------------------------------------------------------------------------------
-- File : test1.vhd
-- Author : <kristoffer.nordstrom@HELVNB0100>
-- Company :
-- Created : 2015-04-27
-- Last update: 2015-05-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-27 1.0 kn Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity A is
port (
Clk : in std_logic;
Clr : in std_logic;
A_A : in std_logic_vector(3 downto 0);
A_B : in std_logic_vector(3 downto 0);
A_AB : out std_logic_vector(4 downto 0)
);
end entity A;
-------------------------------------------------------------------------------
architecture str of A is
signal Cents_A : std_logic_vector(3 downto 0);
signal Cents_B : std_logic_vector(3 downto 0);
signal Cents_AB : std_logic_vector(4 downto 0);
signal B_A : std_logic_vector(3 downto 0);
signal B_B : std_logic_vector(3 downto 0);
signal B_AB : std_logic_vector(4 downto 0);
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal AB : unsigned(A_AB'range);
begin -- architecture str
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
A_AB <= std_logic_vector(AB);
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
p_addAandB: process (Clk) is
begin -- process p_addAandB
if Clk'event and Clk = '1' then -- rising clock edge
if Clr = '1' then
AB <= to_unsigned(0, AB'length);
else
AB <= resize(unsigned(A_A), AB'length) + resize(unsigned(A_B), AB'length);
end if;
end if;
end process p_addAandB;
i_B_1: entity work.B
port map (
Clk => Clk,
Clr => Clr,
B_A => B_A,
B_B => B_B,
B_AB => B_AB);
i_Cents_1: entity work.Cents
port map (
Clk => Clk,
Clr => Clr,
Cents_A => Cents_A,
Cents_B => Cents_B,
Cents_AB => Cents_AB);
end architecture str;
-------------------------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity MUX8_1_Icontrol is
port(
Sel : in vl_logic_vector(2 downto 0);
S0 : in vl_logic;
S1 : in vl_logic;
S2 : in vl_logic;
S3 : in vl_logic;
S4 : in vl_logic;
S5 : in vl_logic;
S6 : in vl_logic;
S7 : in vl_logic;
\out\ : out vl_logic
);
end MUX8_1_Icontrol;
|
-- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementations.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
package corelib_List is
generic (
type ELEMENT_TYPE;
InitialMasterListSize : POSITIVE := 4;
InitialChunkListSize : POSITIVE := 8;
MasterListResize : POSITIVE := 8;
ChunkListResize : POSITIVE := 8
);
type ELEMENT_ARRAY is array(NATURAL range <>) of ELEMENT_TYPE;
-- protected list implementation
type PT_LIST is protected
procedure Init;
-- procedure Clear;
procedure Append(Value : ELEMENT_TYPE);
impure function Append(Value : ELEMENT_TYPE) return NATURAL;
procedure Append(Values : ELEMENT_ARRAY);
impure function Append(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Prepend(Value : ELEMENT_TYPE);
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Prepend(Values : ELEMENT_ARRAY);
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE);
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY);
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE);
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE;
impure function Get(Index : NATURAL) return ELEMENT_TYPE;
procedure RemoveAt(Index : NATURAL);
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE;
procedure Remove(Value : ELEMENT_TYPE);
impure function Remove(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Remove(Values : ELEMENT_ARRAY);
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY;
impure function Count return natural;
impure function Size return positive;
-- procedure Resize(Size : positive);
end protected;
end package;
package body corelib_List is
-- protected list implementation
type PT_LIST is protected body
subtype T_Chunk is ELEMENT_ARRAY;
type P_Chunk is access T_Chunk;
type T_MasterListItem is record
Count : NATURAL;
Pointer : P_Chunk;
end record;
type T_MasterList is array(NATURAL range <>) of T_MasterListItem;
type P_MasterList is access T_MasterList;
type T_AddressTuple is record
MasterIndex : INTEGER;
ChunkIndex : INTEGER;
ListIndex : INTEGER;
end record;
variable I_Count : NATURAL := 0;
variable I_MasterList_Size : POSITIVE := InitialMasterListSize;
variable I_MasterList_Count : NATURAL := 0;
variable I_MasterList_Last : NATURAL := 0;
variable I_MasterList : P_MasterList := null;
procedure Init is
begin
I_Count := 0;
I_MasterList_Size := InitialMasterListSize;
I_MasterList_Count := 1;
I_MasterList_Last := 0;
I_MasterList := new T_MasterList(0 to InitialMasterListSize - 1);
I_MasterList(0).Count := 0;
I_MasterList(0).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end procedure;
procedure CheckResize(Size : positive) is
variable i : NATURAL;
variable j : NATURAL;
variable Remaining : INTEGER;
variable New_Chunks : NATURAL;
variable New_MasterList_Size : NATURAL;
variable New_MasterList : P_MasterList;
begin
Remaining := Size;
i := I_MasterList_Last;
Remaining := Remaining - (InitialChunkListSize - I_MasterList(i).Count);
New_Chunks := (Remaining + ChunkListResize - 1) / ChunkListResize;
if ((I_MasterList_Size - I_MasterList_Count) < New_Chunks) then
New_MasterList_Size := I_MasterList_Size + ((New_Chunks + MasterListResize - 1) / MasterListResize) * MasterListResize;
New_MasterList := new T_MasterList(0 to New_MasterList_Size - 1);
for j in 0 to I_MasterList_Count - 1 loop
New_MasterList(j).Count := I_MasterList(j).Count;
New_MasterList(j).Pointer := I_MasterList(j).Pointer;
end loop;
deallocate(I_MasterList);
I_MasterList := New_MasterList;
I_MasterList_Size := New_MasterList_Size;
end if;
for j in I_MasterList_Count to I_MasterList_Count + New_Chunks - 1 loop
I_MasterList(j).Count := 0;
I_MasterList(j).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end loop;
I_MasterList_Count := I_MasterList_Count + New_Chunks;
end procedure;
-- procedure Clear is
-- begin
-- end procedure;
procedure Append(Value : ELEMENT_TYPE) is
variable i : NATURAL;
variable j : NATURAL;
begin
CheckResize(1);
i := I_MasterList_Last;
if (I_MasterList(i).Count >= InitialChunkListSize) then
i := i + 1;
I_MasterList_Last := i;
end if;
j := I_MasterList(i).Count;
I_MasterList(i).Pointer(j) := Value;
I_MasterList(i).Count := j + 1;
I_Count := I_Count + 1;
end procedure;
impure function Append(Value : ELEMENT_TYPE) return NATURAL is
begin
Append(Value);
return I_Count - 1;
end function;
procedure Append(Values : ELEMENT_ARRAY) is
begin
end procedure;
impure function Append(Values : ELEMENT_ARRAY) return NATURAL is
begin
Append(Values);
return I_Count - Values'length;
end function;
-- procedure Prepend(Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL is
-- begin
-- end function;
-- procedure Prepend(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL is
-- begin
-- end function;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function AddressOf(Value : ELEMENT_TYPE) return T_AddressTuple is
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
if (I_MasterList(i).Pointer(j) = Value) then
return (i, j, k);
end if;
k := k + 1;
end loop;
end loop;
return (-1, -1, -1);
end function;
impure function AddressOf(Index : NATURAL) return T_AddressTuple is
variable j : NATURAL;
variable k : NATURAL;
begin
if (Index >= I_Count) then
report "Index is out of range." severity ERROR;
return (-1, -1, -1);
end if;
k := Index;
for i in 0 to I_MasterList_Count - 1 loop
j := I_MasterList(i).Count;
if (k < j) then
return (i, k, Index);
else
k := k - j;
end if;
end loop;
return (-1, -1, -1);
end function;
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER is
constant idx : T_AddressTuple := AddressOf(Value);
begin
return idx.ListIndex;
end function;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE) is
constant idx : T_AddressTuple := AddressOf(Index);
begin
if (idx.ListIndex /= -1) then
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
end procedure;
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable old : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
old := I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
return old;
end function;
impure function Get(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable Empty : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
return I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
end if;
return Empty;
end function;
procedure RemoveChunk(ChunkIndex : NATURAL) is
begin
deallocate(I_MasterList(ChunkIndex).Pointer);
for i in ChunkIndex to I_MasterList_Count - 2 loop
I_MasterList(i).Count := I_MasterList(i + 1).Count;
I_MasterList(i).Pointer := I_MasterList(i + 1).Pointer;
end loop;
I_MasterList_Count := I_MasterList_Count - 1;
end procedure;
procedure Remove(Idx : T_AddressTuple) is
constant i : INTEGER := idx.MasterIndex;
begin
if ((Idx.ChunkIndex = 0) and (I_MasterList(i).Count = 1)) then
RemoveChunk(i);
else
for j in Idx.ChunkIndex to InitialChunkListSize - 2 loop
I_MasterList(i).Pointer(j) := I_MasterList(i).Pointer(j + 1);
end loop;
I_MasterList(i).Count := I_MasterList(i).Count - 1;
end if;
I_Count := I_Count - 1;
end procedure;
procedure RemoveAt(Index : NATURAL) is
begin
Remove(AddressOf(Index));
end procedure;
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
constant i : INTEGER := idx.MasterIndex;
constant j : INTEGER := idx.ChunkIndex;
constant Value : ELEMENT_TYPE := I_MasterList(i).Pointer(j);
begin
Remove(idx);
return Value;
end function;
procedure Remove(Value : ELEMENT_TYPE) is
begin
Remove(AddressOf(Value));
end procedure;
impure function Remove(Value : ELEMENT_TYPE) return NATURAL is
constant idx : T_AddressTuple := AddressOf(Value);
begin
Remove(idx);
return idx.ListIndex;
end function;
-- procedure Remove(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY is
variable Result : ELEMENT_ARRAY(0 to I_Count - 1);
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
Result(k) := I_MasterList(i).Pointer(j);
k := k + 1;
end loop;
end loop;
return Result;
end function;
impure function Count return natural is
begin
return I_Count;
end function;
impure function Size return positive is
begin
return I_MasterList_Size * InitialChunkListSize;
end function;
-- procedure Resize(Size : positive) is
-- begin
-- end procedure;
end protected body;
end package body;
|
-- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementations.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
package corelib_List is
generic (
type ELEMENT_TYPE;
InitialMasterListSize : POSITIVE := 4;
InitialChunkListSize : POSITIVE := 8;
MasterListResize : POSITIVE := 8;
ChunkListResize : POSITIVE := 8
);
type ELEMENT_ARRAY is array(NATURAL range <>) of ELEMENT_TYPE;
-- protected list implementation
type PT_LIST is protected
procedure Init;
-- procedure Clear;
procedure Append(Value : ELEMENT_TYPE);
impure function Append(Value : ELEMENT_TYPE) return NATURAL;
procedure Append(Values : ELEMENT_ARRAY);
impure function Append(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Prepend(Value : ELEMENT_TYPE);
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Prepend(Values : ELEMENT_ARRAY);
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE);
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY);
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE);
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE;
impure function Get(Index : NATURAL) return ELEMENT_TYPE;
procedure RemoveAt(Index : NATURAL);
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE;
procedure Remove(Value : ELEMENT_TYPE);
impure function Remove(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Remove(Values : ELEMENT_ARRAY);
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY;
impure function Count return natural;
impure function Size return positive;
-- procedure Resize(Size : positive);
end protected;
end package;
package body corelib_List is
-- protected list implementation
type PT_LIST is protected body
subtype T_Chunk is ELEMENT_ARRAY;
type P_Chunk is access T_Chunk;
type T_MasterListItem is record
Count : NATURAL;
Pointer : P_Chunk;
end record;
type T_MasterList is array(NATURAL range <>) of T_MasterListItem;
type P_MasterList is access T_MasterList;
type T_AddressTuple is record
MasterIndex : INTEGER;
ChunkIndex : INTEGER;
ListIndex : INTEGER;
end record;
variable I_Count : NATURAL := 0;
variable I_MasterList_Size : POSITIVE := InitialMasterListSize;
variable I_MasterList_Count : NATURAL := 0;
variable I_MasterList_Last : NATURAL := 0;
variable I_MasterList : P_MasterList := null;
procedure Init is
begin
I_Count := 0;
I_MasterList_Size := InitialMasterListSize;
I_MasterList_Count := 1;
I_MasterList_Last := 0;
I_MasterList := new T_MasterList(0 to InitialMasterListSize - 1);
I_MasterList(0).Count := 0;
I_MasterList(0).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end procedure;
procedure CheckResize(Size : positive) is
variable i : NATURAL;
variable j : NATURAL;
variable Remaining : INTEGER;
variable New_Chunks : NATURAL;
variable New_MasterList_Size : NATURAL;
variable New_MasterList : P_MasterList;
begin
Remaining := Size;
i := I_MasterList_Last;
Remaining := Remaining - (InitialChunkListSize - I_MasterList(i).Count);
New_Chunks := (Remaining + ChunkListResize - 1) / ChunkListResize;
if ((I_MasterList_Size - I_MasterList_Count) < New_Chunks) then
New_MasterList_Size := I_MasterList_Size + ((New_Chunks + MasterListResize - 1) / MasterListResize) * MasterListResize;
New_MasterList := new T_MasterList(0 to New_MasterList_Size - 1);
for j in 0 to I_MasterList_Count - 1 loop
New_MasterList(j).Count := I_MasterList(j).Count;
New_MasterList(j).Pointer := I_MasterList(j).Pointer;
end loop;
deallocate(I_MasterList);
I_MasterList := New_MasterList;
I_MasterList_Size := New_MasterList_Size;
end if;
for j in I_MasterList_Count to I_MasterList_Count + New_Chunks - 1 loop
I_MasterList(j).Count := 0;
I_MasterList(j).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end loop;
I_MasterList_Count := I_MasterList_Count + New_Chunks;
end procedure;
-- procedure Clear is
-- begin
-- end procedure;
procedure Append(Value : ELEMENT_TYPE) is
variable i : NATURAL;
variable j : NATURAL;
begin
CheckResize(1);
i := I_MasterList_Last;
if (I_MasterList(i).Count >= InitialChunkListSize) then
i := i + 1;
I_MasterList_Last := i;
end if;
j := I_MasterList(i).Count;
I_MasterList(i).Pointer(j) := Value;
I_MasterList(i).Count := j + 1;
I_Count := I_Count + 1;
end procedure;
impure function Append(Value : ELEMENT_TYPE) return NATURAL is
begin
Append(Value);
return I_Count - 1;
end function;
procedure Append(Values : ELEMENT_ARRAY) is
begin
end procedure;
impure function Append(Values : ELEMENT_ARRAY) return NATURAL is
begin
Append(Values);
return I_Count - Values'length;
end function;
-- procedure Prepend(Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL is
-- begin
-- end function;
-- procedure Prepend(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL is
-- begin
-- end function;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function AddressOf(Value : ELEMENT_TYPE) return T_AddressTuple is
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
if (I_MasterList(i).Pointer(j) = Value) then
return (i, j, k);
end if;
k := k + 1;
end loop;
end loop;
return (-1, -1, -1);
end function;
impure function AddressOf(Index : NATURAL) return T_AddressTuple is
variable j : NATURAL;
variable k : NATURAL;
begin
if (Index >= I_Count) then
report "Index is out of range." severity ERROR;
return (-1, -1, -1);
end if;
k := Index;
for i in 0 to I_MasterList_Count - 1 loop
j := I_MasterList(i).Count;
if (k < j) then
return (i, k, Index);
else
k := k - j;
end if;
end loop;
return (-1, -1, -1);
end function;
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER is
constant idx : T_AddressTuple := AddressOf(Value);
begin
return idx.ListIndex;
end function;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE) is
constant idx : T_AddressTuple := AddressOf(Index);
begin
if (idx.ListIndex /= -1) then
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
end procedure;
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable old : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
old := I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
return old;
end function;
impure function Get(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable Empty : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
return I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
end if;
return Empty;
end function;
procedure RemoveChunk(ChunkIndex : NATURAL) is
begin
deallocate(I_MasterList(ChunkIndex).Pointer);
for i in ChunkIndex to I_MasterList_Count - 2 loop
I_MasterList(i).Count := I_MasterList(i + 1).Count;
I_MasterList(i).Pointer := I_MasterList(i + 1).Pointer;
end loop;
I_MasterList_Count := I_MasterList_Count - 1;
end procedure;
procedure Remove(Idx : T_AddressTuple) is
constant i : INTEGER := idx.MasterIndex;
begin
if ((Idx.ChunkIndex = 0) and (I_MasterList(i).Count = 1)) then
RemoveChunk(i);
else
for j in Idx.ChunkIndex to InitialChunkListSize - 2 loop
I_MasterList(i).Pointer(j) := I_MasterList(i).Pointer(j + 1);
end loop;
I_MasterList(i).Count := I_MasterList(i).Count - 1;
end if;
I_Count := I_Count - 1;
end procedure;
procedure RemoveAt(Index : NATURAL) is
begin
Remove(AddressOf(Index));
end procedure;
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
constant i : INTEGER := idx.MasterIndex;
constant j : INTEGER := idx.ChunkIndex;
constant Value : ELEMENT_TYPE := I_MasterList(i).Pointer(j);
begin
Remove(idx);
return Value;
end function;
procedure Remove(Value : ELEMENT_TYPE) is
begin
Remove(AddressOf(Value));
end procedure;
impure function Remove(Value : ELEMENT_TYPE) return NATURAL is
constant idx : T_AddressTuple := AddressOf(Value);
begin
Remove(idx);
return idx.ListIndex;
end function;
-- procedure Remove(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY is
variable Result : ELEMENT_ARRAY(0 to I_Count - 1);
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
Result(k) := I_MasterList(i).Pointer(j);
k := k + 1;
end loop;
end loop;
return Result;
end function;
impure function Count return natural is
begin
return I_Count;
end function;
impure function Size return positive is
begin
return I_MasterList_Size * InitialChunkListSize;
end function;
-- procedure Resize(Size : positive) is
-- begin
-- end procedure;
end protected body;
end package body;
|
---------------------------------------------------------------------
-- IBUS adapter
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Converts the Low Latency Interface to WISHBONE registered
-- feedback protocol.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ibus_adapter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ibus_cyc_i: in std_logic;
ibus_stb_i: in std_logic;
ibus_cti_i: in std_logic_vector(2 downto 0);
ibus_bte_i: in std_logic_vector(1 downto 0);
ibus_ack_o: out std_logic;
ibus_adr_i: in std_logic_vector(29 downto 0);
ibus_dat_o: out std_logic_vector(31 downto 0);
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic
);
end entity;
architecture rtl of ibus_adapter is
constant burst_delay: integer:=5;
signal burst_delay_cnt: integer:=0;
signal delay_burst: std_logic;
signal re: std_logic;
signal requested: std_logic:='0';
signal adr: unsigned(29 downto 0);
signal ack: std_logic;
begin
-- Insert burst delay
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
burst_delay_cnt<=0;
elsif ibus_cyc_i='0' then
burst_delay_cnt<=burst_delay;
elsif burst_delay_cnt/=0 then
burst_delay_cnt<=burst_delay_cnt-1;
end if;
end if;
end process;
delay_burst<='1' when burst_delay_cnt/=0 else '0';
-- Generate ACK signal
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
requested<='0';
elsif lli_busy_i='0' then
requested<=re;
end if;
end if;
end process;
ack<=requested and not lli_busy_i;
-- Generate LLI signals
re<=(ibus_cyc_i and ibus_stb_i and not delay_burst) when ack='0' or
(ibus_cti_i="010" and ibus_bte_i="00") else '0';
adr<=unsigned(ibus_adr_i) when re='1' and ack='0' else
unsigned(ibus_adr_i)+1 when re='1' and ack='1' else
(others=>'-');
lli_re_o<=re;
lli_adr_o<=std_logic_vector(adr);
-- Generate IBUS signals
ibus_ack_o<=ack;
ibus_dat_o<=lli_dat_i when ack='1' else (others=>'-');
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:26 02/12/2014
-- Design Name:
-- Module Name: rca_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rca_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end rca_4_bit;
architecture Behavioral of rca_4_bit is
signal c0, c1, c2 : std_logic:='0';
signal b0, b1, b2, b3 : std_logic:='0';
begin
--add/sub control; If Cin is high, then we are subtracting, and these
--muxes output the inverse of B. If Cin is low, then we are adding, and
--these muxes just pass B.
mux0: entity work.mux2 port map (B(0),NOT(B(0)),Cin,b0);
mux1: entity work.mux2 port map (B(1),NOT(B(1)),Cin,b1);
mux2: entity work.mux2 port map (B(2),NOT(B(2)),Cin,b2);
mux3: entity work.mux2 port map (B(3),NOT(B(3)),Cin,b3);
FA0: entity work.full_adder_1_bit port map (A(0),b0,Cin,c0,Sum(0));
FA1: entity work.full_adder_1_bit port map (A(1),b1,c0,c1,Sum(1));
FA2: entity work.full_adder_1_bit port map (A(2),b2,c1,c2,Sum(2));
FA3: entity work.full_adder_1_bit port map (A(3),b3,c2,Cout,Sum(3));
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity IF_STAGE is
port(
clk : in vl_logic;
rst : in vl_logic;
instr_fetch_enable: in vl_logic;
imm_branch_offset: in vl_logic_vector(5 downto 0);
branch_enable : in vl_logic;
jump : in vl_logic;
pc : out vl_logic_vector(7 downto 0);
instr : out vl_logic_vector(15 downto 0)
);
end IF_STAGE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Lookup table for scaling values to apply to the vector after rotating. It depends on the number of steps of the algorithm
entity scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end scaling_values_lut;
architecture scaling_values_lut_arq of scaling_values_lut is
constant max_representable_value_index: integer := 9; --After this index, the fixed point representation can't show any difference
type scaling_values_table is array (natural range <>) of std_logic_vector(TOTAL_BITS - 1 downto 0);
constant scaling_values : scaling_values_table := (
"00000000000000001011010100000100", ---0.707092285156
"00000000000000001010000111101000", ---0.632446289062
"00000000000000001001110100010011", ---0.613571166992
"00000000000000001001101111011100", ---0.608825683594
"00000000000000001001101110001110", ---0.607635498047
"00000000000000001001101101111011", ---0.607345581055
"00000000000000001001101101110110", ---0.607269287109
"00000000000000001001101101110101", ---0.60725402832
"00000000000000001001101101110101", ---0.60725402832
"00000000000000001001101101110100" ---0.607238769531
);
begin
process (steps) is
begin
if(steps > max_representable_value_index) then
scaling_value <= scaling_values(max_representable_value_index);
elsif(steps = 0) then
scaling_value <= (others => '0');
else
scaling_value <= scaling_values(steps - 1);
end if;
end process;
end architecture; |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
function min(iv : invect) return entry is
begin
return iv(0);
end;
begin
process
begin
minimum <= min(invect); -- should be vec not invect
wait;
end process;
end behav;
|
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
function min(iv : invect) return entry is
begin
return iv(0);
end;
begin
process
begin
minimum <= min(invect); -- should be vec not invect
wait;
end process;
end behav;
|
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
function min(iv : invect) return entry is
begin
return iv(0);
end;
begin
process
begin
minimum <= min(invect); -- should be vec not invect
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: score_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY score_tb IS
END ENTITY;
ARCHITECTURE score_tb_ARCH OF score_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
score_synth_inst:ENTITY work.score_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- axi_vdma_sg_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sg_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator for Scatter Gather signals
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_vdma_sg_cdc is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- From Register Module (Primary Clk Domain) --
reg2cdc_run_stop : in std_logic ; --
reg2cdc_stop : in std_logic ; --
reg2cdc_taildesc_wren : in std_logic ; --
reg2cdc_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
reg2cdc_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- To Scatter Gather Engine (Secondary Clk Domain --
cdc2sg_run_stop : out std_logic ; --
cdc2sg_stop : out std_logic ; --
cdc2sg_taildesc_wren : out std_logic ; --
cdc2sg_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2sg_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- From Scatter Gather Engine (Secondary Clk Domain) --
sg2cdc_ftch_idle : in std_logic ; --
sg2cdc_ftch_interr_set : in std_logic ; --
sg2cdc_ftch_slverr_set : in std_logic ; --
sg2cdc_ftch_decerr_set : in std_logic ; --
sg2cdc_ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
sg2cdc_ftch_err : in std_logic ; --
--
-- To DMA Controller --
cdc2dmac_ftch_idle : out std_logic ; --
--
-- To Register Module --
cdc2reg_ftch_interr_set : out std_logic ; --
cdc2reg_ftch_slverr_set : out std_logic ; --
cdc2reg_ftch_decerr_set : out std_logic ; --
cdc2reg_ftch_err_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2reg_ftch_err : out std_logic --
);
end axi_vdma_sg_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sg_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg2cdc_taildesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal sg2cdc_ftch_err_addr_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal reg2cdc_curdesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Aysnchronous mode therefore instantiate clock domain crossing logic
GEN_CDC_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- CUR_DESC_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '1' ,
---- prmry_vect_in => reg2cdc_curdesc ,
---- scndry_vect_out => cdc2sg_curdesc
---- );
-- Register signal in to give clear FF output to CDC
P_IN_CUR_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_curdesc_i <= (others => '0');
else
reg2cdc_curdesc_i <= reg2cdc_curdesc;
end if;
end if;
end process P_IN_CUR_DESC;
CUR_DESC_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_curdesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_curdesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_taildesc_wren ,
---- scndry_out => cdc2sg_taildesc_wren ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- scndry_vect_out => open
---- );
TAIL_DESC_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_taildesc_wren,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_taildesc_wren,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_VECT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => reg2cdc_taildesc_wren ,
---- prmry_vect_in => reg2cdc_taildesc ,
---- scndry_vect_out => cdc2sg_taildesc
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_TAIL_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_taildesc_i <= (others => '0');
elsif(reg2cdc_taildesc_wren = '1')then
reg2cdc_taildesc_i <= reg2cdc_taildesc;
end if;
end if;
end process P_IN_TAIL_DESC;
TAIL_DESC_VECT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_taildesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_taildesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- RUNSTOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_run_stop ,
---- scndry_out => cdc2sg_run_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
RUNSTOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_run_stop,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_stop ,
---- scndry_out => cdc2sg_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_stop,
scndry_vect_out => open
);
-- From SG Engine (secondary clock domain) to
-- DMA Controller (primary clock domain)
---- FTCH_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1 ,
---- C_RESET_STATE => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_idle ,
---- prmry_out => cdc2dmac_ftch_idle ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2dmac_ftch_idle,
scndry_vect_out => open
);
--sg to reg
-- From SG Engine (secondary clock domain) to
-- Register Block (primary clock domain)
---- FTCH_INTERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_interr_set ,
---- prmry_out => cdc2reg_ftch_interr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_INTERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_interr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_interr_set,
scndry_vect_out => open
);
---- FTCH_SLVERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_slverr_set ,
---- prmry_out => cdc2reg_ftch_slverr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_SLVERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_slverr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_slverr_set,
scndry_vect_out => open
);
---- FTCH_DECERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_decerr_set ,
---- prmry_out => cdc2reg_ftch_decerr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_DECERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_decerr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_decerr_set,
scndry_vect_out => open
);
---- ERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_err ,
---- prmry_out => cdc2reg_ftch_err ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
ERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_err,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_err,
scndry_vect_out => open
);
---- ERR_VECT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => sg2cdc_ftch_err ,
---- scndry_vect_in => sg2cdc_ftch_err_addr ,
---- prmry_vect_out => cdc2reg_ftch_err_addr ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_ERR_VECT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
sg2cdc_ftch_err_addr_i <= (others => '0');
elsif(sg2cdc_ftch_err = '1')then
sg2cdc_ftch_err_addr_i <= sg2cdc_ftch_err_addr;
end if;
end if;
end process P_IN_ERR_VECT;
ERR_VECT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => '0',
prmry_vect_in => sg2cdc_ftch_err_addr_i,
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => open,
scndry_vect_out => cdc2reg_ftch_err_addr
);
end generate GEN_CDC_FOR_ASYNC;
-- Synchronous Mode therefore map inputs to associated
-- outputs directly.
GEN_NO_CDC_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
cdc2sg_run_stop <= reg2cdc_run_stop ;
cdc2sg_stop <= reg2cdc_stop ;
cdc2sg_taildesc_wren <= reg2cdc_taildesc_wren ;
cdc2sg_taildesc <= reg2cdc_taildesc ;
cdc2sg_curdesc <= reg2cdc_curdesc ;
cdc2dmac_ftch_idle <= sg2cdc_ftch_idle ;
cdc2reg_ftch_interr_set <= sg2cdc_ftch_interr_set ;
cdc2reg_ftch_slverr_set <= sg2cdc_ftch_slverr_set ;
cdc2reg_ftch_decerr_set <= sg2cdc_ftch_decerr_set ;
cdc2reg_ftch_err <= sg2cdc_ftch_err ;
cdc2reg_ftch_err_addr <= sg2cdc_ftch_err_addr ;
end generate GEN_NO_CDC_FOR_SYNC;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_sg_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sg_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator for Scatter Gather signals
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_vdma_sg_cdc is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- From Register Module (Primary Clk Domain) --
reg2cdc_run_stop : in std_logic ; --
reg2cdc_stop : in std_logic ; --
reg2cdc_taildesc_wren : in std_logic ; --
reg2cdc_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
reg2cdc_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- To Scatter Gather Engine (Secondary Clk Domain --
cdc2sg_run_stop : out std_logic ; --
cdc2sg_stop : out std_logic ; --
cdc2sg_taildesc_wren : out std_logic ; --
cdc2sg_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2sg_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- From Scatter Gather Engine (Secondary Clk Domain) --
sg2cdc_ftch_idle : in std_logic ; --
sg2cdc_ftch_interr_set : in std_logic ; --
sg2cdc_ftch_slverr_set : in std_logic ; --
sg2cdc_ftch_decerr_set : in std_logic ; --
sg2cdc_ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
sg2cdc_ftch_err : in std_logic ; --
--
-- To DMA Controller --
cdc2dmac_ftch_idle : out std_logic ; --
--
-- To Register Module --
cdc2reg_ftch_interr_set : out std_logic ; --
cdc2reg_ftch_slverr_set : out std_logic ; --
cdc2reg_ftch_decerr_set : out std_logic ; --
cdc2reg_ftch_err_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
cdc2reg_ftch_err : out std_logic --
);
end axi_vdma_sg_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sg_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg2cdc_taildesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal sg2cdc_ftch_err_addr_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
signal reg2cdc_curdesc_i : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Aysnchronous mode therefore instantiate clock domain crossing logic
GEN_CDC_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- CUR_DESC_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '1' ,
---- prmry_vect_in => reg2cdc_curdesc ,
---- scndry_vect_out => cdc2sg_curdesc
---- );
-- Register signal in to give clear FF output to CDC
P_IN_CUR_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_curdesc_i <= (others => '0');
else
reg2cdc_curdesc_i <= reg2cdc_curdesc;
end if;
end if;
end process P_IN_CUR_DESC;
CUR_DESC_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_curdesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_curdesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_taildesc_wren ,
---- scndry_out => cdc2sg_taildesc_wren ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- scndry_vect_out => open
---- );
TAIL_DESC_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_taildesc_wren,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_taildesc_wren,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- TAIL_DESC_VECT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_P_S ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT -- Not Used
---- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => reg2cdc_taildesc_wren ,
---- prmry_vect_in => reg2cdc_taildesc ,
---- scndry_vect_out => cdc2sg_taildesc
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_TAIL_DESC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
reg2cdc_taildesc_i <= (others => '0');
elsif(reg2cdc_taildesc_wren = '1')then
reg2cdc_taildesc_i <= reg2cdc_taildesc;
end if;
end if;
end process P_IN_TAIL_DESC;
TAIL_DESC_VECT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => '0',
prmry_vect_in => reg2cdc_taildesc_i,
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => open,
scndry_vect_out => cdc2sg_taildesc
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- RUNSTOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_run_stop ,
---- scndry_out => cdc2sg_run_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
RUNSTOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_run_stop,
scndry_vect_out => open
);
-- From register module (primary clock domain) to
-- scatter gather engine (secondary clock domain)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => reg2cdc_stop ,
---- scndry_out => cdc2sg_stop ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_aclk,
prmry_resetn => prmry_resetn,
prmry_in => reg2cdc_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => scndry_aclk,
scndry_resetn => scndry_resetn,
scndry_out => cdc2sg_stop,
scndry_vect_out => open
);
-- From SG Engine (secondary clock domain) to
-- DMA Controller (primary clock domain)
---- FTCH_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1 ,
---- C_RESET_STATE => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_idle ,
---- prmry_out => cdc2dmac_ftch_idle ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2dmac_ftch_idle,
scndry_vect_out => open
);
--sg to reg
-- From SG Engine (secondary clock domain) to
-- Register Block (primary clock domain)
---- FTCH_INTERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_interr_set ,
---- prmry_out => cdc2reg_ftch_interr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_INTERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_interr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_interr_set,
scndry_vect_out => open
);
---- FTCH_SLVERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_slverr_set ,
---- prmry_out => cdc2reg_ftch_slverr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_SLVERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_slverr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_slverr_set,
scndry_vect_out => open
);
---- FTCH_DECERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_decerr_set ,
---- prmry_out => cdc2reg_ftch_decerr_set ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FTCH_DECERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_decerr_set,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_decerr_set,
scndry_vect_out => open
);
---- ERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => sg2cdc_ftch_err ,
---- prmry_out => cdc2reg_ftch_err ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
ERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => sg2cdc_ftch_err,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => cdc2reg_ftch_err,
scndry_vect_out => open
);
---- ERR_VECT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_VECTR_S_P ,
---- C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => '0' , -- Not Used
---- scndry_out => open , -- Not Used
---- scndry_vect_s_h => sg2cdc_ftch_err ,
---- scndry_vect_in => sg2cdc_ftch_err_addr ,
---- prmry_vect_out => cdc2reg_ftch_err_addr ,
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(C_M_AXI_SG_ADDR_WIDTH-1 downto 0), -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
-- Register signal in to give clear FF output to CDC
P_IN_ERR_VECT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
sg2cdc_ftch_err_addr_i <= (others => '0');
elsif(sg2cdc_ftch_err = '1')then
sg2cdc_ftch_err_addr_i <= sg2cdc_ftch_err_addr;
end if;
end if;
end process P_IN_ERR_VECT;
ERR_VECT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 0, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => '0',
prmry_vect_in => sg2cdc_ftch_err_addr_i,
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => open,
scndry_vect_out => cdc2reg_ftch_err_addr
);
end generate GEN_CDC_FOR_ASYNC;
-- Synchronous Mode therefore map inputs to associated
-- outputs directly.
GEN_NO_CDC_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
cdc2sg_run_stop <= reg2cdc_run_stop ;
cdc2sg_stop <= reg2cdc_stop ;
cdc2sg_taildesc_wren <= reg2cdc_taildesc_wren ;
cdc2sg_taildesc <= reg2cdc_taildesc ;
cdc2sg_curdesc <= reg2cdc_curdesc ;
cdc2dmac_ftch_idle <= sg2cdc_ftch_idle ;
cdc2reg_ftch_interr_set <= sg2cdc_ftch_interr_set ;
cdc2reg_ftch_slverr_set <= sg2cdc_ftch_slverr_set ;
cdc2reg_ftch_decerr_set <= sg2cdc_ftch_decerr_set ;
cdc2reg_ftch_err <= sg2cdc_ftch_err ;
cdc2reg_ftch_err_addr <= sg2cdc_ftch_err_addr ;
end generate GEN_NO_CDC_FOR_SYNC;
end implementation;
|
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.tbfuncs.all;
package tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
return integer;
function CalcTRFSMConfigLength (
constant InputWidth : integer;
constant OutputWidth : integer;
constant StateWidth : integer;
constant UseResetRow : integer;
constant UseCurrentState : integer;
constant NumRows0 : integer;
constant NumRows1 : integer;
constant NumRows2 : integer;
constant NumRows3 : integer;
constant NumRows4 : integer;
constant NumRows5 : integer;
constant NumRows6 : integer;
constant NumRows7 : integer;
constant NumRows8 : integer;
constant NumRows9 : integer)
return integer;
-- InputPattern: accepts a string with a comma (',') separated list of input
-- patterns for which the transition rows should be activated. Each pattern
-- has to contain exactly TotalInputWidth characters of which up to MyInputWidth
-- are either '0' or '1', the others must be 'x'. The places of these must
-- match for all patterns.
function GenTRConfigBitStream (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer;
constant InputPattern : string; --InputPatterns_t;
constant State : std_logic_vector;
constant NextState : std_logic_vector;
constant Output : std_logic_vector)
return std_logic_vector;
end tb_trfsmpkg;
package body tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
return integer is
variable ISMplusIPG : integer;
begin
if MyInputWidth > 0 then
ISMplusIPG :=
TotalInputWidth + -- Input Switching Matrix
2**MyInputWidth; -- Input Pattern Gate
else
ISMplusIPG := 0;
end if;
return
StateWidth + -- State Selection Gate
ISMplusIPG +
StateWidth + -- Next State Register
OutputWidth; -- Output Pattern Gate
end CalcTRConfigLength;
function CalcTRFSMConfigLength (
constant InputWidth : integer;
constant OutputWidth : integer;
constant StateWidth : integer;
constant UseResetRow : integer;
constant UseCurrentState : integer;
constant NumRows0 : integer;
constant NumRows1 : integer;
constant NumRows2 : integer;
constant NumRows3 : integer;
constant NumRows4 : integer;
constant NumRows5 : integer;
constant NumRows6 : integer;
constant NumRows7 : integer;
constant NumRows8 : integer;
constant NumRows9 : integer)
return integer is
begin
return
NumRows0*CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth) +
NumRows1*CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth) +
NumRows2*CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth) +
NumRows3*CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth) +
NumRows4*CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth) +
NumRows5*CalcTRConfigLength(StateWidth,InputWidth,5,OutputWidth) +
NumRows6*CalcTRConfigLength(StateWidth,InputWidth,6,OutputWidth) +
NumRows7*CalcTRConfigLength(StateWidth,InputWidth,7,OutputWidth) +
NumRows8*CalcTRConfigLength(StateWidth,InputWidth,8,OutputWidth) +
NumRows9*CalcTRConfigLength(StateWidth,InputWidth,9,OutputWidth);
end CalcTRFSMConfigLength;
function GenTRConfigBitStream (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer;
constant InputPattern : string;
constant State : std_logic_vector;
constant NextState : std_logic_vector;
constant Output : std_logic_vector
) return std_logic_vector is
variable CfgOurState : std_logic_vector(StateWidth-1 downto 0);
variable CfgInputSelect : std_logic_vector(TotalInputWidth-1 downto 0);
variable CfgInputPattern : std_logic_vector(2**MyInputWidth-1 downto 0);
variable CfgNextState : std_logic_vector(StateWidth-1 downto 0);
variable CfgOutput : std_logic_vector(OutputWidth-1 downto 0);
variable InputPatternCondensed : std_logic_vector(MyInputWidth-1 downto 0);
variable IPGInputIdx : integer;
variable PatternIdx : integer;
variable Inverted : boolean;
begin
assert false report "GenTRConfigBitStream: InputPattern = " & InputPattern & ", State = " & Vector2String(State) & ", NextState = " & Vector2String(NextState) & ", Output = " & Vector2String(Output) severity note;
CfgOurState := State;
CfgInputPattern := (others => '0');
CfgInputSelect := (others => '0');
if (InputPattern'length > 0) and (InputPattern(1) = '!') then
Inverted := true;
PatternIdx := 2;
else
Inverted := false;
PatternIdx := 1;
end if;
while InputPattern'length >= PatternIdx loop -- should be "true" but we spare the "if InputPattern'length > 0 then" around this loop
IPGInputIdx := MyInputWidth-1;
InputPatternCondensed := (others => '0'); -- fill with zeros because if we have an unused input, it will be 0 from the ISM
for ISMInputIdx in TotalInputWidth-1 downto 0 loop
if InputPattern(PatternIdx) /= 'x' then
-- enable this output for the ISM
CfgInputSelect(ISMInputIdx) := '1';
-- correct IPGInputIdx if we select an input at the right end where we can spare switches
if (ISMInputIdx < (MyInputWidth-1)) and (IPGInputIdx > ISMInputIdx) then
IPGInputIdx := ISMInputIdx;
end if;
-- copy this state to the IPG input pattern
case InputPattern(PatternIdx) is
when '0' => InputPatternCondensed(IPGInputIdx) := '0';
when '1' => InputPatternCondensed(IPGInputIdx) := '1';
when others => assert false report "Invalid input character " & InputPattern(ISMInputIdx) & " at " & integer'image(PatternIdx) severity failure;
end case;
IPGInputIdx := IPGInputIdx - 1;
-- ensure that we have at most MyInputWidth '0's and '1's
assert IPGInputIdx >= -1 report "Input pattern has too many sensitive bits at " & integer'image(PatternIdx) severity failure;
end if;
PatternIdx := PatternIdx + 1;
end loop; -- ISMInputIdx
assert false report "Condensed = " & Vector2String(InputPatternCondensed) severity note;
assert false report "PatternIdx = " & integer'image(PatternIdx) severity note;
CfgInputPattern(conv_integer(InputPatternCondensed)) := '1';
if PatternIdx >= InputPattern'length then
exit; -- leave this loop
end if;
assert InputPattern(PatternIdx) = ',' report "Invalid character '" & InputPattern(PatternIdx) & "' in InputPattern at " & integer'image(PatternIdx) severity failure;
PatternIdx := PatternIdx + 1;
end loop;
if Inverted then
CfgInputPattern := not CfgInputPattern;
end if;
CfgNextState := NextState;
CfgOutput := Output;
-- special case: MyInputWidth = 0
if MyInputWidth = 0 then
return
CfgOurState &
CfgNextState &
CfgOutput;
end if;
-- general case: MyInputWidth > 0
assert false report "CfgInputSelect = " & Vector2String(CfgInputSelect) severity note;
assert false report "CfgInputPattern = " & Vector2String(CfgInputPattern) severity note;
return
CfgOurState &
CfgInputSelect &
CfgInputPattern &
CfgNextState &
CfgOutput;
end GenTRConfigBitStream;
end tb_trfsmpkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.tbfuncs.all;
package tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
return integer;
function CalcTRFSMConfigLength (
constant InputWidth : integer;
constant OutputWidth : integer;
constant StateWidth : integer;
constant UseResetRow : integer;
constant UseCurrentState : integer;
constant NumRows0 : integer;
constant NumRows1 : integer;
constant NumRows2 : integer;
constant NumRows3 : integer;
constant NumRows4 : integer;
constant NumRows5 : integer;
constant NumRows6 : integer;
constant NumRows7 : integer;
constant NumRows8 : integer;
constant NumRows9 : integer)
return integer;
-- InputPattern: accepts a string with a comma (',') separated list of input
-- patterns for which the transition rows should be activated. Each pattern
-- has to contain exactly TotalInputWidth characters of which up to MyInputWidth
-- are either '0' or '1', the others must be 'x'. The places of these must
-- match for all patterns.
function GenTRConfigBitStream (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer;
constant InputPattern : string; --InputPatterns_t;
constant State : std_logic_vector;
constant NextState : std_logic_vector;
constant Output : std_logic_vector)
return std_logic_vector;
end tb_trfsmpkg;
package body tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
return integer is
variable ISMplusIPG : integer;
begin
if MyInputWidth > 0 then
ISMplusIPG :=
TotalInputWidth + -- Input Switching Matrix
2**MyInputWidth; -- Input Pattern Gate
else
ISMplusIPG := 0;
end if;
return
StateWidth + -- State Selection Gate
ISMplusIPG +
StateWidth + -- Next State Register
OutputWidth; -- Output Pattern Gate
end CalcTRConfigLength;
function CalcTRFSMConfigLength (
constant InputWidth : integer;
constant OutputWidth : integer;
constant StateWidth : integer;
constant UseResetRow : integer;
constant UseCurrentState : integer;
constant NumRows0 : integer;
constant NumRows1 : integer;
constant NumRows2 : integer;
constant NumRows3 : integer;
constant NumRows4 : integer;
constant NumRows5 : integer;
constant NumRows6 : integer;
constant NumRows7 : integer;
constant NumRows8 : integer;
constant NumRows9 : integer)
return integer is
begin
return
NumRows0*CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth) +
NumRows1*CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth) +
NumRows2*CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth) +
NumRows3*CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth) +
NumRows4*CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth) +
NumRows5*CalcTRConfigLength(StateWidth,InputWidth,5,OutputWidth) +
NumRows6*CalcTRConfigLength(StateWidth,InputWidth,6,OutputWidth) +
NumRows7*CalcTRConfigLength(StateWidth,InputWidth,7,OutputWidth) +
NumRows8*CalcTRConfigLength(StateWidth,InputWidth,8,OutputWidth) +
NumRows9*CalcTRConfigLength(StateWidth,InputWidth,9,OutputWidth);
end CalcTRFSMConfigLength;
function GenTRConfigBitStream (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer;
constant InputPattern : string;
constant State : std_logic_vector;
constant NextState : std_logic_vector;
constant Output : std_logic_vector
) return std_logic_vector is
variable CfgOurState : std_logic_vector(StateWidth-1 downto 0);
variable CfgInputSelect : std_logic_vector(TotalInputWidth-1 downto 0);
variable CfgInputPattern : std_logic_vector(2**MyInputWidth-1 downto 0);
variable CfgNextState : std_logic_vector(StateWidth-1 downto 0);
variable CfgOutput : std_logic_vector(OutputWidth-1 downto 0);
variable InputPatternCondensed : std_logic_vector(MyInputWidth-1 downto 0);
variable IPGInputIdx : integer;
variable PatternIdx : integer;
variable Inverted : boolean;
begin
assert false report "GenTRConfigBitStream: InputPattern = " & InputPattern & ", State = " & Vector2String(State) & ", NextState = " & Vector2String(NextState) & ", Output = " & Vector2String(Output) severity note;
CfgOurState := State;
CfgInputPattern := (others => '0');
CfgInputSelect := (others => '0');
if (InputPattern'length > 0) and (InputPattern(1) = '!') then
Inverted := true;
PatternIdx := 2;
else
Inverted := false;
PatternIdx := 1;
end if;
while InputPattern'length >= PatternIdx loop -- should be "true" but we spare the "if InputPattern'length > 0 then" around this loop
IPGInputIdx := MyInputWidth-1;
InputPatternCondensed := (others => '0'); -- fill with zeros because if we have an unused input, it will be 0 from the ISM
for ISMInputIdx in TotalInputWidth-1 downto 0 loop
if InputPattern(PatternIdx) /= 'x' then
-- enable this output for the ISM
CfgInputSelect(ISMInputIdx) := '1';
-- correct IPGInputIdx if we select an input at the right end where we can spare switches
if (ISMInputIdx < (MyInputWidth-1)) and (IPGInputIdx > ISMInputIdx) then
IPGInputIdx := ISMInputIdx;
end if;
-- copy this state to the IPG input pattern
case InputPattern(PatternIdx) is
when '0' => InputPatternCondensed(IPGInputIdx) := '0';
when '1' => InputPatternCondensed(IPGInputIdx) := '1';
when others => assert false report "Invalid input character " & InputPattern(ISMInputIdx) & " at " & integer'image(PatternIdx) severity failure;
end case;
IPGInputIdx := IPGInputIdx - 1;
-- ensure that we have at most MyInputWidth '0's and '1's
assert IPGInputIdx >= -1 report "Input pattern has too many sensitive bits at " & integer'image(PatternIdx) severity failure;
end if;
PatternIdx := PatternIdx + 1;
end loop; -- ISMInputIdx
assert false report "Condensed = " & Vector2String(InputPatternCondensed) severity note;
assert false report "PatternIdx = " & integer'image(PatternIdx) severity note;
CfgInputPattern(conv_integer(InputPatternCondensed)) := '1';
if PatternIdx >= InputPattern'length then
exit; -- leave this loop
end if;
assert InputPattern(PatternIdx) = ',' report "Invalid character '" & InputPattern(PatternIdx) & "' in InputPattern at " & integer'image(PatternIdx) severity failure;
PatternIdx := PatternIdx + 1;
end loop;
if Inverted then
CfgInputPattern := not CfgInputPattern;
end if;
CfgNextState := NextState;
CfgOutput := Output;
-- special case: MyInputWidth = 0
if MyInputWidth = 0 then
return
CfgOurState &
CfgNextState &
CfgOutput;
end if;
-- general case: MyInputWidth > 0
assert false report "CfgInputSelect = " & Vector2String(CfgInputSelect) severity note;
assert false report "CfgInputPattern = " & Vector2String(CfgInputPattern) severity note;
return
CfgOurState &
CfgInputSelect &
CfgInputPattern &
CfgNextState &
CfgOutput;
end GenTRConfigBitStream;
end tb_trfsmpkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.VHDL_lib.all;
entity mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end mux;
architecture arch of mux is
signal y : std_logic_vector(size-1 downto 0);
signal z : std_logic_vector( ( size * (s'length+1) ) -1 downto 0);
component or_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component and_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
begin
ORX: or_gate generic map(width=>size) port map(y,output);
GEN_REG:
for I in 0 to size-1 generate
z(I*(s'length+1)+s'length downto I*(s'length+1)) <= (s xor std_logic_vector(to_unsigned(I,s'length))) & input(size-1-I);
REGX : and_gate generic map(width=> s'length+1 ) port map ( z(I*(s'length+1)+s'length downto I*(s'length+1)) ,y(I) );
end generate ;
end arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
library sys;
use sys.sys_pkg.all;
use work.uart_pkg.all;
entity uart is
generic (
base_paddr : sys_paddr_type;
ifilename : string := "uartin";
ofilename : string := "uartout"
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
sys_master_ctrl_out : in sys_master_ctrl_out_type;
sys_master_dp_out : in sys_master_dp_out_type;
sys_slave_ctrl_out : out sys_master_ctrl_out_type;
sys_slave_dp_out : out sys_master_dp_out_type
);
end;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Add-compare-select unit for trellis processing.
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details The ACS decides which path is the the surviving trellis path.
--! In the design there are 2^{K-1} ACS instances.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_helper.all;
entity acs is
generic(
-- Reset value
INITIALIZE_VALUE : in signed(BW_MAX_PROBABILITY - 1 downto 0)
);
port(
clk : in std_logic;
rst : in std_logic;
--
-- Values from branch distance, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inbranch_tvalid : in std_logic;
s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tlast : in std_logic;
s_axis_inbranch_tready : out std_logic;
--
-- Probabilities from previous nodes, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inprev_tvalid : in std_logic;
s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tready : out std_logic;
-- probability result of the add compare and select
m_axis_outprob_tvalid : out std_logic;
m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
m_axis_outprob_tready : in std_logic;
-- decision result of the add compare and select
m_axis_outdec_tvalid : out std_logic;
m_axis_outdec_tdata : out std_logic;
m_axis_outdec_tlast : out std_logic;
m_axis_outdec_tready : in std_logic
);
end entity acs;
architecture rtl of acs is
signal s_axis_inbranch_tlast_d : std_logic;
signal m_axis_outdec_tvalid_int : std_logic;
signal s_axis_inbranch_tready_int : std_logic;
begin
s_axis_inbranch_tready_int <= '1' when m_axis_outdec_tready = '1' or m_axis_outdec_tvalid_int = '0' else
'0';
s_axis_inbranch_tready <= s_axis_inbranch_tready_int;
m_axis_outdec_tvalid <= m_axis_outdec_tvalid_int;
-- Add branch to previous, compare both paths and select survivor.
pr_add_compare : process(clk) is
variable v_diff, v_high, v_low : signed(BW_MAX_PROBABILITY - 1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
m_axis_outdec_tvalid_int <= '0';
m_axis_outdec_tdata <= '0';
m_axis_outdec_tlast <= '0';
m_axis_outprob_tvalid <= '0';
s_axis_inprev_tready <= '0';
s_axis_inbranch_tlast_d <= '0';
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
else
-- If this is the last value, prepare for processing of next incoming value.
if s_axis_inbranch_tlast_d = '1' then
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
s_axis_inbranch_tlast_d <= '0';
m_axis_outdec_tvalid_int <= '0';
end if;
if m_axis_outdec_tvalid_int = '1' and m_axis_outdec_tready = '1' then
m_axis_outdec_tvalid_int <= '0';
end if;
-- Process only if we receive valid data.
if s_axis_inbranch_tvalid = '1' and s_axis_inbranch_tready_int = '1' then
s_axis_inbranch_tlast_d <= s_axis_inbranch_tlast;
-- Add.
v_low := signed(s_axis_inbranch_tdata_low) + signed(s_axis_inprev_tdata_low);
v_high := signed(s_axis_inbranch_tdata_high) + signed(s_axis_inprev_tdata_high);
-- Use modulo normalization, do not extend the sign here!
v_diff := v_low - v_high;
-- Compare, select the correct path.
if v_diff < 0 then
m_axis_outdec_tdata <= '1';
m_axis_outprob_tdata <= std_logic_vector(v_high);
else
m_axis_outdec_tdata <= '0';
m_axis_outprob_tdata <= std_logic_vector(v_low);
end if;
m_axis_outdec_tvalid_int <= '1';
end if;
m_axis_outdec_tlast <= s_axis_inbranch_tlast;
end if;
end if;
end process pr_add_compare;
end architecture rtl;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Add-compare-select unit for trellis processing.
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details The ACS decides which path is the the surviving trellis path.
--! In the design there are 2^{K-1} ACS instances.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_helper.all;
entity acs is
generic(
-- Reset value
INITIALIZE_VALUE : in signed(BW_MAX_PROBABILITY - 1 downto 0)
);
port(
clk : in std_logic;
rst : in std_logic;
--
-- Values from branch distance, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inbranch_tvalid : in std_logic;
s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tlast : in std_logic;
s_axis_inbranch_tready : out std_logic;
--
-- Probabilities from previous nodes, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inprev_tvalid : in std_logic;
s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tready : out std_logic;
-- probability result of the add compare and select
m_axis_outprob_tvalid : out std_logic;
m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
m_axis_outprob_tready : in std_logic;
-- decision result of the add compare and select
m_axis_outdec_tvalid : out std_logic;
m_axis_outdec_tdata : out std_logic;
m_axis_outdec_tlast : out std_logic;
m_axis_outdec_tready : in std_logic
);
end entity acs;
architecture rtl of acs is
signal s_axis_inbranch_tlast_d : std_logic;
signal m_axis_outdec_tvalid_int : std_logic;
signal s_axis_inbranch_tready_int : std_logic;
begin
s_axis_inbranch_tready_int <= '1' when m_axis_outdec_tready = '1' or m_axis_outdec_tvalid_int = '0' else
'0';
s_axis_inbranch_tready <= s_axis_inbranch_tready_int;
m_axis_outdec_tvalid <= m_axis_outdec_tvalid_int;
-- Add branch to previous, compare both paths and select survivor.
pr_add_compare : process(clk) is
variable v_diff, v_high, v_low : signed(BW_MAX_PROBABILITY - 1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
m_axis_outdec_tvalid_int <= '0';
m_axis_outdec_tdata <= '0';
m_axis_outdec_tlast <= '0';
m_axis_outprob_tvalid <= '0';
s_axis_inprev_tready <= '0';
s_axis_inbranch_tlast_d <= '0';
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
else
-- If this is the last value, prepare for processing of next incoming value.
if s_axis_inbranch_tlast_d = '1' then
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
s_axis_inbranch_tlast_d <= '0';
m_axis_outdec_tvalid_int <= '0';
end if;
if m_axis_outdec_tvalid_int = '1' and m_axis_outdec_tready = '1' then
m_axis_outdec_tvalid_int <= '0';
end if;
-- Process only if we receive valid data.
if s_axis_inbranch_tvalid = '1' and s_axis_inbranch_tready_int = '1' then
s_axis_inbranch_tlast_d <= s_axis_inbranch_tlast;
-- Add.
v_low := signed(s_axis_inbranch_tdata_low) + signed(s_axis_inprev_tdata_low);
v_high := signed(s_axis_inbranch_tdata_high) + signed(s_axis_inprev_tdata_high);
-- Use modulo normalization, do not extend the sign here!
v_diff := v_low - v_high;
-- Compare, select the correct path.
if v_diff < 0 then
m_axis_outdec_tdata <= '1';
m_axis_outprob_tdata <= std_logic_vector(v_high);
else
m_axis_outdec_tdata <= '0';
m_axis_outprob_tdata <= std_logic_vector(v_low);
end if;
m_axis_outdec_tvalid_int <= '1';
end if;
m_axis_outdec_tlast <= s_axis_inbranch_tlast;
end if;
end if;
end process pr_add_compare;
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Module Name: top_level - Behavioral
--
-- Description: Top level of my DisplayPort design.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email (hamster@snap.net.nz)?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-29 | Updated for Opsis
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top_level is
port (
clk100 : in std_logic;
debug : out std_logic_vector(7 downto 0) := (others => '0');
------------------------------
gtptxp : out std_logic_vector(1 downto 0);
gtptxn : out std_logic_vector(1 downto 0);
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end top_level;
architecture Behavioral of top_level is
constant use_hw_8b10b_support : std_logic := '1'; -- Note HW 8b/10b not yet working for SPartan 6
COMPONENT channel_management
PORT(
clk100 : IN std_logic;
debug : out std_logic_vector(7 downto 0);
hpd : IN std_logic;
stream_channel_count : IN std_logic_vector(2 downto 0);
source_channel_count : IN std_logic_vector(2 downto 0);
tx_clock_train : out std_logic;
tx_align_train : out std_logic;
tx_running : IN std_logic_vector(3 downto 0);
aux_tx_p : INOUT std_logic;
aux_tx_n : INOUT std_logic;
aux_rx_p : INOUT std_logic;
aux_rx_n : INOUT std_logic;
tx_powerup_channel : OUT std_logic_vector(3 downto 0);
tx_preemp_0p0 : OUT std_logic;
tx_preemp_3p5 : OUT std_logic;
tx_preemp_6p0 : OUT std_logic;
tx_swing_0p4 : OUT std_logic;
tx_swing_0p6 : OUT std_logic;
tx_swing_0p8 : OUT std_logic;
tx_link_established : OUT std_logic
);
END COMPONENT;
component test_source is
port (
clk : in std_logic;
stream_channel_count : out std_logic_vector(2 downto 0);
ready : out std_logic;
data : out std_logic_vector(72 downto 0)
);
end component;
COMPONENT main_stream_processing
generic( use_hw_8b10b_support : std_logic);
PORT(
symbol_clk : IN std_logic;
tx_link_established : IN std_logic;
source_ready : IN std_logic;
tx_clock_train : IN std_logic;
tx_align_train : IN std_logic;
in_data : IN std_logic_vector(72 downto 0);
tx_symbols : OUT std_logic_vector(79 downto 0)
);
END COMPONENT;
component Transceiver is
generic( use_hw_8b10b_support : std_logic);
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC_vector;
debug : out std_logic_vector(7 downto 0);
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC_vector;
symbolclk : out STD_LOGIC;
in_symbols : in std_logic_vector(79 downto 0);
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtptxp : out std_logic_vector(1 downto 0);
gtptxn : out std_logic_vector(1 downto 0));
end component;
component video_generator is
Port ( clk : in STD_LOGIC;
h_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
h_front_len : in std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
v_front_len : in std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
vid_blank : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vsync : out STD_LOGIC);
end component;
--------------------------------------------------------------------------
signal tx_powerup : std_logic := '0';
signal tx_clock_train : std_logic := '0';
signal tx_align_train : std_logic := '0';
---------------------------------------------
-- Transceiver signals
---------------------------------------------
signal txresetdone : std_logic := '0';
signal txoutclk : std_logic := '0';
signal symbolclk : std_logic := '0';
signal tx_running : std_logic_vector(3 downto 0) := (others => '0');
signal tx_powerup_channel : std_logic_vector(3 downto 0);
signal tx_preemp_0p0 : std_logic := '1';
signal tx_preemp_3p5 : STD_LOGIC := '0';
signal tx_preemp_6p0 : STD_LOGIC := '0';
signal tx_swing_0p4 : STD_LOGIC := '1';
signal tx_swing_0p6 : STD_LOGIC := '0';
signal tx_swing_0p8 : STD_LOGIC := '0';
------------------------------------------------
signal tx_link_established : std_logic := '0';
------------------------------------------------
signal tx_debug : std_logic_vector(7 downto 0);
signal mgmt_debug:std_logic_vector(7 downto 0);
constant source_channel_count : std_logic_vector(2 downto 0) := "010";
signal stream_channel_count : std_logic_vector(2 downto 0) := "000";
signal test_signal_ready : std_logic;
signal msa_merged_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal tx_symbols : std_logic_vector(79 downto 0) := (others => '0');
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
begin
i_channel_management: channel_management PORT MAP(
clk100 => clk100,
debug => mgmt_debug,
hpd => dp_tx_hp_detect,
aux_tx_p => dp_tx_aux_p,
aux_tx_n => dp_tx_aux_n,
aux_rx_p => dp_rx_aux_p,
aux_rx_n => dp_rx_aux_n,
stream_channel_count => stream_channel_count,
source_channel_count => source_channel_count,
tx_clock_train => tx_clock_train,
tx_align_train => tx_align_train,
tx_powerup_channel => tx_powerup_channel,
tx_preemp_0p0 => tx_preemp_0p0,
tx_preemp_3p5 => tx_preemp_3p5,
tx_preemp_6p0 => tx_preemp_6p0,
tx_swing_0p4 => tx_swing_0p4,
tx_swing_0p6 => tx_swing_0p6,
tx_swing_0p8 => tx_swing_0p8,
tx_running => tx_running,
tx_link_established => tx_link_established
);
i_test_source: test_source port map (
clk => symbolclk,
stream_channel_count => stream_channel_count,
ready => test_signal_ready,
data => msa_merged_data
);
----------------------------------------------------------------------
Inst_main_stream_processing: main_stream_processing generic map (
use_hw_8b10b_support => use_hw_8b10b_support
) PORT MAP(
symbol_clk => symbolclk,
tx_link_established => tx_link_established,
source_ready => test_signal_ready,
tx_clock_train => tx_clock_train,
tx_align_train => tx_align_train,
in_data => msa_merged_data,
tx_symbols => tx_symbols
);
i_tx0: Transceiver generic map (
use_hw_8b10b_support => use_hw_8b10b_support
) Port map (
mgmt_clk => clk100,
powerup_channel => tx_powerup_channel,
tx_running => tx_running,
debug => tx_debug,
preemp_0p0 => tx_preemp_0p0,
preemp_3p5 => tx_preemp_3p5,
preemp_6p0 => tx_preemp_6p0,
swing_0p4 => tx_swing_0p4,
swing_0p6 => tx_swing_0p6,
swing_0p8 => tx_swing_0p8,
in_symbols => tx_symbols,
gtptxp => gtptxp,
gtptxn => gtptxn,
symbolclk => symbolclk,
refclk0_p => refclk0_p,
refclk0_n => refclk0_n,
refclk1_p => refclk1_p,
refclk1_n => refclk1_n);
-- debug(0) <= tx_link_established;
debug(0) <= mgmt_debug(0);
-- debug(0) <= tx_clock_train;
--process(symbolclk)
-- begin
--
-- -- SHow the HBLANK as a debug of the video stream.
-- if rising_edge(symbolclk) then
-- -- Look for BS symbols
-- if sr_inserted_data(8 downto 0) = "110111100" or sr_inserted_data(17 downto 9) = "110111100" then
-- debug(0) <= toggle and tx_link_established; --'1';
-- toggle <= not toggle;
-- end if;
-- -- Look for BE symbols
-- if sr_inserted_data(8 downto 0) = "111111011" or sr_inserted_data(17 downto 9) = "111111011" then
-- debug(0) <= toggle and tx_link_established; --'0';
-- toggle <= not toggle;
-- end if;
-- end if;
-- end process;
--process(gclk)
-- begin
-- if rising_edge(gclk) then
-- count <= count + 1;
-- case count(10 downto 8) is
-- when "000" => debug(0) <= not count(7);
-- when "001" => debug(0) <= tx_debug(0);
-- when "010" => debug(0) <= tx_debug(1);
-- when "011" => debug(0) <= tx_debug(2);
-- when "100" => debug(0) <= tx_debug(3);
-- when "101" => debug(0) <= tx_debug(4);
-- when "110" => debug(0) <= tx_debug(5);
-- when others => debug(0) <= tx_debug(6);
-- end case;
-- end if;
-- end process;
end Behavioral;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mem_ctrl_pkg is
type MCCmdType is (
MC_NOP,
MC_RD,
MC_WR,
MC_REF
);
component mem_ctrl is
generic (
INIT_COUNT : unsigned(12 downto 0); -- cycles to wait during initialisation
REFRESH_DELAY : unsigned(12 downto 0); -- gap between refresh cycles
REFRESH_LENGTH : unsigned(12 downto 0) -- length of a refresh cycle
);
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- Client interface
mcAutoMode_in : in std_logic;
mcCmd_in : in MCCmdType;
mcAddr_in : in std_logic_vector(22 downto 0);
mcData_in : in std_logic_vector(15 downto 0);
mcData_out : out std_logic_vector(15 downto 0);
mcRDV_out : out std_logic;
mcReady_out : out std_logic;
-- SDRAM interface
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end component;
end package;
|
------------------------------------------------------------------------------
-- Title : Trigger to Tag generator
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2019-04-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Generates a tag given a trigger
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trigger2tag is
generic (
g_delay_width : natural := 9;
g_tag_size : natural := 1
);
port (
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic;
-- Pulse programmable delay
pulse_dly_i : in std_logic_vector(g_delay_width-1 downto 0);
-- Pulse input
pulse_i : in std_logic;
-- Output counter
tag_o : out std_logic
);
end trigger2tag;
architecture rtl of trigger2tag is
signal square : std_logic;
signal tag_dly : std_logic;
signal tag_out : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of tag_out : signal is "no";
attribute keep : string;
attribute keep of tag_out : signal is "true";
component gc_shiftreg
generic (
g_size : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector
);
end component;
component pulse2square
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear square
clr_i : in std_logic;
-- square output
square_o : out std_logic
);
end component;
begin
cmp_tbt_tag_generate : pulse2square
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
-- Pulse input
pulse_i => pulse_i,
-- Clear square
clr_i => '0',
-- square output
square_o => square
);
cmp_gc_shiftreg: gc_shiftreg
generic map (
g_size => 2**g_delay_width
)
port map (
clk_i => fs_clk_i,
en_i => '1',
d_i => square,
q_o => tag_dly,
a_i => pulse_dly_i
);
-- Additional ff for timing
p_output_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
tag_out <= '0';
else
tag_out <= tag_dly;
end if;
end if;
end process;
tag_o <= tag_out;
end rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
begin
alt_dspbuilder_delay_GNHYCSAEGT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_0: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNUECIBFDH_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_1: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
begin
alt_dspbuilder_delay_GNHYCSAEGT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_0: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNUECIBFDH_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_1: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal x_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 1
signal y_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 2
--Outputs
signal x_out : std_logic_vector(31 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
x_in => x_in,
y_in => y_in,
x_out => x_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
x_in <= X"CAFECAFE";
y_in <= x"FACEFACE";
wait for clk_period;
assert x_out = X"30303030"
report "GAMMA ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal x_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 1
signal y_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 2
--Outputs
signal x_out : std_logic_vector(31 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
x_in => x_in,
y_in => y_in,
x_out => x_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
x_in <= X"CAFECAFE";
y_in <= x"FACEFACE";
wait for clk_period;
assert x_out = X"30303030"
report "GAMMA ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal x_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 1
signal y_in : std_logic_vector(31 downto 0) := (others => '0'); -- input 2
--Outputs
signal x_out : std_logic_vector(31 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
x_in => x_in,
y_in => y_in,
x_out => x_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
x_in <= X"CAFECAFE";
y_in <= x"FACEFACE";
wait for clk_period;
assert x_out = X"30303030"
report "GAMMA ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
--
-- Written by Ryan Kim, Digilent Inc.
-- Modified by Michael Mattioli
--
-- Description: Runs the initialization sequence for the OLED display.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity oled_init is
port ( clk : in std_logic; -- System clock
rst : in std_logic; -- Global synchronous reset
en : in std_logic; -- Block enable pin
sdout : out std_logic; -- SPI data out
oled_sclk : out std_logic; -- SPI clock
oled_dc : out std_logic; -- Data/Command pin
oled_res : out std_logic; -- OLED reset
oled_vbat : out std_logic; -- oled_vbat enable
oled_vdd : out std_logic; -- oled_vdd enable
fin : out std_logic); -- Finish flag for block
end oled_init;
architecture behavioral of oled_init is
component spi_ctrl
port ( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
sdata : in std_logic_vector (7 downto 0);
sdout : out std_logic;
oled_sclk : out std_logic;
fin : out std_logic);
end component;
component delay
port ( clk : in std_logic;
rst : in std_logic;
delay_ms : in std_logic_vector (11 downto 0);
delay_en : in std_logic;
delay_fin : out std_logic);
end component;
type states is (Transition1,
Transition2,
Transition3,
Transition4,
Transition5,
Idle,
VddOn,
Wait1,
DispOff,
ResetOn,
Wait2,
ResetOff,
ChargePump1,
ChargePump2,
PreCharge1,
PreCharge2,
VbatOn,
Wait3,
DispContrast1,
DispContrast2,
InvertDisp1,
InvertDisp2,
ComConfig1,
ComConfig2,
DispOn,
FullDisp,
Done);
signal current_state : states := Idle;
signal after_state : states := Idle;
signal temp_dc : std_logic := '0';
signal temp_res : std_logic := '1';
signal temp_vbat : std_logic := '1';
signal temp_vdd : std_logic := '1';
signal temp_fin : std_logic := '0';
signal temp_delay_ms : std_logic_vector (11 downto 0) := (others => '0');
signal temp_delay_en : std_logic := '0';
signal temp_delay_fin : std_logic;
signal temp_spi_en : std_logic := '0';
signal temp_sdata : std_logic_vector (7 downto 0) := (others => '0');
signal temp_spi_fin : std_logic;
begin
spi_comp: spi_ctrl port map ( clk => clk,
rst => rst,
en => temp_spi_en,
sdata => temp_sdata,
sdout => sdout,
oled_sclk => oled_sclk,
fin => temp_spi_fin);
delay_comp: delay port map (clk => clk,
rst => rst,
delay_ms => temp_delay_ms,
delay_en => temp_delay_en,
delay_fin => temp_delay_fin);
oled_dc <= temp_dc;
oled_res <= temp_res;
oled_vbat <= temp_vbat;
oled_vdd <= temp_vdd;
fin <= temp_fin;
-- Delay 100 ms after VbatOn
temp_delay_ms <= "000001100100" when after_state = DispContrast1 else -- 100ms
"000000000001"; -- 1ms
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
current_state <= Idle;
temp_res <= '0';
else
temp_res <= '1';
case current_state is
when Idle =>
if en = '1' then
temp_dc <= '0';
current_state <= VddOn;
end if;
-- Initialization Sequence
-- This should be done everytime the OLED display is started
when VddOn =>
temp_vdd <= '0';
current_state <= Wait1;
when Wait1 =>
after_state <= DispOff;
current_state <= Transition3;
when DispOff =>
temp_sdata <= "10101110"; -- 0xAE
after_state <= ResetOn;
current_state <= Transition1;
when ResetOn =>
temp_res <= '0';
current_state <= Wait2;
when Wait2 =>
after_state <= ResetOff;
current_state <= Transition3;
when ResetOff =>
temp_res <= '1';
after_state <= ChargePump1;
current_state <= Transition3;
when ChargePump1 =>
temp_sdata <= "10001101"; -- 0x8D
after_state <= ChargePump2;
current_state <= Transition1;
when ChargePump2 =>
temp_sdata <= "00010100"; -- 0x14
after_state <= PreCharge1;
current_state <= Transition1;
when PreCharge1 =>
temp_sdata <= "11011001"; -- 0xD9
after_state <= PreCharge2;
current_state <= Transition1;
when PreCharge2 =>
temp_sdata <= "11110001"; -- 0xF1
after_state <= VbatOn;
current_state <= Transition1;
when VbatOn =>
temp_vbat <= '0';
current_state <= Wait3;
when Wait3 =>
after_state <= DispContrast1;
current_state <= Transition3;
when DispContrast1=>
temp_sdata <= "10000001"; -- 0x81
after_state <= DispContrast2;
current_state <= Transition1;
when DispContrast2=>
temp_sdata <= "00001111"; -- 0x0F
after_state <= InvertDisp1;
current_state <= Transition1;
when InvertDisp1 =>
temp_sdata <= "10100000"; -- 0xA0
after_state <= InvertDisp2;
current_state <= Transition1;
when InvertDisp2 =>
temp_sdata <= "11000000"; -- 0xC0
after_state <= ComConfig1;
current_state <= Transition1;
when ComConfig1 =>
temp_sdata <= "11011010"; -- 0xDA
after_state <= ComConfig2;
current_state <= Transition1;
when ComConfig2 =>
temp_sdata <= "00000000"; -- 0x00
after_state <= DispOn;
current_state <= Transition1;
when DispOn =>
temp_sdata <= "10101111"; -- 0xAF
after_state <= Done;
current_state <= Transition1;
-- End Initialization sequence
-- Used for debugging, turns the entire screen on regardless of memory
when FullDisp =>
temp_sdata <= "10100101"; -- 0xA5
after_state <= Done;
current_state <= Transition1;
-- Done state
when Done =>
if en = '0' then
temp_fin <= '0';
current_state <= Idle;
else
temp_fin <= '1';
end if;
-- SPI transitions
-- 1. Set en to 1
-- 2. Waits for spi_ctrl to finish
-- 3. Goes to clear state (Transition5)
when Transition1 =>
temp_spi_en <= '1';
current_state <= Transition2;
when Transition2 =>
if temp_spi_fin = '1' then
current_state <= Transition5;
end if;
-- End SPI transitions
-- Delay transitions
-- 1. Set delay_en to 1
-- 2. Waits for delay to finish
-- 3. Goes to Clear state (Transition5)
when Transition3 =>
temp_delay_en <= '1';
current_state <= Transition4;
when Transition4 =>
if temp_delay_fin = '1' then
current_state <= Transition5;
end if;
-- End delay transitions
-- Clear transitions
-- 1. Sets both delay_en and en to 0
-- 2. Go to after state
when Transition5 =>
temp_spi_en <= '0';
temp_delay_en <= '0';
current_state <= after_state;
-- End Clear transitions
when others =>
current_state <= Idle;
end case;
end if;
end if;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal rec : AbstractMmRecType(
writedata(31 downto 0),
readdata(31 downto 0),
address(4 downto 0),
byteen(3 downto 0)
);
begin
end architecture TB;
|
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