content stringlengths 1 1.04M ⌀ |
|---|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualiza... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualiza... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualiza... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos_4bits is
PORT (
entrada: IN STD_LOGIC_VECTOR(3 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos_4bits;
architecture Behavioral of siete_segmentos_4bits is
begin
visualiza... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Trigger logic core
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
-- # Adress Map:
-- #
-- # 0x0 - Trigger mask [3:0] ext, [4] eudet... |
entity tb_case01 is
end tb_case01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_case01 is
signal a : std_logic_vector (1 downto 0);
signal o : std_logic_vector (1 downto 0);
signal clk : std_logic;
begin
dut: entity work.case01
port map (a, clk, o);
process
procedure pulse is... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- $Id: sys_tst_rlink_cuff_atlys.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eit... |
architecture RTL of FIFO is
procedure average_samples;
begin
average_samples;
PROC1 : process () is
begin
average_samples;
average_samples;
average_samples;
end process;
end architecture RTL;
|
-- rgb_win.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---
-- Provides RGB window bus. Converts WIN_SIZE rows to
-- a window of size WIN_SIZE x WIN_SIZE.
-- Current i... |
-- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not ... |
-- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not ... |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
RISE : out vl_logic
);
end F2DSS_ACE_MISC_RDET;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:50:30 09/18/2015
-- Design Name:
-- Module Name: Magnitude_Comparator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Magnitude Comparator... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
`protect begin_protected
`protect version = 1
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`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
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`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect begin_protected
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`protect begin_protected
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`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Compon... |
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Compon... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Ext_Mem_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
mem_mux_input : in std_logi... |
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Re... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: main_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================================... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF R... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 8 axis version with 24 I/O bits
entity HostMot5_8 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:02 2017
-- Host : EffulgentTome running 64-bit m... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- The testbench for t8243 core.
--
-- $Id: tb_t8243.vhd,v 1.1 2006-07-14 01:02:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezis... |
-------------------------------------------------------------------------------
-- Title : test1
-- Project :
-------------------------------------------------------------------------------
-- File : test1.vhd
-- Author : <kristoffer.nordstrom@HELVNB0100>
-- Company :
-- Created : 201... |
library verilog;
use verilog.vl_types.all;
entity MUX8_1_Icontrol is
port(
Sel : in vl_logic_vector(2 downto 0);
S0 : in vl_logic;
S1 : in vl_logic;
S2 : in vl_logic;
S3 : in vl_logic;
... |
-- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementatio... |
-- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementatio... |
---------------------------------------------------------------------
-- IBUS adapter
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Converts the Low Latency Interface to WISHBONE registered
-- feedback protocol.
--
-- Note: regardless of whether this description is synthesiza... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:26 02/12/2014
-- Design Name:
-- Module Name: rca_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
library verilog;
use verilog.vl_types.all;
entity IF_STAGE is
port(
clk : in vl_logic;
rst : in vl_logic;
instr_fetch_enable: in vl_logic;
imm_branch_offset: in vl_logic_vector(5 downto 0);
branch_enable : in vl_logic;
jum... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Lookup table for scaling values to apply to the vector after rotating. It depends on the number of steps of the algorithm
entity scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
-- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write ... |
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
functi... |
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
functi... |
library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- A testbench has no ports.
entity system is
end system;
architecture behav of system is
subtype entry is unsigned(7 downto 0);
type invect is array (natural range <>) of entry;
signal minimum : entry;
signal vec : invect(0 to 20);
functi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights ... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights ... |
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
entity bug1 is
end bug1;
architecture behav of bug1 is
constant c : natural := 5;
function c return natural is
begin
return 7;
end;
begin -- behav
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.tbfuncs.all;
package tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.tbfuncs.all;
package tb_trfsmpkg is
function CalcTRConfigLength (
constant StateWidth : integer;
constant TotalInputWidth : integer;
constant MyInputWidth : integer;
constant OutputWidth : integer)
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.VHDL_lib.all;
entity mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end mux;
architecture arch of mux is
si... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Add-compare-select unit for trellis processing.
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
-... |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Add-compare-select unit for trellis processing.
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
-... |
----------------------------------------------------------------------------------
-- Module Name: top_level - Behavioral
--
-- Description: Top level of my DisplayPort design.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamste... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
------------------------------------------------------------------------------
-- Title : Trigger to Tag generator
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2019-04-01
-- Platform : FPGA-generi... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT... |
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT... |
-- SIMON 64/128
-- feistel round function operation gamma test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT... |
--
-- Written by Ryan Kim, Digilent Inc.
-- Modified by Michael Mattioli
--
-- Description: Runs the initialization sequence for the OLED display.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity oled_init is
port ( clk : in std_logic; --... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal rec : AbstractMmRecType(
writedata(31 downto 0),
readdata(31 downto 0),
address(4 downto 0),
byteen(3 downto 0)
);
begin
end a... |
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