content stringlengths 1 1.04M ⌀ |
|---|
-- NEED RESULT: ENT00206: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/07/2016 04:39:42 PM
-- Design Name:
-- Module Name: EXP8_wrrapper_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/07/2016 04:39:42 PM
-- Design Name:
-- Module Name: EXP8_wrrapper_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp... |
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is begin
end process;
process begin
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_stack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eithe... |
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eithe... |
-------------------------------------------------------------------------------
-- system_microblaze_0_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lm... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: RxIn_Delay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.10 - MAX_SIZE_EXCEEDED recalculated for bet... |
-- File name: sub_bytes_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel sub_bytes
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sub_bytes_p is
port (
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Registers is
port(
RR1, RR2, WR : in std_logic_vector(4 downto 0);
WD : in std_logic_vector(31 downto 0);
RegWrite, Clk : in std_logic;
RD1, RD2 : out std_logic_vector(31 downto 0)
);
end Registers;
architecture Structural... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v4
-- Module Name: Tb_Find_Correct_Errors_N_v4
-- Proj... |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- RAPID PROTOTYPING LABORATORY --
-- ... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.boa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg is
type bus_t is record
data : std_logic_vector;
valid : std_logic;
end record;
end package pkg;
|
library IEEE, stratixgx_gxb;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use stratixgx_gxb.hssi_pack.all;
package STRATIXGX_HSSI_COMPONENTS is
-- Beginning of testing section
-- these components are added for testing
component stratixgx_comp_fifo
GENERIC (
use_rate_match_fifo : string :=... |
architecture rtl of fifo is
alias designator : subtype_indication is name;
alias designator is name;
alias designator : subtype_indication is name;
alias designator : (subtype_indication) is name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Twofish_ecb_encryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at y... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
------------
-- pcore top level wrapper
-- generated at 2008-02-11 12:40:48.826899 by 'mkhwtask.py hwt_semaphore_post 1 ../src/hwt_semaphore_post.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.r... |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CSA16bits IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END CSA16bits ;
ARCHITECTURE s... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_rnd;
architecture behaviour of keyb_rnd is
constant st0: std_logic_vector(4 downto 0) := "... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_nov;
architecture behaviour of ex4_nov is
constant s1: std_logic_vector(3 downto 0) := "0010... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: measures a input freque... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: measures a input freque... |
-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eith... |
--------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 09:00:40 11/Okt/2013
-- Design Name: parallel_to_i2s
-- Description:
--
-- VHDL Test Bench for module: i2s_out
--
-- version: 00.01
--
-----------------------------------------------... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:01 01/21/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/BoothPartProdRed/BoothPartProdRed_tb.vhd
-- Project Name: BoothPartProdRed
-- Target Device:
-- Too... |
-- ***************************************************************************
-- File Name: DSP_TX_FSM.vhd
-- File Description:
-- This module works on the received packet and sends a new packet to DSP.
-- The state machine(main if-else logic) has few states such as Initialization, receiver ready,
-- packet test, e... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
------------------------------------------------------------------------------
-- Title : Simple Position Counters for debugging
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2017-01-20
-- Platform ... |
-------------------------------------------------------------------------------
-- Module: tb_uart_transmit
-- Purpose: Testbench for module e_uart_transmit.
--
-- Author: Leander Schulz
-- Date: 07.09.2017
-- Last change: 22.10.2017
---------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg IS
PORT(
clk, din, rst : IN std_logic;
dout : OUT std_logic
);
END ENTITY shiftreg;
ARCHITECTURE behavior OF shiftreg IS
SIGNAL sint: std_logic;
BEGIN
PROCESS (clk, rst)
BEGIN
if rst='1' THEN
dout <= (others => '0');
... |
entity test_id is
end entity;
architecture rtl of test_id is
type T_TUPLE is record
A : NATURAL;
B : NATURAL;
end record;
type T_VECTOR is array (NATURAL range <>) of T_TUPLE;
constant LIST : T_VECTOR := ((8, 32), (8, 20), (8, 36));
begin
genTests : for i in LIST'range generate
constant LOCAL_... |
entity test_id is
end entity;
architecture rtl of test_id is
type T_TUPLE is record
A : NATURAL;
B : NATURAL;
end record;
type T_VECTOR is array (NATURAL range <>) of T_TUPLE;
constant LIST : T_VECTOR := ((8, 32), (8, 20), (8, 36));
begin
genTests : for i in LIST'range generate
constant LOCAL_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_controller is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
por... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RaspiFpgaCtrlE is
port (
--+ System if
Rst_n_i : in std_logic;
Clk_i : in std_logic;
--+ local register if
LocalWen_o : out std_logic;
LocalRen_o : out std_logic;
LocalAdress_o : o... |
entity TOP is
end entity TOP;
architecture ARCH of TOP is
signal S1, S2, S3: BIT;
alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Legal
constant DATA_WIDTH: INTEGER:= <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
-- Illegal, because .TOP.DUT.DATA has not yet been elaborated
-- when the expression is ... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg_toplevel
-- Project Name: SevenSegmentDisplay
-- Target Devices... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_fifo_wrptr_inc is
port(
ge2_free : in vl_logic;
ge3_free : in vl_logic;
input_tm_cnt : in vl_logic_vector(1 downto 0);
fifo_wrptr_inc : out vl_logic_vector(3 downto 0)
);... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps is
generic (
CLK_PROC_FREQ : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
RXD ... |
----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 19:03:40 09/24/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depen... |
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.... |
architecture RTl of FIFO is
component fifo is
end COMPONENT fifo;
-- Failures below
component fifo is
end COMPONENT fifo;
component fifo is
end COMPONENT fifo;
begin
end architecture RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- Title : Position Calcualtion Error Counters (single)
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2014-01-13
-- Plat... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:40:01 2014
-- Host : CE-2013-124 running 64-bit Service Pa... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library verilog;
use verilog.vl_types.all;
entity chip_top is
port(
clk_ref : in vl_logic;
reset_sw : in vl_logic;
uart_rx : in vl_logic;
uart_tx : out vl_logic;
gpio_in : in vl_logic_vector(3 downto 0);
gpio_o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
---------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
---------------------------------------... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity T2logic is
generic(N:integer:=NSUMG);
port(
R1 : in std_logic_vector(N-1 downto 0);
R2 : in std_logic_vector(N-1 downto 0);
S1 : in std_logic;
S2 : in std_logic;
S3 : in std_logic;
L_OUT : out s... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 20... |
package repro4_gen is
generic (type t;
function id (a : t) return t);
function id2 (p : t) return t;
end repro4_gen;
package body repro4_gen is
function id2 (p : t) return t
is
-- constant c : t := p;
begin
return id (p);
end id2;
end repro4_gen;
package repro4_sortnet_tb is
generic (... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
library nuand ;
entity bladerf_tb is
end entity ; -- bladerf_tb
architecture arch of bladerf_tb is
constant C4_CLOCK_HALF_PERIOD : time := 1 sec * (1.0/38.4e6/2.0) ;
... |
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ie... |
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ie... |
entity proctarg is
end proctarg;
architecture behav of proctarg is
procedure proc (n : natural) is
begin
proc := true;
end proc;
procedure proc (n : boolean) is
begin
proc <= true;
end proc;
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:25 11/02/2011
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
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