content stringlengths 1 1.04M ⌀ |
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-- NEED RESULT: ENT00206: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00206
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00206(ARCH00206)
-- ENT00206_Test_Bench(ARCH00206_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00206 is
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00206 ;
--
--
architecture ARCH00206 of ENT00206 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_int1_vector : inout st_int1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(1 to 2) <= transport
c_st_int1_vector_2(1 to 2) after 10 ns ;
wait until s_st_int1_vector(1 to 2) =
c_st_int1_vector_2(1 to 2) ;
Test_Report (
"ENT00206",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(1 to 2) =
c_st_int1_vector_2(1 to 2) )) ;
--
when 1
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(G-1 to G) <= transport
c_st_int1_vector_2(G-1 to G) after 10 ns ;
wait until s_st_int1_vector(G-1 to G) =
c_st_int1_vector_2(G-1 to G) ;
Test_Report (
"ENT00206",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(G-1 to G) =
c_st_int1_vector_2(G-1 to G) )) ;
--
when 2
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(CG-1 to CG) <= transport
c_st_int1_vector_2(CG-1 to CG) after 10 ns ;
wait until s_st_int1_vector(CG-1 to CG) =
c_st_int1_vector_2(CG-1 to CG) ;
Test_Report (
"ENT00206",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG-1 to CG) =
c_st_int1_vector_2(CG-1 to CG) )) ;
--
when 3
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(CG'Attr-1 to CG'Attr) <= transport
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) after 10 ns ;
wait until s_st_int1_vector(CG'Attr-1 to CG'Attr) =
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) ;
Test_Report (
"ENT00206",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG'Attr-1 to CG'Attr) =
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_int1_vector
, counter
, correct
, savtime
, chk_st_int1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00206 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00206_Test_Bench is
end ENT00206_Test_Bench ;
--
--
architecture ARCH00206_Test_Bench of ENT00206_Test_Bench is
begin
L1:
block
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00206 ( ARCH00206 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_int1_vector
)
;
end block L1 ;
end ARCH00206_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/07/2016 04:39:42 PM
-- Design Name:
-- Module Name: EXP8_wrrapper_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EXP8_wrapper_tb is
end EXP8_wrapper_tb;
architecture Behavioral of EXP8_wrapper_tb is
component RAT_Basys3_wrapper
Port( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
signal switches_tb : std_logic_vector(7 downto 0) :="00000000";
signal leds_tb : std_logic_vector(7 downto 0) :="00000000";
signal clk_tb : std_logic := '0';
signal rst_tb : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut: RAT_Basys3_wrapper PORT MAP (
LEDS => leds_tb,
SWITCHES => switches_tb,
RST => rst_tb,
CLK => clk_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst_tb <= '1';
switches_tb <= "10101010";
wait for 50 ns;
rst_tb <= '0';
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/07/2016 04:39:42 PM
-- Design Name:
-- Module Name: EXP8_wrrapper_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EXP8_wrapper_tb is
end EXP8_wrapper_tb;
architecture Behavioral of EXP8_wrapper_tb is
component RAT_Basys3_wrapper
Port( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
signal switches_tb : std_logic_vector(7 downto 0) :="00000000";
signal leds_tb : std_logic_vector(7 downto 0) :="00000000";
signal clk_tb : std_logic := '0';
signal rst_tb : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut: RAT_Basys3_wrapper PORT MAP (
LEDS => leds_tb,
SWITCHES => switches_tb,
RST => rst_tb,
CLK => clk_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst_tb <= '1';
switches_tb <= "10101010";
wait for 50 ns;
rst_tb <= '0';
wait;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp is record
data : std_logic_vector(7 downto 0);
ack : std_logic;
irq : std_logic;
end record;
constant c_io_req_init : t_io_req := (
read => '0',
write => '0',
address => X"00000",
data => X"00" );
constant c_io_resp_init : t_io_resp := (
data => X"00",
irq => '0',
ack => '0' );
type t_io_req_array is array(natural range <>) of t_io_req;
type t_io_resp_array is array(natural range <>) of t_io_resp;
function or_reduce(ar: t_io_resp_array) return t_io_resp;
end package;
package body io_bus_pkg is
function or_reduce(ar: t_io_resp_array) return t_io_resp is
variable ret : t_io_resp;
begin
ret := c_io_resp_init;
for i in ar'range loop
ret.ack := ret.ack or ar(i).ack;
ret.irq := ret.irq or ar(i).irq;
ret.data := ret.data or ar(i).data;
end loop;
return ret;
end function or_reduce;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp is record
data : std_logic_vector(7 downto 0);
ack : std_logic;
irq : std_logic;
end record;
constant c_io_req_init : t_io_req := (
read => '0',
write => '0',
address => X"00000",
data => X"00" );
constant c_io_resp_init : t_io_resp := (
data => X"00",
irq => '0',
ack => '0' );
type t_io_req_array is array(natural range <>) of t_io_req;
type t_io_resp_array is array(natural range <>) of t_io_resp;
function or_reduce(ar: t_io_resp_array) return t_io_resp;
end package;
package body io_bus_pkg is
function or_reduce(ar: t_io_resp_array) return t_io_resp is
variable ret : t_io_resp;
begin
ret := c_io_resp_init;
for i in ar'range loop
ret.ack := ret.ack or ar(i).ack;
ret.irq := ret.irq or ar(i).irq;
ret.data := ret.data or ar(i).data;
end loop;
return ret;
end function or_reduce;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp is record
data : std_logic_vector(7 downto 0);
ack : std_logic;
irq : std_logic;
end record;
constant c_io_req_init : t_io_req := (
read => '0',
write => '0',
address => X"00000",
data => X"00" );
constant c_io_resp_init : t_io_resp := (
data => X"00",
irq => '0',
ack => '0' );
type t_io_req_array is array(natural range <>) of t_io_req;
type t_io_resp_array is array(natural range <>) of t_io_resp;
function or_reduce(ar: t_io_resp_array) return t_io_resp;
end package;
package body io_bus_pkg is
function or_reduce(ar: t_io_resp_array) return t_io_resp is
variable ret : t_io_resp;
begin
ret := c_io_resp_init;
for i in ar'range loop
ret.ack := ret.ack or ar(i).ack;
ret.irq := ret.irq or ar(i).irq;
ret.data := ret.data or ar(i).data;
end loop;
return ret;
end function or_reduce;
end package body;
|
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is begin
end process;
process begin
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_stack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity befunge_stack is
generic(
stack_depth_pow : integer := 4;
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end befunge_stack;
architecture stack_v1 of befunge_stack is
type stack_type is array ((2**stack_depth_pow)-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_type;
signal stack_ptr : Signed(stack_depth_pow-1 downto 0);
begin
stack_0_o <= stack(to_integer(Unsigned(stack_ptr)));
stack_1_o <= stack(to_integer(Unsigned(stack_ptr- 1)));
process(reset,clk)
variable ptr_incr : integer range -2 to 1;
begin
if(reset = '1') then
--stack_0_o <= (others => '0');
--stack_1_o <= (others => '0');
stack <= (others => (others => '0'));
stack_ptr <= (others => '0');
else
if rising_edge(clk) then
ptr_incr := 0;
if ( en = '1' ) then
if (pop1 = '1' or pop2 = '1' or push = '1') then
if ( pop1 = '1' ) then
ptr_incr := - 1;
elsif ( pop2 = '1' ) then
ptr_incr := - 2;
elsif ( push = '1' ) then
ptr_incr := 1;
stack(to_integer(Unsigned(stack_ptr + ptr_incr))) <= stack_i;
end if;
elsif (swap = '1' ) then
stack(to_integer(stack_ptr)) <= stack(to_integer(stack_ptr - 1));
stack(to_integer(stack_ptr - 1)) <= stack(to_integer(stack_ptr));
--stack_0_o <= stack(to_integer(stack_ptr + ptr_incr -1));
--stack_1_o <= stack(to_integer(stack_ptr + ptr_incr));
end if;
stack_ptr <= stack_ptr + ptr_incr;
end if;
end if;
end if;
end process;
end stack_v1; |
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`protect end_protected
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
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-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 12/21/2009 First Version
-- GAB 3/23/2010 renamed for axi_dma
--
-- GAB 10/15/10 v4_03
-- ^^^^^^
-- - Updated libraries to v4_03
-- ~~~~~~
-- GAB 2/15/11 v4_030_a
-- ^^^^^^
-- Updated libraries to v4_030_a
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-- GAB 7/19/11 v4_03
-- ^^^^^^
-- Update for use with axi_sg_v4_03
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex6"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_SYNCHRONIZER_STAGE => 4,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_EN_SAFETY_CKT => 1,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 12/21/2009 First Version
-- GAB 3/23/2010 renamed for axi_dma
--
-- GAB 10/15/10 v4_03
-- ^^^^^^
-- - Updated libraries to v4_03
-- ~~~~~~
-- GAB 2/15/11 v4_030_a
-- ^^^^^^
-- Updated libraries to v4_030_a
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-- GAB 7/19/11 v4_03
-- ^^^^^^
-- Update for use with axi_sg_v4_03
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex6"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_SYNCHRONIZER_STAGE => 4,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_EN_SAFETY_CKT => 1,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 12/21/2009 First Version
-- GAB 3/23/2010 renamed for axi_dma
--
-- GAB 10/15/10 v4_03
-- ^^^^^^
-- - Updated libraries to v4_03
-- ~~~~~~
-- GAB 2/15/11 v4_030_a
-- ^^^^^^
-- Updated libraries to v4_030_a
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-- GAB 7/19/11 v4_03
-- ^^^^^^
-- Update for use with axi_sg_v4_03
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex6"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_SYNCHRONIZER_STAGE => 4,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_EN_SAFETY_CKT => 1,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 12/21/2009 First Version
-- GAB 3/23/2010 renamed for axi_dma
--
-- GAB 10/15/10 v4_03
-- ^^^^^^
-- - Updated libraries to v4_03
-- ~~~~~~
-- GAB 2/15/11 v4_030_a
-- ^^^^^^
-- Updated libraries to v4_030_a
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-- GAB 7/19/11 v4_03
-- ^^^^^^
-- Update for use with axi_sg_v4_03
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex6"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_SYNCHRONIZER_STAGE => 4,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_EN_SAFETY_CKT => 1,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
architecture syn of bp_rs232_4line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
|
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
architecture syn of bp_rs232_4line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
|
-------------------------------------------------------------------------------
-- system_microblaze_0_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_microblaze_0_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end system_microblaze_0_ilmb_wrapper;
architecture STRUCTURE of system_microblaze_0_ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
microblaze_0_ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: RxIn_Delay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.10 - MAX_SIZE_EXCEEDED recalculated for better timing. 31.03.2008
--
-- Revision 1.00 - first release. 20.02.2007
--
-- Additional Comments: Virtual channels resolution.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RxIn_Delay is
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
m_axis_rx_tready : out std_logic;
Pool_wrBuf_full : in std_logic;
wb_FIFO_full : in std_logic;
-- Delay for one clock
m_axis_rx_tlast_dly : out std_logic;
m_axis_rx_tdata_dly : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep_dly : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd_dly : out std_logic;
m_axis_rx_tvalid_dly : out std_logic;
m_axis_rx_tready_dly : out std_logic;
m_axis_rx_tbar_hit_dly : out std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
MRd_Type : out std_logic_vector(3 downto 0);
MWr_Type : out std_logic_vector(1 downto 0);
CplD_Type : out std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
dsDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB : out std_logic;
-- To Cpl/D channel
Tlp_has_4KB : out std_logic;
Tlp_has_1DW : out std_logic;
CplD_is_the_Last : out std_logic;
CplD_on_Pool : out std_logic;
CplD_on_EB : out std_logic;
Req_ID_Match : out std_logic;
usDex_Tag_Matched : out std_logic;
dsDex_Tag_Matched : out std_logic;
CplD_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity RxIn_Delay;
architecture Behavioral of RxIn_Delay is
-- Max Length Checking
signal Tlp_has_0_Length : std_logic;
signal Tlp_has_1DW_Length_i : std_logic;
signal MaxReadReqSize_Exceeded : std_logic;
signal MaxPayloadSize_Exceeded : std_logic;
signal Tlp_straddles_4KB_i : std_logic;
signal Tlp_has_4KB_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
signal cfg_MRS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
signal cfg_MPS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
type CfgThreshold is array (C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE downto 0)
of std_logic_vector (C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal MaxSize_Thresholds : CfgThreshold;
-- As one clock of delay
signal m_axis_rx_tlast_r1 : std_logic;
signal m_axis_rx_tkeep_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tdata_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_terrfwd_r1 : std_logic;
signal m_axis_rx_tvalid_r1 : std_logic;
signal m_axis_rx_tready_i : std_logic;
signal m_axis_rx_tready_r1 : std_logic;
signal m_axis_rx_tbar_hit_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP type decision
signal TLP_is_MRd_BAR0_H3DW : std_logic;
signal TLP_is_MRd_BAR1_H3DW : std_logic;
signal TLP_is_MRd_BAR2_H3DW : std_logic;
signal TLP_is_MRd_BAR3_H3DW : std_logic;
signal TLP_is_MRd_BAR0_H4DW : std_logic;
signal TLP_is_MRd_BAR1_H4DW : std_logic;
signal TLP_is_MRd_BAR2_H4DW : std_logic;
signal TLP_is_MRd_BAR3_H4DW : std_logic;
signal TLP_is_MRdLk_BAR0_H3DW : std_logic;
signal TLP_is_MRdLk_BAR1_H3DW : std_logic;
signal TLP_is_MRdLk_BAR2_H3DW : std_logic;
signal TLP_is_MRdLk_BAR3_H3DW : std_logic;
signal TLP_is_MRdLk_BAR0_H4DW : std_logic;
signal TLP_is_MRdLk_BAR1_H4DW : std_logic;
signal TLP_is_MRdLk_BAR2_H4DW : std_logic;
signal TLP_is_MRdLk_BAR3_H4DW : std_logic;
signal TLP_is_MWr_BAR0_H3DW : std_logic;
signal TLP_is_MWr_BAR1_H3DW : std_logic;
signal TLP_is_MWr_BAR2_H3DW : std_logic;
signal TLP_is_MWr_BAR3_H3DW : std_logic;
signal TLP_is_MWr_BAR0_H4DW : std_logic;
signal TLP_is_MWr_BAR1_H4DW : std_logic;
signal TLP_is_MWr_BAR2_H4DW : std_logic;
signal TLP_is_MWr_BAR3_H4DW : std_logic;
signal TLP_is_CplD : std_logic;
signal TLP_is_Cpl : std_logic;
signal TLP_is_CplDLk : std_logic;
signal TLP_is_CplLk : std_logic;
signal TLP_is_MRd_H3DW : std_logic;
signal TLP_is_MRd_H4DW : std_logic;
signal TLP_is_MRdLk_H3DW : std_logic;
signal TLP_is_MRdLk_H4DW : std_logic;
signal TLP_is_MWr_H3DW : std_logic;
signal TLP_is_MWr_H4DW : std_logic;
signal MRd_Type_i : std_logic_vector(3 downto 0);
signal MWr_Type_i : std_logic_vector(1 downto 0);
signal CplD_Type_i : std_logic_vector(3 downto 0);
signal Req_ID_Match_i : std_logic;
signal usDex_Tag_Matched_i : std_logic;
signal dsDex_Tag_Matched_i : std_logic;
-----------------------------------------------------------------
-- Inbound DW counter
signal TLP_DW_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal MWr_on_Pool : std_logic;
signal MWr_on_EB : std_logic;
signal CplD_on_Pool_i : std_logic;
signal CplD_on_EB_i : std_logic;
signal CplD_is_the_Last_i : std_logic;
signal CplD_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Counter inside a TLP
type TLPCntStates is (TK_RST
, TK_Idle
-- , TK_MWr_3Hdr_B
, TK_MWr_3Hdr_C
-- , TK_MWr_4Hdr_B
, TK_MWr_4Hdr_C
-- , TK_MWr_4Hdr_D
-- , TK_CplD_Hdr_B
, TK_CplD_Hdr_C
, TK_Body
);
signal FSM_TLP_Cnt : TLPCntStates;
-- CplD tag capture FSM (Address at tRAM)
type AddrOnRAM_States is (AOtSt_RST
, AOtSt_Idle
, AOtSt_HdrA
, AOtSt_HdrB
, AOtSt_Body
);
signal FSM_AOtRAM : AddrOnRAM_States;
--old interface helper signals
signal in_packet_reg : std_logic;
signal trn_rsof_n : std_logic;
begin
m_axis_rx_tready <= m_axis_rx_tready_i; -- Delay
m_axis_rx_tlast_dly <= m_axis_rx_tlast_r1;
m_axis_rx_tkeep_dly <= m_axis_rx_tkeep_r1;
m_axis_rx_tdata_dly <= m_axis_rx_tdata_r1;
m_axis_rx_terrfwd_dly <= m_axis_rx_terrfwd_r1;
m_axis_rx_tvalid_dly <= m_axis_rx_tvalid_r1;
m_axis_rx_tready_dly <= m_axis_rx_tready_r1; -- m_axis_rx_tready_r1 ;
m_axis_rx_tbar_hit_dly <= m_axis_rx_tbar_hit_r1;
-- TLP resolution
MRd_Type <= MRd_Type_i;
MWr_Type <= MWr_Type_i;
CplD_Type <= CplD_Type_i;
-- To Cpl/D channel
Req_ID_Match <= Req_ID_Match_i;
usDex_Tag_Matched <= usDex_Tag_Matched_i;
dsDex_Tag_Matched <= dsDex_Tag_Matched_i;
CplD_Tag <= CplD_Tag_i;
CplD_is_the_Last <= CplD_is_the_Last_i;
CplD_on_Pool <= CplD_on_Pool_i;
CplD_on_EB <= CplD_on_EB_i;
Tlp_has_4KB <= Tlp_has_4KB_i;
Tlp_has_1DW <= Tlp_has_1DW_Length_i;
Tlp_straddles_4KB <= '0'; --Tlp_straddles_4KB_i ;
-- !! !!
MaxReadReqSize_Exceeded <= '0';
MaxPayloadSize_Exceeded <= '0';
----------------------------------------------
--
-- Synchronous Registered: TLP_DW_Length
-- Tlp_has_4KB
-- Tlp_has_1DW_Length
-- Tlp_has_0_Length
--
FSM_TLP_1ST_DW_Info :
process (user_clk, user_reset)
begin
if user_reset = '1' then
TLP_DW_Length_i <= (others => '0');
Tlp_has_4KB_i <= '0';
Tlp_has_1DW_Length_i <= '0';
Tlp_has_0_Length <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n = '0' then
TLP_DW_Length_i <= m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
else
TLP_DW_Length_i <= TLP_DW_Length_i;
end if;
if trn_rsof_n = '0' then
if m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) = C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) then
Tlp_has_4KB_i <= '1';
else
Tlp_has_4KB_i <= '0';
end if;
else
Tlp_has_4KB_i <= Tlp_has_4KB_i;
end if;
if trn_rsof_n = '0' then
if m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
Tlp_has_1DW_Length_i <= '1';
else
Tlp_has_1DW_Length_i <= '0';
end if;
else
Tlp_has_1DW_Length_i <= Tlp_has_1DW_Length_i;
end if;
if trn_rsof_n = '0' then
if m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and m_axis_rx_tdata(32+2) = '0' then
Tlp_has_0_Length <= '1';
else
Tlp_has_0_Length <= '0';
end if;
else
Tlp_has_0_Length <= Tlp_has_0_Length;
end if;
end if;
end process;
---- --------------------------------------------------------------------------
-- -- Max Payload Size bits
-- cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
--
-- -- Max Read Request Size bits
-- cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
--
--
--
-- -- --------------------------------
-- -- Decoding MPS
-- --
-- Trn_Rx_Decoding_MPS:
-- process ( user_clk )
-- begin
-- if user_clk'event and user_clk = '1' then
--
-- case cfg_MPS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Decoding MRS
-- --
-- Trn_Rx_Decoding_MRS:
-- process ( user_clk )
-- begin
-- if user_clk'event and user_clk = '1' then
--
-- case cfg_MRS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -------------------------------------------------------------
-- MaxSize_Thresholds(0) <= (CBIT_SENSE_OF_MAXSIZE=>'1', Others=>'0');
-- Gen_MaxSizes:
-- FOR i IN 1 TO C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE GENERATE
-- MaxSize_Thresholds(i) <= MaxSize_Thresholds(i-1)(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)&'0';
-- END GENERATE;
--
-- -- --------------------------------
-- -- Calculation of MPS exceed
-- --
-- Trn_Rx_MaxPayloadSize_Exceeded:
-- process ( user_clk )
-- begin
-- if user_clk'event and user_clk = '1' then
--
-- case cfg_MPS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxPayloadSize_Exceeded <= '1';
---- else
---- MaxPayloadSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxPayloadSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Calculation of MRS exceed
-- --
-- Trn_Rx_MaxReadReqSize_Exceeded:
-- process ( user_clk )
-- begin
-- if user_clk'event and user_clk = '1' then
--
-- case cfg_MRS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxReadReqSize_Exceeded <= '1';
---- else
---- MaxReadReqSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxReadReqSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if m_axis_rx_tdata(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
-- ---------------------------------------------------------
---- Pipelining all trn_rx input signals for one clock
---- to get better timing
----
Trn_Rx_Inputs_Delayed :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
m_axis_rx_tlast_r1 <= m_axis_rx_tlast;
m_axis_rx_tkeep_r1 <= m_axis_rx_tkeep;
m_axis_rx_tdata_r1 <= m_axis_rx_tdata;
m_axis_rx_terrfwd_r1 <= m_axis_rx_terrfwd;
m_axis_rx_tvalid_r1 <= m_axis_rx_tvalid;
m_axis_rx_tready_r1 <= m_axis_rx_tready_i;
m_axis_rx_tbar_hit_r1 <= m_axis_rx_tbar_hit;
end if;
end process;
-- -----------------------------------------
-- TLP Types
--
TLP_Decision_Registered :
process (user_clk, user_reset)
begin
if user_reset = '1' then
TLP_is_MRd_H3DW <= '0';
TLP_is_MRdLk_H3DW <= '0';
TLP_is_MRd_H4DW <= '0';
TLP_is_MRdLk_H4DW <= '0';
TLP_is_MWr_H3DW <= '0';
TLP_is_MWr_H4DW <= '0';
TLP_is_CplD <= '0';
TLP_is_CplDLk <= '0';
TLP_is_Cpl <= '0';
TLP_is_CplLk <= '0';
elsif user_clk'event and user_clk = '1' then
-- MRd
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MRd_H3DW <= '1';
else
TLP_is_MRd_H3DW <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MRd_H4DW <= '1';
else
TLP_is_MRd_H4DW <= '0';
end if;
-- MRdLk
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MRdLk_H3DW <= '1';
else
TLP_is_MRdLk_H3DW <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MRdLk_H4DW <= '1';
else
TLP_is_MRdLk_H4DW <= '0';
end if;
-- MWr
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MWr_H3DW <= '1';
else
TLP_is_MWr_H3DW <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_WITH_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tbar_hit(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0)
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_MWr_H4DW <= '1';
else
TLP_is_MWr_H4DW <= '0';
end if;
-- CplD, Cpl/CplDLk, CplLk
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_CplD <= '1';
else
TLP_is_CplD <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_CplDLk <= '1';
else
TLP_is_CplDLk <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_Cpl <= '1';
else
TLP_is_Cpl <= '0';
end if;
if m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and m_axis_rx_tdata(C_TLP_EP_BIT) = '0'
and m_axis_rx_tvalid = '1'
and trn_rsof_n = '0'
then
TLP_is_CplLk <= '1';
else
TLP_is_CplLk <= '0';
end if;
end if;
end process;
-- --------------------------------------------------------------------------
-- TLP_is_MRd_H3DW <= TLP_is_MRd_BAR0_H3DW or TLP_is_MRd_BAR1_H3DW;
-- TLP_is_MRdLk_H3DW <= TLP_is_MRdLk_BAR0_H3DW or TLP_is_MRdLk_BAR1_H3DW;
-- TLP_is_MRd_H4DW <= TLP_is_MRd_BAR0_H4DW or TLP_is_MRd_BAR1_H4DW;
-- TLP_is_MRdLk_H4DW <= TLP_is_MRdLk_BAR0_H4DW or TLP_is_MRdLk_BAR1_H4DW;
-- TLP_is_MWr_H3DW <= TLP_is_MWr_BAR0_H3DW or TLP_is_MWr_BAR1_H3DW;
-- TLP_is_MWr_H4DW <= TLP_is_MWr_BAR0_H4DW or TLP_is_MWr_BAR1_H4DW;
-- --------------------------------------------------------------------------
MRd_Type_i <= (TLP_is_MRd_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRd_H4DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H4DW and not MaxReadReqSize_Exceeded);
MWr_Type_i <= (TLP_is_MWr_H3DW and not MaxPayloadSize_Exceeded)
& (TLP_is_MWr_H4DW and not MaxPayloadSize_Exceeded);
CplD_Type_i <= (TLP_is_CplD and not MaxPayloadSize_Exceeded)
& (TLP_is_Cpl and not MaxPayloadSize_Exceeded)
& (TLP_is_CplDLk and not MaxPayloadSize_Exceeded)
& (TLP_is_CplLk and not MaxPayloadSize_Exceeded);
---------------------------------------------------
--
-- Synchronous Registered: TLP_Header_Resolution
--
FSM_TLP_Header_Resolution :
process (user_clk, user_reset)
begin
if user_reset = '1' then
FSM_TLP_Cnt <= TK_RST;
MWr_on_Pool <= '0';
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
m_axis_rx_tready_i <= '0';
elsif user_clk'event and user_clk = '1' then
-- States transition
case FSM_TLP_Cnt is
when TK_RST =>
FSM_TLP_Cnt <= TK_Idle;
m_axis_rx_tready_i <= '0';
when TK_Idle =>
m_axis_rx_tready_i <= '1';
if trn_rsof_n = '0' and m_axis_rx_tvalid = '1' and m_axis_rx_tready_i = '1'
and m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = "10"
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "00"
then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
elsif trn_rsof_n = '0' and m_axis_rx_tvalid = '1' and m_axis_rx_tready_i = '1'
and m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = "11"
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "00"
then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
elsif trn_rsof_n = '0' and m_axis_rx_tvalid = '1' and m_axis_rx_tready_i = '1'
and m_axis_rx_tdata(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = "10"
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "01"
then
FSM_TLP_Cnt <= TK_CplD_Hdr_C;
else
FSM_TLP_Cnt <= TK_Idle;
end if;
when TK_MWr_3Hdr_C =>
m_axis_rx_tready_i <= '1';
if m_axis_rx_tlast = '1' and m_axis_rx_tlast_r1 = '0' -- raising edge
and m_axis_rx_tready_i = '1' then
FSM_TLP_Cnt <= TK_Idle;
elsif m_axis_rx_tvalid = '0' then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_MWr_4Hdr_C =>
m_axis_rx_tready_i <= '1';
if m_axis_rx_tlast = '1' and m_axis_rx_tlast_r1 = '0' -- raising edge
and m_axis_rx_tready_i = '1' then
FSM_TLP_Cnt <= TK_Idle;
elsif m_axis_rx_tvalid = '0' then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
else
FSM_TLP_Cnt <= TK_Body; -- TK_MWr_4Hdr_D;
end if;
when TK_Cpld_Hdr_C =>
m_axis_rx_tready_i <= '1';
if m_axis_rx_tlast = '1' and m_axis_rx_tlast_r1 = '0' -- raising edge
and m_axis_rx_tready_i = '1' then
FSM_TLP_Cnt <= TK_Idle;
elsif m_axis_rx_tvalid = '0' then
FSM_TLP_Cnt <= TK_Cpld_Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_Body =>
--for TLP body we can't wait for rising edge because there is a chance that TLP EOF
--will hit when *_tready_i = 0 which will cause deadlock
if m_axis_rx_tlast = '1' and m_axis_rx_tvalid = '1' and m_axis_rx_tready_i = '1' then
FSM_TLP_Cnt <= TK_Idle;
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
or ((MWr_on_EB or CplD_on_EB_i) and wb_fifo_full));
else
FSM_TLP_Cnt <= TK_Body;
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
or ((MWr_on_EB or CplD_on_EB_i) and wb_fifo_full));
end if;
when others =>
FSM_TLP_Cnt <= TK_RST;
end case;
-- MWr_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
MWr_on_Pool <= '0';
MWr_on_EB <= '0';
when TK_Idle =>
if trn_rsof_n = '0' and m_axis_rx_tvalid = '1'
and m_axis_rx_tdata(C_TLP_FMT_BIT_TOP) = '1'
and m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "00"
then
MWr_on_Pool <= m_axis_rx_tbar_hit(CINT_DDR_SPACE_BAR);
MWr_on_EB <= m_axis_rx_tbar_hit(CINT_FIFO_SPACE_BAR);
else
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end if;
when others =>
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end case;
-- CplD_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_Idle =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_CplD_Hdr_C =>
CplD_on_Pool_i <= not m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP) and not m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP-1);
CplD_on_EB_i <= not m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP) and m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP-1);
when others =>
CplD_on_Pool_i <= CplD_on_Pool_i;
CplD_on_EB_i <= CplD_on_EB_i;
end case;
-- CplD_Tag
case FSM_TLP_Cnt is
when TK_RST =>
CplD_Tag_i <= (others => '1');
when TK_CplD_Hdr_C =>
if m_axis_rx_tvalid = '1' -- and m_axis_rx_tready='1'
then
CplD_Tag_i <= m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT);
else
CplD_Tag_i <= CplD_Tag_i;
end if;
when others =>
CplD_Tag_i <= CplD_Tag_i;
end case;
end if;
end process;
---------------------------------------------------
--
-- Synchronous Registered: CplD_is_the_Last
--
Syn_Calc_CplD_is_the_Last :
process (user_clk, user_reset)
begin
if user_reset = '1' then
CplD_is_the_Last_i <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n = '0' and m_axis_rx_tvalid = '1' then
if m_axis_rx_tdata(C_TLP_TYPE_BIT_TOP-1) = '1'
and (m_axis_rx_tdata(C_CPLD_BC_BIT_TOP downto C_CPLD_BC_BIT_BOT+2) = m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
or m_axis_rx_tdata(32+1 downto 32+0) = CONV_STD_LOGIC_VECTOR(1, 2)) -- Zero-length
then
CplD_is_the_Last_i <= '1';
else
CplD_is_the_Last_i <= '0';
end if;
else
CplD_is_the_Last_i <= CplD_is_the_Last_i;
end if;
end if;
end process;
-- ---------------------------------------------------------
-- To Cpl/D channel as indicator when ReqID matched
--
TLP_ReqID_Matched :
process (user_clk, user_reset)
begin
if user_reset = '1' then
Req_ID_Match_i <= '0';
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tdata(C_CPLD_REQID_BIT_TOP downto C_CPLD_REQID_BIT_BOT) = localID then
Req_ID_Match_i <= '1';
else
Req_ID_Match_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when us Tag_Descriptor matched
--
TLP_usDexTag_Matched :
process (user_clk, user_reset)
begin
if user_reset = '1' then
usDex_Tag_Matched_i <= '0';
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = usDMA_dex_Tag then
usDex_Tag_Matched_i <= '1';
else
usDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when ds Tag_Descriptor matched
--
TLP_dsDexTag_Matched :
process (user_clk, user_reset)
begin
if user_reset = '1' then
dsDex_Tag_Matched_i <= '0';
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tdata(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = dsDMA_dex_Tag then
dsDex_Tag_Matched_i <= '1';
else
dsDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid and m_axis_rx_tready_i) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
|
-- File name: sub_bytes_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel sub_bytes
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sub_bytes_p is
port (
d_in : in state_type;
d_out : out state_type
);
end entity sub_bytes_p;
architecture structural of sub_bytes_p is
begin
gen_sbox : for i in g_index generate
sub_bytes_b : entity work.sbox(dataflow) port map (
clk => '0', a => d_in(i mod 4, i / 4), b => d_out(i mod 4, i / 4)
);
end generate gen_sbox;
end architecture structural;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_11;
USE axi_gpio_v2_0_11.axi_gpio;
ENTITY block_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END block_design_axi_gpio_0_0;
ARCHITECTURE block_design_axi_gpio_0_0_arch OF block_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 9,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END block_design_axi_gpio_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_11;
USE axi_gpio_v2_0_11.axi_gpio;
ENTITY block_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END block_design_axi_gpio_0_0;
ARCHITECTURE block_design_axi_gpio_0_0_arch OF block_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 9,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END block_design_axi_gpio_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Registers is
port(
RR1, RR2, WR : in std_logic_vector(4 downto 0);
WD : in std_logic_vector(31 downto 0);
RegWrite, Clk : in std_logic;
RD1, RD2 : out std_logic_vector(31 downto 0)
);
end Registers;
architecture Structural of Registers is
type mem_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal reg_mem: mem_array :=(
X"00000000", --0 $zero (constant value 0)
X"00000000", -- $at (reserved for the assembler)
X"00000000", -- $v0 (value for results and expression)
X"00000000", -- $v1
X"00000000", -- $a0 (arguments)
X"00000000", --5 $a1
X"00000000", -- $a2
X"00000000", -- $a3
X"00000004", -- $t0 (temporaries)
X"00000000", -- $t1
X"00000000", --10 $t2
X"00000000", -- $t3
X"00000000", -- $t4
X"00000000", -- $t5
X"00000000", -- $t6
X"00000000", --15 $t7
X"00000000", -- $s0 (saved)
X"00000000", -- $s1
X"0000000D", -- $s2
X"00000004", -- $s3
X"00000000", --20 $s4
X"00000000", -- $s5
X"00000000", -- $s6
X"00000000", -- $s7
X"00000000", -- $t8 (more temporaries)
X"00000000", --25 $t9
X"00000000", -- $k0 (reserved for the operating system)
X"00000000", -- $k1
X"00000000", -- $gp (global pointer)
X"00000000", -- $sp (stack pointer)
X"00000000", --30 $fp (frame pointer)
X"00000000" -- $ra (return address)
);
begin
RD1 <= reg_mem(to_integer(unsigned(RR1)));
RD2 <= reg_mem(to_integer(unsigned(RR2)));
process(Clk)
begin
if rising_edge(Clk) then
if RegWrite = '1' then
reg_mem(to_integer(unsigned(WR))) <= WD;
end if;
end if;
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v4
-- Module Name: Tb_Find_Correct_Errors_N_v4
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for polynomial_syndrome_computing_n_v2 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the size of the pipeline.
-- This is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
-- x_memory_file :
--
-- File that holds the values to be evaluated on the polynomial. Support elements L.
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
--
-- resp_memory_file :
--
-- File that holds all evaluations of support L on polynomial sigma.
-- This file holds the output of the circuit,
-- it is needed to detect if polynomial evaluator circuit worked properly.
--
-- dump_acc_memory_file :
--
-- File that will hold the output of all support L evaluations on polynomial sigma,
-- that were done by the circuit.
--
-- codeword_memory_file :
--
-- File that holds the ciphertext that will be corrected according to the polynomial
-- sigma roots that were found.
--
-- message_memory_file :
--
-- File that holds the ciphertext already corrected.
-- This file is necessary to detect
-- if the ciphertext correction was performed correctly by the circuit.
--
-- dump_codeword_memory_file :
--
-- File that will hold the ciphertext corrected by the circuit.
--
-- dump_error_memory_file :
--
-- File that will hold the errors found on the ciphertext by the circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n_v2 Rev 1.0
-- ram Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_find_correct_errors_n_v4 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- sigma_degree : integer := 4;
-- size_sigma_degree : integer := 2;
-- length_support_elements: integer := 52;
-- size_support_elements : integer := 6;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_52_28_4_6.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_52_28_4_6.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 4;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 27;
-- size_sigma_degree : integer := 5;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1751_27_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1751_27_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1751_27_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 50;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1498_50_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1498_50_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1498_50_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 66;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_3307_2515_66_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_3307_2515_66_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_3307_2515_66_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 33;
size_pipeline_size : integer := 6;
gf_2_m : integer range 1 to 20 := 12;
sigma_degree : integer := 32;
size_sigma_degree : integer := 6;
length_support_elements: integer := 2528;
size_support_elements : integer := 12;
x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12.dat";
resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2528_2144_32_12.dat";
dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2528_2144_32_12.dat";
dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2816_2048_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_3328_2560_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 129;
-- size_pipeline_size : integer := 8;
-- gf_2_m : integer range 1 to 20 := 13;
-- sigma_degree : integer := 128;
-- size_sigma_degree : integer := 8;
-- length_support_elements: integer := 7296;
-- size_support_elements : integer := 13;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_7296_5632_128_13.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_7296_5632_128_13.dat"
);
end tb_find_correct_errors_n_v4;
architecture Behavioral of tb_find_correct_errors_n_v4 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component polynomial_syndrome_computing_n_v2
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
number_of_errors : integer;
size_number_of_errors : integer;
number_of_support_elements : integer;
size_number_of_support_elements : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal mode_polynomial_syndrome : STD_LOGIC;
signal computation_finalized : STD_LOGIC;
signal address_value_polynomial : STD_LOGIC_VECTOR((size_sigma_degree - 1) downto 0);
signal address_value_x : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_sigma_degree) downto 0);
signal address_value_error : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_acc : STD_LOGIC;
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_value_error : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_error : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant test_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant true_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant error_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant x_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant sigma_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant true_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant test_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
signal test_codeword_dump : std_logic := '0';
signal true_codeword_dump : std_logic := '0';
signal x_dump : std_logic := '0';
signal sigma_dump : std_logic := '0';
signal true_acc_dump : std_logic := '0';
signal test_acc_dump : std_logic := '0';
signal error_dump : std_logic := '0';
signal test_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal test_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_value : STD_LOGIC_VECTOR (((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal true_codeword_value : STD_LOGIC_VECTOR ((number_of_pipelines - 1) downto 0);
signal error_acc : STD_LOGIC;
signal error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for true_codeword : ram_bank use entity work.ram_bank(file_load);
for test_codeword : ram_double_bank use entity work.ram_double_bank(file_load);
for x : ram_bank use entity work.ram_bank(file_load);
for sigma : ram use entity work.ram(file_load);
for true_acc : ram_bank use entity work.ram_bank(file_load);
for test_acc : ram_double_bank use entity work.ram_double_bank(simple);
for error : ram_bank use entity work.ram_bank(simple);
begin
test_codeword : ram_double_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => dump_codeword_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_message,
rw_a => '0',
rw_b => write_enable_new_value_message,
clk => clk,
rst => rst,
dump => test_codeword_dump,
address_a => test_codeword_address,
address_b => address_new_value_message,
rst_value => test_codeword_rst_value,
data_out_a => value_message,
data_out_b => open
);
error : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_error_memory_file
)
Port Map(
data_in => value_error,
rw => write_enable_value_error,
clk => clk,
rst => rst,
dump => error_dump,
address => address_value_error,
rst_value => error_rst_value,
data_out => open
);
true_codeword : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_codeword_dump,
address => true_codeword_address,
rst_value => true_codeword_rst_value,
data_out => true_codeword_value
);
x : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => x_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => x_dump,
address => address_value_x,
rst_value => x_rst_value,
data_out => value_x
);
true_acc : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => resp_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_acc_dump,
address => true_acc_address,
rst_value => true_acc_rst_value,
data_out => true_acc_value
);
test_acc : ram_double_bank
Generic Map(
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_acc_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_acc,
rw_a => '0',
rw_b => write_enable_new_value_acc,
clk => clk,
rst => rst,
dump => test_acc_dump,
address_a => test_acc_address,
address_b => address_new_value_acc,
rst_value => test_acc_rst_value,
data_out_a => value_acc,
data_out_b => open
);
sigma : ram
Generic Map (
ram_address_size => size_sigma_degree,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => sigma_dump,
address => address_value_polynomial,
rst_value => sigma_rst_value,
data_out => value_polynomial
);
poly : polynomial_syndrome_computing_n_v2
Generic Map(
number_of_pipelines => number_of_pipelines,
pipeline_size => pipeline_size,
size_pipeline_size => size_pipeline_size,
gf_2_m => gf_2_m,
number_of_support_elements => length_support_elements,
size_number_of_support_elements => size_support_elements,
number_of_errors => sigma_degree,
size_number_of_errors => size_sigma_degree
)
Port Map(
value_x => value_x,
value_acc => value_acc,
value_polynomial => value_polynomial,
value_message => value_message,
value_h => value_h,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
rst => rst,
computation_finalized => computation_finalized,
address_value_polynomial => address_value_polynomial,
address_value_x => address_value_x,
address_value_acc => address_value_acc,
address_value_message => address_value_message,
address_new_value_message => address_new_value_message,
address_new_value_acc => address_new_value_acc,
address_new_value_syndrome => address_new_value_syndrome,
address_value_error => address_value_error,
write_enable_new_value_acc => write_enable_new_value_acc,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_value_error => write_enable_value_error,
new_value_syndrome => new_value_syndrome,
new_value_acc => new_value_acc,
new_value_message => new_value_message,
value_error => value_error
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
test_acc_address <= address_value_acc when computation_finalized = '0' else
true_acc_address;
test_codeword_address <= address_value_x when computation_finalized = '0' else
true_codeword_address;
mode_polynomial_syndrome <= '0';
process
variable i : integer;
begin
true_acc_address <= (others => '0');
true_codeword_address <= (others => '0');
rst <= '1';
error_acc <= '0';
error_message <= '0';
wait for PERIOD*2;
rst <= '0';
wait until computation_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_support_elements)) loop
error_message <= '0';
error_acc <= '0';
true_acc_address <= std_logic_vector(to_unsigned(i, true_acc_address'Length));
true_codeword_address <= std_logic_vector(to_unsigned(i, true_codeword_address'Length));
wait for PERIOD*2;
if (true_acc_value = value_acc) then
error_acc <= '0';
else
error_acc <= '1';
report "Computed values do not match expected ones";
end if;
if (true_codeword_value = value_message) then
error_message <= '0';
else
error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_acc <= '0';
error_message <= '0';
wait for PERIOD;
i := i + number_of_pipelines;
end loop;
error_message <= '0';
error_acc <= '0';
test_acc_dump <= '1';
test_codeword_dump <= '1';
wait for PERIOD;
test_acc_dump <= '0';
test_codeword_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral; |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- RAPID PROTOTYPING LABORATORY --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | Nov. 2014 --
--======================================================--
--**********************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--**********************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Rounding addition --
----------------------------------------------------------
entity round_add is
generic
(
exp_bits : integer := 0;
man_bits_in : integer := 0;
man_bits_out : integer := 0
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
SIGN_IN : in std_logic;
EXP_IN : in std_logic_vector(exp_bits-1 downto 0);
MAN_IN : in std_logic_vector(man_bits_in-1 downto 0);
READY : in std_logic;
ENABLE : in std_logic;
EXCEPTION_IN : in std_logic;
--outputs
DONE : out std_logic;
SIGN_OUT : out std_logic;
EXP_OUT : out std_logic_vector(exp_bits-1 downto 0);
MAN_OUT : out std_logic_vector(man_bits_out-1 downto 0);
EXCEPTION_OUT : out std_logic
);
end round_add;
----------------------------------------------------------
-- Rounding addition --
----------------------------------------------------------
architecture round_add_arch of round_add is
--SIGNALS
signal exponent : std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal slice : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal exp_int : std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal man_int : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal man_carry: std_logic := '0';
signal exc_int : std_logic := '0';
signal exc_pa : std_logic := '0';
signal zeros : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal zeros_exp: std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal int : integer;
signal ifzero : std_logic_vector(man_bits_in-man_bits_out-3 downto 0) := (others => '0');
begin
--ASYNCHRONOUS
--component instantiation
pa : parameterized_adder
generic map
(
bits => man_bits_out+1
)
port map
(
A => slice,
B => zeros,
CIN => ENABLE,
S => man_int,
--COUT => exc_pa
COUT => man_carry
);
pe : parameterized_adder
generic map
(
bits => exp_bits
)
port map
(
A => exponent,
B => zeros_exp,
CIN => man_carry,
S => exp_int,
COUT => exc_pa
);
--signal connections
exponent <= EXP_IN;
slice <= MAN_IN(man_bits_in-2 downto man_bits_in-man_bits_out-2);
exc_int <= exc_pa OR EXCEPTION_IN;
ifzero <= MAN_IN(man_bits_in-man_bits_out-3 downto 0);
int <= conv_integer(ifzero);
--SYNCHRONOUS
main: process (CLK,RESET,STALL) is
begin
if (RESET = '1') then
SIGN_OUT <= '0';
EXP_OUT <= (others=>'0');
MAN_OUT <= (others=>'0');
EXCEPTION_OUT <= '0';
DONE <= '0';
elsif(rising_edge(CLK) and STALL = '0') then
if(int = 0 and MAN_IN(man_bits_in-man_bits_out-2) = '1' and ENABLE = '1') then
SIGN_OUT <= SIGN_IN;
EXP_OUT <= exp_int;
MAN_OUT <= man_int(man_bits_out downto 2)&'0';
EXCEPTION_OUT <= exc_int;
DONE <= READY;
else
SIGN_OUT <= SIGN_IN;
EXP_OUT <= exp_int;
MAN_OUT <= man_int(man_bits_out downto 1);
EXCEPTION_OUT <= exc_int;
DONE <= READY;
end if;
end if; --CLK
end process; --main
end round_add_arch; -- end of architecture
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.board_pkg.all;
entity serial_port is
generic (
g_PORT_WIDTH : integer := 32
);
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input
enable_i : in std_logic;
data_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
idle_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
sync_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
sync_interval_i : in std_logic_vector(7 downto 0);
pulse_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
pulse_interval_i : in std_logic_vector(15 downto 0);
data_valid_i : in std_logic;
-- Output
data_o : out std_logic;
data_read_o : out std_logic
);
end serial_port;
architecture behavioral of serial_port is
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
-- Signals
constant c_ZEROS : std_logic_vector(g_PORT_WIDTH-1 downto 0) := (others => '0');
signal bit_count : unsigned(log2_ceil(g_PORT_WIDTH) downto 0);
signal sreg : std_logic_vector(g_PORT_WIDTH-1 downto 0);
signal sync_cnt : unsigned(7 downto 0);
signal pulse_cnt : unsigned(15 downto 0);
signal bx_tick : std_logic;
begin
-- Serializer proc
serialize: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sreg <= (others => '0');
bit_count <= (others => '0');
data_read_o <= '0';
sync_cnt <= (others => '0');
pulse_cnt <= (others => '0');
data_o <= '0';
elsif rising_edge(clk_i) then
-- Output register
data_o <= sreg(g_PORT_WIDTH-1);
-- Priority encoder
-- 1. Input via data_i port (fifo/looper) [only when enabled]
-- 3. Autozero word [only when enabled]
-- 2. Sync word
-- 4. Idle
if (bit_count = g_PORT_WIDTH-1 and data_valid_i = '1' and enable_i = '1') then
sreg <= data_i;
data_read_o <= '1';
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= pulse_cnt + 1;
elsif (bit_count = g_PORT_WIDTH-1 and pulse_cnt >= unsigned(pulse_interval_i) and (pulse_i /= c_ZEROS) and (enable_i = '1')) then --
sreg <= pulse_i;
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= (others => '0');
elsif (bit_count = g_PORT_WIDTH-1 and sync_cnt >= unsigned(sync_interval_i) and (sync_i /= c_ZEROS)) then
sreg <= sync_i;
bit_count <= (others => '0');
sync_cnt <= (others => '0');
pulse_cnt <= pulse_cnt + 1;
--elsif (bit_count = g_PORT_WIDTH-1 and data_valid_i = '0') then
elsif (bit_count = g_PORT_WIDTH-1) then
sreg <= idle_i;
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= pulse_cnt + 1;
else
sreg <= sreg(g_PORT_WIDTH-2 downto 0) & '0';
data_read_o <= '0';
bit_count <= bit_count + 1;
end if;
bx_tick <= '0';
if (bit_count mod c_TX_40_DIVIDER = 0) then
bx_tick <= '1';
end if;
end if;
end process serialize;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg is
type bus_t is record
data : std_logic_vector;
valid : std_logic;
end record;
end package pkg;
|
library IEEE, stratixgx_gxb;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use stratixgx_gxb.hssi_pack.all;
package STRATIXGX_HSSI_COMPONENTS is
-- Beginning of testing section
-- these components are added for testing
component stratixgx_comp_fifo
GENERIC (
use_rate_match_fifo : string := "true";
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : string := "true"; -- new in 3.0 SP2
channel_num : integer := 0
);
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
errdetectinpre : IN std_logic;
syncstatusinpre : IN std_logic;
disperrinpre : IN std_logic;
patterndetectinpre : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
re : IN std_logic;
we : IN std_logic;
fifordin : IN std_logic;
disablefifordin : IN std_logic;
disablefifowrin : IN std_logic;
alignstatus : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
errdetectout : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
codevalid : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostful : OUT std_logic;
fifoempty : OUT std_logic;
fifoalmostempty : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
fifordout : OUT std_logic);
end component;
component stratixgx_deskew_fifo
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
writeclock : IN std_logic;
readclock : IN std_logic;
adetectdeskew : OUT std_logic;
fiforesetrd : IN std_logic;
enabledeskew : IN std_logic;
reset : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
dataoutpre : OUT std_logic_vector(9 DOWNTO 0);
errdetect : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
errdetectpre : OUT std_logic;
syncstatuspre : OUT std_logic;
disperrpre : OUT std_logic;
patterndetectpre : OUT std_logic;
rdalign : OUT std_logic);
END component;
component stratixgx_rx_core
GENERIC (
channel_width : integer := 10;
use_double_data_mode : string := "false";
use_channel_align : string := "false";
use_8b_10b_mode : string := "true";
synchronization_mode : string := "none";
align_pattern : string := "0000000101111100");
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
errdetectin : IN std_logic;
patterndetectin : IN std_logic;
decdatavalid : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
post8b10b : IN std_logic_vector(9 DOWNTO 0);
datain : IN std_logic_vector(9 DOWNTO 0);
xgmctrlin : IN std_logic;
ctrldetectin : IN std_logic;
syncstatusin : IN std_logic;
disparityerrin : IN std_logic;
syncstatus : OUT std_logic_vector(1 DOWNTO 0);
errdetect : OUT std_logic_vector(1 DOWNTO 0);
ctrldetect : OUT std_logic_vector(1 DOWNTO 0);
disparityerr : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(19 DOWNTO 0);
a1a2sizeout : OUT std_logic_vector(1 DOWNTO 0);
clkout : OUT std_logic);
END component;
component stratixgx_tx_core
GENERIC (
use_double_data_mode : string := "false";
use_fifo_mode : string := "true";
transmit_protocol : string := "none";
channel_width : integer := 10;
KCHAR : std_logic := '0';
ECHAR : std_logic := '0');
PORT (
reset : IN std_logic;
datain : IN std_logic_vector(19 DOWNTO 0);
writeclk : IN std_logic;
readclk : IN std_logic;
ctrlena : IN std_logic_vector(1 DOWNTO 0);
forcedisp : IN std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(9 DOWNTO 0);
forcedispout : OUT std_logic;
ctrlenaout : OUT std_logic;
rdenasync : OUT std_logic;
xgmctrlena : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
pre8b10bdataout : OUT std_logic_vector(7 DOWNTO 0));
END component;
component stratixgx_8b10b_encoder
GENERIC (
transmit_protocol : string := "none";
use_8b_10b_mode : string := "true";
force_disparity_mode : string := "false");
PORT (
clk : IN std_logic;
reset : IN std_logic;
xgmctrl : IN std_logic;
kin : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
datain : IN std_logic_vector(7 DOWNTO 0);
forcedisparity : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
parafbkdataout : OUT std_logic_vector(9 DOWNTO 0));
END component;
component stratixgx_8b10b_decoder
PORT (
clk : IN std_logic;
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
datainvalid : IN std_logic;
datain : IN std_logic_vector(9 DOWNTO 0);
valid : OUT std_logic;
dataout : OUT std_logic_vector(7 DOWNTO 0);
tenBdata : OUT std_logic_vector(9 DOWNTO 0);
errdetect : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
kout : OUT std_logic;
rderr : OUT std_logic;
decdatavalid : OUT std_logic;
xgmdatavalid : OUT std_logic;
xgmrunningdisp : OUT std_logic;
xgmctrldet : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0));
end component;
component stratixgx_hssi_rx_serdes
generic (
channel_width : integer := 10;
rlv_length : integer := 1;
run_length_enable : String := "false";
cruclk_period : integer :=5000;
cruclk_multiplier : integer :=4;
use_cruclk_divider : String := "false";
use_double_data_mode : String := "false";
tipd_0 : VitalDelayType01 := DefpropDelay01
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
areset : in std_logic := '0';
feedback : in std_logic := '0';
fbkcntl : in std_logic := '0';
dataout : out std_logic_vector(9 downto 0);
clkout : out std_logic;
rlv : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
signaldetect: out std_logic
);
end component;
component stratixgx_hssi_tx_serdes
generic (
channel_width : integer := 10
);
port (
clk : in std_logic := '0';
clk1 : in std_logic := '0';
datain : in std_logic_vector(9 downto 0) := "0000000000";
serialdatain : in std_logic := '0';
srlpbk : in std_logic := '0';
areset : in std_logic := '0';
dataout : out std_logic
);
end component;
component stratixgx_hssi_word_aligner
generic (
channel_width : integer := 10;
align_pattern_length: integer := 10;
align_pattern : string := "0000000101111100";
synchronization_mode: string := "XAUI";
use_8b_10b_mode : string := "true";
use_auto_bit_slip : string := "true"
);
port (
datain : in std_logic_vector(9 downto 0) := "0000000000";
clk : in std_logic := '0';
softreset : in std_logic := '0';
enacdet : in std_logic := '0';
bitslip : in std_logic := '0';
a1a2size : in std_logic := '0';
aligneddata : out std_logic_vector(9 downto 0);
aligneddatapre : out std_logic_vector(9 downto 0);
invalidcode : out std_logic;
invalidcodepre : out std_logic;
syncstatus : out std_logic;
syncstatusdeskew : out std_logic;
disperr : out std_logic;
disperrpre : out std_logic;
patterndetect : out std_logic;
patterndetectpre : out std_logic
);
end component;
component stratixgx_xgm_rx_sm
port (
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0)
);
end component;
component stratixgx_xgm_tx_sm
port (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
resetall : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0));
end component;
component stratixgx_xgm_dskw_sm
port (
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic);
end component;
-- End of testing section
component stratixgx_hssi_receiver
generic (
channel_num : integer := 1;
channel_width : integer := 20;
deserialization_factor : integer := 10;
run_length : integer := 4;
run_length_enable : String := "false";
use_8b_10b_mode : String := "false";
use_double_data_mode : String := "false";
use_rate_match_fifo : String := "false";
rate_matching_fifo_mode : String := "none";
use_channel_align : String := "false";
use_symbol_align : String := "true";
use_auto_bit_slip : String := "false";
use_parallel_feedback : String := "false";
use_post8b10b_feedback : String := "false";
send_reverse_parallel_feedback : String := "false";
synchronization_mode : String := "none";
align_pattern : String := "0000000000000000";
align_pattern_length : integer := 7;
infiniband_invalid_code : integer := 0;
disparity_mode : String := "false";
clk_out_mode_reference : String := "false";
cruclk_period : integer := 5000;
cruclk_multiplier : integer := 4;
use_cruclk_divider : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
use_equalizer_ctrl_signal : String := "false";
enable_dc_coupling : String := "false";
equalizer_ctrl_setting : integer := 20;
signal_threshold_select : integer := 2;
vco_bypass : String := "false";
force_signal_detect : String := "false";
bandwidth_type : String := "low";
for_engineering_sample_device : String := "true"; -- new in 3.0 SP2
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_cruclk : VitalDelayType01 := DefpropDelay01;
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_post8b10b : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_slpbk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_enacdet : VitalDelayType01 := DefpropDelay01;
tipd_we : VitalDelayType01 := DefpropDelay01;
tipd_re : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tsetup_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_dataout_posedge : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_syncstatus_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_patterndetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_ctrldetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_errdetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_disperr_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_a1a2sizeout_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_fifofull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoempty_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostfull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostempty_posedge : VitalDelayType01 := DefPropDelay01
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
pllclk : in std_logic := '0';
masterclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
serialfdbk : in std_logic := '0';
parallelfdbk : in std_logic_vector(9 downto 0) := "0000000000";
post8b10b : in std_logic_vector(9 downto 0) := "0000000000";
slpbk : in std_logic := '0';
bitslip : in std_logic := '0';
enacdet : in std_logic := '0';
we : in std_logic := '0';
re : in std_logic := '0';
alignstatus : in std_logic := '0';
disablefifordin : in std_logic := '0';
disablefifowrin : in std_logic := '0';
fifordin : in std_logic := '0';
enabledeskew : in std_logic := '0';
fiforesetrd : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrlin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
a1a2size : in std_logic := '0';
locktorefclk : in std_logic := '0';
locktodata : in std_logic := '0';
equalizerctrl : in std_logic_vector(2 downto 0) := "000";
syncstatus : out std_logic_vector(1 downto 0);
patterndetect : out std_logic_vector(1 downto 0);
ctrldetect : out std_logic_vector(1 downto 0);
errdetect : out std_logic_vector(1 downto 0);
disperr : out std_logic_vector(1 downto 0);
syncstatusdeskew : out std_logic;
adetectdeskew : out std_logic;
rdalign : out std_logic;
dataout : out std_logic_vector(19 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrldet : out std_logic;
xgmrunningdisp : out std_logic;
xgmdatavalid : out std_logic;
fifofull : out std_logic;
fifoalmostfull : out std_logic;
fifoempty : out std_logic;
fifoalmostempty : out std_logic;
disablefifordout : out std_logic;
disablefifowrout : out std_logic;
fifordout : out std_logic;
signaldetect : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
rlv : out std_logic;
clkout : out std_logic;
recovclkout : out std_logic;
bisterr : out std_logic := '0';
bistdone : out std_logic := '1';
a1a2sizeout : out std_logic_vector(1 downto 0)
);
end component;
component stratixgx_hssi_transmitter
generic (
channel_num : integer := 1;
channel_width : integer := 20;
serialization_factor: integer := 10;
use_8b_10b_mode : String := "false";
use_double_data_mode: String := "false";
use_fifo_mode : String := "false";
use_reverse_parallel_feedback : String := "false";
force_disparity_mode: String := "false";
transmit_protocol : String := "none";
use_vod_ctrl_signal : String := "false";
use_preemphasis_ctrl_signal : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
vod_ctrl_setting : integer := 4;
preemphasis_ctrl_setting : integer := 5;
termination : integer := 0;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_fastpllclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_forcedisparity : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_srlpbk : VitalDelayType01 := DefpropDelay01;
tsetup_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_forcedisparity_coreclk_noedge_posedge: VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_forcedisparity_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst)
);
port (
datain : in std_logic_vector(19 downto 0);
pllclk : in std_logic := '0';
fastpllclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
ctrlenable : in std_logic_vector(1 downto 0) := "00";
forcedisparity : in std_logic_vector(1 downto 0) := "00";
serialdatain : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrl : in std_logic := '0';
srlpbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
vodctrl : in std_logic_vector(2 downto 0) := "000";
preemphasisctrl : in std_logic_vector(2 downto 0) := "000";
dataout : out std_logic;
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic;
rdenablesync : out std_logic;
parallelfdbkdata : out std_logic_vector(9 downto 0);
pre8b10bdata : out std_logic_vector(9 downto 0)
);
end component;
component stratixgx_xgm_interface
generic (
use_continuous_calibration_mode : String := "false";
mode_is_xaui : String := "false";
rx_ppm_setting_0 : integer := 0;
rx_ppm_setting_1 : integer := 0;
digital_test_output_select : integer := 0;
analog_test_output_signal_select : integer := 0;
analog_test_output_channel_select : integer := 0;
use_rx_calibration_status : String := "false";
use_global_serial_loopback : String := "false";
rx_calibration_test_write_value : integer := 0;
enable_rx_calibration_test_write : String := "false";
tx_calibration_test_write_value : integer := 0;
enable_tx_calibration_test_write : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_txdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_txctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_rxrunningdisp : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_resetall : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_syncstatus : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdalign : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01
);
PORT (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
devpor : IN std_logic := '0';
devclrn : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
resetout : OUT std_logic;
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
-- NEW MDIO/PE ONLY PORTS
mdioclk : IN std_logic := '0';
mdiodisable : IN std_logic := '0';
mdioin : IN std_logic := '0';
rxppmselect : IN std_logic := '0';
scanclk : IN std_logic := '0';
scanin : IN std_logic := '0';
scanmode : IN std_logic := '0';
scanshift : IN std_logic := '0';
-- NEW MDIO/PE ONLY PORTS
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
digitalsmtest : OUT std_logic_vector(3 DOWNTO 0);
mdiooe : OUT std_logic;
mdioout : OUT std_logic;
scanout : OUT std_logic;
test : OUT std_logic;
-- RESET PORTS
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
pllreset : IN std_logic := '0';
pllenable : IN std_logic := '1';
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
pllresetout : OUT std_logic
);
end component;
end stratixgx_hssi_components;
|
architecture rtl of fifo is
alias designator : subtype_indication is name;
alias designator is name;
alias designator : subtype_indication is name;
alias designator : (subtype_indication) is name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SW_standalone_axi_gpio_0_0_arch OF design_SW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SW_standalone_axi_gpio_0_0_arch;
|
-- Twofish_ecb_encryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench256 is
end ecb_encryption_monte_carlo_testbench256;
architecture ecb_encryption256_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round256
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_encryption_circuit: twofish_encryption_round256
port map (
in1_ter256 => to_round(127 downto 96),
in2_ter256 => to_round(95 downto 64),
in3_ter256 => to_round(63 downto 32),
in4_ter256 => to_round(31 downto 0),
in_Sfirst_ter256 => Sfirst,
in_Ssecond_ter256 => Ssecond,
in_Sthird_ter256 => Sthird,
in_Sfourth_ter256 => Sfourth,
in_key_up_ter256 => key_up,
in_key_down_ter256 => key_down,
out1_ter256 => to_encr_reg128(127 downto 96),
out2_ter256 => to_encr_reg128(95 downto 64),
out3_ter256 => to_encr_reg128(63 downto 32),
out4_ter256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption256_monte_carlo_testbench_arch;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_9 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_9 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 9, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_9 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_9 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 9, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_9 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_9 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 9, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_9 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_9 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 9, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_9 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_9 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 9, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
------------
-- pcore top level wrapper
-- generated at 2008-02-11 12:40:48.826899 by 'mkhwtask.py hwt_semaphore_post 1 ../src/hwt_semaphore_post.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_semaphore_post_i : entity hwt_semaphore_post
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CSA16bits IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END CSA16bits ;
ARCHITECTURE strc_CSA16bits OF CSA16bits IS
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL Outs10, Outs11, Outs20, Outs21, Outs30, Outs31, Outs40, Outs41: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Couts10, Couts11, Couts20, Couts21, Couts30, Couts31, Couts40, Couts41: STD_LOGIC;
SIGNAL sel1,sel2,sel3: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg16Bit
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
END COMPONENT ;
COMPONENT RCA
port (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT mux84
port (
In0, In1: in std_logic_vector(3 downto 0);
sel: in std_logic;
Outs : out std_logic_vector(3 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som10: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'0',
CarryOut=>Couts10,
SomaResult=>Outs10
);
Som11: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'1',
CarryOut=>Couts11,
SomaResult=>Outs11
);
Mux1: mux84 PORT MAP (
In1=>Outs11,
In0=>Outs10,
sel=>Cin_sig,
Outs=>SomaT1
);
sel1 <= Couts10 OR (Couts11 AND Cin_sig);
Som20: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'0',
CarryOut=>Couts20,
SomaResult=>Outs20
);
Som21: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'1',
CarryOut=>Couts21,
SomaResult=>Outs21
);
Mux2: mux84 PORT MAP (
In1=>Outs21,
In0=>Outs20,
sel=>sel1,
Outs=>SomaT2
);
sel2 <= Couts20 OR (Couts21 AND sel1);
--asdfasdf
Som30: RCA PORT MAP (
val1 => A_sig(11 DOWNTO 8),
val2 => B_sig(11 DOWNTO 8),
CarryIn=>'0',
CarryOut=>Couts30,
SomaResult=>Outs30
);
Som31: RCA PORT MAP (
val1 => A_sig(11 DOWNTO 8),
val2 => B_sig(11 DOWNTO 8),
CarryIn=>'1',
CarryOut=>Couts31,
SomaResult=>Outs31
);
Mux3: mux84 PORT MAP (
In1=>Outs31,
In0=>Outs30,
sel=>sel2,
Outs=>SomaT3
);
sel3 <= Couts30 OR (Couts31 AND sel2);
Som40: RCA PORT MAP (
val1 => A_sig(15 DOWNTO 12),
val2 => B_sig(15 DOWNTO 12),
CarryIn=>'0',
CarryOut=>Couts40,
SomaResult=>Outs40
);
Som41: RCA PORT MAP (
val1 => A_sig(15 DOWNTO 12),
val2 => B_sig(15 DOWNTO 12),
CarryIn=>'1',
CarryOut=>Couts41,
SomaResult=>Outs41
);
Mux4: mux84 PORT MAP (
In1=>Outs41,
In0=>Outs40,
sel=>sel3,
Outs=>SomaT4
);
Cout_sig <= Couts40 OR (Couts41 AND sel3);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CSA16bits ; |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_rnd;
architecture behaviour of keyb_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st1: std_logic_vector(4 downto 0) := "00010";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st3: std_logic_vector(4 downto 0) := "11110";
constant st4: std_logic_vector(4 downto 0) := "11111";
constant st5: std_logic_vector(4 downto 0) := "10001";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st8: std_logic_vector(4 downto 0) := "01111";
constant st9: std_logic_vector(4 downto 0) := "00001";
constant st10: std_logic_vector(4 downto 0) := "10000";
constant st11: std_logic_vector(4 downto 0) := "11010";
constant st12: std_logic_vector(4 downto 0) := "11000";
constant st13: std_logic_vector(4 downto 0) := "01000";
constant st14: std_logic_vector(4 downto 0) := "00100";
constant st15: std_logic_vector(4 downto 0) := "01001";
constant st16: std_logic_vector(4 downto 0) := "00110";
constant st17: std_logic_vector(4 downto 0) := "11100";
constant st18: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_nov;
architecture behaviour of ex4_nov is
constant s1: std_logic_vector(3 downto 0) := "0010";
constant s3: std_logic_vector(3 downto 0) := "1101";
constant s2: std_logic_vector(3 downto 0) := "0011";
constant s5: std_logic_vector(3 downto 0) := "1100";
constant s7: std_logic_vector(3 downto 0) := "0000";
constant s11: std_logic_vector(3 downto 0) := "1111";
constant s12: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "1110";
constant s4: std_logic_vector(3 downto 0) := "0110";
constant s13: std_logic_vector(3 downto 0) := "1001";
constant s14: std_logic_vector(3 downto 0) := "0111";
constant s6: std_logic_vector(3 downto 0) := "1000";
constant s9: std_logic_vector(3 downto 0) := "0100";
constant s10: std_logic_vector(3 downto 0) := "1011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---------";
case current_state is
when s1 =>
if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
end if;
when s3 =>
if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
end if;
when s2 =>
if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
end if;
when s5 =>
if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
end if;
when s7 =>
if std_match(input, "10----") then next_state <= s7; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
end if;
when s11 =>
if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
end if;
when s12 =>
if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
end if;
when s8 =>
if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
end if;
when s4 =>
if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
end if;
when s13 =>
if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
end if;
when s14 =>
if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
end if;
when s6 =>
if std_match(input, "10----") then next_state <= s6; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
end if;
when s9 =>
if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
end if;
when s10 =>
if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
end if;
when others => next_state <= "----"; output <= "---------";
end case;
end process;
end behaviour;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: measures a input frequency relativ to a reference frequency
--
-- Description:
-- ------------------------------------
-- This module counts 1 second in a reference timer at reference clock. This
-- reference time is used to start and stop a timer at input clock. The counter
-- value is the measured frequency in Hz.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
entity misc_FrequencyMeasurement is
generic (
REFERENCE_CLOCK_FREQ : FREQ := 100 MHz
);
port (
Reference_Clock : in STD_LOGIC;
Input_Clock : in STD_LOGIC;
Start : in STD_LOGIC;
Done : out STD_LOGIC;
Result : out T_SLV_32
);
end entity;
architecture rtl of misc_FrequencyMeasurement is
constant TIMEBASE_COUNTER_MAX : POSITIVE := TimingToCycles(ite(SIMULATION, 10 us, 1 sec), REFERENCE_CLOCK_FREQ);
constant TIMEBASE_COUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASE_COUNTER_MAX);
signal TimeBase_Counter_rst : STD_LOGIC;
signal TimeBase_Counter_s : SIGNED(TIMEBASE_COUNTER_BITS downto 0) := to_signed(-1, TIMEBASE_COUNTER_BITS + 1);
signal TimeBase_Counter_nxt : SIGNED(TIMEBASE_COUNTER_BITS downto 0);
signal TimeBase_Counter_uf : STD_LOGIC;
signal Stop : STD_LOGIC;
signal sync_Start : STD_LOGIC;
signal sync_Stop : STD_LOGIC;
signal sync1_Busy : T_SLV_2;
signal Frequency_Counter_en_r : STD_LOGIC := '0';
signal Frequency_Counter_us : UNSIGNED(31 downto 0) := (others => '0');
signal CaptureResult : STD_LOGIC;
signal CaptureResult_d : STD_LOGIC := '0';
signal Result_en : STD_LOGIC;
signal Result_d : T_SLV_32 := (others => '0');
signal Done_r : STD_LOGIC := '0';
begin
TimeBase_Counter_rst <= Start;
TimeBase_Counter_nxt <= TimeBase_Counter_s - 1;
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (TimeBase_Counter_rst = '1') then
TimeBase_Counter_s <= to_signed(TIMEBASE_COUNTER_MAX - 2, TimeBase_Counter_s'length);
elsif (TimeBase_Counter_uf = '0') then
TimeBase_Counter_s <= TimeBase_Counter_nxt;
end if;
end if;
end process;
TimeBase_Counter_uf <= TimeBase_Counter_s(TimeBase_Counter_s'high);
Stop <= not TimeBase_Counter_s(TimeBase_Counter_s'high) and TimeBase_Counter_nxt(TimeBase_Counter_nxt'high);
sync1 : entity poc.sync_Strobe
generic map (
BITS => 2 -- number of bit to be synchronized
)
port map (
Clock1 => Reference_Clock, -- <Clock> input clock
Clock2 => Input_Clock, -- <Clock> output clock
Input(0) => Start, -- @Clock1 input vector
Input(1) => Stop, --
Output(0) => sync_Start, -- @Clock2: output vector
Output(1) => sync_Stop, --
Busy => sync1_Busy
);
Frequency_Counter_en_r <= ffrs(q => Frequency_Counter_en_r, set => sync_Start, rst => sync_Stop) when rising_edge(Input_Clock);
process(Input_Clock)
begin
if rising_edge(Input_Clock) then
if (sync_Start = '1') then
Frequency_Counter_us <= to_unsigned(1, Frequency_Counter_us'length);
elsif (Frequency_Counter_en_r = '1') then
Frequency_Counter_us <= Frequency_Counter_us + 1;
end if;
end if;
end process;
CaptureResult <= sync1_Busy(1);
CaptureResult_d <= CaptureResult when rising_edge(Reference_Clock);
Result_en <= CaptureResult_d and not CaptureResult;
-- Result_d can becaptured from Frequency_Counter_us, because it's stable
-- for more than one clock cycle and will not change until the next Start
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (Result_en = '1') then
Result_d <= std_logic_vector(Frequency_Counter_us);
Done_r <= '1';
elsif (Start = '1') then
Done_r <= '0';
end if;
end if;
end process;
Done <= Done_r;
Result <= Result_d;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: measures a input frequency relativ to a reference frequency
--
-- Description:
-- ------------------------------------
-- This module counts 1 second in a reference timer at reference clock. This
-- reference time is used to start and stop a timer at input clock. The counter
-- value is the measured frequency in Hz.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
entity misc_FrequencyMeasurement is
generic (
REFERENCE_CLOCK_FREQ : FREQ := 100 MHz
);
port (
Reference_Clock : in STD_LOGIC;
Input_Clock : in STD_LOGIC;
Start : in STD_LOGIC;
Done : out STD_LOGIC;
Result : out T_SLV_32
);
end entity;
architecture rtl of misc_FrequencyMeasurement is
constant TIMEBASE_COUNTER_MAX : POSITIVE := TimingToCycles(ite(SIMULATION, 10 us, 1 sec), REFERENCE_CLOCK_FREQ);
constant TIMEBASE_COUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASE_COUNTER_MAX);
signal TimeBase_Counter_rst : STD_LOGIC;
signal TimeBase_Counter_s : SIGNED(TIMEBASE_COUNTER_BITS downto 0) := to_signed(-1, TIMEBASE_COUNTER_BITS + 1);
signal TimeBase_Counter_nxt : SIGNED(TIMEBASE_COUNTER_BITS downto 0);
signal TimeBase_Counter_uf : STD_LOGIC;
signal Stop : STD_LOGIC;
signal sync_Start : STD_LOGIC;
signal sync_Stop : STD_LOGIC;
signal sync1_Busy : T_SLV_2;
signal Frequency_Counter_en_r : STD_LOGIC := '0';
signal Frequency_Counter_us : UNSIGNED(31 downto 0) := (others => '0');
signal CaptureResult : STD_LOGIC;
signal CaptureResult_d : STD_LOGIC := '0';
signal Result_en : STD_LOGIC;
signal Result_d : T_SLV_32 := (others => '0');
signal Done_r : STD_LOGIC := '0';
begin
TimeBase_Counter_rst <= Start;
TimeBase_Counter_nxt <= TimeBase_Counter_s - 1;
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (TimeBase_Counter_rst = '1') then
TimeBase_Counter_s <= to_signed(TIMEBASE_COUNTER_MAX - 2, TimeBase_Counter_s'length);
elsif (TimeBase_Counter_uf = '0') then
TimeBase_Counter_s <= TimeBase_Counter_nxt;
end if;
end if;
end process;
TimeBase_Counter_uf <= TimeBase_Counter_s(TimeBase_Counter_s'high);
Stop <= not TimeBase_Counter_s(TimeBase_Counter_s'high) and TimeBase_Counter_nxt(TimeBase_Counter_nxt'high);
sync1 : entity poc.sync_Strobe
generic map (
BITS => 2 -- number of bit to be synchronized
)
port map (
Clock1 => Reference_Clock, -- <Clock> input clock
Clock2 => Input_Clock, -- <Clock> output clock
Input(0) => Start, -- @Clock1 input vector
Input(1) => Stop, --
Output(0) => sync_Start, -- @Clock2: output vector
Output(1) => sync_Stop, --
Busy => sync1_Busy
);
Frequency_Counter_en_r <= ffrs(q => Frequency_Counter_en_r, set => sync_Start, rst => sync_Stop) when rising_edge(Input_Clock);
process(Input_Clock)
begin
if rising_edge(Input_Clock) then
if (sync_Start = '1') then
Frequency_Counter_us <= to_unsigned(1, Frequency_Counter_us'length);
elsif (Frequency_Counter_en_r = '1') then
Frequency_Counter_us <= Frequency_Counter_us + 1;
end if;
end if;
end process;
CaptureResult <= sync1_Busy(1);
CaptureResult_d <= CaptureResult when rising_edge(Reference_Clock);
Result_en <= CaptureResult_d and not CaptureResult;
-- Result_d can becaptured from Frequency_Counter_us, because it's stable
-- for more than one clock cycle and will not change until the next Start
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (Result_en = '1') then
Result_d <= std_logic_vector(Frequency_Counter_us);
Done_r <= '1';
elsif (Start = '1') then
Done_r <= '0';
end if;
end if;
end process;
Done <= Done_r;
Result <= Result_d;
end;
|
-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_cuff_ic_n2
-- Description: Configuration for tb_tst_rlink_cuff_ic_n2 for
-- tb_nexys2_fusp_cuff
--
-- Dependencies: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- To test: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-01-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_cuff_ic_n2 of tb_nexys2_fusp_cuff is
for sim
for all : nexys2_fusp_cuff_aif
use entity work.sys_tst_rlink_cuff_n2;
end for;
end for;
end tb_tst_rlink_cuff_ic_n2;
|
--------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 09:00:40 11/Okt/2013
-- Design Name: parallel_to_i2s
-- Description:
--
-- VHDL Test Bench for module: i2s_out
--
-- version: 00.01
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY i2s_out_tb_vhd IS
END i2s_out_tb_vhd;
ARCHITECTURE behavior OF i2s_out_tb_vhd IS
constant width : integer := 24;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2s_out
generic(width : integer := width);
PORT(
LR_CLK : IN std_logic;
BIT_CLK : IN std_logic;
DOUT : OUT std_logic;
RESET : IN std_logic;
DATA_L : IN std_logic_vector(width-1 downto 0);
DATA_R : IN std_logic_vector(width-1 downto 0);
DATA_RDY_L : OUT std_logic;
DATA_RDY_R : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL LR_CLK : std_logic := '0';
SIGNAL BIT_CLK : std_logic := '0';
SIGNAL DOUT : std_logic := '0';
SIGNAL RESET : std_logic := '0';
--Outputs
SIGNAL DATA_L : std_logic_vector(width-1 downto 0);
SIGNAL DATA_R : std_logic_vector(width-1 downto 0);
SIGNAL DATA_RDY_L : std_logic;
SIGNAL DATA_RDY_R : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2s_out
PORT MAP(
LR_CLK => LR_CLK,
BIT_CLK => BIT_CLK,
DOUT => DOUT,
RESET => RESET,
DATA_L => DATA_L,
DATA_R => DATA_R,
DATA_RDY_L => DATA_RDY_L,
DATA_RDY_R => DATA_RDY_R
);
-- creates a reset signal at the start of the sequence
p_reset : process
begin
RESET <= '0';
--LR_CK <= '1';
wait for 640 ns;
RESET <= '1';
-- Reset finished
wait;
end process p_reset;
-- generates the bit clock signal
p_bit_clk : process
begin
BIT_CLK <= '0';
wait for 10 ns;
BIT_CLK <= '1';
wait for 10 ns;
end process p_bit_clk;
-- generates the LR clock signal
p_lr_clk : process
begin
LR_CLK <= '0';
wait for 480 ns;
LR_CLK <= '1';
wait for 480 ns;
end process p_lr_clk;
-- provides the parallel input signal
p_dout : process
variable i : POSITIVE :=1;
begin
wait for 20 ns;
DATA_L <= "111111111111111111111111";
DATA_R <= "111111111111111111111111";
wait for 480 ns;
DATA_L <= "001100000000000000000000";
DATA_R <= "001100000000000000000000";
wait for 480 ns;
DATA_L <= "110011001100110011001100";
DATA_R <= "110011001100110011001100";
wait for 480 ns;
DATA_L <= "101010101010101010101010";
DATA_R <= "101010101010101010101010";
wait for 480 ns;
DATA_L <= "110011001100110011001100";
DATA_R <= "110011001100110011001100";
wait for 480 ns;
DATA_L <= "110011000000000000000011";
DATA_R <= "110011000000000000000011";
wait for 480 ns;
DATA_L <= "001100000000000000000000";
DATA_R <= "001100000000000000000000";
wait for 480 ns;
DATA_L <= "111111111111111111111111";
DATA_R <= "111111111111111111111111";
wait for 480 ns;
DATA_L <= "001100000000000000000000";
DATA_R <= "001100000000000000000000";
wait for 480 ns;
DATA_L <= "110011001100110011001100";
DATA_R <= "110011001100110011001100";
wait for 480 ns;
DATA_L <= "101010101010101010101010";
DATA_R <= "101010101010101010101010";
wait for 480 ns;
DATA_L <= "110011001100110011001100";
DATA_R <= "110011001100110011001100";
wait for 480 ns;
DATA_L <= "110011000000000000000011";
DATA_R <= "110011000000000000000011";
wait for 480 ns;
DATA_L <= "001100000000000000000000";
DATA_R <= "001100000000000000000000";
wait for 480 ns;
end process p_dout;
END;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_funnel_tb is
end entity;
architecture behavioural of spi_funnel_tb is
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
signal cpuWrData : std_logic_vector(15 downto 0);
signal cpuWrValid : std_logic;
signal cpuRdData : std_logic_vector(15 downto 0);
signal cpuByteWide : std_logic;
signal sendData : std_logic_vector(7 downto 0);
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
signal recvReady : std_logic;
signal spiClk : std_logic;
signal spiDataOut : std_logic;
signal spiDataIn : std_logic;
begin
-- Instantiate the memory arbiter for testing
uut: entity work.spi_funnel
port map(
clk_in => sysClk,
reset_in => reset,
-- CPU I/O
cpuByteWide_in => cpuByteWide,
cpuWrData_in => cpuWrData,
cpuWrValid_in => cpuWrValid,
cpuRdData_out => cpuRdData,
cpuRdStrobe_in => '0',
-- Sending SPI data
sendData_out => sendData,
sendValid_out => sendValid,
sendReady_in => sendReady,
-- Receiving SPI data
recvData_in => recvData,
recvValid_in => recvValid,
recvReady_out => recvReady
);
-- SPI master
spi_master : entity work.spi_master
generic map(
SLOW_COUNT => "111011", -- spiClk = sysClk/120 (400kHz @48MHz)
FAST_COUNT => "000000", -- spiClk = sysClk/2 (24MHz @48MHz)
BIT_ORDER => '1' -- MSB first
)
port map(
clk_in => sysClk,
reset_in => reset,
-- Send pipe
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
-- Receive pipe
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
-- SPI interface
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset one cycle after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
process
begin
cpuByteWide <= 'X';
cpuWrData <= (others => 'X');
cpuWrValid <= '0';
spiDataIn <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"0306";
cpuByteWide <= '0';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"55CA";
cpuByteWide <= '1';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
--cpuByteWide <= '1';
--cpuWrData <= x"0055";
--cpuWrValid <= '1';
--wait until rising_edge(sysClk);
--cpuWrData <= (others => 'X');
--cpuWrValid <= '0';
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:01 01/21/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/BoothPartProdRed/BoothPartProdRed_tb.vhd
-- Project Name: BoothPartProdRed
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BoothPartProdRed
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY BoothPartProdRed_tb IS
END BoothPartProdRed_tb;
ARCHITECTURE behavior OF BoothPartProdRed_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BoothPartProdRed
PORT(
prod0 : IN std_logic_vector(19 downto 0);
prod1 : IN std_logic_vector(20 downto 2);
prod2 : IN std_logic_vector(22 downto 4);
prod3 : IN std_logic_vector(24 downto 6);
prod4 : IN std_logic_vector(26 downto 8);
prod5 : IN std_logic_vector(28 downto 10);
prod6 : IN std_logic_vector(30 downto 12);
prod7 : IN std_logic_vector(31 downto 14);
result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal prod0 : std_logic_vector(19 downto 0) := (others => '0');
signal prod1 : std_logic_vector(20 downto 2) := (others => '0');
signal prod2 : std_logic_vector(22 downto 4) := (others => '0');
signal prod3 : std_logic_vector(24 downto 6) := (others => '0');
signal prod4 : std_logic_vector(26 downto 8) := (others => '0');
signal prod5 : std_logic_vector(28 downto 10) := (others => '0');
signal prod6 : std_logic_vector(30 downto 12) := (others => '0');
signal prod7 : std_logic_vector(31 downto 14) := (others => '0');
--Outputs
signal result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
prod0 <= "11111111111111111111";
prod1 <= "1111111111111111111";
prod2 <= "0000000000000000001";
prod3 <= "1111111111111111111";
prod4 <= "0000000000000000001";
prod5 <= "0000000000000000001";
prod6 <= "0000000000000000001";
prod7 <= "000000000000000001";
wait for 100 ns;
wait for 100 ns;
wait;
end process;
END;
|
-- ***************************************************************************
-- File Name: DSP_TX_FSM.vhd
-- File Description:
-- This module works on the received packet and sends a new packet to DSP.
-- The state machine(main if-else logic) has few states such as Initialization, receiver ready,
-- packet test, error packet action1, error packet action2, packet unload and packet trasnmission.
-- INITIALIZATION: reset all signals to default
-- RECEIVER READY : wait untill rx K-car goes low and timer expires
-- PACKET TEST: test the packet valididty by partially comparing known predefined sections in packet
-- ERROR ACTION1: check if this is the third consecutive packet with error. If it is then MMC shut down due to
-- communication error.
-- ERROR ACTION2: packet error has occured therefore prepare packet to send to DSP informing that
-- previous received packet had error.
-- PACKET UNLOAD: No packet error occured(it is probabilistically good assumption), therfore unload the packet data into
-- BRAM4.
-- PACKET TRANSMISSION: transmitt the packet to DSP. HMB_tx module make the packet ready to send and
-- loads into BRAM3. This module then simply sends it. This saves time for DSP communication.
--
-- ***************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
entity DSP_TX_FSM is
port
(
--%%%%%%%%%%%%%%%%%%%%% INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
USER_CLK : in std_logic;
START_OPERATION : in std_logic;
MASTER : in std_logic;
RX1_CHAR_IS_K : in std_logic;
USE_BRAM4 : in std_logic;
USE_BRAM3 : in std_logic;
HMB : in std_logic_vector(1 downto 0);
BRAM2_DOB : in std_logic_vector(7 downto 0);
BRAM3_DOB : in std_logic_vector(7 downto 0);
BRAM4_DOA : in std_logic_vector(7 downto 0);
--%%%%%%%%%%%%%%%%%%%%% OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PACKET_ERROR : out std_logic;
COMMUNICATION_ERROR : out std_logic;
REQ_BRAM3 : out std_logic;
DONE_BRAM3 : out std_logic;
REQ_BRAM4 : out std_logic;
DONE_BRAM4 : out std_logic;
RECEIVER_READY : out std_logic;
TX1_CHAR_IS_K : out std_logic;
BRAM2_ENB : out std_logic;
BRAM3_ENB : out std_logic;
BRAM4_ENA : out std_logic;
BRAM2_WEB : out std_logic;
BRAM3_WEB : out std_logic;
BRAM4_WEA : out std_logic;
TX1_DATA : out std_logic_vector(7 downto 0);
BRAM2_DIB : out std_logic_vector(7 downto 0);
BRAM3_DIB : out std_logic_vector(7 downto 0);
BRAM4_DIA : out std_logic_vector(7 downto 0);
BRAM2_ADDRB : out std_logic_vector(11 downto 0);
BRAM3_ADDRB : out std_logic_vector(11 downto 0);
BRAM4_ADDRA : out std_logic_vector(11 downto 0);
CHIPSCOPE_DEBUG : out std_logic_vector(9 downto 0)
);
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of DSP_TX_FSM : entity is "v4fx_mgtwizard_v1_7, Coregen v12.1";
end DSP_TX_FSM;
architecture RTL of DSP_TX_FSM is
----*********************************Signal Declarations********************************
signal master_i : std_logic := '0';
signal start_operation_i : std_logic := '0';
signal packet_error_i : std_logic := '0';
signal tx1_char_is_k_i : std_logic := '0';
signal bram2_enb_i : std_logic := '0';
signal bram2_web_i : std_logic := '0';
signal bram3_enb_i : std_logic := '0';
signal bram3_web_i : std_logic := '0';
signal bram4_ena_i : std_logic := '0';
signal bram4_wea_i : std_logic := '0';
signal req_bram3_i : std_logic := '0';
signal use_bram3_i : std_logic := '0';
signal done_bram3_i : std_logic := '0';
signal req_bram4_i : std_logic := '0';
signal use_bram4_i : std_logic := '0';
signal done_bram4_i : std_logic := '0';
signal communication_error_i: std_logic := '0';
signal rx1_char_is_k_i : std_logic := '0';
signal rx1_k_i : std_logic := '0';
signal hmb_i : std_logic_vector(1 downto 0) := "00";
signal TX_STATE : std_logic_vector(3 downto 0) := x"0";
signal tx1_data_i : std_logic_vector(7 downto 0) := x"00";
signal tx1_data1_i : std_logic_vector(7 downto 0) := x"00";
signal test_packet_i : std_logic_vector(7 downto 0) := x"00";
signal test_reg_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_dob_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_dib_i : std_logic_vector(7 downto 0) := x"00";
signal bram3_dob_i : std_logic_vector(7 downto 0) := x"00";
signal bram3_dib_i : std_logic_vector(7 downto 0) := x"00";
signal bram4_doa_i : std_logic_vector(7 downto 0) := x"00";
signal bram4_dia_i : std_logic_vector(7 downto 0) := x"00";
signal bram4_addra_i : std_logic_vector(11 downto 0) := x"000";
signal bram2_addrb_i : std_logic_vector(11 downto 0) := x"000";
signal bram3_addrb_i : std_logic_vector(11 downto 0) := x"000";
signal chipscope_debug_i : std_logic_vector(9 downto 0) := "0000000000";
constant byte_00 : std_logic_vector(7 downto 0):= x"00";
constant byte_FF : std_logic_vector(7 downto 0):= x"FF";
constant addr_000 : std_logic_vector(11 downto 0):= x"000";
constant addr_001 : std_logic_vector(11 downto 0):= x"001";
signal TOKEN_TIMER : integer range 0 to 1000 := 0;
signal S2_COUNT : integer range 0 to 100 := 0;
signal S3_COUNT : integer range 0 to 10 := 0;
signal S4_COUNT : integer range 0 to 10 := 0;
signal S4_LOAD_BRAM4_COUNT : integer range 0 to 500 := 0;
signal S5_TX_COUNT : integer range 0 to 500 := 0;
--*********************************Main Body of Code**********************************
------------------------------------------------------
begin
--%%%%%%%%%%% signal connections for INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
start_operation_i <= START_OPERATION;
master_i <= MASTER;
use_bram4_i <= USE_BRAM4;
use_bram3_i <= USE_BRAM3;
hmb_i <= HMB;
rx1_char_is_k_i <= RX1_CHAR_IS_K;
bram2_dob_i <= BRAM2_DOB;
bram3_dob_i <= BRAM3_DOB;
bram4_doa_i <= BRAM4_DOA;
--%%%%%%%%%%% signal connections for OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
REQ_BRAM3 <= req_bram3_i;
DONE_BRAM3 <= done_bram3_i;
REQ_BRAM4 <= req_bram4_i;
DONE_BRAM4 <= done_bram4_i;
TX1_CHAR_IS_K <= tx1_char_is_k_i;
BRAM2_ENB <= bram2_enb_i;
BRAM3_ENB <= bram3_enb_i;
BRAM4_ENA <= bram4_ena_i;
BRAM2_WEB <= bram2_web_i;
BRAM3_WEB <= bram3_web_i;
BRAM4_WEA <= bram4_wea_i;
TX1_DATA <= tx1_data1_i;
BRAM2_DIB <= bram2_dib_i;
BRAM3_DIB <= bram3_dib_i;
BRAM4_DIA <= bram4_dia_i;
BRAM2_ADDRB <= bram2_addrb_i;
BRAM3_ADDRB <= bram3_addrb_i;
BRAM4_ADDRA <= bram4_addra_i;
CHIPSCOPE_DEBUG <= chipscope_debug_i;
PACKET_ERROR <= packet_error_i;
COMMUNICATION_ERROR <= communication_error_i;
tx1_data1_i <= tx1_data_i;
process(USER_CLK)
begin
if (rising_edge(USER_CLK)) then
chipscope_debug_i(0) <= TX_STATE(0);
chipscope_debug_i(1) <= TX_STATE(1);
chipscope_debug_i(2) <= TX_STATE(2);
chipscope_debug_i(3) <= TX_STATE(3);
rx1_k_i <= rx1_char_is_k_i;
--###################################################################################################################################################
--###################################################################################################################################################
--###################################################################################################################################################
--##################################################### State Machine for DSP comunication ############################################################
--###################################################################################################################################################
--###################################################################################################################################################
--###################################################################################################################################################
--###################################################################################################################################################
--##################################################### Initialization state #############################################################
--###################################################################################################################################################
-- reset all to their default values
case TX_STATE is
when x"0" =>
-- reset unused signals to default value or keep last value
test_reg_i <= byte_00;
test_packet_i <= byte_00;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
communication_error_i <= '0';
bram2_enb_i <= '0';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram3_i <= '0';
done_bram3_i <= '0';
req_bram4_i <= '0';
done_bram4_i <= '0';
S2_COUNT <= 0;
S3_COUNT <= 0;
S4_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
S5_TX_COUNT <= 0;
TOKEN_TIMER <= 0;
-- during power ON this state would wait for start operation but to go high.
-- the initial power on time delay is defined in MMC_top_level module using 3 cascaded counters.
if(start_operation_i = '0')then
TX_STATE <= x"0";
elsif(start_operation_i = '1' and master_i = '0')then
TX_STATE <= x"0";
else -- only go to state 1 if the board is master(meaning connected to DSP)
TX_STATE <= x"1";
end if;
------------------------------------------------------------------------------------------------------------------------------------*/
--###################################################################################################################################################
--#################################################### Receiver ready state ##################################################################
--###################################################################################################################################################
when x"1" =>
-- reset unused signals to default value or keep last value
test_reg_i <= byte_00;
test_packet_i <= byte_00;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
communication_error_i <= '0';
bram2_enb_i <= '0';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram3_i <= '0';
done_bram3_i <= '0';
req_bram4_i <= '0';
done_bram4_i <= '0';
S2_COUNT <= 0;
S3_COUNT <= 0;
S4_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
S5_TX_COUNT <= 0;
-- when k-char goes low start timer and wait for 300 cycles during which
-- dsp_rx would load packet data into BRAM2
if(rx1_k_i = '0' or(TOKEN_TIMER > 0 and TOKEN_TIMER < 300))then
TOKEN_TIMER <= TOKEN_TIMER+1;
TX_STATE <= x"1";
elsif(rx1_k_i = '1' and TOKEN_TIMER = 300)then -- go to next state
TOKEN_TIMER <= 0;
TX_STATE <= x"2";
else
TOKEN_TIMER <= 0;
TX_STATE <= x"1";
end if;
--###################################################################################################################################################
--##################################################### Packet testing state #####################################################################
--###################################################################################################################################################
-- test part of the packet with predefined expected data. Any mismatch in this test would
-- mean the packet has error.
when x"2" =>
-- reset unused signals to default value or keep last value
test_reg_i <= byte_00;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
communication_error_i <= '0';
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram3_i <= '0';
done_bram3_i <= '0';
req_bram4_i <= '0';
done_bram4_i <= '0';
TOKEN_TIMER <= 0;
S3_COUNT <= 0;
S4_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
S5_TX_COUNT <= 0;
bram2_enb_i <= '1';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
test_packet_i <= bram2_dob_i;
--- this if logic tells which memory location to read packet from.
-- predefined data sequence is distributed over the length of packet.
if(S2_COUNT = 16)then
S2_COUNT <= S2_COUNT+1;
bram2_addrb_i <= x"023";
elsif(S2_COUNT = 28)then
S2_COUNT <= 0;
bram2_addrb_i <= addr_001;
else
S2_COUNT <= S2_COUNT+1;
bram2_addrb_i <= bram2_addrb_i+ addr_001;
end if;
-- this if logic compares the BRAM data with predefined data
-- if any mismatch occurs then remaining comparison is bypassed and it goes to next state
if(S2_COUNT <= 2)then
TX_STATE <= x"2";
elsif(S2_COUNT = 3 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 4 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 5 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 6 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 7 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 8 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 9 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 10 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 11 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 12 and test_packet_i = x"55")then
TX_STATE <= x"2";
elsif(S2_COUNT = 13 and test_packet_i = x"68")then
TX_STATE <= x"2";
elsif(S2_COUNT = 14 and test_packet_i = x"12")then
TX_STATE <= x"2";
elsif(S2_COUNT = 15 and test_packet_i = x"04")then
TX_STATE <= x"2";
elsif(S2_COUNT = 16 and test_packet_i = byte_00)then
TX_STATE <= x"2";
elsif(S2_COUNT = 17 and test_packet_i = byte_00)then
TX_STATE <= x"2";
elsif(S2_COUNT = 18 and test_packet_i = byte_00)then
TX_STATE <= x"2";
elsif(S2_COUNT = 19 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 20 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 21 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 22 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 23 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 24 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 25 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 26 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 27 and test_packet_i = x"AA")then
TX_STATE <= x"2";
elsif(S2_COUNT = 28 and test_packet_i = x"AA")then
TX_STATE <= x"5";
else
TX_STATE <= x"3";
end if;
--###################################################################################################################################################
--##################################################### error packet action 1 state ########################################################
--###################################################################################################################################################
-- every time packet error occurs increment a counter value in BRAM.
-- If this value is 3 then communication error has occured. MMC should shut down now.
when x"3" =>
-- reset unused signals to default value or keep last value
test_packet_i <= byte_00;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram3_i <= '0';
done_bram3_i <= '0';
req_bram4_i <= '0';
done_bram4_i <= '0';
TOKEN_TIMER <= 0;
S2_COUNT <= 0;
S4_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
S5_TX_COUNT <= 0;
bram2_enb_i <= '1';
test_reg_i <= bram2_dob_i;
if(S3_COUNT <= 2)then
bram2_web_i <= '0';
communication_error_i <= '0';
TX_STATE <= x"3";
bram2_dib_i <= byte_00;
bram2_addrb_i <= x"100";
S3_COUNT <= S3_COUNT+1;
elsif(S3_COUNT = 3)then
bram2_web_i <= '1';
communication_error_i <= '0';
TX_STATE <= x"3";
bram2_dib_i <= test_reg_i + x"01"; -- increment value in memory to keep track of consecutive packet errors
bram2_addrb_i <= x"100";
S3_COUNT <= S3_COUNT+1;
elsif(S3_COUNT = 4 and bram2_dob_i >= x"03")then
bram2_web_i <= '0';
communication_error_i <= '1'; -- communication error occured due to 3 straight error packets
TX_STATE <= x"4";
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
S3_COUNT <= 0;
else
bram2_web_i <= '0';
communication_error_i <= '0';
TX_STATE <= x"4";
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
S3_COUNT <= 0;
end if;
--###################################################################################################################################################
--########################################################## Error packet action 2 state ################################################################
--##################################################################################################################################################
-- the only action this state takes is to write '02' at '00F' memory address(or packet) location which would
-- let DSP know that there was an error detected in previous packet. The DSP should send the paket again
-- upon detecting 02 at that location in packet.
when x"4" =>
-- reset unused signals to default value or keep last value
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
communication_error_i<= '0';
bram2_enb_i <= '1';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram4_i <= '0';
done_bram4_i <= '0';
TOKEN_TIMER <= 0;
S2_COUNT <= 0;
S3_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
test_packet_i <= byte_00;
test_reg_i <= byte_00;
if(use_bram3_i = '0')then
-- request BRAM3 access.
-- It will stay in this condition untill acess is granted.
TX_STATE <= x"4";
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
req_bram3_i <= '1'; -- request access to BRAM3
done_bram3_i <= '0';
S4_COUNT <= 0;
else -- BRAM3 access granted
if(S4_COUNT = 0)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
S4_COUNT <= S4_COUNT+1;
TX_STATE <= x"4";
elsif(S4_COUNT = 1)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '1'; -- BRAM3 write enable
bram3_dib_i <= x"02"; -- write 02 indicating prev packet error to DSP
bram3_addrb_i <= x"00F";
S4_COUNT <= S4_COUNT+1;
TX_STATE <= x"4";
else
req_bram3_i <= '0';
done_bram3_i <= '1'; -- done using BRAM3
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
S4_COUNT <= 0;
TX_STATE <= x"6";
end if;
end if;
--###################################################################################################################################################
--##################################################### Packet Unload (Copy packet to BRAM4) ########################################################
--###################################################################################################################################################
-- in this state the some packet data from BRAM2 is loaded into BRAM4(which is shared by HMB_tx module)
-- HMB doesn't need entire packet came from DSP. It only needs te Vrefs and Commands.
-- Those necessary bytes are copied from BRAM2 to BRAM4.
when x"5" =>
-- reset unused signals to default value or keep last value
test_reg_i <= byte_00;
test_packet_i <= byte_00;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
communication_error_i <= '0';
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
req_bram3_i <= '0';
done_bram3_i <= '0';
TOKEN_TIMER <= 0;
S2_COUNT <= 0;
S3_COUNT <= 0;
S4_COUNT <= 0;
S5_TX_COUNT <= 1;
if(use_bram4_i = '0')then
-- request BRAM4 access.
-- It will stay in this if condition untill acess is granted.
TX_STATE <= x"5";
bram2_enb_i <= '1';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram4_i <= '1';
done_bram4_i <= '0';
S4_LOAD_BRAM4_COUNT <= 1;
else
bram2_enb_i <= '1';
-- use counter to
if(S4_LOAD_BRAM4_COUNT = 23)then
TX_STATE <= x"6";
req_bram4_i <= '1';
done_bram4_i <= '0';
S4_LOAD_BRAM4_COUNT <= 1;
else
TX_STATE <= x"5";
req_bram4_i <= '0';
done_bram4_i <= '1';
S4_LOAD_BRAM4_COUNT <= S4_LOAD_BRAM4_COUNT+1;
end if;
-- at each count increment BRAM address and
if(S4_LOAD_BRAM4_COUNT = 1)then
bram2_addrb_i <= addr_000;
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram4_ena_i <= '1';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
elsif(S4_LOAD_BRAM4_COUNT = 2)then
bram2_addrb_i <= x"011";
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram4_ena_i <= '1';
bram4_wea_i <= '1'; --write enable
bram4_dia_i <= x"FF";-- "FF" means new data from DSP is available(to let hmb_tx module know)
bram4_addra_i <= addr_000;
elsif(S4_LOAD_BRAM4_COUNT = 3)then
bram2_addrb_i <= bram2_addrb_i + addr_001;
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram4_ena_i <= '1';
bram4_wea_i <= '1';
bram4_dia_i <= x"FF";
bram4_addra_i <= addr_000;
elsif(S4_LOAD_BRAM4_COUNT = 4)then
bram2_addrb_i <= bram2_addrb_i + addr_001;
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram4_ena_i <= '1';
bram4_wea_i <= '1';
bram4_dia_i <= bram2_dob_i;
bram4_addra_i <= addr_001;
-- transfer all required data from BRAM2 to BRAM4
elsif(S4_LOAD_BRAM4_COUNT >= 5 and S4_LOAD_BRAM4_COUNT <= 21)then
bram2_addrb_i <= bram2_addrb_i+ addr_001;
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram4_ena_i <= '1';
bram4_wea_i <= '1';
bram4_dia_i <= bram2_dob_i;
bram4_addra_i <= bram4_addra_i+ addr_001;
elsif(S4_LOAD_BRAM4_COUNT = 22)then
bram2_addrb_i <= x"100";
bram2_web_i <= '1';
bram2_dib_i <= byte_00;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
else
bram2_addrb_i <= addr_000;
bram2_web_i <= '0';
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
end if;
end if;
--###################################################################################################################################################
--########################################################## Packet Transmission state ################################################################
--###################################################################################################################################################
-- this state transmitts data from BRAM3 to RocketIO MGT3.
-- after transmitting packet the state changes to receiver ready state.
when others =>
-- reset unused signals to default value or keep last value
communication_error_i<= '0';
bram2_enb_i <= '0';
bram2_web_i <= '0';
bram2_dib_i <= byte_00;
bram2_addrb_i <= addr_000;
bram4_ena_i <= '0';
bram4_wea_i <= '0';
bram4_dia_i <= byte_00;
bram4_addra_i <= addr_000;
req_bram4_i <= '0';
done_bram4_i <= '0';
TOKEN_TIMER <= 0;
S2_COUNT <= 0;
S3_COUNT <= 0;
S4_COUNT <= 0;
S4_LOAD_BRAM4_COUNT <= 0;
test_packet_i <= byte_00;
if(use_bram3_i = '0')then
-- request BRAM3 access.
-- It will stay in this condition untill acess is granted.
TX_STATE <= x"6";
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1';
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
req_bram3_i <= '1';
done_bram3_i <= '0';
S5_TX_COUNT <= 0;
else
if(S5_TX_COUNT <= 1)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1'; -- comma character is being sent
S5_TX_COUNT <= S5_TX_COUNT+1;
TX_STATE <= x"6";
elsif(S5_TX_COUNT >= 2 and S5_TX_COUNT <= 5)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_001;
tx1_data_i <= x"3C";-- send "3C" as comma character.
-- it was used to avoid some weird MGT receiver behaviour at the begining of packet receiption.
tx1_char_is_k_i <= '1'; -- comma character is being sent
S5_TX_COUNT <= S5_TX_COUNT+1;
TX_STATE <= x"6";
elsif(S5_TX_COUNT = 6)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= bram3_addrb_i+ addr_001;
tx1_data_i <= x"3C";
tx1_char_is_k_i <= '1'; -- comma character is being sent
S5_TX_COUNT <= S5_TX_COUNT+1;
TX_STATE <= x"6";
-- send the packet byte one by one to RocektIO
elsif(S5_TX_COUNT >= 7 and S5_TX_COUNT <= 174)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '1';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= bram3_addrb_i+ addr_001;
tx1_data_i <= bram3_dob_i;
tx1_char_is_k_i <= '0'; -- packet data is being sent
S5_TX_COUNT <= S5_TX_COUNT+1;
TX_STATE <= x"6";
elsif(S5_TX_COUNT >= 175 and S5_TX_COUNT <= 179)then
req_bram3_i <= '1';
done_bram3_i <= '0';
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
tx1_data_i <= x"3C";
tx1_char_is_k_i <= '1'; -- comma character is being sent
S5_TX_COUNT <= S5_TX_COUNT+1;
TX_STATE <= x"6";
else
req_bram3_i <= '0';
done_bram3_i <= '1'; -- done using BRAM3
bram3_enb_i <= '0';
bram3_web_i <= '0';
bram3_dib_i <= byte_00;
bram3_addrb_i <= addr_000;
tx1_data_i <= x"BC";
tx1_char_is_k_i <= '1'; -- comma character is being sent
TX_STATE <= x"1";
S5_TX_COUNT <= 0;
end if;
end if;
end case;
end if;
end process;
end RTL;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- disk(0): ctrl(31)=oper[1=rd, 0=wr], (30)=doInterrupt,
-- (11..0)=transferSize in words, aligned, <= 1024
-- disk(1): stat(31)=oper[1rd, 0wr], (30)=doInterrupt, (29)=busy,
-- (28)=interrupt pending, (27)=0,
-- (26)=errSize [transfer larger than 1024 words],
-- (25,24)=file error [00=ok, 01=status, 10=name, 11=mode].
-- (23..0)=last address referenced
-- disk(2): src [rd=disk file {0,1,2,3}, wr=memory address]
-- disk(3): dst [rd=memory address, wr=disk file {0,1,2,3}]
-- disk(4): interr, (1)=setIRQ, (0)=clrIRQ
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulates a disk controller with DMA transfers, word only transfers
-- transfers AT MOST 4Kbytes or 1024 memory cycles
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic; -- active in '0'
dma_aval : out std_logic; -- active in '0'
dma_type : out reg4);
constant NUM_BITS : integer := 32;
constant START_VALUE : reg32 := (others => '0');
end entity DISK;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulation version -- logic too complex for synthesis,
-- as there is no hw disk, model is for simulation
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of DISK is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
constant C_OPER : integer := 31; -- operation 1=rd, 0=wr
constant C_OPER_RD : std_logic := '1';
constant C_OPER_WR : std_logic := '0';
constant C_INT : integer := 30; -- interrupt when finished=1
constant S_BUSY : integer := 29; -- controller busy=1
constant I_SET : integer := 1; -- set IRQ
constant I_CLR : integer := 0; -- clear IRQ
constant DSK_OK : std_logic_vector(1 downto 0) := b"00";
constant DSK_STATUS : std_logic_vector(1 downto 0) := b"01";
constant DSK_NAME : std_logic_vector(1 downto 0) := b"10";
constant DSK_MODE : std_logic_vector(1 downto 0) := b"11";
type int_file is file of integer;
file my_file : int_file;
type dma_state is (st_init, st_idle, st_src, st_dst, st_check,
st_bus, st_xfer, st_int, st_assert, st_wait, st_err);
attribute SYN_ENCODING of dma_state : type is "safe";
signal dma_current_st, dma_next_st : dma_state;
signal dma_curr_dbg, current_int, ctrl_int, addr_int : integer;
signal ld_ctrl, s_ctrl, s_stat, ld_src, s_src, ld_dst, s_dst : std_logic;
signal busy, take_bus, ld_curr, rst_curr, en_curr : std_logic;
signal ctrl, src, dst, stat, datum : reg32 := (others => '0');
signal current, xfer_sz : reg10;
signal last_addr : reg24;
signal base_addr, curr_addr, address : reg32;
signal s_intw, s_intr, set_irq, clear_irq, s_dat, err_sz : std_logic;
signal d_set_interrupt, interrupt, do_interr, ld_last : std_logic;
signal done, last_one : boolean;
signal err_dsk : reg2 := b"00";
signal clear_hold_done, set_hold_done, d_set_hold_done, hold_done : std_logic;
begin -- functional
rdy <= ZERO; -- simulation only, never waits
s_ctrl <= '1' when sel = '0' and addr = b"000" else '0'; -- R+W
s_stat <= '1' when sel = '0' and addr = b"001" else '0'; -- R+W
s_src <= '1' when sel = '0' and addr = b"010" else '0'; -- W
s_dst <= '1' when sel = '0' and addr = b"011" else '0'; -- W
s_intw <= '1' when sel = '0' and addr = b"100" and wr = '0' else '0'; -- W
s_intr <= '1' when sel = '0' and addr = b"100" and wr = '1' else '0'; -- R
s_dat <= '1' when sel = '0' and addr = b"111" else '0'; -- W, DEBUG
ld_ctrl <= '0' when s_ctrl = '1' and wr = '0' else '1';
U_CTRL: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_ctrl, data_inp, ctrl);
ld_src <= '0' when s_src = '1' and wr = '0' else '1';
U_SRC: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_src, data_inp, src);
ld_dst <= '0' when s_dst = '1' and wr = '0' else '1';
U_DST: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_dst, data_inp, dst);
stat <= ctrl(C_OPER) & ctrl(C_INT) & busy & interrupt &
'0' & err_sz & err_dsk & last_addr;
with addr select
data_out <= ctrl when "000",
stat when "001",
src when "010",
dst when "011",
x"00000000" when others; -- interrupts, does RD-mod-WR
irq <= interrupt;
busReq <= take_bus;
dma_type <= b"1111"; -- always transfers words
dma_wr <= not(ctrl(C_OPER)) or not(take_bus); -- write to RAM
dma_aVal <= not(take_bus);
base_addr <= dst when ctrl(C_OPER) = C_OPER_RD else src;
curr_addr <= x"0000" & b"0000" & current & b"00"; -- word aligned
address <= std_logic_vector( signed(base_addr) + signed(curr_addr) );
dma_addr <= address;
dma_dout <= datum when ctrl(C_OPER) = C_OPER_RD else (others => 'X');
xfer_sz <= ctrl(9 downto 0) when ctrl_int <= 1024 else (others => '0');
addr_int <= to_integer(unsigned( ctrl(10 downto 0)));
err_sz <= YES when addr_int > 1024 else NO; -- check if size > 1024
rst_curr <= not(ld_curr) and rst;
U_CURRENT: countNup generic map (10) -- current DMA reference
port map (clk, rst_curr, '0', en_curr, xfer_sz, current);
last_one <= (current_int = (ctrl_int - 1));
ld_last <= BOOL2SL(not(last_one));
U_LAST_ADDR: registerN generic map (24, x"000000") -- for status
port map (clk, rst, ld_last, address(23 downto 0), last_addr);
current_int <= to_integer(unsigned(current));
ctrl_int <= to_integer(unsigned(ctrl(9 downto 0))); -- check == 1024
done <= ( (current = (ctrl(9 downto 0))) and (hold_done = NO) );
clear_hold_done <= en_curr; -- first increment, makes current /= 0
set_hold_done <= s_ctrl; -- wait 1 DMA access to check for done
d_set_hold_done <= (set_hold_done or hold_done) and not(clear_hold_done);
U_HOLD_DONE: FFDsimple port map (clk, rst, d_set_hold_done, hold_done);
-- file operations -----------------------------------------------------
U_FILE_CTRL: process(rst, clk, s_ctrl, s_src, s_dst, data_inp, ctrl)
variable status : file_open_status := open_ok;
variable i_status : integer := 0;
begin
if rst = '1' then
if (s_src = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_RD)
then -- read file
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.src", read_mode);
when b"01" => file_open(status, my_file, "DMA_1.src", read_mode);
when b"10" => file_open(status, my_file, "DMA_2.src", read_mode);
when b"11" => file_open(status, my_file, "DMA_3.src", read_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileRDopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if;
if (s_dst = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_WR)
then
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.dst", write_mode);
when b"01" => file_open(status, my_file, "DMA_1.dst", write_mode);
when b"10" => file_open(status, my_file, "DMA_2.dst", write_mode);
when b"11" => file_open(status, my_file, "DMA_3.dst", write_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileWRopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if; -- end write file
end if; -- reset
end process U_FILE_CTRL; -----------------------------------------------
clear_irq <= s_intw and data_inp(I_CLR);
set_irq <= ( (ctrl(C_INT) and do_interr) or (s_intw and data_inp(I_SET)) );
d_set_interrupt <= set_irq or (interrupt and not(clear_irq));
U_tx_int: FFDsimple port map (clk, rst, d_set_interrupt, interrupt);
-- state register-------------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = ZERO then
dma_current_st <= st_init;
elsif rising_edge(clk) then
dma_current_st <= dma_next_st;
end if;
end process U_st_reg;
dma_curr_dbg <= dma_state'pos(dma_current_st); -- debugging only
U_st_transitions: process(dma_current_st, strobe, done,
s_ctrl, s_src, s_dst, s_stat,
busFree, busGrant, current, ctrl, interrupt,
dma_dinp, err_sz, err_dsk)
variable i_datum : integer;
variable i_addr, i_val : reg32;
begin
case dma_current_st is
when st_init => -- 0
dma_next_st <= st_idle;
when st_idle => -- 1
if s_ctrl = YES then
dma_next_st <= st_src;
else
dma_next_st <= st_idle;
end if;
when st_src => -- 2
if s_src = YES then
dma_next_st <= st_dst;
else
dma_next_st <= st_src;
end if;
when st_dst => -- 3
if s_dst = YES then
dma_next_st <= st_check;
else
dma_next_st <= st_dst;
end if;
when st_check => -- 4 are there any errors?
if err_sz = NO and err_dsk = b"00" then
dma_next_st <= st_bus;
else
dma_next_st <= st_err; -- YES, wait for status to be read
end if;
when st_bus => -- 5
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
when st_xfer => -- 6
if not(done) then -- not done
i_addr := x"00000" & current & b"00";
if ( rising_edge(strobe) and (busGrant = YES) )then
if ctrl(C_OPER) = C_OPER_RD then -- read
if not(endfile(my_file)) then
read( my_file, i_datum );
datum <= std_logic_vector(to_signed(i_datum, 32));
i_val := std_logic_vector(to_signed(i_datum, 32));
assert TRUE
report "DISKrd["&SLV32HEX(i_addr)&"]="&SLV32HEX(i_val);
else
datum <= (others => 'X');
end if;
else -- write = ctrl(C_OPER) = C_OPER_WR
write( my_file, to_integer(signed(dma_dinp)) );
assert TRUE
report "DISKwr["&SLV32HEX(i_addr)&"]="&SLV32HEX(dma_dinp);
end if;
end if;
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
else -- done
dma_next_st <= st_int;
end if;
when st_int => -- 7
if ctrl(C_INT) = YES then -- shall we raise an interrupt?
dma_next_st <= st_assert;
else
dma_next_st <= st_idle;
end if;
file_close(my_file);
when st_assert => -- 8
dma_next_st <= st_wait;
when st_wait => -- 9
if interrupt = YES then -- wait for IRQ to be cleared
dma_next_st <= st_wait;
else
dma_next_st <= st_idle;
end if;
when st_err => -- 10
if s_stat = NO then
dma_next_st <= st_err;
else
dma_next_st <= st_idle;
end if;
when others => -- ??
dma_next_st <= st_idle;
end case;
end process U_st_transitions; -- -----------------------------------
U_st_outputs: process(dma_current_st, done)
begin
case dma_current_st is
when st_init | st_idle | st_src =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_dst =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= YES; -- load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_bus | st_check | st_wait =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_xfer =>
busy <= YES; -- busy
en_curr <= YES; -- increment address
if not(done) then
take_bus <= YES; -- request bus
else
take_bus <= NO;
end if;
ld_curr <= NO; -- do not load address
do_interr <= NO;
when st_int =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_assert =>
busy <= NO; -- free
en_curr <= NO; -- increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= YES; -- raise interrupt request
when others =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
end case;
end process U_st_outputs; -- -----------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- synthesis version - compiler will optimize all away (one hopes)
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of DISK is
begin
rdy <= 'X';
busReq <= NO;
irq <= NO;
data_out <= (others => 'X');
dma_addr <= (others => 'X');
dma_dout <= (others => 'X');
dma_wr <= 'X';
dma_aval <= 'X';
dma_type <= (others => 'X');
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- disk(0): ctrl(31)=oper[1=rd, 0=wr], (30)=doInterrupt,
-- (11..0)=transferSize in words, aligned, <= 1024
-- disk(1): stat(31)=oper[1rd, 0wr], (30)=doInterrupt, (29)=busy,
-- (28)=interrupt pending, (27)=0,
-- (26)=errSize [transfer larger than 1024 words],
-- (25,24)=file error [00=ok, 01=status, 10=name, 11=mode].
-- (23..0)=last address referenced
-- disk(2): src [rd=disk file {0,1,2,3}, wr=memory address]
-- disk(3): dst [rd=memory address, wr=disk file {0,1,2,3}]
-- disk(4): interr, (1)=setIRQ, (0)=clrIRQ
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulates a disk controller with DMA transfers, word only transfers
-- transfers AT MOST 4Kbytes or 1024 memory cycles
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic; -- active in '0'
dma_aval : out std_logic; -- active in '0'
dma_type : out reg4);
constant NUM_BITS : integer := 32;
constant START_VALUE : reg32 := (others => '0');
end entity DISK;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulation version -- logic too complex for synthesis,
-- as there is no hw disk, model is for simulation
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of DISK is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
constant C_OPER : integer := 31; -- operation 1=rd, 0=wr
constant C_OPER_RD : std_logic := '1';
constant C_OPER_WR : std_logic := '0';
constant C_INT : integer := 30; -- interrupt when finished=1
constant S_BUSY : integer := 29; -- controller busy=1
constant I_SET : integer := 1; -- set IRQ
constant I_CLR : integer := 0; -- clear IRQ
constant DSK_OK : std_logic_vector(1 downto 0) := b"00";
constant DSK_STATUS : std_logic_vector(1 downto 0) := b"01";
constant DSK_NAME : std_logic_vector(1 downto 0) := b"10";
constant DSK_MODE : std_logic_vector(1 downto 0) := b"11";
type int_file is file of integer;
file my_file : int_file;
type dma_state is (st_init, st_idle, st_src, st_dst, st_check,
st_bus, st_xfer, st_int, st_assert, st_wait, st_err);
attribute SYN_ENCODING of dma_state : type is "safe";
signal dma_current_st, dma_next_st : dma_state;
signal dma_curr_dbg, current_int, ctrl_int, addr_int : integer;
signal ld_ctrl, s_ctrl, s_stat, ld_src, s_src, ld_dst, s_dst : std_logic;
signal busy, take_bus, ld_curr, rst_curr, en_curr : std_logic;
signal ctrl, src, dst, stat, datum : reg32 := (others => '0');
signal current, xfer_sz : reg10;
signal last_addr : reg24;
signal base_addr, curr_addr, address : reg32;
signal s_intw, s_intr, set_irq, clear_irq, s_dat, err_sz : std_logic;
signal d_set_interrupt, interrupt, do_interr, ld_last : std_logic;
signal done, last_one : boolean;
signal err_dsk : reg2 := b"00";
signal clear_hold_done, set_hold_done, d_set_hold_done, hold_done : std_logic;
begin -- functional
rdy <= ZERO; -- simulation only, never waits
s_ctrl <= '1' when sel = '0' and addr = b"000" else '0'; -- R+W
s_stat <= '1' when sel = '0' and addr = b"001" else '0'; -- R+W
s_src <= '1' when sel = '0' and addr = b"010" else '0'; -- W
s_dst <= '1' when sel = '0' and addr = b"011" else '0'; -- W
s_intw <= '1' when sel = '0' and addr = b"100" and wr = '0' else '0'; -- W
s_intr <= '1' when sel = '0' and addr = b"100" and wr = '1' else '0'; -- R
s_dat <= '1' when sel = '0' and addr = b"111" else '0'; -- W, DEBUG
ld_ctrl <= '0' when s_ctrl = '1' and wr = '0' else '1';
U_CTRL: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_ctrl, data_inp, ctrl);
ld_src <= '0' when s_src = '1' and wr = '0' else '1';
U_SRC: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_src, data_inp, src);
ld_dst <= '0' when s_dst = '1' and wr = '0' else '1';
U_DST: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_dst, data_inp, dst);
stat <= ctrl(C_OPER) & ctrl(C_INT) & busy & interrupt &
'0' & err_sz & err_dsk & last_addr;
with addr select
data_out <= ctrl when "000",
stat when "001",
src when "010",
dst when "011",
x"00000000" when others; -- interrupts, does RD-mod-WR
irq <= interrupt;
busReq <= take_bus;
dma_type <= b"1111"; -- always transfers words
dma_wr <= not(ctrl(C_OPER)) or not(take_bus); -- write to RAM
dma_aVal <= not(take_bus);
base_addr <= dst when ctrl(C_OPER) = C_OPER_RD else src;
curr_addr <= x"0000" & b"0000" & current & b"00"; -- word aligned
address <= std_logic_vector( signed(base_addr) + signed(curr_addr) );
dma_addr <= address;
dma_dout <= datum when ctrl(C_OPER) = C_OPER_RD else (others => 'X');
xfer_sz <= ctrl(9 downto 0) when ctrl_int <= 1024 else (others => '0');
addr_int <= to_integer(unsigned( ctrl(10 downto 0)));
err_sz <= YES when addr_int > 1024 else NO; -- check if size > 1024
rst_curr <= not(ld_curr) and rst;
U_CURRENT: countNup generic map (10) -- current DMA reference
port map (clk, rst_curr, '0', en_curr, xfer_sz, current);
last_one <= (current_int = (ctrl_int - 1));
ld_last <= BOOL2SL(not(last_one));
U_LAST_ADDR: registerN generic map (24, x"000000") -- for status
port map (clk, rst, ld_last, address(23 downto 0), last_addr);
current_int <= to_integer(unsigned(current));
ctrl_int <= to_integer(unsigned(ctrl(9 downto 0))); -- check == 1024
done <= ( (current = (ctrl(9 downto 0))) and (hold_done = NO) );
clear_hold_done <= en_curr; -- first increment, makes current /= 0
set_hold_done <= s_ctrl; -- wait 1 DMA access to check for done
d_set_hold_done <= (set_hold_done or hold_done) and not(clear_hold_done);
U_HOLD_DONE: FFDsimple port map (clk, rst, d_set_hold_done, hold_done);
-- file operations -----------------------------------------------------
U_FILE_CTRL: process(rst, clk, s_ctrl, s_src, s_dst, data_inp, ctrl)
variable status : file_open_status := open_ok;
variable i_status : integer := 0;
begin
if rst = '1' then
if (s_src = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_RD)
then -- read file
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.src", read_mode);
when b"01" => file_open(status, my_file, "DMA_1.src", read_mode);
when b"10" => file_open(status, my_file, "DMA_2.src", read_mode);
when b"11" => file_open(status, my_file, "DMA_3.src", read_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileRDopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if;
if (s_dst = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_WR)
then
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.dst", write_mode);
when b"01" => file_open(status, my_file, "DMA_1.dst", write_mode);
when b"10" => file_open(status, my_file, "DMA_2.dst", write_mode);
when b"11" => file_open(status, my_file, "DMA_3.dst", write_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileWRopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if; -- end write file
end if; -- reset
end process U_FILE_CTRL; -----------------------------------------------
clear_irq <= s_intw and data_inp(I_CLR);
set_irq <= ( (ctrl(C_INT) and do_interr) or (s_intw and data_inp(I_SET)) );
d_set_interrupt <= set_irq or (interrupt and not(clear_irq));
U_tx_int: FFDsimple port map (clk, rst, d_set_interrupt, interrupt);
-- state register-------------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = ZERO then
dma_current_st <= st_init;
elsif rising_edge(clk) then
dma_current_st <= dma_next_st;
end if;
end process U_st_reg;
dma_curr_dbg <= dma_state'pos(dma_current_st); -- debugging only
U_st_transitions: process(dma_current_st, strobe, done,
s_ctrl, s_src, s_dst, s_stat,
busFree, busGrant, current, ctrl, interrupt,
dma_dinp, err_sz, err_dsk)
variable i_datum : integer;
variable i_addr, i_val : reg32;
begin
case dma_current_st is
when st_init => -- 0
dma_next_st <= st_idle;
when st_idle => -- 1
if s_ctrl = YES then
dma_next_st <= st_src;
else
dma_next_st <= st_idle;
end if;
when st_src => -- 2
if s_src = YES then
dma_next_st <= st_dst;
else
dma_next_st <= st_src;
end if;
when st_dst => -- 3
if s_dst = YES then
dma_next_st <= st_check;
else
dma_next_st <= st_dst;
end if;
when st_check => -- 4 are there any errors?
if err_sz = NO and err_dsk = b"00" then
dma_next_st <= st_bus;
else
dma_next_st <= st_err; -- YES, wait for status to be read
end if;
when st_bus => -- 5
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
when st_xfer => -- 6
if not(done) then -- not done
i_addr := x"00000" & current & b"00";
if ( rising_edge(strobe) and (busGrant = YES) )then
if ctrl(C_OPER) = C_OPER_RD then -- read
if not(endfile(my_file)) then
read( my_file, i_datum );
datum <= std_logic_vector(to_signed(i_datum, 32));
i_val := std_logic_vector(to_signed(i_datum, 32));
assert TRUE
report "DISKrd["&SLV32HEX(i_addr)&"]="&SLV32HEX(i_val);
else
datum <= (others => 'X');
end if;
else -- write = ctrl(C_OPER) = C_OPER_WR
write( my_file, to_integer(signed(dma_dinp)) );
assert TRUE
report "DISKwr["&SLV32HEX(i_addr)&"]="&SLV32HEX(dma_dinp);
end if;
end if;
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
else -- done
dma_next_st <= st_int;
end if;
when st_int => -- 7
if ctrl(C_INT) = YES then -- shall we raise an interrupt?
dma_next_st <= st_assert;
else
dma_next_st <= st_idle;
end if;
file_close(my_file);
when st_assert => -- 8
dma_next_st <= st_wait;
when st_wait => -- 9
if interrupt = YES then -- wait for IRQ to be cleared
dma_next_st <= st_wait;
else
dma_next_st <= st_idle;
end if;
when st_err => -- 10
if s_stat = NO then
dma_next_st <= st_err;
else
dma_next_st <= st_idle;
end if;
when others => -- ??
dma_next_st <= st_idle;
end case;
end process U_st_transitions; -- -----------------------------------
U_st_outputs: process(dma_current_st, done)
begin
case dma_current_st is
when st_init | st_idle | st_src =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_dst =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= YES; -- load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_bus | st_check | st_wait =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_xfer =>
busy <= YES; -- busy
en_curr <= YES; -- increment address
if not(done) then
take_bus <= YES; -- request bus
else
take_bus <= NO;
end if;
ld_curr <= NO; -- do not load address
do_interr <= NO;
when st_int =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_assert =>
busy <= NO; -- free
en_curr <= NO; -- increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= YES; -- raise interrupt request
when others =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
end case;
end process U_st_outputs; -- -----------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- synthesis version - compiler will optimize all away (one hopes)
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of DISK is
begin
rdy <= 'X';
busReq <= NO;
irq <= NO;
data_out <= (others => 'X');
dma_addr <= (others => 'X');
dma_dout <= (others => 'X');
dma_wr <= 'X';
dma_aval <= 'X';
dma_type <= (others => 'X');
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lotde_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lotde_shiftReg;
architecture rtl of start_for_Loop_lotde_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lotde is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lotde is
component start_for_Loop_lotde_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lotde_shiftReg : start_for_Loop_lotde_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
------------------------------------------------------------------------------
-- Title : Simple Position Counters for debugging
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2017-01-20
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core for generating coutners sync'ed with each incoming data rate.
-- Used for debugging.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-01-20 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Counter Generator Definitions
use work.counters_gen_pkg.all;
entity counters_gen is
generic
(
g_cnt_width : t_cnt_width_array := c_default_cnt_width_array
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
---------------------------------
-- Counter generation interface
---------------------------------
cnt_ce_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_up_array_i : in std_logic_vector(g_cnt_width'length-1 downto 0);
cnt_array_o : out t_cnt_array (g_cnt_width'length-1 downto 0)
);
end counters_gen;
architecture rtl of counters_gen is
-- Constants
constant c_num_counters : natural := g_cnt_width'length;
-- Signals
signal cnt_array : t_cnt_array (c_num_counters-1 downto 0);
begin
gen_counters : for i in 0 to c_num_counters-1 generate
p_counters : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cnt_array(i) <= to_unsigned(0, cnt_array(i)'length);
elsif cnt_ce_array_i(i) = '1' then
if cnt_up_array_i(i) = '1' then
if cnt_array(i) = 2**g_cnt_width(i)-1 then
cnt_array(i) <= to_unsigned(0, cnt_array(i)'length);
else
cnt_array(i) <= cnt_array(i) + 1;
end if;
end if;
end if;
end if;
end process;
end generate;
cnt_array_o <= cnt_array;
end rtl;
|
-------------------------------------------------------------------------------
-- Module: tb_uart_transmit
-- Purpose: Testbench for module e_uart_transmit.
--
-- Author: Leander Schulz
-- Date: 07.09.2017
-- Last change: 22.10.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_uart_transmit IS
END ENTITY tb_uart_transmit;
ARCHITECTURE tb_arch OF tb_uart_transmit IS
-- IMPORT UART COMPONENT
COMPONENT e_uart_transmit IS
GENERIC(
baud_rate : IN NATURAL RANGE 1200 TO 500000;
M : integer
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
verify_i : IN std_logic;
start_i : IN std_logic;
data_i : IN std_logic_vector (7 DOWNTO 0);
tx_o : OUT std_logic;
reg_o : OUT std_logic );
END COMPONENT e_uart_transmit;
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL s_mode : std_logic := '0';
SIGNAL s_verify : std_logic := '0';
SIGNAL s_start_bit : std_logic := '0';
SIGNAL s_uart_data : std_logic_vector (7 DOWNTO 0) := "00000000";
SIGNAL s_tx : std_logic;
SIGNAL s_reg_ctrl : std_logic;
BEGIN
-- Instantiate uart transmitter
transmit_instance : e_uart_transmit
GENERIC MAP (
baud_rate => 500000,
M => 8 -- key length [bit]
) PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
mode_i => s_mode,
verify_i => s_verify,
start_i => s_start_bit,
data_i => s_uart_data,
tx_o => s_tx,
reg_o => s_reg_ctrl
);
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
tx_gen : PROCESS
BEGIN
s_uart_data <= "10011001";
WAIT FOR 80 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 200 ns;
s_start_bit <= '1';
WAIT FOR 20 ns;
s_start_bit <= '0';
WAIT FOR 20 us;
s_uart_data <= "01011010";
WAIT FOR 20 us;
s_uart_data <= "01100110";
WAIT FOR 20 us;
s_uart_data <= "01010101";
WAIT;
END PROCESS tx_gen;
END ARCHITECTURE tb_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg IS
PORT(
clk, din, rst : IN std_logic;
dout : OUT std_logic
);
END ENTITY shiftreg;
ARCHITECTURE behavior OF shiftreg IS
SIGNAL sint: std_logic;
BEGIN
PROCESS (clk, rst)
BEGIN
if rst='1' THEN
dout <= (others => '0');
elsif clk = '1' AND clk'EVENT THEN
sint <= din;
dout <= sint;
end if;
END PROCESS;
END behavior;
|
entity test_id is
end entity;
architecture rtl of test_id is
type T_TUPLE is record
A : NATURAL;
B : NATURAL;
end record;
type T_VECTOR is array (NATURAL range <>) of T_TUPLE;
constant LIST : T_VECTOR := ((8, 32), (8, 20), (8, 36));
begin
genTests : for i in LIST'range generate
constant LOCAL_A : NATURAL := LIST(i).A;
constant LOCAL_B : NATURAL := LIST(i).B;
begin
-- my tests
end generate;
end architecture;
|
entity test_id is
end entity;
architecture rtl of test_id is
type T_TUPLE is record
A : NATURAL;
B : NATURAL;
end record;
type T_VECTOR is array (NATURAL range <>) of T_TUPLE;
constant LIST : T_VECTOR := ((8, 32), (8, 20), (8, 36));
begin
genTests : for i in LIST'range generate
constant LOCAL_A : NATURAL := LIST(i).A;
constant LOCAL_B : NATURAL := LIST(i).B;
begin
-- my tests
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_controller is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- interface with hps
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0);
noc_ctrl : in std_logic_vector(31 downto 0);
noc_sts : out std_logic_vector(31 downto 0);
--network sending interface
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--network receiving interface
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
--debugging
has_rxd : out std_logic;
tx_non_zero : out std_logic
);
end entity noc_controller;
architecture fsmd of noc_controller is
constant identifier_msb : integer := 7;
constant identifier_lsb : integer := 0;
constant num_data_regs : integer := 1;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
type regs is array(num_data_regs-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal data_register_d, data_register_q : regs;
signal data_in_buffer_q, data_in_buffer_delay : std_logic_vector(num_vc-1 downto 0);
signal write_enable : std_logic;
signal selected_vc_q, selected_vc_d, selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal id_select : std_logic_vector(7 downto 0);
signal has_rxd_d, has_rxd_q : std_logic;
signal send_flit_once_edge, send_flit_once_d, send_flit_once_q, send_flit_once_q2 : std_logic;
type send_states is (idle, send, waiting);
signal send_state, next_send_state : send_states;
type rx_states is (rx_idle, rx_addr_rst, rx_start_read, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits);
signal rx_state, next_rx_state : rx_states;
signal selected_vc_one_hot : std_logic_vector(1 downto 0);
signal state : std_logic_vector(3 downto 0);
signal cpu_read_ctrl : std_logic;
begin
---------------------------------------------------------------------------
-- Sending Controls -------------------------------------------------------
---------------------------------------------------------------------------
-- output logic
send_data <= data_in;
dest_addr <= noc_ctrl(addr_width-1 downto 0);
set_tail_flit <= noc_ctrl(8);
send_flit <= '1' when send_state = send else '0';
-- state register
process(clk, rst) begin
if rst = '1' then
send_state <= idle;
elsif rising_edge(clk) then
send_state <= next_send_state;
end if;
end process;
-- state transition logic
process(send_state, noc_ctrl(9)) begin
next_send_state <= send_state;
if send_state = idle and noc_ctrl(9) = '1' then
next_send_state <= send;
end if;
if send_state = send then
next_send_state <= waiting;
end if;
if send_state = waiting and noc_ctrl(9) = '0' then
next_send_state <= idle;
end if;
end process;
---------------------------------------------------------------------------
-- receive inteface controls ----------------------------------------------
---------------------------------------------------------------------------
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits, rx_addr_rst, rx_start_read
--- output logic ---
dequeue <= "01" when selected_vc_q = "0" and rx_state = rx_dequeue else
"10" when selected_vc_q = "1" and rx_state = rx_dequeue else
"00";
selected_vc_one_hot <= "01" when selected_vc_q = "0" else
"10";
select_vc_read <= selected_vc_q;
state <= std_logic_vector(to_unsigned(0, 4)) when rx_state = rx_idle else
std_logic_vector(to_unsigned(1, 4)) when rx_state = rx_sel_vc else
std_logic_vector(to_unsigned(2, 4)) when rx_state = rx_addr_rst else
std_logic_vector(to_unsigned(3, 4)) when rx_state = rx_start_read else
std_logic_vector(to_unsigned(4, 4)) when rx_state = rx_rxd else
std_logic_vector(to_unsigned(5, 4)) when rx_state = rx_wait_cpu else
std_logic_vector(to_unsigned(6, 4)) when rx_state = rx_dequeue else
std_logic_vector(to_unsigned(7, 4)) when rx_state = rx_wait_flits else
std_logic_vector(to_unsigned(15, 4));
--- data path ---
-- data path registers
process(clk, rst) begin
if rst = '1' then
selected_vc_q <=(others => '0');
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
end if;
end process;
--data path components
u0: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_encoder);
-- data path logic
selected_vc_d <= selected_vc_encoder when rx_state = rx_sel_vc else selected_vc_q;
cpu_read_ctrl <= noc_ctrl(14);
--- FSM ---
-- state register
process(clk, rst) begin
if rst = '1' then
rx_state <= rx_idle;
elsif rising_edge(clk) then
rx_state <= next_rx_state;
end if;
end process;
--- state transition logic
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits
process(rx_state, data_in_buffer, selected_vc_q) begin
next_rx_state <= rx_state;
if rx_state = rx_idle and or_reduce(data_in_buffer) = '1' then
next_rx_state <= rx_sel_vc;
end if;
if rx_state = rx_sel_vc then
next_rx_state <= rx_addr_rst;
end if;
if rx_state = rx_addr_rst and cpu_read_ctrl = '1' then
next_rx_state <= rx_start_read;
end if;
if rx_state = rx_start_read and cpu_read_ctrl = '0' then
next_rx_state <= rx_rxd;
end if;
if rx_state = rx_rxd and cpu_read_ctrl = '1' then
next_rx_state <= rx_wait_cpu;
end if;
if rx_state = rx_wait_cpu and cpu_read_ctrl = '0' then
next_rx_state <= rx_dequeue;
end if;
if rx_state = rx_dequeue and is_tail_flit = '1' then
next_rx_state <= rx_idle;
end if;
if rx_state = rx_dequeue and is_tail_flit = '0' then
next_rx_state <= rx_wait_flits;
end if;
if rx_state = rx_wait_flits and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_rx_state <= rx_rxd;
end if;
end process;
---------------------------------------------------------------------------
-- User Rx Interface -----------------------------------------------------
---------------------------------------------------------------------------
id_select <= noc_ctrl(31 downto 24);
--data_out <= data_register_q(to_integer(unsigned(id_select)));
data_out <= recv_data;
noc_sts(24 + addr_width - 1 downto 24) <= src_addr;
noc_sts(23 downto 20) <= state;
noc_sts(0) <= not ready_to_send;
noc_sts(19 downto 1) <= (others => '0');
---------------------------------------------------------------------------
-- debug ------------------------------------------------------------------
---------------------------------------------------------------------------
has_rxd <= or_reduce(data_in_buffer); --has_rxd_q;
tx_non_zero <= or_reduce(recv_data);
end architecture fsmd;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RaspiFpgaCtrlE is
port (
--+ System if
Rst_n_i : in std_logic;
Clk_i : in std_logic;
--+ local register if
LocalWen_o : out std_logic;
LocalRen_o : out std_logic;
LocalAdress_o : out std_logic_vector(7 downto 0);
LocalData_i : in std_logic_vector(7 downto 0);
LocalData_o : out std_logic_vector(7 downto 0);
LocalAck_i : in std_logic;
LocalError_i : in std_logic;
--+ EFB if
EfbSpiIrq_i : in std_logic;
--+ RNG if
RngStart_o : out std_logic;
RngWait_o : out std_logic_vector(7 downto 0);
RngRun_o : out std_logic_vector(7 downto 0);
RngDataValid_i : in std_logic;
RngData_i : in std_logic_vector(7 downto 0)
);
end entity RaspiFpgaCtrlE;
architecture rtl of RaspiFpgaCtrlE is
--+ EFB SPI slave register addresses
constant C_SPICR0 : std_logic_vector(7 downto 0) := x"54"; --* ctrl reg 0
constant C_SPICR1 : std_logic_vector(7 downto 0) := x"55"; --* ctrl reg 1
constant C_SPICR2 : std_logic_vector(7 downto 0) := x"56"; --* ctrl reg 2
constant C_SPIBR : std_logic_vector(7 downto 0) := x"57"; --* clk pre-scale
constant C_SPICSR : std_logic_vector(7 downto 0) := x"58"; --* master chip select
constant C_SPITXDR : std_logic_vector(7 downto 0) := x"59"; --* transmit data
constant C_SPIISR : std_logic_vector(7 downto 0) := x"5A"; --* status
constant C_SPIRXDR : std_logic_vector(7 downto 0) := x"5B"; --* receive data
constant C_SPIIRQ : std_logic_vector(7 downto 0) := x"5C"; --* interrupt request
constant C_SPIIRQEN : std_logic_vector(7 downto 0) := x"5D"; --* interrupt request enable
--+ Register file addresses
constant C_REG_RNGSTATUS : natural := 0;
constant C_REG_RNGWAIT : natural := 1;
constant C_REG_RNGRUN : natural := 2;
constant C_REG_RNGDATA : natural := 3;
type t_cmdctrl_fsm is (IDLE, INIT_SET, INIT_ACK, TXDR_SET, TXDR_ACK, INT_WAIT,
RXDR_SET, RXDR_ACK, INT_CLEAR_SET, INT_CLEAR_ACK);
signal s_cmdctrl_fsm : t_cmdctrl_fsm;
type t_wb_master is record
adr : std_logic_vector(7 downto 0);
data : std_logic_vector(7 downto 0);
end record t_wb_master;
type t_wb_master_array is array (natural range <>) of t_wb_master;
constant C_INIT : t_wb_master_array := ((C_SPICR1, x"80"),
(C_SPICR2, x"00"),
(C_SPIIRQEN, x"08"));
signal s_init_cnt : natural range 0 to C_INIT'length;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
signal s_register : t_byte_array(0 to 127);
signal s_register_we : std_logic;
signal s_register_address : natural range s_register'range;
type t_spi_frame is (NOP, HEADER, WRITE_DATA, READ_DATA);
signal s_spi_frame : t_spi_frame;
begin
--+ FSM to write/request data from the wishbone master
--+ Combinatoral outputs
LocalWen_o <= '1' when s_cmdctrl_fsm = INIT_SET or s_cmdctrl_fsm = TXDR_SET or s_cmdctrl_fsm = INT_CLEAR_SET else '0';
LocalRen_o <= '1' when s_cmdctrl_fsm = RXDR_SET else '0';
LocalAdress_o <= C_INIT(s_init_cnt).adr when s_cmdctrl_fsm = INIT_SET else
C_SPITXDR when s_cmdctrl_fsm = TXDR_SET else
C_SPIRXDR when s_cmdctrl_fsm = RXDR_SET else
C_SPIIRQ when s_cmdctrl_fsm = INT_CLEAR_SET else
(others => '0');
LocalData_o <= C_INIT(s_init_cnt).data when s_cmdctrl_fsm = INIT_SET else
s_register(s_register_address) when s_cmdctrl_fsm = TXDR_SET and s_spi_frame = READ_DATA else
x"FF";
--+ FSM to write/request data from the wishbone master
--+ State logic/register
CmdCtrlP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_cmdctrl_fsm <= IDLE;
else
FsmC : case s_cmdctrl_fsm is
when IDLE =>
s_cmdctrl_fsm <= INIT_SET;
when INIT_SET =>
s_cmdctrl_fsm <= INIT_ACK;
when INIT_ACK =>
if (LocalAck_i = '1') then
if (s_init_cnt = C_INIT'length) then
s_cmdctrl_fsm <= TXDR_SET;
else
s_cmdctrl_fsm <= INIT_SET;
end if;
end if;
when TXDR_SET =>
s_cmdctrl_fsm <= TXDR_ACK;
when TXDR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= INT_WAIT;
end if;
when INT_WAIT =>
if (EfbSpiIrq_i = '1') then
s_cmdctrl_fsm <= RXDR_SET;
end if;
when RXDR_SET =>
s_cmdctrl_fsm <= RXDR_ACK;
when RXDR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= INT_CLEAR_SET;
end if;
when INT_CLEAR_SET =>
s_cmdctrl_fsm <= INT_CLEAR_ACK;
when INT_CLEAR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= TXDR_SET;
end if;
when others =>
null;
end case FsmC;
end if;
end if;
end process CmdCtrlP;
--+ FSM to write/request data from the wishbone master
--+ Registered outputs
CmdRegisterP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_init_cnt <= 0;
s_spi_frame <= NOP;
s_register_address <= 0;
else
case s_cmdctrl_fsm is
when IDLE =>
s_init_cnt <= 0;
s_spi_frame <= NOP;
s_register_address <= 0;
when INIT_SET =>
s_init_cnt <= s_init_cnt + 1;
when RXDR_ACK =>
if (LocalAck_i = '1') then
if (s_spi_frame = HEADER) then
s_register_address <= to_integer(unsigned(LocalData_i(6 downto 0)));
if (LocalData_i(7) = '0') then
s_spi_frame <= READ_DATA;
else
s_spi_frame <= WRITE_DATA;
end if;
else
if (LocalData_i = x"00") then
s_spi_frame <= HEADER;
else
s_spi_frame <= NOP;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
end if;
end process CmdRegisterP;
--+ Register bank write enable
s_register_we <= LocalAck_i when s_cmdctrl_fsm = RXDR_ACK and s_spi_frame = WRITE_DATA else '0';
--+ Register bank 127x8
RegisterFileP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_register <= (others => (others => '0'));
s_register(C_REG_RNGWAIT) <= x"0F";
s_register(C_REG_RNGRUN) <= x"0F";
else
s_register(C_REG_RNGSTATUS)(0) <= '0'; -- reset RNG start after each clock cycle
if (s_register_we = '1') then
s_register(s_register_address) <= LocalData_i;
end if;
-- register RNG data
if (RngDataValid_i = '1') then
s_register(C_REG_RNGSTATUS)(1) <= '1';
s_register(C_REG_RNGDATA) <= RngData_i;
end if;
-- clear RNG done flag when RNG was started
if (s_register(C_REG_RNGSTATUS)(0) = '1') then
s_register(C_REG_RNGSTATUS)(1) <= '0';
end if;
end if;
end if;
end process RegisterFileP;
--+ RNG control outputs
RngStart_o <= s_register(C_REG_RNGSTATUS)(0);
RngWait_o <= s_register(C_REG_RNGWAIT);
RngRun_o <= s_register(C_REG_RNGRUN);
end architecture rtl;
|
entity TOP is
end entity TOP;
architecture ARCH of TOP is
signal S1, S2, S3: BIT;
alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Legal
constant DATA_WIDTH: INTEGER:= <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
-- Illegal, because .TOP.DUT.DATA has not yet been elaborated
-- when the expression is evaluated
begin
P1: process ( DONE_SIG ) is -- Legal
begin
if DONE_SIG then -- Legal ...;
end if;
end process P1;
MONITOR: entity WORK.MY_MONITOR port map (DONE_SIG);
-- Illegal, because .TOP.DUT.DONE has not yet been elaborated
-- when the association element is elaborated
DUT: entity WORK.MY_DESIGN port map (s1, S2, S3);
MONITOR2: entity WORK.MY_MONITOR port map (DONE_SIG);
-- Legal, because .TOP.DUT.DONE has now been elaborated
B1: block
constant DATA_WIDTH: INTEGER := <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH
-- Legal, because .TOP.DUT.DATA has now been elaborated
begin
end block B1;
B2: block
constant C0: INTEGER := 6;
constant C1: INTEGER := <<constant .TOP.B3.C2: INTEGER>>;
-- Illegal, because .TOP.B3.C2 has not yet been elaborated
begin
end block B2;
B3: block
constant C2: INTEGER := <<constant .TOP.B2.C0: INTEGER>>; -- Legal
begin
end block B3;
-- Together, B2 and B3 are illegal, because they cannot be ordered
-- so that the objects are elaborated in the order .TOP.B2.C0,
-- then .TOP.B3.C2, and finally .TOP.B2.C1.
end architecture ARCH;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg_toplevel
-- Project Name: SevenSegmentDisplay
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description: 7-segment toplevel example
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity SSeg_toplevel is
port (
CLK : in STD_LOGIC; -- 50 MHz input
SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0)
);
end SSeg_toplevel;
architecture Structural of SSeg_toplevel is
signal s2 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal s3 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
signal cen : STD_LOGIC := '0';
begin
----- Structural Components: -----
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => BTN,
EN => enl,
SEG_0 => SW(3 downto 0),
SEG_1 => SW(7 downto 4),
SEG_2 => s2,
SEG_3 => s3,
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
----- End Structural Components -----
end Structural;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_fifo_wrptr_inc is
port(
ge2_free : in vl_logic;
ge3_free : in vl_logic;
input_tm_cnt : in vl_logic_vector(1 downto 0);
fifo_wrptr_inc : out vl_logic_vector(3 downto 0)
);
end finalproject_cpu_nios2_oci_fifo_wrptr_inc;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps is
generic (
CLK_PROC_FREQ : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
RXD : in std_logic;
TXD : out std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gps;
architecture rtl of gps is
component top_GPS
port (
clk : in std_logic;
reset : in std_logic;
RXD : in std_logic;
TXD : out std_logic;
parameters : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(7 downto 0);
flow_valid : out std_logic;
data_valid : out std_logic
);
end component;
component gps_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
sat_reg : out std_logic_vector(31 downto 0);
update_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal enable_reg : std_logic_vector (31 downto 0);
signal sat_reg : std_logic_vector (31 downto 0);
signal update_reg : std_logic_vector (31 downto 0);
signal parameters : std_logic_vector(31 downto 0);
begin
gps_slave_inst : gps_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
enable_reg => enable_reg,
sat_reg => sat_reg,
update_reg => update_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
top_GPS_inst : top_GPS
port map(
clk => clk_proc,
reset => reset_n,
RXD => RXD,
TXD => TXD,
parameters => parameters,
data_out => out_data ,
flow_valid => out_fv ,
data_valid => out_dv
);
parameters(31 downto 22) <= enable_reg(0) & sat_reg(0) & update_reg(7 downto 0);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 19:03:40 09/24/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port (
En: in STD_LOGIC;
LM: in STD_LOGIC; --Logical operation mode
A : in STD_LOGIC_VECTOR (11 downto 0);
B : in STD_LOGIC_VECTOR (11 downto 0);
Func: in STD_LOGIC_VECTOR (3 downto 0);
Output : out STD_LOGIC_VECTOR (11 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process (En, A, B, Func, LM)
begin
if(En = '1') then
if(LM = '0') then
if(Func = "0000") then
Output <= (A) + (B);
elsif(Func = "0001") then
Output <= (A) - (B);
elsif(Func = "0010") then
Output <= (B) - (A);
elsif(Func = "0011") then
Output <= (B) - 1;
elsif(Func = "0100") then
Output <= (B) + 1;
elsif(Func = "0101") then
Output <= 0 - (B);
elsif(Func = "0110") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
elsif(Func = "0111") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
else
if(Func = "0000") then
Output <= not B;
elsif(Func = "0001") then
Output <= A nor B;
elsif(Func = "0010") then
Output <= (not B) and A;
elsif(Func = "0011") then
Output <= "000000000000";
elsif(Func = "0100") then
Output <= B nand A;
elsif(Func = "0101") then
Output <= not A;
elsif(Func = "0110") then
Output <= B xor A;
elsif(Func = "0111") then
Output <= B and (not A);
elsif(Func = "1000") then
Output <= (not B) or A;
elsif(Func = "1001") then
Output <= B xnor A;
elsif(Func = "1010") then
Output <= A;
elsif(Func = "1011") then
Output <= B and A;
elsif(Func = "1100") then
Output <= "000000000001";
elsif(Func = "1101") then
Output <= B or (not A);
elsif(Func = "1110") then
Output <= B or A;
elsif(Func = "1111") then
if(B = 0) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
end if;
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:bit_vector(3 downto 0);
alias Q0:bit is State(0);
alias Q1:bit is State(1);
alias Q2:bit is State(2);
alias Q3:bit is State(3);
begin
stateout<=to_integer(unsigned(State));
Z<=(Q3 or Q2 )and not Q1 and not Q0;
--Q0`=x(q0'q1'+q0q2+q1q0')+x'(q3'q2'+q2q0')
nextState(0)<=(X and ((not Q0 and not Q2) or (Q0 and Q2)or (Q1 and not Q0)))or (not X and ((not Q3 and not Q2)or (Q2 and not Q0 )));
nextState(1)<=(x and ((Q1 and not Q0 and not Q2)or (not Q1 and Q0 and not Q2)))or(not x and ((not Q1 and Q0 and Q2)or (Q1 and not Q0 and Q2) )) ;
nextState(2)<=(X and ( (not Q1 and not Q0 and Q2) or (Q1 and Q0 and not Q2) ))or(not X and ( (not Q3 and not Q2) or (Q1 and not Q0 ) or (not Q1 and Q2) ));
nextState(3)<=not X and ( (Q3 and not Q2) or (Q1 and Q0 and Q2) );
process(CLK,reset)
begin
if reset='0' then State<="0000";
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View_input.vhd
------------------------------------------------------------
--------------------------------------------------------------
entity View_input is
port (reset:in bit;
w: in bit;
clk:in bit;
z: out bit;
state8_0:out bit_vector(8 downto 0));--LED Red for showing State table
end entity View_input;
architecture match of View_input is
component FSM_core
port(
X: in bit;
CLK: in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z: out bit);
end component;
signal stateout:integer range 0 to 8;
begin
lable_1:fsm_core port map(w,clk,reset,stateout,z);
with stateout select --mux choice
state8_0 <= "000000001" when 0,
"000000010" when 1,
"000000100" when 2,
"000001000" when 3,
"000010000" when 4,
"000100000" when 5,
"001000000" when 6,
"010000000" when 7,
"100000000" when 8;
end architecture match;
|
architecture RTl of FIFO is
component fifo is
end COMPONENT fifo;
-- Failures below
component fifo is
end COMPONENT fifo;
component fifo is
end COMPONENT fifo;
begin
end architecture RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03075pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
end c12s06b02x00p06n01i03075pkg;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03075ent_a;
ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03075arch_a;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent IS
END c12s06b02x00p06n01i03075ent;
ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
signal S1 : severity_level_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03075"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03075arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03075pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
end c12s06b02x00p06n01i03075pkg;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03075ent_a;
ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03075arch_a;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent IS
END c12s06b02x00p06n01i03075ent;
ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
signal S1 : severity_level_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03075"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03075arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03075pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
end c12s06b02x00p06n01i03075pkg;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03075ent_a;
ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03075arch_a;
use work.c12s06b02x00p06n01i03075pkg.all;
ENTITY c12s06b02x00p06n01i03075ent IS
END c12s06b02x00p06n01i03075ent;
ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
signal S1 : severity_level_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03075"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03075arch;
|
------------------------------------------------------------------------------
-- Title : Position Calcualtion Error Counters (single)
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2014-01-13
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple counters for errors on the DSP chain
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-13 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.position_calc_core_pkg.all;
entity position_calc_counters is
generic (
g_cntr_size : natural := 16
);
port (
fs_clk2x_i : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i : in std_logic;
-- Clock enables for various rates
tbt_ce_i : in std_logic;
fofb_ce_i : in std_logic;
monit_cic_ce_i : in std_logic;
monit_cfir_ce_i : in std_logic;
monit_pfir_ce_i : in std_logic;
monit_01_ce_i : in std_logic;
tbt_decim_q_ch01_incorrect_i : in std_logic;
tbt_decim_q_ch23_incorrect_i : in std_logic;
tbt_decim_err_clr_i : in std_logic;
fofb_decim_q_ch01_missing_i : in std_logic;
fofb_decim_q_ch23_missing_i : in std_logic;
fofb_decim_err_clr_i : in std_logic;
monit_cic_unexpected_i : in std_logic;
monit_cfir_incorrect_i : in std_logic;
monit_part1_err_clr_i : in std_logic;
monit_pfir_incorrect_i : in std_logic;
monit_pos_1_incorrect_i : in std_logic;
monit_part2_err_clr_i : in std_logic;
tbt_incorrect_ctnr_ch01_o : out std_logic_vector(g_cntr_size-1 downto 0);
tbt_incorrect_ctnr_ch23_o : out std_logic_vector(g_cntr_size-1 downto 0);
fofb_incorrect_ctnr_ch01_o : out std_logic_vector(g_cntr_size-1 downto 0);
fofb_incorrect_ctnr_ch23_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_cic_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_cfir_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_pfir_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_01_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0)
);
end position_calc_counters;
architecture rtl of position_calc_counters is
begin
-------------------------------------------------------------------------------
-- TBT error counters
-------------------------------------------------------------------------------
cmp_tbt_ch01_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => tbt_ce_i,
-- Error inputs (one clock cycle long)
err1_i => tbt_decim_q_ch01_incorrect_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => tbt_decim_err_clr_i,
-- Output counter
cntr_o => tbt_incorrect_ctnr_ch01_o
);
cmp_tbt_ch23_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => tbt_ce_i,
-- Error inputs (one clock cycle long)
err1_i => tbt_decim_q_ch23_incorrect_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => tbt_decim_err_clr_i,
-- Output counter
cntr_o => tbt_incorrect_ctnr_ch23_o
);
-------------------------------------------------------------------------------
-- FOFB error counters
-------------------------------------------------------------------------------
cmp_fofb_ch01_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => fofb_ce_i,
-- Error inputs (one clock cycle long)
err1_i => fofb_decim_q_ch01_missing_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => fofb_decim_err_clr_i,
-- Output counter
cntr_o => fofb_incorrect_ctnr_ch01_o
);
cmp_fofb_ch23_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => fofb_ce_i,
-- Error inputs (one clock cycle long)
err1_i => fofb_decim_q_ch23_missing_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => fofb_decim_err_clr_i,
-- Output counter
cntr_o => fofb_incorrect_ctnr_ch23_o
);
-------------------------------------------------------------------------------
-- Monit part 1 error counters
-------------------------------------------------------------------------------
cmp_monit_cic_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => monit_cic_ce_i,
-- Error inputs (one clock cycle long)
err1_i => monit_cic_unexpected_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => monit_part1_err_clr_i,
-- Output counter
cntr_o => monit_cic_incorrect_ctnr_o
);
cmp_monit_cfir_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => monit_cfir_ce_i,
-- Error inputs (one clock cycle long)
err1_i => monit_cfir_incorrect_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => monit_part1_err_clr_i,
-- Output counter
cntr_o => monit_cfir_incorrect_ctnr_o
);
-------------------------------------------------------------------------------
-- Monit part 2 error counters
-------------------------------------------------------------------------------
cmp_monit_pfir_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => monit_pfir_ce_i,
-- Error inputs (one clock cycle long)
err1_i => monit_pfir_incorrect_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => monit_part2_err_clr_i,
-- Output counter
cntr_o => monit_pfir_incorrect_ctnr_o
);
cmp_monit_0_1_calc_counters : position_calc_counters_single
port map (
fs_clk2x_i => fs_clk2x_i,
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enable
ce_i => monit_01_ce_i,
-- Error inputs (one clock cycle long)
err1_i => monit_pos_1_incorrect_i,
-- Counter clear (synchronous to fs_clk2x_i and NOT to fs_clk2x_i and ce_i)
cntr_clr_i => monit_part2_err_clr_i,
-- Output counter
cntr_o => monit_01_incorrect_ctnr_o
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity simple_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sreset : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end simple_counter;
architecture Behavioral of simple_counter is
signal Qp : std_logic_vector(NBIT - 1 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0') ;
elsif clk'event and clk = '1' then
if sreset = '1' then
Qp <= (others => '0') ;
elsif load = '1' then
Qp <= E ;
elsif en = '1' then
Qp <= Qp + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Qp;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity simple_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sreset : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end simple_counter;
architecture Behavioral of simple_counter is
signal Qp : std_logic_vector(NBIT - 1 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0') ;
elsif clk'event and clk = '1' then
if sreset = '1' then
Qp <= (others => '0') ;
elsif load = '1' then
Qp <= E ;
elsif en = '1' then
Qp <= Qp + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Qp;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mutex is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mutex;
architecture Behavioral of test_mutex is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
type t_state is (STATE_INIT, STATE_HALLO, STATE_LOCK, STATE_READ, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
out_value <= in_value + 1;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
if done then
state <= STATE_HALLO;
end if;
when STATE_HALLO =>
reconos_write(done, o_osif, i_osif, X"10000002", X"AFFEDEAD");
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, in_value);
if done then
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, out_value);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_2_d;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_2_d;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_2_d;
end architecture test;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:40:01 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.vhdl
-- Design : fifo_generator_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_generator_0 is
Port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC
);
end fifo_generator_0;
architecture stub of fifo_generator_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[9:0],wr_en,rd_en,dout[9:0],full,empty,valid";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2014.1";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb888_to_rgb565_0_0 -prefix
-- system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_stub.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_rgb565_0_0 is
Port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_rgb888_to_rgb565_0_0;
architecture stub of system_rgb888_to_rgb565_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb_888[23:0],rgb_565[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_rgb565,Vivado 2016.4";
begin
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
u1 : mt46v16m16
generic map (index => 1, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
u2 : mt46v16m16
generic map (index => 0, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(3 downto 2));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use std.textio.all;
use work.csv_file_reader_pkg.all;
use work.local_adaptations_pkg.all;
package spec_cov_pkg is
file RESULT_FILE : text;
procedure initialize_req_cov(
constant testcase : string;
constant req_list_file : string;
constant partial_cov_file : string
);
-- Overloading procedure
procedure initialize_req_cov(
constant testcase : string;
constant partial_cov_file : string
);
procedure tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
);
procedure cond_tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
);
procedure disable_cond_tick_off_req_cov(
constant requirement : string
);
procedure enable_cond_tick_off_req_cov(
constant requirement : string
);
procedure finalize_req_cov(
constant VOID : t_void
);
--=================================================================================================
-- Functions and procedures declared below this line are intended as private internal functions
--=================================================================================================
procedure priv_log_entry(
constant index : natural
);
procedure priv_read_and_parse_csv_file(
constant req_list_file : string
);
procedure priv_initialize_result_file(
constant file_name : string
);
impure function priv_get_description(
requirement : string
) return string;
impure function priv_requirement_exists(
requirement : string
) return boolean;
impure function priv_get_num_requirement_tick_offs(
requirement : string
) return natural;
procedure priv_inc_num_requirement_tick_offs(
requirement : string
);
function priv_test_status_to_string(
constant test_status : t_test_status
) return string;
impure function priv_get_summary_string
return string;
procedure priv_set_default_testcase_name(
constant testcase : string
);
impure function priv_get_default_testcase_name
return string;
impure function priv_find_string_length(
constant search_string : string
) return natural;
impure function priv_get_requirement_name_length(
requirement : string)
return natural;
impure function priv_req_listed_in_disabled_tick_off_array(
constant requirement : string
) return boolean;
end package spec_cov_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body spec_cov_pkg is
constant C_FAIL_STRING : string := "FAIL";
constant C_PASS_STRING : string := "PASS";
type t_line_vector is array(0 to shared_spec_cov_config.max_testcases_per_req-1) of line;
type t_requirement_entry is record
valid : boolean;
requirement : line;
description : line;
num_tcs : natural;
tc_list : t_line_vector;
num_tickoffs : natural;
end record;
type t_requirement_entry_array is array (natural range <>) of t_requirement_entry;
-- Shared variables used internally in this context
shared variable priv_csv_file : csv_file_reader_type;
shared variable priv_requirement_array : t_requirement_entry_array(0 to shared_spec_cov_config.max_requirements);
shared variable priv_requirements_in_array : natural := 0;
shared variable priv_testcase_name : string(1 to C_CSV_FILE_MAX_LINE_LENGTH) := (others => NUL);
shared variable priv_testcase_passed : boolean;
shared variable priv_requirement_file_exists : boolean;
type t_disabled_tick_off_array is array(0 to shared_spec_cov_config.max_requirements) of string(1 to C_CSV_FILE_MAX_LINE_LENGTH);
shared variable priv_disabled_tick_off_array : t_disabled_tick_off_array := (others => (others => NUL));
--
-- Initialize testcase requirement coverage
--
procedure initialize_req_cov(
constant testcase : string;
constant req_list_file : string;
constant partial_cov_file : string
) is
begin
priv_set_default_testcase_name(testcase);
-- update pkg local variables
priv_testcase_passed := true;
priv_requirement_file_exists := true;
priv_read_and_parse_csv_file(req_list_file);
priv_initialize_result_file(partial_cov_file);
end procedure initialize_req_cov;
-- Overloading procedure
procedure initialize_req_cov(
constant testcase : string;
constant partial_cov_file : string
) is
begin
log(ID_SPEC_COV, "Requirement Coverage initialized with no requirement file.", C_SCOPE);
priv_set_default_testcase_name(testcase);
-- update pkg local variables
priv_testcase_passed := true;
priv_requirement_file_exists := false;
priv_initialize_result_file(partial_cov_file);
end procedure initialize_req_cov;
--
-- Log the requirement and testcase
--
procedure tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
) is
variable v_requirement_to_file_line : line;
variable v_requirement_status : t_test_status;
variable v_prev_test_status : t_test_status;
begin
if priv_requirements_in_array = 0 and priv_requirement_file_exists = true then
alert(TB_ERROR, "Requirements have not been parsed. Please use initialize_req_cov() with a requirement file before calling tick_off_req_cov().", scope);
return;
end if;
-- Check if requirement exists
if (priv_requirement_exists(requirement) = false) and (priv_requirement_file_exists = true) then
alert(shared_spec_cov_config.missing_req_label_severity, "Requirement not found in requirement list: " & to_string(requirement), C_SCOPE);
end if;
-- Save testcase status
if priv_testcase_passed then
v_prev_test_status := PASS;
else
v_prev_test_status := FAIL;
end if;
---- Check if there were any errors globally or testcase was explicit set to FAIL
if (shared_uvvm_status.found_unexpected_simulation_errors_or_worse = 1) or (test_status = FAIL) then
v_requirement_status := FAIL;
-- Set failing testcase for finishing summary line
priv_testcase_passed := false;
else
v_requirement_status := PASS;
end if;
-- Check if requirement tick-off should be written
if (tickoff_extent = LIST_EVERY_TICKOFF) or (priv_get_num_requirement_tick_offs(requirement) = 0) or
(v_prev_test_status = PASS and test_status = FAIL) then
-- Log result to transcript
log(ID_SPEC_COV, "Logging requirement " & requirement & " [" & priv_test_status_to_string(v_requirement_status) & "]. '" &
priv_get_description(requirement) & "'. " & msg, scope);
-- Log to file
write(v_requirement_to_file_line, requirement & C_CSV_DELIMITER & priv_get_default_testcase_name & C_CSV_DELIMITER & priv_test_status_to_string(v_requirement_status));
writeline(RESULT_FILE, v_requirement_to_file_line);
-- Increment number of tick off for this requirement
priv_inc_num_requirement_tick_offs(requirement);
end if;
end procedure tick_off_req_cov;
--
-- Conditional tick_off_req_cov() for selected requirement.
-- If the requirement has been enabled for conditional tick_off_req_cov()
-- with enable_cond_tick_off_req_cov() it will not be ticked off.
procedure cond_tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
) is
begin
-- Check: is requirement listed in the conditional tick off array?
if priv_req_listed_in_disabled_tick_off_array(requirement) = false then
-- requirement was not listed, call tick off method.
tick_off_req_cov(requirement, test_status, msg, tickoff_extent, scope);
end if;
end procedure cond_tick_off_req_cov;
--
-- Disable conditional tick_off_req_cov() setting for
-- selected requirement.
--
procedure disable_cond_tick_off_req_cov(
constant requirement : string
) is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check: is requirement already tracked?
-- method will also check if the requirement exist in the requirement file.
if priv_req_listed_in_disabled_tick_off_array(requirement) = true then
alert(TB_WARNING, "Requirement " & requirement & " is already listed in the conditional tick off array.", C_SCOPE);
return;
end if;
-- add requirement to conditional tick off array.
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- find a free entry, add requirement and exit loop
if priv_disabled_tick_off_array(idx)(1) = NUL then
priv_disabled_tick_off_array(idx)(1 to c_requirement_length) := to_upper(requirement);
exit;
end if;
end loop;
end procedure disable_cond_tick_off_req_cov;
--
-- Enable conditional tick_off_req_cov() setting for
-- selected requirement.
--
procedure enable_cond_tick_off_req_cov(
constant requirement : string
) is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check: is requirement not tracked?
-- method will also check if the requirement exist in the requirement file.
if priv_req_listed_in_disabled_tick_off_array(requirement) = false then
alert(TB_WARNING, "Requirement " & requirement & " is not listed in the conditional tick off array.", C_SCOPE);
else -- requirement is tracked
-- find the requirement and wipe it out from conditional tick off array
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- found requirement, wipe the entry and exit
if priv_disabled_tick_off_array(idx)(1 to c_requirement_length) = to_upper(requirement) then
priv_disabled_tick_off_array(idx) := (others => NUL);
exit;
end if;
end loop;
end if;
end procedure enable_cond_tick_off_req_cov;
--
-- Deallocate memory usage and write summary line to partial_cov file
--
procedure finalize_req_cov(
constant VOID : t_void
) is
variable v_checksum_string : line;
begin
-- Free used memory
log(ID_SPEC_COV, "Freeing stored requirements from memory", C_SCOPE);
for i in 0 to priv_requirements_in_array-1 loop
deallocate(priv_requirement_array(i).requirement);
deallocate(priv_requirement_array(i).description);
for tc in 0 to priv_requirement_array(i).num_tcs-1 loop
deallocate(priv_requirement_array(i).tc_list(tc));
end loop;
priv_requirement_array(i).num_tcs := 0;
priv_requirement_array(i).valid := false;
priv_requirement_array(i).num_tickoffs := 0;
end loop;
priv_requirements_in_array := 0;
-- Add closing line
log(ID_SPEC_COV, "Marking requirement coverage result.", C_SCOPE);
write(v_checksum_string, priv_get_summary_string);
writeline(RESULT_FILE, v_checksum_string);
file_close(RESULT_FILE);
log(ID_SPEC_COV, "Requirement coverage finalized.", C_SCOPE);
end procedure finalize_req_cov;
--=================================================================================================
-- Functions and procedures declared below this line are intended as private internal functions
--=================================================================================================
--
-- Initialize the partial_cov result file
--
procedure priv_initialize_result_file(
constant file_name : string
) is
variable v_file_open_status : FILE_OPEN_STATUS;
variable v_settings_to_file_line : line;
begin
file_open(v_file_open_status, RESULT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
-- Write info and settings to CSV file for Python post-processing script
log(ID_SPEC_COV, "Adding test and configuration information to coverage file. ", C_SCOPE);
write(v_settings_to_file_line, "NOTE: This coverage file is only valid when the last line is 'SUMMARY, " & priv_get_default_testcase_name & ", PASS'" & LF);
write(v_settings_to_file_line, "TESTCASE_NAME: " & priv_get_default_testcase_name & LF);
write(v_settings_to_file_line, "DELIMITER: " & shared_spec_cov_config.csv_delimiter & LF);
writeline(RESULT_FILE, v_settings_to_file_line);
end procedure priv_initialize_result_file;
--
-- Read requirement CSV file
--
procedure priv_read_and_parse_csv_file(
constant req_list_file : string
) is
variable v_tc_valid : boolean;
variable v_file_ok : boolean;
begin
log(ID_SPEC_COV, "Reading and parsing requirement file, " & req_list_file, C_SCOPE);
if priv_requirements_in_array > 0 then
alert(TB_ERROR, "Requirements have already been read from file, please call finalize_req_cov before starting a new requirement coverage process.", C_SCOPE);
return;
end if;
-- Open file and check status, return if failing
v_file_ok := priv_csv_file.initialize(req_list_file, C_CSV_DELIMITER);
if v_file_ok = false then
return;
end if;
-- File ok, read file
while not priv_csv_file.end_of_file loop
priv_csv_file.readline;
-- Read requirement
priv_requirement_array(priv_requirements_in_array).requirement := new string'(priv_csv_file.read_string);
-- Read description
priv_requirement_array(priv_requirements_in_array).description := new string'(priv_csv_file.read_string);
-- Read testcases
v_tc_valid := true;
priv_requirement_array(priv_requirements_in_array).num_tcs := 0;
while v_tc_valid loop
priv_requirement_array(priv_requirements_in_array).tc_list(priv_requirement_array(priv_requirements_in_array).num_tcs) := new string'(priv_csv_file.read_string);
if (priv_requirement_array(priv_requirements_in_array).tc_list(priv_requirement_array(priv_requirements_in_array).num_tcs).all(1) /= NUL) then
priv_requirement_array(priv_requirements_in_array).num_tcs := priv_requirement_array(priv_requirements_in_array).num_tcs + 1;
else
v_tc_valid := false;
end if;
end loop;
-- Validate entry
priv_requirement_array(priv_requirements_in_array).valid := true;
-- Set number of tickoffs for this requirement to 0
priv_requirement_array(priv_requirements_in_array).num_tickoffs := 0;
priv_log_entry(priv_requirements_in_array);
priv_requirements_in_array := priv_requirements_in_array + 1;
end loop;
log(ID_SPEC_COV, "Closing requirement file", C_SCOPE);
priv_csv_file.dispose;
end procedure priv_read_and_parse_csv_file;
--
-- Log CSV readout to terminal
--
procedure priv_log_entry(
constant index : natural
) is
begin
if priv_requirement_array(index).valid then
-- log requirement and description to terminal
log(ID_SPEC_COV, "Requirement: " & priv_requirement_array(index).requirement.all, C_SCOPE);
log(ID_SPEC_COV, "Description: " & priv_requirement_array(index).description.all, C_SCOPE);
-- log testcases to terminal
for i in 0 to priv_requirement_array(index).num_tcs-1 loop
log(ID_SPEC_COV, " TC: " & priv_requirement_array(index).tc_list(i).all, C_SCOPE);
end loop;
else
log(ID_SPEC_COV, "Requirement entry was not valid", C_SCOPE);
end if;
end procedure priv_log_entry;
--
-- Check if requirement exists, return boolean
--
impure function priv_requirement_exists(
requirement : string
) return boolean is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
return true;
end if;
end if;
end loop;
return false;
end function priv_requirement_exists;
--
-- Get number of tick offs for requirement
--
impure function priv_get_num_requirement_tick_offs(
requirement : string
) return natural is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
return priv_requirement_array(i).num_tickoffs;
end if;
end if;
end loop;
return 0;
end function priv_get_num_requirement_tick_offs;
--
-- Increment number of tick offs for requirement
--
procedure priv_inc_num_requirement_tick_offs(
requirement : string
) is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
priv_requirement_array(i).num_tickoffs := priv_requirement_array(i).num_tickoffs + 1;
end if;
end if;
end loop;
end procedure priv_inc_num_requirement_tick_offs;
--
-- Get description of requirement
--
impure function priv_get_description(
requirement : string
) return string is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_requirement_array(i).requirement.all(1 to requirement'length) = requirement(1 to requirement'length) then
-- Found requirement
return priv_requirement_array(i).description.all;
end if;
end loop;
if priv_requirement_file_exists = false then
return "";
else
return "DESCRIPTION NOT FOUND";
end if;
end function priv_get_description;
--
-- Get the t_test_status parameter as string
--
function priv_test_status_to_string(
constant test_status : t_test_status
) return string is
begin
if test_status = PASS then
return C_PASS_STRING;
else -- test_status = FAIL
return C_FAIL_STRING;
end if;
end function priv_test_status_to_string;
--
-- Get a string for finalize summary in the partial_cov CSV file.
--
impure function priv_get_summary_string
return string is
begin
-- Create a CSV coverage file summary string
if (priv_testcase_passed = true) and (shared_uvvm_status.found_unexpected_simulation_errors_or_worse = 0) then
return "SUMMARY, " & priv_get_default_testcase_name & ", " & C_PASS_STRING;
else
return "SUMMARY, " & priv_get_default_testcase_name & ", " & C_FAIL_STRING;
end if;
end function priv_get_summary_string;
--
-- Set the default testcase name.
--
procedure priv_set_default_testcase_name(
constant testcase : string
) is
begin
priv_testcase_name(1 to testcase'length) := testcase;
end procedure priv_set_default_testcase_name;
--
-- Return the default testcase name set when initialize_req_cov() was called.
--
impure function priv_get_default_testcase_name
return string is
variable v_testcase_length : natural := priv_find_string_length(priv_testcase_name);
begin
return priv_testcase_name(1 to v_testcase_length);
end function priv_get_default_testcase_name;
--
-- Find the length of a string which will contain NUL characters.
--
impure function priv_find_string_length(
constant search_string : string
) return natural is
variable v_return : natural := 0;
begin
-- loop string until NUL is found and return idx-1
for idx in 1 to search_string'length loop
if search_string(idx) = NUL then
return idx - 1;
end if;
end loop;
-- NUL was not found, return full length
return search_string'length;
end function priv_find_string_length;
--
-- Get length of requirement name
--
impure function priv_get_requirement_name_length(
requirement : string)
return natural is
variable v_length : natural := 0;
begin
for i in 1 to requirement'length loop
if requirement(i) = NUL then
exit;
else
v_length := v_length + 1;
end if;
end loop;
return v_length;
end function priv_get_requirement_name_length;
--
-- Check if requirement is listed in the priv_disabled_tick_off_array() array.
--
impure function priv_req_listed_in_disabled_tick_off_array(
constant requirement : string
) return boolean is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check if requirement exists
if (priv_requirement_exists(requirement) = false) and (priv_requirement_file_exists = true) then
alert(shared_spec_cov_config.missing_req_label_severity, "Requirement not found in requirement list: " & to_string(requirement), C_SCOPE);
end if;
-- Check if requirement is listed in priv_disabled_tick_off_array() array
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- found
if priv_disabled_tick_off_array(idx)(1 to c_requirement_length) = to_upper(requirement(1 to c_requirement_length)) then
return true;
end if;
end loop;
-- not found
return false;
end function priv_req_listed_in_disabled_tick_off_array;
end package body spec_cov_pkg;
|
library verilog;
use verilog.vl_types.all;
entity chip_top is
port(
clk_ref : in vl_logic;
reset_sw : in vl_logic;
uart_rx : in vl_logic;
uart_tx : out vl_logic;
gpio_in : in vl_logic_vector(3 downto 0);
gpio_out : out vl_logic_vector(17 downto 0);
gpio_io : inout vl_logic_vector(15 downto 0)
);
end chip_top;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
architecture test of inline_08 is
type T is (t1, t2, t3);
-- code from book:
type T_ptr is access T;
procedure deallocate ( P : inout T_ptr );
-- end of code from book
procedure deallocate ( P : inout T_ptr ) is
begin
null;
end procedure deallocate;
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
architecture test of inline_08 is
type T is (t1, t2, t3);
-- code from book:
type T_ptr is access T;
procedure deallocate ( P : inout T_ptr );
-- end of code from book
procedure deallocate ( P : inout T_ptr ) is
begin
null;
end procedure deallocate;
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
architecture test of inline_08 is
type T is (t1, t2, t3);
-- code from book:
type T_ptr is access T;
procedure deallocate ( P : inout T_ptr );
-- end of code from book
procedure deallocate ( P : inout T_ptr ) is
begin
null;
end procedure deallocate;
begin
end architecture test;
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity dff is
port ( signal d, clk : in std_ulogic; q : out std_ulogic );
end entity dff;
----------------------------------------------------------------
architecture behav of dff is
begin
storage : process ( clk ) is
begin
if clk'event and (clk = '1' or clk = 'H') then
q <= d after 5 ns;
end if;
end process storage;
end architecture behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity dff is
port ( signal d, clk : in std_ulogic; q : out std_ulogic );
end entity dff;
----------------------------------------------------------------
architecture behav of dff is
begin
storage : process ( clk ) is
begin
if clk'event and (clk = '1' or clk = 'H') then
q <= d after 5 ns;
end if;
end process storage;
end architecture behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity dff is
port ( signal d, clk : in std_ulogic; q : out std_ulogic );
end entity dff;
----------------------------------------------------------------
architecture behav of dff is
begin
storage : process ( clk ) is
begin
if clk'event and (clk = '1' or clk = 'H') then
q <= d after 5 ns;
end if;
end process storage;
end architecture behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity T2logic is
generic(N:integer:=NSUMG);
port(
R1 : in std_logic_vector(N-1 downto 0);
R2 : in std_logic_vector(N-1 downto 0);
S1 : in std_logic;
S2 : in std_logic;
S3 : in std_logic;
L_OUT : out std_logic_vector(N-1 downto 0)
);
end T2logic;
architecture structural of T2logic is
signal NEG_R1:std_logic_vector(N-1 downto 0);
signal NEG_R2:std_logic_vector(N-1 downto 0);
signal L1,L2,L3:std_logic_vector(N-1 downto 0);
signal L_temp:std_logic_vector(N-1 downto 0);
component nand3to1
port(
R1 : in std_logic_vector(N-1 downto 0);
R2 : in std_logic_vector(N-1 downto 0);
S : in std_logic;
L : out std_logic_vector(N-1 downto 0)
);
end component;
begin
-- LUT: S1 S2 S3 OUT
-- 0 0 1 R1 and R2
-- 1 1 1 R1 or R2
-- 1 1 0 R1 xor R2
neg_R1 <= not R1;
neg_R2 <= not R2;
L1_GEN : nand3to1 port map (neg_R1,R2,S1,L1);
L2_GEN : nand3to1 port map (R1,neg_R2,S2,L2);
L3_GEN : nand3to1 port map (R1,R2,S3,L3);
L_OUT_TEMP: nand3to1 port map (L1,L2,'1',L_temp);
L_OUT_GEN:
for i in 0 to N-1 generate
L_OUT(i) <= L_temp(i) or (not L3(i));
end generate;
end structural;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.net.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- clocks
signal OSC_50_BANK2 : std_logic := '0';
signal OSC_50_BANK3 : std_logic := '0';
signal OSC_50_BANK4 : std_logic := '0';
signal OSC_50_BANK5 : std_logic := '0';
signal OSC_50_BANK6 : std_logic := '0';
signal OSC_50_BANK7 : std_logic := '0';
signal PLL_CLKIN_p : std_logic := '0';
signal SMA_CLKIN_p : std_logic := '0';
--signal SMA_GXBCLK_p : std_logic;
signal GCLKIN : std_logic := '0';
-- signal GCLKOUT_FPGA : std_logic := '0';
-- signal SMA_CLKOUT_p : std_logic := '0';
signal clk_125 : std_logic := '0';
-- cpu reset
signal CPU_RESET_n : std_ulogic := '0';
-- max i/o
-- signal MAX_CONF_D : std_logic_vector(3 downto 0);
-- signal MAX_I2C_SCLK : std_logic;
-- signal MAX_I2C_SDAT : std_logic;
-- LEDs
signal LED : std_logic_vector(7 downto 0);
-- buttons
signal BUTTON : std_logic_vector(3 downto 0);
-- switches
signal SW : std_logic_vector(3 downto 0);
-- slide switches
signal SLIDE_SW : std_logic_vector(3 downto 0);
-- temperature
-- signal TEMP_SMCLK : std_logic;
-- signal TEMP_SMDAT : std_logic;
-- signal TEMP_INT_n : std_logic;
-- current
signal CSENSE_ADC_FO : std_logic;
signal CSENSE_SCK : std_logic;
signal CSENSE_SDI : std_logic;
signal CSENSE_SDO : std_logic;
signal CSENSE_CS_n : std_logic_vector(1 downto 0);
-- fan
signal FAN_CTRL : std_logic;
-- eeprom
signal EEP_SCL : std_logic;
signal EEP_SDA : std_logic;
-- sdcard
-- signal SD_CLK : std_logic;
-- signal SD_CMD : std_logic;
-- signal SD_DAT : std_logic_vector(3 downto 0);
-- signal SD_WP_n : std_logic;
-- Ethernet interfaces
signal ETH_INT_n : std_logic_vector(3 downto 0);
signal ETH_MDC : std_logic_vector(3 downto 0);
signal ETH_MDIO : std_logic_vector(3 downto 0);
signal ETH_RST_n : std_ulogic;
signal ETH_RX_p : std_logic_vector(3 downto 0);
signal ETH_TX_p : std_logic_vector(3 downto 0);
-- PCIe interfaces
--signal PCIE_PREST_n : std_ulogic;
--signal PCIE_REFCLK_p : std_ulogic;
--signal PCIE_RX_p : std_logic_vector(7 downto 0);
--signal PCIE_SMBCLK : std_logic;
--signal PCIE_SMBDAT : std_logic;
--signal PCIE_TX_p : std_logic_vector(7 downto 0);
--signal PCIE_WAKE_n : std_logic;
-- Flash and SRAM, shared signals
signal FSM_A : std_logic_vector(25 downto 1);
signal FSM_D : std_logic_vector(15 downto 0);
-- Flash control
signal FLASH_ADV_n : std_ulogic;
signal FLASH_CE_n : std_ulogic;
signal FLASH_CLK : std_ulogic;
signal FLASH_OE_n : std_ulogic;
signal FLASH_RESET_n : std_ulogic;
signal FLASH_RYBY_n : std_ulogic;
signal FLASH_WE_n : std_ulogic;
-- SSRAM control
signal SSRAM_ADV : std_ulogic;
signal SSRAM_BWA_n : std_ulogic;
signal SSRAM_BWB_n : std_ulogic;
signal SSRAM_CE_n : std_ulogic;
signal SSRAM_CKE_n : std_ulogic;
signal SSRAM_CLK : std_ulogic;
signal SSRAM_OE_n : std_ulogic;
signal SSRAM_WE_n : std_ulogic;
-- USB OTG
--signal OTG_A : std_logic_vector(17 downto 1);
--signal OTG_CS_n : std_ulogic;
--signal OTG_D : std_logic_vector(31 downto 0);
--signal OTG_DC_DACK : std_ulogic;
--signal OTG_DC_DREQ : std_ulogic;
--signal OTG_DC_IRQ : std_ulogic;
--signal OTG_HC_DACK : std_ulogic;
--signal OTG_HC_DREQ : std_ulogic;
--signal OTG_HC_IRQ : std_ulogic;
--signal OTG_OE_n : std_ulogic;
--signal OTG_RESET_n : std_ulogic;
--signal OTG_WE_n : std_ulogic;
-- SATA
--signal SATA_REFCLK_p : std_logic;
--signal SATA_HOST_RX_p : std_logic_vector(1 downto 0);
--signal SATA_HOST_TX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_RX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_TX_p : std_logic_vector(1 downto 0);
-- DDR2 SODIMM
signal M1_DDR2_addr : std_logic_vector(15 downto 0);
signal M1_DDR2_ba : std_logic_vector(2 downto 0);
signal M1_DDR2_cas_n : std_logic;
signal M1_DDR2_cke : std_logic_vector(1 downto 0);
signal M1_DDR2_clk : std_logic_vector(1 downto 0);
signal M1_DDR2_clk_n : std_logic_vector(1 downto 0);
signal M1_DDR2_cs_n : std_logic_vector(1 downto 0);
signal M1_DDR2_dm : std_logic_vector(7 downto 0);
signal M1_DDR2_dq : std_logic_vector(63 downto 0);
signal M1_DDR2_dqs : std_logic_vector(7 downto 0);
signal M1_DDR2_dqsn : std_logic_vector(7 downto 0);
signal M1_DDR2_odt : std_logic_vector(1 downto 0);
signal M1_DDR2_ras_n : std_logic;
-- signal M1_DDR2_SA : std_logic_vector(1 downto 0);
-- signal M1_DDR2_SCL : std_logic;
-- signal M1_DDR2_SDA : std_logic;
signal M1_DDR2_we_n : std_logic;
signal M1_DDR2_oct_rdn : std_logic;
signal M1_DDR2_oct_rup : std_logic;
-- DDR2 SODIMM
--signal M2_DDR2_addr : std_logic_vector(15 downto 0);
--signal M2_DDR2_ba : std_logic_vector(2 downto 0);
--signal M2_DDR2_cas_n : std_logic;
--signal M2_DDR2_cke : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_cs_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_dm : std_logic_vector(7 downto 0);
--signal M2_DDR2_dq : std_logic_vector(63 downto 0);
--signal M2_DDR2_dqs : std_logic_vector(7 downto 0);
--signal M2_DDR2_dqsn : std_logic_vector(7 downto 0);
--signal M2_DDR2_odt : std_logic_vector(1 downto 0);
--signal M2_DDR2_ras_n : std_logic;
--signal M2_DDR2_SA : std_logic_vector(1 downto 0);
--signal M2_DDR2_SCL : std_logic;
--signal M2_DDR2_SDA : std_logic;
--signal M2_DDR2_we_n : std_logic;
-- GPIO
signal GPIO0_D : std_logic_vector(35 downto 0);
-- signal GPIO1_D : std_logic_vector(35 downto 0);
-- Ext I/O
signal EXT_IO : std_logic;
-- HSMC A
-- signal HSMA_CLKIN_n1 : std_logic;
-- signal HSMA_CLKIN_n2 : std_logic;
-- signal HSMA_CLKIN_p1 : std_logic;
-- signal HSMA_CLKIN_p2 : std_logic;
-- signal HSMA_CLKIN0 : std_logic;
signal HSMA_CLKOUT_n2 : std_logic;
signal HSMA_CLKOUT_p2 : std_logic;
-- signal HSMA_D : std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : std_logic_vector(3 downto 0);
-- signal HSMA_OUT_n1 : std_logic;
-- signal HSMA_OUT_p1 : std_logic;
-- signal HSMA_OUT0 : std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- signal HSMA_RX_n : std_logic_vector(16 downto 0);
-- signal HSMA_RX_p : std_logic_vector(16 downto 0);
-- signal HSMA_TX_n : std_logic_vector(16 downto 0);
-- signal HSMA_TX_p : std_logic_vector(16 downto 0);
-- HSMC_B
-- signal HSMB_CLKIN_n1 : std_logic;
-- signal HSMB_CLKIN_n2 : std_logic;
-- signal HSMB_CLKIN_p1 : std_logic;
-- signal HSMB_CLKIN_p2 : std_logic;
-- signal HSMB_CLKIN0 : std_logic;
-- signal HSMB_CLKOUT_n2 : std_logic;
-- signal HSMB_CLKOUT_p2 : std_logic;
-- signal HSMB_D : std_logic_vector(3 downto 0);
-- signal HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- signal HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- signal HSMB_OUT_n1 : std_logic;
-- signal HSMB_OUT_p1 : std_logic;
-- signal HSMB_OUT0 : std_logic;
-- signal HSMB_REFCLK_p : in std_logic;
-- signal HSMB_RX_n : std_logic_vector(16 downto 0);
-- signal HSMB_RX_p : std_logic_vector(16 downto 0);
-- signal HSMB_TX_n : std_logic_vector(16 downto 0);
-- signal HSMB_TX_p : std_logic_vector(16 downto 0);
-- HSMC i2c
-- signal HSMC_SCL : std_logic;
-- signal HSMC_SDA : std_logic;
-- Display
-- signal SEG0_D : std_logic_vector(6 downto 0);
-- signal SEG1_D : std_logic_vector(6 downto 0);
-- signal SEG0_DP : std_ulogic;
-- signal SEG1_DP : std_ulogic;
-- UART
signal UART_CTS : std_ulogic;
signal UART_RTS : std_ulogic;
signal UART_RXD : std_logic;
signal UART_TXD : std_logic;
signal dsuen, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal rst_125 : std_logic;
constant lresp : boolean := false;
constant slips : integer := 11;
signal ETH_RX_p_0_d : std_logic;
signal ETH_RX_p_1_d : std_logic;
begin
-- clock and reset
-- 50 MHz clocks
OSC_50_BANK2 <= not OSC_50_BANK2 after 10 ns;
OSC_50_BANK3 <= not OSC_50_BANK3 after 10 ns;
OSC_50_BANK4 <= not OSC_50_BANK4 after 10 ns;
OSC_50_BANK5 <= not OSC_50_BANK5 after 10 ns;
OSC_50_BANK6 <= not OSC_50_BANK6 after 10 ns;
OSC_50_BANK7 <= not OSC_50_BANK7 after 10 ns;
-- 100 MHz
PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns;
SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns;
GCLKIN <= not GCLKIN after 10 ns;
clk_125 <= not clk_125 after 4 ns;
CPU_RESET_n <= '0', '1' after 200 ns;
-- various interfaces
-- MAX_CONF_D <= (others => 'H');
-- MAX_I2C_SDAT <= 'H';
BUTTON <= "HHHH";
SW <= (others => 'H');
SLIDE_SW <= (others => 'L');
-- TEMP_SMDAT <= 'H';
-- TEMP_INT_n <= 'H';
CSENSE_SCK <= 'H';
CSENSE_SDO <= 'H';
EEP_SDA <= 'H';
-- SD_CMD <= 'H';
-- SD_DAT <= (others => 'H');
-- SD_WP_n <= 'H';
GPIO0_D <= (others => 'H');
-- GPIO1_D <= (others => 'H');
EXT_IO <= 'H';
LED(0) <= 'H';
-- HSMC_SDA <= 'H';
UART_RTS <= '1';
UART_RXD <= 'H';
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6,
OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p,
-- SMA_GXBCLK_p
GCLKIN,
-- GCLKOUT_FPGA, SMA_CLKOUT_p,
-- cpu reset
CPU_RESET_n,
-- max i/o
-- MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT,
-- LEDs
LED,
-- buttons
BUTTON,
-- switches
SW,
-- slide switches
SLIDE_SW,
-- temperature
-- TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n,
-- current
CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n,
-- fan
FAN_CTRL,
-- eeprom
EEP_SCL, EEP_SDA,
-- sdcard
-- SD_CLK, SD_CMD, SD_DAT, SD_WP_n,
-- Ethernet interfaces
ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p,
-- PCIe interfaces
-- PCIE_PREST_n, PCIE_REFCLK_p, PCIE_RX_p, PCIE_SMBCLK,
-- PCIE_SMBDAT, PCIE_TX_p PCIE_WAKE_n
-- Flash and SRAM, shared signals
FSM_A, FSM_D,
-- Flash control
FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n,
FLASH_RESET_n, FLASH_RYBY_n, FLASH_WE_n,
-- SSRAM control
SSRAM_ADV, SSRAM_BWA_n, SSRAM_BWB_n, SSRAM_CE_n,
SSRAM_CKE_n, SSRAM_CLK, SSRAM_OE_n, SSRAM_WE_n,
-- USB OTG
-- OTG_A, OTG_CS_n, OTG_D, OTG_DC_DACK, OTG_DC_DRE, OTG_DC_IRQ,
-- OTG_HC_DACK, OTG_HC_DREQ, OTG_HC_IRQ, OTG_OE_n, OTG_RESET_n,
-- OTG_WE_n,
-- SATA
-- SATA_REFCLK_p, SATA_HOST_RX_p, SATA_HOST_TX_p, SATA_DEVICE_RX_p, SATA_DEVICE_TX_p,
-- DDR2 SODIMM
M1_DDR2_addr, M1_DDR2_ba, M1_DDR2_cas_n, M1_DDR2_cke, M1_DDR2_clk, M1_DDR2_clk_n,
M1_DDR2_cs_n, M1_DDR2_dm, M1_DDR2_dq, M1_DDR2_dqs, M1_DDR2_dqsn, M1_DDR2_odt,
M1_DDR2_ras_n,
-- M1_DDR2_SA, M1_DDR2_SCL, M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_oct_rdn, M1_DDR2_oct_rup,
-- DDR2 SODIMM
-- M2_DDR2_addr, M2_DDR2_ba, M2_DDR2_cas_n, M2_DDR2_cke, M2_DDR2_clk, M2_DDR2_clk_n
-- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt,
-- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n
-- GPIO
GPIO0_D,
-- GPIO1_D,
-- Ext I/O
-- EXT_IO,
-- HSMC A
-- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0,
HSMA_CLKOUT_n2, HSMA_CLKOUT_p2,
-- HSMA_D,
-- HSMA_GXB_RX_p, HSMA_GXB_TX_p,
-- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0,
-- HSMA_REFCLK_p,
-- HSMA_RX_n, HSMA_RX_p, HSMA_TX_n, HSMA_TX_p,
-- HSMC_B
-- HSMB_CLKIN_n1, HSMB_CLKIN_n2, HSMB_CLKIN_p1, HSMB_CLKIN_p2, HSMB_CLKIN0,
-- HSMB_CLKOUT_n2, HSMB_CLKOUT_p2, HSMB_D,
-- HSMB_GXB_RX_p, HSMB_GXB_TX_p,
-- HSMB_OUT_n1, HSMB_OUT_p1, HSMB_OUT0,
-- HSMB_REFCLK_p,
-- HSMB_RX_n, HSMB_RX_p, HSMB_TX_n, HSMB_TX_p,
-- HSMC i2c
-- HSMC_SCL, HSMC_SDA,
-- Display
-- SEG0_D, SEG1_D, SEG0_DP, SEG1_DP,
-- UART
UART_CTS, UART_RTS, UART_RXD, UART_TXD
);
ethsim0 : if CFG_GRETH /= 0 generate
rst_125 <= not CPU_RESET_n;
-- delaying rx line
ETH_RX_p(0) <= transport ETH_RX_p_0_d after 0.8 ns * slips;
p0: ser_phy
generic map(
address => 0,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => CFG_GRETH1G,
base1000_x_hd => CFG_GRETH1G,
base1000_t_fd => CFG_GRETH1G,
base1000_t_hd => CFG_GRETH1G,
fabtech => fabtech,
memtech => memtech
)
port map(
rstn => CPU_RESET_n,
clk_125 => clk_125,
rst_125 => rst_125,
eth_rx_p => ETH_RX_p_0_d,
eth_tx_p => ETH_TX_p(0),
mdio => ETH_MDIO(0),
mdc => ETH_MDC(0)
);
end generate;
ethsim1 : if CFG_GRETH2 /= 0 generate
-- delaying rx line
ETH_RX_p(1) <= transport ETH_RX_p_1_d after 0.8 ns * slips;
p1: ser_phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => CFG_GRETH21G,
base1000_x_hd => CFG_GRETH21G,
base1000_t_fd => CFG_GRETH21G,
base1000_t_hd => CFG_GRETH21G,
fabtech => fabtech,
memtech => memtech
)
port map(
rstn => CPU_RESET_n,
clk_125 => clk_125,
rst_125 => rst_125,
eth_rx_p => ETH_RX_p_1_d,
eth_tx_p => ETH_TX_p(1),
mdio => ETH_MDIO(1),
mdc => ETH_MDC(1)
);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n,
FLASH_WE_n, FLASH_OE_n);
FLASH_RYBY_n <= 'H';
ddr2mem0 : ddr2ram
generic map(
width => 64,
abits => 14,
babits => 3,
colbits => 10,
rowbits => 11,
implbanks => 8,
fname => sdramfile,
speedbin => 1,
density => 3,
lddelay => (0 ns),
swap => 0,
ldguard => 1
)
port map (
a => M1_DDR2_addr(13 downto 0), -- ddr2_addr,
ba => M1_DDR2_ba, -- ddr2_ba,
ck => M1_DDR2_clk(0), -- ddr2_ck_p(0),
ckn => M1_DDR2_clk_n(0), -- ddr2_ck_n(0),
cke => M1_DDR2_cke(0), -- ddr2_cke(0),
csn => M1_DDR2_cs_n(0), -- ddr2_cs_n(0),
dm => M1_DDR2_dm, -- ddr2_dm,
rasn => M1_DDR2_ras_n, -- ddr2_ras_n,
casn => M1_DDR2_cas_n, -- ddr2_cas_n,
wen => M1_DDR2_we_n, -- ddr2_we_n,
dq => M1_DDR2_dq, -- ddr2_dq(15 downto 0),
dqs => M1_DDR2_dqs, -- ddr2_dqs_p,
dqsn => M1_DDR2_dqsn, -- ddr2_dqs_n,
odt => M1_DDR2_odt(0), -- ddr2_odt(0),
doload => LED(2)
);
test0 : grtestmod
generic map ( width => 16 )
port map ( CPU_RESET_n, OSC_50_BANK3, LED(0), FSM_A(20 downto 1), FSM_D,
'0', FLASH_OE_n, FLASH_WE_n);
iuerr : process
begin
wait for 2500 ns;
if to_x01(LED(0)) = '1' then wait on LED(0); end if;
assert (to_x01(LED(0)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
FSM_D <= buskeep(FSM_D) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);--
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);--
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);--
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
end;--
begin--
dsucfg(UART_TXD, UART_RXD);--
wait;
end process;
end ;
|
package repro4_gen is
generic (type t;
function id (a : t) return t);
function id2 (p : t) return t;
end repro4_gen;
package body repro4_gen is
function id2 (p : t) return t
is
-- constant c : t := p;
begin
return id (p);
end id2;
end repro4_gen;
package repro4_sortnet_tb is
generic (
DATA_BITS : positive;
LEN : Positive
);
subtype T_DATA is bit_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(1 to LEN) of T_DATA;
function id (a : t_data_vector) return t_data_vector;
package inst is new work.repro4_gen
generic map (t => t_data_vector, id => id);
end repro4_sortnet_tb;
package body repro4_sortnet_tb is
function id (a : t_data_vector) return t_data_vector is
begin
return a;
end id;
end repro4_sortnet_tb;
entity repro4 is
end repro4;
architecture behav of repro4 is
package tb is new work.repro4_sortnet_tb generic map (3, 4);
begin
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02292ent IS
END c07s02b06x00p32n01i02292ent;
ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert ((1 A * 10.0) > 1 A)
report "Assertion error.(1)";
assert ((1 nm * 1000.0) > 1 nm)
report "Assertion error.(2)";
assert ((1 um * 1000.0) > 1 um)
report "Assertion error.(3)";
assert ((1 mm * 10.0) > 1 mm)
report "Assertion error.(4)";
assert ((10.0 * 1 A) > 1 A)
report "Assertion error.(6)";
assert ((1000.0 * 1 nm) > 1 nm)
report "Assertion error.(7)";
assert ((1000.0 * 1 um) > 1 um)
report "Assertion error.(8)";
assert ((10.0 * 1 mm) > 1 mm)
report "Assertion error.(9)";
assert ((1 A * 254000.0) > 1 A)
report "Assertion error.(16)";
assert ((1 mil * 1000.0) > 1 mil)
report "Assertion error.(17)";
assert ((254000.0 * 1 A) > 1 A)
report "Assertion error.(20)";
assert ((1000.0 * 1 mil) > 1 mil)
report "Assertion error.(21)";
assert NOT( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***PASSED TEST: c07s02b06x00p32n01i02292"
severity NOTE;
assert ( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02292arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02292ent IS
END c07s02b06x00p32n01i02292ent;
ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert ((1 A * 10.0) > 1 A)
report "Assertion error.(1)";
assert ((1 nm * 1000.0) > 1 nm)
report "Assertion error.(2)";
assert ((1 um * 1000.0) > 1 um)
report "Assertion error.(3)";
assert ((1 mm * 10.0) > 1 mm)
report "Assertion error.(4)";
assert ((10.0 * 1 A) > 1 A)
report "Assertion error.(6)";
assert ((1000.0 * 1 nm) > 1 nm)
report "Assertion error.(7)";
assert ((1000.0 * 1 um) > 1 um)
report "Assertion error.(8)";
assert ((10.0 * 1 mm) > 1 mm)
report "Assertion error.(9)";
assert ((1 A * 254000.0) > 1 A)
report "Assertion error.(16)";
assert ((1 mil * 1000.0) > 1 mil)
report "Assertion error.(17)";
assert ((254000.0 * 1 A) > 1 A)
report "Assertion error.(20)";
assert ((1000.0 * 1 mil) > 1 mil)
report "Assertion error.(21)";
assert NOT( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***PASSED TEST: c07s02b06x00p32n01i02292"
severity NOTE;
assert ( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02292arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02292ent IS
END c07s02b06x00p32n01i02292ent;
ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert ((1 A * 10.0) > 1 A)
report "Assertion error.(1)";
assert ((1 nm * 1000.0) > 1 nm)
report "Assertion error.(2)";
assert ((1 um * 1000.0) > 1 um)
report "Assertion error.(3)";
assert ((1 mm * 10.0) > 1 mm)
report "Assertion error.(4)";
assert ((10.0 * 1 A) > 1 A)
report "Assertion error.(6)";
assert ((1000.0 * 1 nm) > 1 nm)
report "Assertion error.(7)";
assert ((1000.0 * 1 um) > 1 um)
report "Assertion error.(8)";
assert ((10.0 * 1 mm) > 1 mm)
report "Assertion error.(9)";
assert ((1 A * 254000.0) > 1 A)
report "Assertion error.(16)";
assert ((1 mil * 1000.0) > 1 mil)
report "Assertion error.(17)";
assert ((254000.0 * 1 A) > 1 A)
report "Assertion error.(20)";
assert ((1000.0 * 1 mil) > 1 mil)
report "Assertion error.(21)";
assert NOT( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***PASSED TEST: c07s02b06x00p32n01i02292"
severity NOTE;
assert ( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02292arch;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
library nuand ;
entity bladerf_tb is
end entity ; -- bladerf_tb
architecture arch of bladerf_tb is
constant C4_CLOCK_HALF_PERIOD : time := 1 sec * (1.0/38.4e6/2.0) ;
type lms_rx_t is record
clock : std_logic ;
clock_out : std_logic ;
data : signed(11 downto 0) ;
enable : std_logic ;
iq_select : std_logic ;
end record ;
type lms_tx_t is record
clock : std_logic ;
data : signed(11 downto 0) ;
enable : std_logic ;
iq_select : std_logic ;
end record ;
type lms_spi_t is record
sclk : std_logic ;
sen : std_logic ;
sdio : std_logic ;
sdo : std_logic ;
end record ;
type fx3_gpif_t is record
pclk : std_logic ;
gpif : std_logic_vector(31 downto 0) ;
ctl : std_logic_vector(12 downto 0) ;
end record ;
type fx3_uart_t is record
rxd : std_logic ;
txd : std_logic ;
csx : std_logic ;
end record ;
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
for i in 1 to count loop
wait until rising_edge(clock) ;
end loop ;
end procedure ;
procedure uart_send( signal clock : in std_logic ; signal txd : out std_logic ; data : in std_logic_vector(7 downto 0) ; cpb : in natural ) is
begin
wait until rising_edge(clock) ;
-- Send start bit
txd <= '0' ;
nop( clock, cpb ) ;
-- Send data
for i in 0 to data'high loop
txd <= data(i) ;
nop( clock, cpb ) ;
end loop ;
-- Send stop bit
txd <= '1' ;
nop( clock, cpb ) ;
end procedure ;
signal c4_clock : std_logic := '1' ;
signal lms_rx : lms_rx_t ;
signal lms_tx : lms_tx_t ;
signal lms_spi : lms_spi_t ;
signal lms_pll_out : std_logic ;
signal lms_reset : std_logic ;
signal fx3_gpif : fx3_gpif_t ;
signal fx3_uart : fx3_uart_t ;
signal refexp_1pps : std_logic ;
begin
-- Main 38.4MHz clock input
c4_clock <= not c4_clock after C4_CLOCK_HALF_PERIOD ;
-- Top level of the FPGA
U_bladerf : entity nuand.bladerf
port map (
-- Main system clock
c4_clock => c4_clock,
-- VCTCXO DAC
dac_sclk => open,
dac_sdi => '0',
dac_sdo => open,
dac_csx => open,
-- LMS RX Interface
lms_rx_clock => lms_rx.clock,
lms_rx_clock_out => lms_rx.clock_out,
lms_rx_data => lms_rx.data,
lms_rx_enable => lms_rx.enable,
lms_rx_iq_select => lms_rx.iq_select,
-- LMS TX Interface
lms_tx_clock => lms_tx.clock,
lms_tx_data => lms_tx.data,
lms_tx_enable => lms_tx.enable,
lms_tx_iq_select => lms_tx.iq_select,
-- LMS SPI Interface
lms_sclk => lms_spi.sclk,
lms_sen => lms_spi.sen,
lms_sdio => lms_spi.sdio,
lms_sdo => lms_spi.sdo,
-- LMS Control Interface
lms_pll_out => lms_pll_out,
lms_reset => lms_reset,
-- FX3 Interface
fx3_pclk => fx3_gpif.pclk,
fx3_gpif => fx3_gpif.gpif,
fx3_ctl => fx3_gpif.ctl,
fx3_uart_rxd => fx3_uart.rxd,
fx3_uart_txd => fx3_uart.txd,
fx3_uart_csx => fx3_uart.csx,
-- 1pps reference
refexp_1pps => refexp_1pps,
-- Expansion Interface
exp_clock => open,
exp_present => '0',
exp_spi_clock => open,
exp_spi_miso => '0',
exp_spi_mosi => open,
exp_gpio => open
) ;
-- LMS6002D Model
U_lms6002d : entity nuand.lms6002d_model
port map (
-- LMS RX Interface
lms_rx_clock => lms_rx.clock,
lms_rx_clock_out => lms_rx.clock_out,
lms_rx_data => lms_rx.data,
lms_rx_enable => lms_rx.enable,
lms_rx_iq_select => lms_rx.iq_select,
-- LMS TX Interface
lms_tx_clock => lms_tx.clock,
lms_tx_data => lms_tx.data,
lms_tx_enable => lms_tx.enable,
lms_tx_iq_select => lms_tx.iq_select,
-- LMS SPI Interface
lms_sclk => lms_spi.sclk,
lms_sen => lms_spi.sen,
lms_sdio => lms_spi.sdio,
lms_sdo => lms_spi.sdo,
-- LMS Control Interface
lms_pll_out => lms_pll_out,
lms_reset => lms_reset
) ;
-- FX3 Model
U_fx3 : entity nuand.fx3_model(digital_loopback)
port map (
-- GPIF
fx3_pclk => fx3_gpif.pclk,
fx3_gpif => fx3_gpif.gpif,
fx3_ctl => fx3_gpif.ctl,
-- UART
fx3_uart_rxd => fx3_uart.rxd,
fx3_uart_txd => fx3_uart.txd,
fx3_uart_csx => fx3_uart.csx
) ;
-- Create an accurate 1pps signal that is 1 ms wide
create_1pps : process
constant PULSE_PERIOD : time := 1 sec ;
constant PULSE_WIDTH : time := 1 ms ;
begin
if( now = 0 ps ) then
refexp_1pps <= '0' ;
else
refexp_1pps <= '1' ;
end if ;
wait for PULSE_WIDTH ;
refexp_1pps <= '0' ;
wait for PULSE_PERIOD - PULSE_WIDTH ;
end process ;
-- Stimulus
tb : process
begin
wait for 10 ms ;
report "-- End of simulation --" severity failure ;
end process ;
end architecture ; -- arch
|
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
START_CLOCK,
STOP_CLOCK,
SET_CLOCK_PERIOD,
SET_CLOCK_HIGH_TIME
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 8;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
clock_period : time;
clock_high_time : time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
-- VVC dedicated fields
clock_period => 10 ns,
clock_high_time => 5 ns
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--========================================================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--========================================================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--========================================================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--========================================================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--========================================================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--========================================================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
START_CLOCK,
STOP_CLOCK,
SET_CLOCK_PERIOD,
SET_CLOCK_HIGH_TIME
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 8;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
clock_period : time;
clock_high_time : time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
-- VVC dedicated fields
clock_period => 10 ns,
clock_high_time => 5 ns
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--========================================================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--========================================================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--========================================================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--========================================================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--========================================================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--========================================================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
entity proctarg is
end proctarg;
architecture behav of proctarg is
procedure proc (n : natural) is
begin
proc := true;
end proc;
procedure proc (n : boolean) is
begin
proc <= true;
end proc;
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:25 11/02/2011
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( entrada0 : in STD_LOGIC_VECTOR (7 downto 0);
entrada1 : in STD_LOGIC_VECTOR (7 downto 0);
salida : out STD_LOGIC_VECTOR (7 downto 0);
selector : in STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
process(entrada0, entrada1, selector)
begin
if selector = '0' then
salida <= entrada0;
else
salida <= entrada1;
end if;
end process;
end Behavioral;
|
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