content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Sp... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VC... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising... |
-- --------------------------------------------------------------
-- Title : Debounce Logic
-- Project : Counter
-- -------- ------------------------------------------------------
-- File : gen_debouncer_.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update ... |
-------------------------------------------------------------------------------
-- Title : UART receiver/transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
asse... |
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
asse... |
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
asse... |
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
asse... |
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
asse... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, ... |
library verilog;
use verilog.vl_types.all;
entity altstratixii_oct is
generic(
lpm_type : string := "altstratixii_oct"
);
port(
terminationenable: in vl_logic;
terminationclock: in vl_logic;
rdn : in vl_logic;
rup : in v... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM is
generic (
WIDTH : integer := 7 -- that makes 256 bit combinations
);
Port (
CLK_66MHZ : in std_ulogic;
LED : out std_ulogic_vector(3 downto 0);
duty_cycle : in unsigned(7 downto 0)
);
e... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rotr00 is
port(
clkrotr: in std_logic ;
codoprotr: in std_logic_vector ( 3 downto 0 );
portArotr: in std_logic_vector ( 7 downto 0 );
inFlagrotr: in std_logic;
outrotr: out std_logic_vect... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- file: timer_tb.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaime... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilin... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:52 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
--
-- Parameterisable N to M mux.
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ParamMux is
generic(
NSpikeSources : integer := 32; -- The number of spike sources.
NOutputs : integer := 16; -- The number of Synapses in the neuron model.
NSelectBits : integer := 5); -... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity uart_testbench is
end uart_testbench;
architecture sim of uart_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz... |
library ieee;
use ieee.std_logic_1164.all;
entity RAM_T is
end RAM_T;
architecture Beh of RAM_T is
component RAM is
generic(
-- øèíà äàííûé
m: integer := 2;
-- øèíà àäðåñà
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logi... |
----------------------------------------------------------------------------
--
-- Oscilloscope VRAM State Machine
--
-- This is an implementation of a VRAM State machine for a digital scope in
-- VHDL. There are three inputs to the system, one selects the trigger
-- slope and the other two determine the relations... |
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0... |
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0... |
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_distance_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
---------------------------------------... |
--
-- \file bram_wrapper.vhd
--
-- Parametrizable BRAM wrapper for use in burst_ram.vhd
--
-- Instantiates RAMB16_Sn_Sm blocks based on generics.
-- The genrics G_PORTA_AWIDTH and G_PORTB_AWIDTH must be set so that together
-- with the selected data width the RAM will hold 16384 bits. That is,
-- the following equation... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library altera_mf;
use altera_mf.all;
entity fifo_com_rx is
generic
(
DEPTH : POSITIVE := 1024;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port
(
aclr : in std_logic := '0';
data : in... |
library ieee;
use ieee.std_logic_1164.all;
entity mixer is
port (h, l : std_logic_vector(7 downto 0);
o : out std_logic_vector (7 downto 0));
end mixer;
architecture behav of mixer is
signal t1 : std_logic_vector (7 downto 0);
begin
a1: entity work.cmask
port map (l, t1);
o <= t1 or h;
end behav;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
--------------------------------------------------------------------/
---- ----
---- WISHBONE rev.B2 compliant synthesizable I2C Slave model ----
---- ----
---- ... |
--------------------------------------------------------------------/
---- ----
---- WISHBONE rev.B2 compliant synthesizable I2C Slave model ----
---- ----
---- ... |
architecture RTL of ENTITY1 is
begin
PROC : process (a) is
-- These should fail
variable v_var1 : std_logic;
variable s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_s... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Copyright (c) 2016 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, includin... |
-- Copyright (c) 2016 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, includin... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2016 11:43:23
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
-- vsg_off library_008 process_012
library ieee;
use ieee.std_logic_arith.all;
-- vsg_on library_008 process_012
library ieee;
use ieee.std_logic.all;
-- vsg_off : comment
entity FIFO is
port (
WRITE_EN : in std_logic;
READ_EN : in std_logic
);
end entity;
-- vsg_on : comment
-- vsg_off library_002 :... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 14:24:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity test is
constant a : b :=
foo'(bar, baz);
end;
|
library work;
use work.opcodes.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
entity i8080 is
Port (
clk : in STD_LOGIC;
addressBus : out STD_LOGIC_VECTOR (15 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 do... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
use work.interfaces.all;
entity alu_tb is
end;
architecture rtl of alu_tb is
component alu is
port(input : in alu_in_if;
o... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Basic Computer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Mano is
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:42:38 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity FIFO is
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
LABEL1: postponed Proc1 (Clock);
LABEL2 : postponed READ (L => BufLine,
VALUE => Q);
process_and_or : postponed process(a,b,d,e) is
begin
end postponed process process... |
-- niosii_system_green_leds_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI addre... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI addre... |
----------------------------------------------------------------------------------
-- EPP Controller
--
-- Original Author: Chris McClelland
-- Altered for use with EPP periperhals by Kyle Temkin
--
-- Portions copyright (c) 2013 Binghamton University
-- Copyright (c) 2011 Chris McClelland
--
-- This program is free s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_CalcoloIndirizzo.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- ***************************... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library pvz;
use pvz.pvz_objects.all;
entity Input is
port(
clock, reset: in std_logic;
click: out std_logic;
game_state: in game_state;
ps2_clk: inout std_logic;
ps2_data: inout std_logic;
mousex, m... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- NEED RESULT: ARCH00164.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00164: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Inertial transactions enti... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:15:11 05/08/2015
-- Design Name:
-- Module Name: gray2angleinc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin2BCDDecoder is
port( inBin : in std_logic_vector (6 downto 0);
outBCD: out std_logic_vector(3 downto 0);
outBCD2:out std_logic_vector(3 downto 0));
end Bin2BCDDecoder;
architecture Behavioral of Bin2BCDDecoder is
signal n,l,m : ... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.