content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin2BCDDecoder is
port( inBin : in std_logic_vector (6 downto 0);
outBCD: out std_logic_vector(3 downto 0);
outBCD2:out std_logic_vector(3 downto 0));
end Bin2BCDDecoder;
architecture Behavioral of Bin2BCDDecoder is
signal n,l,m : ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is port (
CLK, RST: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end D_4FF;
architecture behv of D_4FF is
begin
process(CLK, D, RST)
begin
if RST = '0' then
Q <= "0001";
elsif (CLK'event and CLK = '0') then
Q... |
library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is port (
CLK, RST: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end D_4FF;
architecture behv of D_4FF is
begin
process(CLK, D, RST)
begin
if RST = '0' then
Q <= "0001";
elsif (CLK'event and CLK = '0') then
Q... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package ram_wb8_init is
constant ADDRLEN : integer := 12; -- bits for number of 8 bit words in memory
type store_t is array(0 to (2**ADDRLEN)-1) of std_logic_vector(7 downto 0);
constant RAM_INIT : store_t := (
-- VGA test program vga.s (hexdump o... |
------------------------------------------------------------------------
-- vga_controller_640_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: reset_mir.vhd,v 1.1 2003/05/19 22:14:03 anitas Exp $
-------------------------------------------------------------------------------
--reset_mir.vhd
-------------------------------------------------------------------------------
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_control_plus is
generic (
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00310
--
-- AUTHOR:
--
-- A. Wilm... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gaussian_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_483;
architecture augh of add_483 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_483;
architecture augh of add_483 is
signal carry_inA : std_l... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul_int1 is
port (in1: in std_logic_vector(23 downto 0);
in2: in std_logic_vector(23 downto 0);
clk,rst: in std_logic;
done:out std_logic;
res: out std_logic_vector(47 downto 0):=(others=>'0')
);
end mul_int1;
archite... |
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in ... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilities.all;
... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity command is
generic
(
MTX_BITS : natural := 6;
TID_BITS : natural ... |
entity test is
generic (
a, b : integer);
begin
assert a = b report "a /= b" severity failure;
end entity;
architecture a of test is
begin
end architecture;
|
entity test is
generic (
a, b : integer);
begin
assert a = b report "a /= b" severity failure;
end entity;
architecture a of test is
begin
end architecture;
|
entity test is
generic (
a, b : integer);
begin
assert a = b report "a /= b" severity failure;
end entity;
architecture a of test is
begin
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block1.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont50.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of t... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deadtime_gen_tb is
generic
(
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of deadtime_gen_tb is
constant CLK_PERIOD : time := 1 sec / 20e7;
signal clk : std_... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- Wrapper of gtx2 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
clk_i : in std_logic;
rst_i : in s... |
-- $Id: bp_swibtnled.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: bp_swibtnled - syn
-- Description: Generic SW... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : entity fifo_dsn.1clk_fifo
port map (
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FSM IS
GENERIC (DATA_WIDTH : integer := 19;
NODES : integer := 15);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
GO : IN std_logic;
COMPL : OUT std_logic;
EN_NODES: in std_logic_vector(NODES-1 down... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- NEED RESULT: ARCH00569: Attribute declarations - composite generic subtypes with static initial values passed
-- NEED RESULT: ARCH00569: Attribute declarations - scalar generic subtypes with generic initial values passed
-------------------------------------------------------------------------------
--
-- C... |
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-------------------------------------------------------------------------------
-- Description: Implementation of a 32 x 8 ROM
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity romMemOpA is
port (
addr : ... |
----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Light Sensor Module
-- Authors : Florian Winkler
-- Lust update : 01.09.2017
-- Description : Reads a digital light sensor by Grove through an I2C bus
-------------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_rx_tb is
end rmii_rx_tb;
architecture behav of rmii_rx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic_vector(1 downto 0) := "00";
signal crsdv : std_logic := '0';
signal rx_dv : std_logic... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
-- We don't have VHDL primitives yet, so declare them in examples for now.
package components is
component OSCH
generic (
NOM_FREQ : string := "2.08"
);
port(
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component;
end c... |
library ieee;
use ieee.std_logic_1164.all;
-- We don't have VHDL primitives yet, so declare them in examples for now.
package components is
component OSCH
generic (
NOM_FREQ : string := "2.08"
);
port(
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component;
end c... |
-- This should pass
library ieee;
use ieee.std_logic_1164.all;
--- this should fail
library ieee;
use ieee.std_logic_1164; library analog;
use analog.all; library digital;
use digital.gates.and;
library ieee;
use ieee.std_logic_1164; library analog;
use
analog.all;
use
analog.all;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port(
clk : in std_logic;
write_data : in std_ulogic;
rst : std_ulogic
);
end;
architecture rtl of test2 is
begin
test_1: process(clk)
begin
if rising_edge(clk) then
if rst = ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
procedure proc(constant value : std_logic_vector) is
begin
end procedure;
begin
main : process is
constant const : unsigned(1 downto 0) := "00";
begin
proc(std_logic_vector(const))... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
procedure proc(constant value : std_logic_vector) is
begin
end procedure;
begin
main : process is
constant const : unsigned(1 downto 0) := "00";
begin
proc(std_logic_vector(const))... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
procedure proc(constant value : std_logic_vector) is
begin
end procedure;
begin
main : process is
constant const : unsigned(1 downto 0) := "00";
begin
proc(std_logic_vector(const))... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:20 05/20/2015
-- Design Name:
-- Module Name: module_Rn - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific con... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity MUX is
generic (BITS : natural := 32);
port (
sel: in ctrl_t;
input0 : in std_logic_vector(BITS-1 downto 0);
input1 : in std_logic_vector(BITS-1 downto 0);
outpu... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity BranchMux is
port (
BranchANDZero: in ctrl_t;
AddrALUresult: in addr_t;
addr : in addr_t;
output : out addr_t
);
end entity;
architecture behav of BranchMux is
begin
output <=... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- $Id: rbdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
-- $Id: rbdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
--------------------------------------------------------------------------------
-- prf_main.vhd
-- Pseudorandom function. PMK, MACs, and Nonces in, PTK out
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under th... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
-----------------------------------------------------------------------
-- Package that declares some special functions needed for RTL netlisting
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package FUNCS is
--- RT... |
-- RS232 sender with Wishbone slave interface and fixed, but generic,
-- baudrate and 8N1 mode.
--
-- The master sends data to this slave by setting dat_i to the byte to send
-- and stb_i to 1 at the rising edge of clk_i. This slave acknowledge the
-- request with ack_o = 1 at the next rising edge of clk_i. Then the ma... |
------------------------------------------------------------------------------
-- axi_cond_vars.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE W... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confid... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:21 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either ve... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:34 10/01/2013
-- Design Name:
-- Module Name: uart_receive - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.ROCACHE_PKG.all;
use work.RWCACHE_PKG.all;
entity DLX_TB is
end DLX_TB;
architecture TEST of DLX_TB is
component ROMEM is
generic (
file_path : string(1 to 87) := "/home/gandalf/Documents/Universit... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Function: VGA Controller
-- Resolutions: 640x480 --- 1920x1080
-- INSTRUCTIONS: For changing the resolution, comment the generic mapping at
-- the entity level for the actual resolution,
-- and uncomment the generic mapping for the desired resolution.
-- NOTE: It is important to wire this component with the specifie... |
-- Function: VGA Controller
-- Resolutions: 640x480 --- 1920x1080
-- INSTRUCTIONS: For changing the resolution, comment the generic mapping at
-- the entity level for the actual resolution,
-- and uncomment the generic mapping for the desired resolution.
-- NOTE: It is important to wire this component with the specifie... |
--!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BE... |
--!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BE... |
--!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BE... |
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