content stringlengths 1 1.04M ⌀ |
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entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS lo... |
entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS lo... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- Th... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity_lv is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:42 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simple_multishot_timer is
generic (
match_val : natural range 1 to natural'high
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === ... |
-------------------------------------------
-- Package Name: Hex4Dig2SSeg_Package --
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Hex4Dig2SSeg_Package is
-- 4 hex digits on SSeg displays
component Hex4Digs2SSeg is
port (
clock : in ... |
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity regfile_tb is
-- Generic declarations of the tested unit
generic(
INITREG_T : STD_LOGIC_VECTOR := "00000000";
ADDRESS_BIT_SIZE_T : INTEGER := 8 );
end regfile_tb;
architect... |
library verilog;
use verilog.vl_types.all;
entity excute is
port(
clock : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_src1 : in vl_logic_vector(31 downto 0);
in_src2 : in vl_logic_vector(31 downto 0);
in_dst ... |
library verilog;
use verilog.vl_types.all;
entity excute is
port(
clock : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_src1 : in vl_logic_vector(31 downto 0);
in_src2 : in vl_logic_vector(31 downto 0);
in_dst ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- Title : Shift Out Register (74HC(T)595 and similar types)
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Robotercl... |
-------------------------------------------------------------------------------
-- Title : Shift Out Register (74HC(T)595 and similar types)
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Robotercl... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize... |
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity WriteBack is
PORT ( Clk, rst : in std_logic;
DataIn1, DataIn2, DataIn3 : in std_logic_vector(15 downto 0);
ControlIn : in std_logic_vector (1 downto 0);
DataOut : out std_logic_vector (15 downto 0)
);
END WriteBack;
architecture arch_Writ... |
architecture RTL of FIFO is
signal sig1 : std_logic;
type state_machine is (idle, write, read, done);
-- Violations below
signal sig1 : std_logic;
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------------------------
-- Pulse Generator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_14.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------------------... |
library verilog;
use verilog.vl_types.all;
entity arm_ex_stage is
port(
clk : in vl_logic;
IDEX_rd_we : in vl_logic;
IDEX_cpsr_we : in vl_logic;
IDEX_rd_data_sel: in vl_logic;
IDEX_is_imm : in vl_logic;
IDEX_alu_or_mac : in ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:13:34 11/16/2015
-- Design Name:
-- Module Name: io_mapping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major relea... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later v... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
ENTITY cpu IS
PORT ( Data : IN STD_LOGIC_VECTOR(24 DOWNTO 0) ;
Clock : IN STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
r0_stream, r1_stream, r2_stream, r3_stream, rsys_stream, rtemp0_stream, rtemp1_stream : OUT STD_L... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 20:59:47 06/19/2008
-- Design Name:
-- Module Name: idea_com_inner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
entity array6 is
end entity;
architecture test of array6 is
type int_vec2 is array (natural range <>) of integer_vector;
constant a : int_vec2(1 to 3)(1 to 2) := ( (1, 2), (3, 4), (5, 6) );
begin
main: process is
variable v : a'subtype := a;
begin
assert a(1)(1) = 1;
assert ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_conte... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_conte... |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Recursion unit for recursive code.
--! @author Markus Fehrenz
--! @date 2011/01/12
--!
--! @details T... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_rnd;
architecture behaviour of s298_rnd is
constant s00000000000000: std_logic_vector(7 do... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Sp... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Sp... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Sp... |
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