content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity testeabc is
port( clk : in std_logic;
reset : in std_logic;
breakIn : in std_logic;
mudouClock : in std_logic;
breakOut : out std_logic
);
end testeabc;
ARCHITECTURE ab of testeabc i... |
entity reserved4 is
end;
architecture behav of reserved4 is
signal xnor : bit;
begin
process
begin
wait;
end process;
end behav;
|
entity reserved4 is
end;
architecture behav of reserved4 is
signal xnor : bit;
begin
process
begin
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:52:53 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_iROM_TB.vhd
-- Project Name: TestCPU1
--... |
-------------------------------------------------------------------------------
-- Model: capacitor
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <vladimir.kolchuzhin@ieee.org>
--
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
--... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- universal "adapter"
-- pipelined <> classic
-- word-aligned/byte-aligned address
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wb_slave_adapter is
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_m... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:17:19 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_pixgen.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Desc... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_always is
constant assert_name : string := "OVL_ALWAYS";
constant path ... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY d_latch IS
PORT(d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END d_latch;
ARCHITECTURE behave OF d_latch I... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spaceship is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_left, nes_right: std_logic;
spaceship_x, spaceship_y: out std_logic_vect... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spaceship is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_left, nes_right: std_logic;
spaceship_x, spaceship_y: out std_logic_vect... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.Display_Management_pkg.all;
entity Translator_XY_to_Video_Memory is --=====================================================================
generic(
enable_debug : boolean := true;
resolution : string := "1920x108... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity cannot_return_safety_check_pkg is
end entity;
architecture test of cannot_return_safety_check_pkg is
type record_t is record
element : natural;
end record;
type record_returner_t is protected
impure function return_record return record_t;
end protected;
type record_returner_t is protected bo... |
entity cannot_return_safety_check_pkg is
end entity;
architecture test of cannot_return_safety_check_pkg is
type record_t is record
element : natural;
end record;
type record_returner_t is protected
impure function return_record return record_t;
end protected;
type record_returner_t is protected bo... |
entity cannot_return_safety_check_pkg is
end entity;
architecture test of cannot_return_safety_check_pkg is
type record_t is record
element : natural;
end record;
type record_returner_t is protected
impure function return_record return record_t;
end protected;
type record_returner_t is protected bo... |
entity cannot_return_safety_check_pkg is
end entity;
architecture test of cannot_return_safety_check_pkg is
type record_t is record
element : natural;
end record;
type record_returner_t is protected
impure function return_record return record_t;
end protected;
type record_returner_t is protected bo... |
entity cannot_return_safety_check_pkg is
end entity;
architecture test of cannot_return_safety_check_pkg is
type record_t is record
element : natural;
end record;
type record_returner_t is protected
impure function return_record return record_t;
end protected;
type record_returner_t is protected bo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro is
port (val : std_logic_vector (63 downto 0);
iperm : std_logic_vector (3*8 - 1 downto 0);
en : std_ulogic;
res : out std_logic_vector (63 downto 0));
end entity repro;
architecture behaviour of repro is
t... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00314
--
-- AUTHOR:
--
-- A. Wilm... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11000... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity counter_test is
end counter_test;
architecture behavior of counter_test is
-- Component Declaration for the Unit Under Test (UUT)
compon... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY AsyncTxTest IS
END AsyncTxTest;
ARCHITECTURE behavioral OF AsyncTxTest IS
COMPONENT AsyncTx
PORT ( TX : OUT STD_LOGIC;
ACTIVE : OUT STD_LOGIC;
SEND : IN STD_LOGIC;
CLR : IN STD_LOGIC;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major releas... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Aug 5 18:37:52 2017
--Host : knuff running 64-bit Debian GNU/Linux 9.0... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Description: A flexible scaler for fixed-point values.
-- The sc... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Description: A flexible scaler for fixed-point values.
-- The sc... |
------------------------------------------------------------------
-- image_capture component
------------------------------------------------------------------
-- This component is used to save an image in memory. It uses two
-- buffers in memory with addresses buff0 and buff1 to do it.
-- When start_capture is assert... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lz4_pkg.all;
entity lz4_utline is
port (
clk_i : in std_logic;
reset_i : in std_logic;
length_i : in std_logic_vector(12 downto 0);
position_i : in std_logic_vector(12 downto 0);
-- flags:
Fs ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_eastsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this fi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity AdderN is
generic (N : integer := 16);
port ( A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
S : out std_logic_vector(N-1 downto 0)
);
end AdderN;
architecture Behavioral of Adde... |
-------------------------------------------------------------------------------
--
-- $Id: dmem_ctrl_pack-p.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-----------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS_GTXE1;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity gtxclk is
port ( clk_p : in std_logic; -- input clock
clk_... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS_GTXE1;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity gtxclk is
port ( clk_p : in std_logic; -- input clock
clk_... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS_GTXE1;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity gtxclk is
port ( clk_p : in std_logic; -- input clock
clk_... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS_GTXE1;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity gtxclk is
port ( clk_p : in std_logic; -- input clock
clk_... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed May 03 18:19:08 2017
--Host : LAPTOP-IQ9G3D1I running 64-bit major rele... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Alam (formely Rick)
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: UKStopLight - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descri... |
-- *************************************************************************
-- File: infer_bram_dual_port.vhd
-- Date: 06/22/05
-- Purpose: File used to instantiate an inferred BRAM (dual port),
-- According to Xilinx, this will only work with 7.1 b/c of shared variables.
-- Author: Jason Agron
-- ******************... |
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMIN... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the testbench for simulating the
--! Plasma-SoC.
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.boot_pac... |
-- NEED RESULT: ARCH00375.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00375: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00375: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport ... |
---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: clk_gen
--
-- Description:
--
-- This module is a simple clock divider which generates the BIT_CLK and the LR_CLK
-- signals for the I2S in... |
-- Baudrate generator.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity baudgen is
port(
clk: in std_logic... |
------------------------------------------------------------------------------
-- Testbench for fifo2.vhd
--
-- Project :
-- File : tb_fifo2.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- Last changed: $... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
--Date : Thu Jun 23 02:18:07 2016
--Host : darkin-UX303LN running 64-bit elementary ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.colors_pkg.all;
use work.graphics_types_pkg.all;
use work.font_pkg.all;
package text_mode_pkg is
-- Constrain text coordinates to optmize resources usage
subtype text_coordinate_type is natural range 0 to 127;
con... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
assert sig = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
--
-------------------------------------------------------------------------------
configuration chip_sd_c0 of chip is
for sd
for spi_boot_b : ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity add is
generic (
WIDTH : integer := 3;
HEIGHT : integer := 2
);
port (
clk : in std_logic;
in : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0)
);
end add;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-------------------------------------------------------------------------------
--! @file pf.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2015-01-19
--! @brief Power FPGA communication.
---------------------------------------------------------------... |
-- reverbBuffer.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
-- nios_dut.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_dut is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- audio_in.data
audio_in_valid : in std_logic ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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